1 /* 2 * Renesas SDHI 3 * 4 * Copyright (C) 2015-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2009 Magnus Damm 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Based on "Compaq ASIC3 support": 14 * 15 * Copyright 2001 Compaq Computer Corporation. 16 * Copyright 2004-2005 Phil Blundell 17 * Copyright 2007-2008 OpenedHand Ltd. 18 * 19 * Authors: Phil Blundell <pb@handhelds.org>, 20 * Samuel Ortiz <sameo@openedhand.com> 21 * 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/clk.h> 26 #include <linux/slab.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mfd/tmio.h> 31 #include <linux/sh_dma.h> 32 #include <linux/delay.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/pinctrl/pinctrl-state.h> 35 #include <linux/regulator/consumer.h> 36 37 #include "renesas_sdhi.h" 38 #include "tmio_mmc.h" 39 40 #define EXT_ACC 0xe4 41 42 #define SDHI_VER_GEN2_SDR50 0x490c 43 #define SDHI_VER_RZ_A1 0x820b 44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45 #define SDHI_VER_GEN2_SDR104 0xcb0d 46 #define SDHI_VER_GEN3_SD 0xcc10 47 #define SDHI_VER_GEN3_SDMMC 0xcd10 48 49 #define host_to_priv(host) \ 50 container_of((host)->pdata, struct renesas_sdhi, mmc_data) 51 52 struct renesas_sdhi { 53 struct clk *clk; 54 struct clk *clk_cd; 55 struct tmio_mmc_data mmc_data; 56 struct tmio_mmc_dma dma_priv; 57 struct pinctrl *pinctrl; 58 struct pinctrl_state *pins_default, *pins_uhs; 59 void __iomem *scc_ctl; 60 }; 61 62 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 63 { 64 u32 val; 65 66 /* 67 * see also 68 * renesas_sdhi_of_data :: dma_buswidth 69 */ 70 switch (sd_ctrl_read16(host, CTL_VERSION)) { 71 case SDHI_VER_GEN2_SDR50: 72 val = (width == 32) ? 0x0001 : 0x0000; 73 break; 74 case SDHI_VER_GEN2_SDR104: 75 val = (width == 32) ? 0x0000 : 0x0001; 76 break; 77 case SDHI_VER_GEN3_SD: 78 case SDHI_VER_GEN3_SDMMC: 79 if (width == 64) 80 val = 0x0000; 81 else if (width == 32) 82 val = 0x0101; 83 else 84 val = 0x0001; 85 break; 86 default: 87 /* nothing to do */ 88 return; 89 } 90 91 sd_ctrl_write16(host, EXT_ACC, val); 92 } 93 94 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 95 { 96 struct mmc_host *mmc = host->mmc; 97 struct renesas_sdhi *priv = host_to_priv(host); 98 int ret = clk_prepare_enable(priv->clk); 99 100 if (ret < 0) 101 return ret; 102 103 ret = clk_prepare_enable(priv->clk_cd); 104 if (ret < 0) { 105 clk_disable_unprepare(priv->clk); 106 return ret; 107 } 108 109 /* 110 * The clock driver may not know what maximum frequency 111 * actually works, so it should be set with the max-frequency 112 * property which will already have been read to f_max. If it 113 * was missing, assume the current frequency is the maximum. 114 */ 115 if (!mmc->f_max) 116 mmc->f_max = clk_get_rate(priv->clk); 117 118 /* 119 * Minimum frequency is the minimum input clock frequency 120 * divided by our maximum divider. 121 */ 122 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 123 124 /* enable 16bit data access on SDBUF as default */ 125 renesas_sdhi_sdbuf_width(host, 16); 126 127 return 0; 128 } 129 130 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 131 unsigned int new_clock) 132 { 133 struct renesas_sdhi *priv = host_to_priv(host); 134 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 135 int i, ret; 136 137 /* tested only on R-Car Gen2+ currently; may work for others */ 138 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 139 return clk_get_rate(priv->clk); 140 141 /* 142 * We want the bus clock to be as close as possible to, but no 143 * greater than, new_clock. As we can divide by 1 << i for 144 * any i in [0, 9] we want the input clock to be as close as 145 * possible, but no greater than, new_clock << i. 146 */ 147 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 148 freq = clk_round_rate(priv->clk, new_clock << i); 149 if (freq > (new_clock << i)) { 150 /* Too fast; look for a slightly slower option */ 151 freq = clk_round_rate(priv->clk, 152 (new_clock << i) / 4 * 3); 153 if (freq > (new_clock << i)) 154 continue; 155 } 156 157 diff = new_clock - (freq >> i); 158 if (diff <= diff_min) { 159 best_freq = freq; 160 diff_min = diff; 161 } 162 } 163 164 ret = clk_set_rate(priv->clk, best_freq); 165 166 return ret == 0 ? best_freq : clk_get_rate(priv->clk); 167 } 168 169 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 170 { 171 struct renesas_sdhi *priv = host_to_priv(host); 172 173 clk_disable_unprepare(priv->clk); 174 clk_disable_unprepare(priv->clk_cd); 175 } 176 177 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 178 { 179 struct tmio_mmc_host *host = mmc_priv(mmc); 180 181 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 182 TMIO_STAT_DAT0); 183 } 184 185 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 186 struct mmc_ios *ios) 187 { 188 struct tmio_mmc_host *host = mmc_priv(mmc); 189 struct renesas_sdhi *priv = host_to_priv(host); 190 struct pinctrl_state *pin_state; 191 int ret; 192 193 switch (ios->signal_voltage) { 194 case MMC_SIGNAL_VOLTAGE_330: 195 pin_state = priv->pins_default; 196 break; 197 case MMC_SIGNAL_VOLTAGE_180: 198 pin_state = priv->pins_uhs; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 /* 205 * If anything is missing, assume signal voltage is fixed at 206 * 3.3V and succeed/fail accordingly. 207 */ 208 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 209 return ios->signal_voltage == 210 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 211 212 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 213 if (ret) 214 return ret; 215 216 return pinctrl_select_state(priv->pinctrl, pin_state); 217 } 218 219 /* SCC registers */ 220 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 221 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 222 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 223 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 224 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 225 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 226 227 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 228 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 229 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 230 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 231 232 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 233 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 234 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 235 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 236 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 237 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 238 239 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 240 struct renesas_sdhi *priv, int addr) 241 { 242 return readl(priv->scc_ctl + (addr << host->bus_shift)); 243 } 244 245 static inline void sd_scc_write32(struct tmio_mmc_host *host, 246 struct renesas_sdhi *priv, 247 int addr, u32 val) 248 { 249 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 250 } 251 252 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 253 { 254 struct renesas_sdhi *priv; 255 256 priv = host_to_priv(host); 257 258 /* set sampling clock selection range */ 259 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 260 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 261 262 /* Initialize SCC */ 263 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 264 265 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 266 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 267 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); 268 269 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 270 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 271 272 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 273 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 274 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 275 276 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 277 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 278 279 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 280 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 281 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 282 283 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos); 284 285 /* Read TAPNUM */ 286 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 287 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 288 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 289 } 290 291 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 292 unsigned long tap) 293 { 294 struct renesas_sdhi *priv = host_to_priv(host); 295 296 /* Set sampling clock position */ 297 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 298 } 299 300 #define SH_MOBILE_SDHI_MAX_TAP 3 301 302 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 303 { 304 struct renesas_sdhi *priv = host_to_priv(host); 305 unsigned long tap_cnt; /* counter of tuning success */ 306 unsigned long tap_set; /* tap position */ 307 unsigned long tap_start;/* start position of tuning success */ 308 unsigned long tap_end; /* end position of tuning success */ 309 unsigned long ntap; /* temporary counter of tuning success */ 310 unsigned long i; 311 312 /* Clear SCC_RVSREQ */ 313 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 314 315 /* 316 * Find the longest consecutive run of successful probes. If that 317 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 318 * center index as the tap. 319 */ 320 tap_cnt = 0; 321 ntap = 0; 322 tap_start = 0; 323 tap_end = 0; 324 for (i = 0; i < host->tap_num * 2; i++) { 325 if (test_bit(i, host->taps)) { 326 ntap++; 327 } else { 328 if (ntap > tap_cnt) { 329 tap_start = i - ntap; 330 tap_end = i - 1; 331 tap_cnt = ntap; 332 } 333 ntap = 0; 334 } 335 } 336 337 if (ntap > tap_cnt) { 338 tap_start = i - ntap; 339 tap_end = i - 1; 340 tap_cnt = ntap; 341 } 342 343 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 344 tap_set = (tap_start + tap_end) / 2 % host->tap_num; 345 else 346 return -EIO; 347 348 /* Set SCC */ 349 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); 350 351 /* Enable auto re-tuning */ 352 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 353 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 354 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 355 356 return 0; 357 } 358 359 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 360 { 361 struct renesas_sdhi *priv = host_to_priv(host); 362 363 /* Check SCC error */ 364 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 365 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 366 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 367 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 368 /* Clear SCC error */ 369 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 370 return true; 371 } 372 373 return false; 374 } 375 376 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 377 { 378 struct renesas_sdhi *priv; 379 380 priv = host_to_priv(host); 381 382 /* Reset SCC */ 383 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 384 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 385 386 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 387 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 388 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 389 390 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 391 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 392 393 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 394 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 395 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 396 397 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 398 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 399 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 400 } 401 402 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 403 { 404 int timeout = 1000; 405 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 406 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 407 408 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 409 & bit) == wait_state) 410 udelay(1); 411 412 if (!timeout) { 413 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 414 return -EBUSY; 415 } 416 417 return 0; 418 } 419 420 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 421 { 422 u32 bit = TMIO_STAT_SCLKDIVEN; 423 424 switch (addr) { 425 case CTL_SD_CMD: 426 case CTL_STOP_INTERNAL_ACTION: 427 case CTL_XFER_BLK_COUNT: 428 case CTL_SD_XFER_LEN: 429 case CTL_SD_MEM_CARD_OPT: 430 case CTL_TRANSACTION_CTL: 431 case CTL_DMA_ENABLE: 432 case EXT_ACC: 433 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 434 bit = TMIO_STAT_CMD_BUSY; 435 /* fallthrough */ 436 case CTL_SD_CARD_CLK_CTL: 437 return renesas_sdhi_wait_idle(host, bit); 438 } 439 440 return 0; 441 } 442 443 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 444 unsigned int direction, int blk_size) 445 { 446 /* 447 * In Renesas controllers, when performing a 448 * multiple block read of one or two blocks, 449 * depending on the timing with which the 450 * response register is read, the response 451 * value may not be read properly. 452 * Use single block read for this HW bug 453 */ 454 if ((direction == MMC_DATA_READ) && 455 blk_size == 2) 456 return 1; 457 458 return blk_size; 459 } 460 461 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 462 { 463 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 464 int width = (host->bus_shift == 2) ? 64 : 32; 465 466 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 467 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 468 } 469 470 int renesas_sdhi_probe(struct platform_device *pdev, 471 const struct tmio_mmc_dma_ops *dma_ops) 472 { 473 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 474 const struct renesas_sdhi_of_data *of_data; 475 struct tmio_mmc_data *mmc_data; 476 struct tmio_mmc_dma *dma_priv; 477 struct tmio_mmc_host *host; 478 struct renesas_sdhi *priv; 479 struct resource *res; 480 int irq, ret, i; 481 482 of_data = of_device_get_match_data(&pdev->dev); 483 484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 485 if (!res) 486 return -EINVAL; 487 488 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 489 GFP_KERNEL); 490 if (!priv) 491 return -ENOMEM; 492 493 mmc_data = &priv->mmc_data; 494 dma_priv = &priv->dma_priv; 495 496 priv->clk = devm_clk_get(&pdev->dev, NULL); 497 if (IS_ERR(priv->clk)) { 498 ret = PTR_ERR(priv->clk); 499 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 500 goto eprobe; 501 } 502 503 /* 504 * Some controllers provide a 2nd clock just to run the internal card 505 * detection logic. Unfortunately, the existing driver architecture does 506 * not support a separation of clocks for runtime PM usage. When 507 * native hotplug is used, the tmio driver assumes that the core 508 * must continue to run for card detect to stay active, so we cannot 509 * disable it. 510 * Additionally, it is prohibited to supply a clock to the core but not 511 * to the card detect circuit. That leaves us with if separate clocks 512 * are presented, we must treat them both as virtually 1 clock. 513 */ 514 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 515 if (IS_ERR(priv->clk_cd)) 516 priv->clk_cd = NULL; 517 518 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 519 if (!IS_ERR(priv->pinctrl)) { 520 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 521 PINCTRL_STATE_DEFAULT); 522 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 523 "state_uhs"); 524 } 525 526 host = tmio_mmc_host_alloc(pdev); 527 if (!host) { 528 ret = -ENOMEM; 529 goto eprobe; 530 } 531 532 if (of_data) { 533 mmc_data->flags |= of_data->tmio_flags; 534 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 535 mmc_data->capabilities |= of_data->capabilities; 536 mmc_data->capabilities2 |= of_data->capabilities2; 537 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 538 mmc_data->max_blk_count = of_data->max_blk_count; 539 mmc_data->max_segs = of_data->max_segs; 540 dma_priv->dma_buswidth = of_data->dma_buswidth; 541 host->bus_shift = of_data->bus_shift; 542 } 543 544 host->dma = dma_priv; 545 host->write16_hook = renesas_sdhi_write16_hook; 546 host->clk_enable = renesas_sdhi_clk_enable; 547 host->clk_update = renesas_sdhi_clk_update; 548 host->clk_disable = renesas_sdhi_clk_disable; 549 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 550 551 /* SDR speeds are only available on Gen2+ */ 552 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 553 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 554 host->card_busy = renesas_sdhi_card_busy; 555 host->start_signal_voltage_switch = 556 renesas_sdhi_start_signal_voltage_switch; 557 } 558 559 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 560 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 561 host->bus_shift = 1; 562 563 if (mmd) 564 *mmc_data = *mmd; 565 566 dma_priv->filter = shdma_chan_filter; 567 dma_priv->enable = renesas_sdhi_enable_dma; 568 569 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 570 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 571 572 /* 573 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 574 * bus width mode. 575 */ 576 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 577 578 /* 579 * All SDHI blocks support SDIO IRQ signalling. 580 */ 581 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 582 583 /* All SDHI have CMD12 control bit */ 584 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 585 586 /* All SDHI have SDIO status bits which must be 1 */ 587 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 588 589 ret = tmio_mmc_host_probe(host, mmc_data, dma_ops); 590 if (ret < 0) 591 goto efree; 592 593 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 594 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 595 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 596 597 /* Enable tuning iff we have an SCC and a supported mode */ 598 if (of_data && of_data->scc_offset && 599 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 600 host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { 601 const struct renesas_sdhi_scc *taps = of_data->taps; 602 bool hit = false; 603 604 host->mmc->caps |= MMC_CAP_HW_RESET; 605 606 for (i = 0; i < of_data->taps_num; i++) { 607 if (taps[i].clk_rate == 0 || 608 taps[i].clk_rate == host->mmc->f_max) { 609 host->scc_tappos = taps->tap; 610 hit = true; 611 break; 612 } 613 } 614 615 if (!hit) 616 dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 617 618 priv->scc_ctl = host->ctl + of_data->scc_offset; 619 host->init_tuning = renesas_sdhi_init_tuning; 620 host->prepare_tuning = renesas_sdhi_prepare_tuning; 621 host->select_tuning = renesas_sdhi_select_tuning; 622 host->check_scc_error = renesas_sdhi_check_scc_error; 623 host->hw_reset = renesas_sdhi_hw_reset; 624 } 625 626 i = 0; 627 while (1) { 628 irq = platform_get_irq(pdev, i); 629 if (irq < 0) 630 break; 631 i++; 632 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 633 dev_name(&pdev->dev), host); 634 if (ret) 635 goto eirq; 636 } 637 638 /* There must be at least one IRQ source */ 639 if (!i) { 640 ret = irq; 641 goto eirq; 642 } 643 644 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 645 mmc_hostname(host->mmc), (unsigned long) 646 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 647 host->mmc->f_max / 1000000); 648 649 return ret; 650 651 eirq: 652 tmio_mmc_host_remove(host); 653 efree: 654 tmio_mmc_host_free(host); 655 eprobe: 656 return ret; 657 } 658 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 659 660 int renesas_sdhi_remove(struct platform_device *pdev) 661 { 662 struct mmc_host *mmc = platform_get_drvdata(pdev); 663 struct tmio_mmc_host *host = mmc_priv(mmc); 664 665 tmio_mmc_host_remove(host); 666 667 return 0; 668 } 669 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 670