1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas SDHI
4  *
5  * Copyright (C) 2015-19 Renesas Electronics Corporation
6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8  * Copyright (C) 2009 Magnus Damm
9  *
10  * Based on "Compaq ASIC3 support":
11  *
12  * Copyright 2001 Compaq Computer Corporation.
13  * Copyright 2004-2005 Phil Blundell
14  * Copyright 2007-2008 OpenedHand Ltd.
15  *
16  * Authors: Phil Blundell <pb@handhelds.org>,
17  *	    Samuel Ortiz <sameo@openedhand.com>
18  *
19  */
20 
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/kernel.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pinctrl/pinctrl-state.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_domain.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/reset.h>
37 #include <linux/sh_dma.h>
38 #include <linux/slab.h>
39 #include <linux/sys_soc.h>
40 
41 #include "renesas_sdhi.h"
42 #include "tmio_mmc.h"
43 
44 #define CTL_HOST_MODE	0xe4
45 #define HOST_MODE_GEN2_SDR50_WMODE	BIT(0)
46 #define HOST_MODE_GEN2_SDR104_WMODE	BIT(0)
47 #define HOST_MODE_GEN3_WMODE		BIT(0)
48 #define HOST_MODE_GEN3_BUSWIDTH		BIT(8)
49 
50 #define HOST_MODE_GEN3_16BIT	HOST_MODE_GEN3_WMODE
51 #define HOST_MODE_GEN3_32BIT	(HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
52 #define HOST_MODE_GEN3_64BIT	0
53 
54 #define CTL_SDIF_MODE	0xe6
55 #define SDIF_MODE_HS400		BIT(0)
56 
57 #define SDHI_VER_GEN2_SDR50	0x490c
58 #define SDHI_VER_RZ_A1		0x820b
59 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
60 #define SDHI_VER_GEN2_SDR104	0xcb0d
61 #define SDHI_VER_GEN3_SD	0xcc10
62 #define SDHI_VER_GEN3_SDMMC	0xcd10
63 
64 #define SDHI_GEN3_MMC0_ADDR	0xee140000
65 
66 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
67 {
68 	u32 val;
69 
70 	/*
71 	 * see also
72 	 *	renesas_sdhi_of_data :: dma_buswidth
73 	 */
74 	switch (sd_ctrl_read16(host, CTL_VERSION)) {
75 	case SDHI_VER_GEN2_SDR50:
76 		val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
77 		break;
78 	case SDHI_VER_GEN2_SDR104:
79 		val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
80 		break;
81 	case SDHI_VER_GEN3_SD:
82 	case SDHI_VER_GEN3_SDMMC:
83 		if (width == 64)
84 			val = HOST_MODE_GEN3_64BIT;
85 		else if (width == 32)
86 			val = HOST_MODE_GEN3_32BIT;
87 		else
88 			val = HOST_MODE_GEN3_16BIT;
89 		break;
90 	default:
91 		/* nothing to do */
92 		return;
93 	}
94 
95 	sd_ctrl_write16(host, CTL_HOST_MODE, val);
96 }
97 
98 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
99 {
100 	struct mmc_host *mmc = host->mmc;
101 	struct renesas_sdhi *priv = host_to_priv(host);
102 	int ret;
103 
104 	ret = clk_prepare_enable(priv->clk_cd);
105 	if (ret < 0)
106 		return ret;
107 
108 	/*
109 	 * The clock driver may not know what maximum frequency
110 	 * actually works, so it should be set with the max-frequency
111 	 * property which will already have been read to f_max.  If it
112 	 * was missing, assume the current frequency is the maximum.
113 	 */
114 	if (!mmc->f_max)
115 		mmc->f_max = clk_get_rate(priv->clk);
116 
117 	/*
118 	 * Minimum frequency is the minimum input clock frequency
119 	 * divided by our maximum divider.
120 	 */
121 	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
122 
123 	/* enable 16bit data access on SDBUF as default */
124 	renesas_sdhi_sdbuf_width(host, 16);
125 
126 	return 0;
127 }
128 
129 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
130 					    unsigned int wanted_clock)
131 {
132 	struct renesas_sdhi *priv = host_to_priv(host);
133 	struct clk *ref_clk = priv->clk;
134 	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
135 	unsigned int new_clock, clkh_shift = 0;
136 	int i;
137 
138 	/*
139 	 * We simply return the current rate if a) we are not on a R-Car Gen2+
140 	 * SoC (may work for others, but untested) or b) if the SCC needs its
141 	 * clock during tuning, so we don't change the external clock setup.
142 	 */
143 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
144 		return clk_get_rate(priv->clk);
145 
146 	if (priv->clkh) {
147 		bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
148 		bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
149 				      (host->mmc->ios.timing == MMC_TIMING_MMC_HS400);
150 		clkh_shift = use_4tap && need_slow_clkh ? 1 : 2;
151 		ref_clk = priv->clkh;
152 	}
153 
154 	new_clock = wanted_clock << clkh_shift;
155 
156 	/*
157 	 * We want the bus clock to be as close as possible to, but no
158 	 * greater than, new_clock.  As we can divide by 1 << i for
159 	 * any i in [0, 9] we want the input clock to be as close as
160 	 * possible, but no greater than, new_clock << i.
161 	 */
162 	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
163 		freq = clk_round_rate(ref_clk, new_clock << i);
164 		if (freq > (new_clock << i)) {
165 			/* Too fast; look for a slightly slower option */
166 			freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
167 			if (freq > (new_clock << i))
168 				continue;
169 		}
170 
171 		diff = new_clock - (freq >> i);
172 		if (diff <= diff_min) {
173 			best_freq = freq;
174 			diff_min = diff;
175 		}
176 	}
177 
178 	clk_set_rate(ref_clk, best_freq);
179 
180 	if (priv->clkh)
181 		clk_set_rate(priv->clk, best_freq >> clkh_shift);
182 
183 	return clk_get_rate(priv->clk);
184 }
185 
186 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
187 				   unsigned int new_clock)
188 {
189 	u32 clk = 0, clock;
190 
191 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
192 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
193 
194 	if (new_clock == 0) {
195 		host->mmc->actual_clock = 0;
196 		goto out;
197 	}
198 
199 	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
200 	clock = host->mmc->actual_clock / 512;
201 
202 	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
203 		clock <<= 1;
204 
205 	/* 1/1 clock is option */
206 	if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
207 		if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
208 			clk |= 0xff;
209 		else
210 			clk &= ~0xff;
211 	}
212 
213 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
214 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
215 		usleep_range(10000, 11000);
216 
217 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
218 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
219 
220 out:
221 	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
222 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
223 		usleep_range(10000, 11000);
224 }
225 
226 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
227 {
228 	struct renesas_sdhi *priv = host_to_priv(host);
229 
230 	clk_disable_unprepare(priv->clk_cd);
231 }
232 
233 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
234 {
235 	struct tmio_mmc_host *host = mmc_priv(mmc);
236 
237 	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
238 		 TMIO_STAT_DAT0);
239 }
240 
241 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
242 						    struct mmc_ios *ios)
243 {
244 	struct tmio_mmc_host *host = mmc_priv(mmc);
245 	struct renesas_sdhi *priv = host_to_priv(host);
246 	struct pinctrl_state *pin_state;
247 	int ret;
248 
249 	switch (ios->signal_voltage) {
250 	case MMC_SIGNAL_VOLTAGE_330:
251 		pin_state = priv->pins_default;
252 		break;
253 	case MMC_SIGNAL_VOLTAGE_180:
254 		pin_state = priv->pins_uhs;
255 		break;
256 	default:
257 		return -EINVAL;
258 	}
259 
260 	/*
261 	 * If anything is missing, assume signal voltage is fixed at
262 	 * 3.3V and succeed/fail accordingly.
263 	 */
264 	if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
265 		return ios->signal_voltage ==
266 			MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
267 
268 	ret = mmc_regulator_set_vqmmc(host->mmc, ios);
269 	if (ret < 0)
270 		return ret;
271 
272 	return pinctrl_select_state(priv->pinctrl, pin_state);
273 }
274 
275 /* SCC registers */
276 #define SH_MOBILE_SDHI_SCC_DTCNTL	0x000
277 #define SH_MOBILE_SDHI_SCC_TAPSET	0x002
278 #define SH_MOBILE_SDHI_SCC_DT2FF	0x004
279 #define SH_MOBILE_SDHI_SCC_CKSEL	0x006
280 #define SH_MOBILE_SDHI_SCC_RVSCNTL	0x008
281 #define SH_MOBILE_SDHI_SCC_RVSREQ	0x00A
282 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
283 #define SH_MOBILE_SDHI_SCC_TMPPORT2	0x00E
284 #define SH_MOBILE_SDHI_SCC_TMPPORT3	0x014
285 #define SH_MOBILE_SDHI_SCC_TMPPORT4	0x016
286 #define SH_MOBILE_SDHI_SCC_TMPPORT5	0x018
287 #define SH_MOBILE_SDHI_SCC_TMPPORT6	0x01A
288 #define SH_MOBILE_SDHI_SCC_TMPPORT7	0x01C
289 
290 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
291 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
292 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK	0xff
293 
294 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL		BIT(0)
295 
296 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN	BIT(0)
297 
298 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN	BIT(0)
299 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP	BIT(1)
300 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR	BIT(2)
301 
302 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN	BIT(8)
303 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP	BIT(24)
304 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR	(BIT(8) | BIT(24))
305 
306 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL	BIT(4)
307 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN	BIT(31)
308 
309 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
310 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START	BIT(0)
311 
312 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
313 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R	BIT(8)
314 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W	(0 << 8)
315 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK	0x3F
316 
317 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
318 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE	0xa5000000
319 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK	0x1f
320 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE		BIT(7)
321 
322 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
323 				struct renesas_sdhi *priv, int addr)
324 {
325 	return readl(priv->scc_ctl + (addr << host->bus_shift));
326 }
327 
328 static inline void sd_scc_write32(struct tmio_mmc_host *host,
329 				  struct renesas_sdhi *priv,
330 				  int addr, u32 val)
331 {
332 	writel(val, priv->scc_ctl + (addr << host->bus_shift));
333 }
334 
335 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
336 {
337 	struct renesas_sdhi *priv;
338 
339 	priv = host_to_priv(host);
340 
341 	/* Initialize SCC */
342 	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
343 
344 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
345 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
346 
347 	/* set sampling clock selection range */
348 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
349 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
350 		       0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
351 
352 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
353 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
354 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
355 
356 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
357 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
358 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
359 
360 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
361 
362 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
363 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
364 
365 	/* Read TAPNUM */
366 	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
367 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
368 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
369 }
370 
371 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
372 {
373 	struct tmio_mmc_host *host = mmc_priv(mmc);
374 	struct renesas_sdhi *priv = host_to_priv(host);
375 	u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
376 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
377 
378 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
379 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
380 
381 	/* Set HS400 mode */
382 	sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
383 			sd_ctrl_read16(host, CTL_SDIF_MODE));
384 
385 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
386 		       priv->scc_tappos_hs400);
387 
388 	/* Gen3 can't do automatic tap correction with HS400, so disable it */
389 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
390 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
391 			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
392 			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
393 
394 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
395 		       (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
396 			SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
397 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
398 
399 	/* Set the sampling clock selection range of HS400 mode */
400 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
401 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
402 		       0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
403 
404 	/* Avoid bad TAP */
405 	if (bad_taps & BIT(priv->tap_set)) {
406 		u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
407 
408 		if (bad_taps & BIT(new_tap))
409 			new_tap = (priv->tap_set - 1) % priv->tap_num;
410 
411 		if (bad_taps & BIT(new_tap)) {
412 			new_tap = priv->tap_set;
413 			dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
414 		}
415 
416 		priv->tap_set = new_tap;
417 	}
418 
419 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
420 		       priv->tap_set / (use_4tap ? 2 : 1));
421 
422 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
423 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
424 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
425 
426 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
427 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
428 
429 	if (priv->adjust_hs400_calib_table)
430 		priv->needs_adjust_hs400 = true;
431 }
432 
433 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
434 {
435 	struct tmio_mmc_host *host = mmc_priv(mmc);
436 	struct renesas_sdhi *priv = host_to_priv(host);
437 
438 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
439 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
440 
441 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
442 		       ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
443 		       sd_scc_read32(host, priv,
444 				     SH_MOBILE_SDHI_SCC_CKSEL));
445 
446 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
447 		       ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
448 		       sd_scc_read32(host, priv,
449 				     SH_MOBILE_SDHI_SCC_DTCNTL));
450 
451 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
452 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
453 }
454 
455 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
456 				 struct renesas_sdhi *priv, u32 addr)
457 {
458 	/* read mode */
459 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
460 		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
461 		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
462 
463 	/* access start and stop */
464 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
465 		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
466 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
467 
468 	return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
469 }
470 
471 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
472 				   struct renesas_sdhi *priv, u32 addr, u32 val)
473 {
474 	/* write mode */
475 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
476 		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
477 		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
478 
479 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
480 
481 	/* access start and stop */
482 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
483 		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
484 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
485 }
486 
487 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
488 {
489 	struct renesas_sdhi *priv = host_to_priv(host);
490 	u32 calib_code;
491 
492 	/* disable write protect */
493 	sd_scc_tmpport_write32(host, priv, 0x00,
494 			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
495 	/* read calibration code and adjust */
496 	calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
497 	calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
498 
499 	sd_scc_tmpport_write32(host, priv, 0x22,
500 			       SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
501 			       priv->adjust_hs400_calib_table[calib_code]);
502 
503 	/* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
504 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
505 
506 	/* adjustment done, clear flag */
507 	priv->needs_adjust_hs400 = false;
508 }
509 
510 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
511 {
512 	struct renesas_sdhi *priv = host_to_priv(host);
513 
514 	/* disable write protect */
515 	sd_scc_tmpport_write32(host, priv, 0x00,
516 			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
517 	/* disable manual calibration */
518 	sd_scc_tmpport_write32(host, priv, 0x22, 0);
519 	/* clear offset value of TMPPORT3 */
520 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
521 }
522 
523 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
524 					  struct renesas_sdhi *priv)
525 {
526 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
527 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
528 
529 	/* Reset HS400 mode */
530 	sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
531 			sd_ctrl_read16(host, CTL_SDIF_MODE));
532 
533 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
534 
535 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
536 		       ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
537 			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
538 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
539 
540 	if (priv->adjust_hs400_calib_table)
541 		renesas_sdhi_adjust_hs400_mode_disable(host);
542 
543 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
544 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
545 }
546 
547 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
548 {
549 	struct tmio_mmc_host *host = mmc_priv(mmc);
550 
551 	renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
552 	return 0;
553 }
554 
555 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
556 {
557 	renesas_sdhi_disable_scc(host->mmc);
558 	renesas_sdhi_reset_hs400_mode(host, priv);
559 	priv->needs_adjust_hs400 = false;
560 
561 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
562 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
563 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
564 }
565 
566 /* only populated for TMIO_MMC_MIN_RCAR2 */
567 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
568 {
569 	struct renesas_sdhi *priv = host_to_priv(host);
570 	int ret;
571 	u16 val;
572 
573 	if (priv->rstc) {
574 		reset_control_reset(priv->rstc);
575 		/* Unknown why but without polling reset status, it will hang */
576 		read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
577 				  false, priv->rstc);
578 		/* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
579 		sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
580 		priv->needs_adjust_hs400 = false;
581 		renesas_sdhi_set_clock(host, host->clk_cache);
582 	} else if (priv->scc_ctl) {
583 		renesas_sdhi_scc_reset(host, priv);
584 	}
585 
586 	if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
587 		val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
588 		val |= CARD_OPT_EXTOP;
589 		sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
590 	}
591 }
592 
593 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
594 {
595 	u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
596 
597 	num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
598 	return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
599 
600 }
601 
602 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
603 
604 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
605 {
606 	struct renesas_sdhi *priv = host_to_priv(host);
607 	unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
608 	unsigned int taps_size = priv->tap_num * 2, min_tap_row;
609 	unsigned long *bitmap;
610 
611 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
612 
613 	/*
614 	 * When tuning CMD19 is issued twice for each tap, merge the
615 	 * result requiring the tap to be good in both runs before
616 	 * considering it for tuning selection.
617 	 */
618 	for (i = 0; i < taps_size; i++) {
619 		int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
620 
621 		if (!test_bit(i, priv->taps))
622 			clear_bit(i + offset, priv->taps);
623 
624 		if (!test_bit(i, priv->smpcmp))
625 			clear_bit(i + offset, priv->smpcmp);
626 	}
627 
628 	/*
629 	 * If all TAP are OK, the sampling clock position is selected by
630 	 * identifying the change point of data.
631 	 */
632 	if (bitmap_full(priv->taps, taps_size)) {
633 		bitmap = priv->smpcmp;
634 		min_tap_row = 1;
635 	} else {
636 		bitmap = priv->taps;
637 		min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
638 	}
639 
640 	/*
641 	 * Find the longest consecutive run of successful probes. If that
642 	 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
643 	 * center index as the tap, otherwise bail out.
644 	 */
645 	for_each_set_bitrange(rs, re, bitmap, taps_size) {
646 		if (re - rs > tap_cnt) {
647 			tap_end = re;
648 			tap_start = rs;
649 			tap_cnt = tap_end - tap_start;
650 		}
651 	}
652 
653 	if (tap_cnt >= min_tap_row)
654 		priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
655 	else
656 		return -EIO;
657 
658 	/* Set SCC */
659 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
660 
661 	/* Enable auto re-tuning */
662 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
663 		       SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
664 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
665 
666 	return 0;
667 }
668 
669 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
670 {
671 	struct tmio_mmc_host *host = mmc_priv(mmc);
672 	struct renesas_sdhi *priv = host_to_priv(host);
673 	int i, ret;
674 
675 	priv->tap_num = renesas_sdhi_init_tuning(host);
676 	if (!priv->tap_num)
677 		return 0; /* Tuning is not supported */
678 
679 	if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
680 		dev_err(&host->pdev->dev,
681 			"Too many taps, please update 'taps' in tmio_mmc_host!\n");
682 		return -EINVAL;
683 	}
684 
685 	bitmap_zero(priv->taps, priv->tap_num * 2);
686 	bitmap_zero(priv->smpcmp, priv->tap_num * 2);
687 
688 	/* Issue CMD19 twice for each tap */
689 	for (i = 0; i < 2 * priv->tap_num; i++) {
690 		int cmd_error = 0;
691 
692 		/* Set sampling clock position */
693 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
694 
695 		if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
696 			set_bit(i, priv->taps);
697 
698 		if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
699 			set_bit(i, priv->smpcmp);
700 
701 		if (cmd_error)
702 			mmc_send_abort_tuning(mmc, opcode);
703 	}
704 
705 	ret = renesas_sdhi_select_tuning(host);
706 	if (ret < 0)
707 		renesas_sdhi_scc_reset(host, priv);
708 	return ret;
709 }
710 
711 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
712 {
713 	struct renesas_sdhi *priv = host_to_priv(host);
714 	unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
715 	u32 val;
716 
717 	val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
718 	if (!val)
719 		return false;
720 
721 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
722 
723 	/* Change TAP position according to correction status */
724 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
725 	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
726 		u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
727 		/*
728 		 * With HS400, the DAT signal is based on DS, not CLK.
729 		 * Therefore, use only CMD status.
730 		 */
731 		u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
732 					   SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
733 		if (!smpcmp) {
734 			return false;	/* no error in CMD signal */
735 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
736 			new_tap++;
737 			error_tap--;
738 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
739 			new_tap--;
740 			error_tap++;
741 		} else {
742 			return true;	/* need retune */
743 		}
744 
745 		/*
746 		 * When new_tap is a bad tap, we cannot change. Then, we compare
747 		 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
748 		 * we can at least retune.
749 		 */
750 		if (bad_taps & BIT(new_tap % priv->tap_num))
751 			return test_bit(error_tap % priv->tap_num, priv->smpcmp);
752 	} else {
753 		if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
754 			return true;    /* need retune */
755 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
756 			new_tap++;
757 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
758 			new_tap--;
759 		else
760 			return false;
761 	}
762 
763 	priv->tap_set = (new_tap % priv->tap_num);
764 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
765 		       priv->tap_set / (use_4tap ? 2 : 1));
766 
767 	return false;
768 }
769 
770 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
771 {
772 	struct renesas_sdhi *priv = host_to_priv(host);
773 
774 	/* Check SCC error */
775 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
776 	    SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
777 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
778 		return true;
779 	}
780 
781 	return false;
782 }
783 
784 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
785 					 struct mmc_request *mrq)
786 {
787 	struct renesas_sdhi *priv = host_to_priv(host);
788 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
789 	bool ret = false;
790 
791 	/*
792 	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
793 	 * any retuning would still result in the same 4 taps being used.
794 	 */
795 	if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
796 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
797 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
798 		return false;
799 
800 	if (mmc_doing_tune(host->mmc))
801 		return false;
802 
803 	if (((mrq->cmd->error == -ETIMEDOUT) ||
804 	     (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
805 	    ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
806 	     (host->ops.get_cd && host->ops.get_cd(host->mmc))))
807 		ret |= true;
808 
809 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
810 	    SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
811 		ret |= renesas_sdhi_auto_correction(host);
812 	else
813 		ret |= renesas_sdhi_manual_correction(host, use_4tap);
814 
815 	return ret;
816 }
817 
818 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
819 {
820 	int timeout = 1000;
821 	/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
822 	u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
823 
824 	while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
825 			      & bit) == wait_state)
826 		udelay(1);
827 
828 	if (!timeout) {
829 		dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
830 		return -EBUSY;
831 	}
832 
833 	return 0;
834 }
835 
836 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
837 {
838 	u32 bit = TMIO_STAT_SCLKDIVEN;
839 
840 	switch (addr) {
841 	case CTL_SD_CMD:
842 	case CTL_STOP_INTERNAL_ACTION:
843 	case CTL_XFER_BLK_COUNT:
844 	case CTL_SD_XFER_LEN:
845 	case CTL_SD_MEM_CARD_OPT:
846 	case CTL_TRANSACTION_CTL:
847 	case CTL_DMA_ENABLE:
848 	case CTL_HOST_MODE:
849 		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
850 			bit = TMIO_STAT_CMD_BUSY;
851 		fallthrough;
852 	case CTL_SD_CARD_CLK_CTL:
853 		return renesas_sdhi_wait_idle(host, bit);
854 	}
855 
856 	return 0;
857 }
858 
859 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
860 				       unsigned int direction, int blk_size)
861 {
862 	/*
863 	 * In Renesas controllers, when performing a
864 	 * multiple block read of one or two blocks,
865 	 * depending on the timing with which the
866 	 * response register is read, the response
867 	 * value may not be read properly.
868 	 * Use single block read for this HW bug
869 	 */
870 	if ((direction == MMC_DATA_READ) &&
871 	    blk_size == 2)
872 		return 1;
873 
874 	return blk_size;
875 }
876 
877 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
878 {
879 	struct renesas_sdhi *priv = host_to_priv(host);
880 
881 	if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
882 		renesas_sdhi_adjust_hs400_mode_enable(host);
883 }
884 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
885 {
886 	/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
887 	int width = (host->bus_shift == 2) ? 64 : 32;
888 
889 	sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
890 	renesas_sdhi_sdbuf_width(host, enable ? width : 16);
891 }
892 
893 int renesas_sdhi_probe(struct platform_device *pdev,
894 		       const struct tmio_mmc_dma_ops *dma_ops,
895 		       const struct renesas_sdhi_of_data *of_data,
896 		       const struct renesas_sdhi_quirks *quirks)
897 {
898 	struct tmio_mmc_data *mmd = pdev->dev.platform_data;
899 	struct tmio_mmc_data *mmc_data;
900 	struct tmio_mmc_dma *dma_priv;
901 	struct tmio_mmc_host *host;
902 	struct renesas_sdhi *priv;
903 	int num_irqs, irq, ret, i;
904 	struct resource *res;
905 	u16 ver;
906 
907 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908 	if (!res)
909 		return -EINVAL;
910 
911 	priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
912 			    GFP_KERNEL);
913 	if (!priv)
914 		return -ENOMEM;
915 
916 	priv->quirks = quirks;
917 	mmc_data = &priv->mmc_data;
918 	dma_priv = &priv->dma_priv;
919 
920 	priv->clk = devm_clk_get(&pdev->dev, NULL);
921 	if (IS_ERR(priv->clk))
922 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock");
923 
924 	priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
925 	if (IS_ERR(priv->clkh))
926 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh");
927 
928 	/*
929 	 * Some controllers provide a 2nd clock just to run the internal card
930 	 * detection logic. Unfortunately, the existing driver architecture does
931 	 * not support a separation of clocks for runtime PM usage. When
932 	 * native hotplug is used, the tmio driver assumes that the core
933 	 * must continue to run for card detect to stay active, so we cannot
934 	 * disable it.
935 	 * Additionally, it is prohibited to supply a clock to the core but not
936 	 * to the card detect circuit. That leaves us with if separate clocks
937 	 * are presented, we must treat them both as virtually 1 clock.
938 	 */
939 	priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd");
940 	if (IS_ERR(priv->clk_cd))
941 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock");
942 
943 	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
944 	if (!IS_ERR(priv->pinctrl)) {
945 		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
946 						PINCTRL_STATE_DEFAULT);
947 		priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
948 						"state_uhs");
949 	}
950 
951 	host = tmio_mmc_host_alloc(pdev, mmc_data);
952 	if (IS_ERR(host))
953 		return PTR_ERR(host);
954 
955 	if (of_data) {
956 		mmc_data->flags |= of_data->tmio_flags;
957 		mmc_data->ocr_mask = of_data->tmio_ocr_mask;
958 		mmc_data->capabilities |= of_data->capabilities;
959 		mmc_data->capabilities2 |= of_data->capabilities2;
960 		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
961 		mmc_data->max_blk_count = of_data->max_blk_count;
962 		mmc_data->max_segs = of_data->max_segs;
963 		dma_priv->dma_buswidth = of_data->dma_buswidth;
964 		host->bus_shift = of_data->bus_shift;
965 		/* Fallback for old DTs */
966 		if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK)
967 			priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
968 
969 	}
970 
971 	host->write16_hook	= renesas_sdhi_write16_hook;
972 	host->clk_enable	= renesas_sdhi_clk_enable;
973 	host->clk_disable	= renesas_sdhi_clk_disable;
974 	host->set_clock		= renesas_sdhi_set_clock;
975 	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
976 	host->dma_ops		= dma_ops;
977 
978 	if (quirks && quirks->hs400_disabled)
979 		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
980 
981 	/* For some SoC, we disable internal WP. GPIO may override this */
982 	if (mmc_can_gpio_ro(host->mmc))
983 		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
984 
985 	/* SDR speeds are only available on Gen2+ */
986 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
987 		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
988 		host->ops.card_busy = renesas_sdhi_card_busy;
989 		host->ops.start_signal_voltage_switch =
990 			renesas_sdhi_start_signal_voltage_switch;
991 		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
992 		host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
993 		host->reset = renesas_sdhi_reset;
994 	}
995 
996 	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
997 	if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
998 		host->bus_shift = 1;
999 
1000 	if (mmd)
1001 		*mmc_data = *mmd;
1002 
1003 	dma_priv->filter = shdma_chan_filter;
1004 	dma_priv->enable = renesas_sdhi_enable_dma;
1005 
1006 	mmc_data->alignment_shift = 1; /* 2-byte alignment */
1007 	mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1008 
1009 	/*
1010 	 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1011 	 * bus width mode.
1012 	 */
1013 	mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1014 
1015 	/*
1016 	 * All SDHI blocks support SDIO IRQ signalling.
1017 	 */
1018 	mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1019 
1020 	/* All SDHI have CMD12 control bit */
1021 	mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1022 
1023 	/* All SDHI have SDIO status bits which must be 1 */
1024 	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1025 
1026 	/* All SDHI support HW busy detection */
1027 	mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1028 
1029 	dev_pm_domain_start(&pdev->dev);
1030 
1031 	ret = renesas_sdhi_clk_enable(host);
1032 	if (ret)
1033 		goto efree;
1034 
1035 	priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1036 	if (IS_ERR(priv->rstc))
1037 		return PTR_ERR(priv->rstc);
1038 
1039 	ver = sd_ctrl_read16(host, CTL_VERSION);
1040 	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
1041 	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1042 		mmc_data->max_blk_count = U16_MAX;
1043 
1044 	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1045 	if (ver == SDHI_VER_GEN2_SDR50)
1046 		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1047 
1048 	if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1049 		host->fixup_request = renesas_sdhi_fixup_request;
1050 		priv->adjust_hs400_calib_table = *(
1051 			res->start == SDHI_GEN3_MMC0_ADDR ?
1052 			quirks->hs400_calib_table :
1053 			quirks->hs400_calib_table + 1);
1054 	}
1055 
1056 	/* these have an EXTOP bit */
1057 	if (ver >= SDHI_VER_GEN3_SD)
1058 		host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1059 
1060 	/* Enable tuning iff we have an SCC and a supported mode */
1061 	if (of_data && of_data->scc_offset &&
1062 	    (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1063 	     host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1064 				 MMC_CAP2_HS400_1_8V))) {
1065 		const struct renesas_sdhi_scc *taps = of_data->taps;
1066 		bool use_4tap = quirks && quirks->hs400_4taps;
1067 		bool hit = false;
1068 
1069 		for (i = 0; i < of_data->taps_num; i++) {
1070 			if (taps[i].clk_rate == 0 ||
1071 			    taps[i].clk_rate == host->mmc->f_max) {
1072 				priv->scc_tappos = taps->tap;
1073 				priv->scc_tappos_hs400 = use_4tap ?
1074 							 taps->tap_hs400_4tap :
1075 							 taps->tap;
1076 				hit = true;
1077 				break;
1078 			}
1079 		}
1080 
1081 		if (!hit)
1082 			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1083 
1084 		priv->scc_ctl = host->ctl + of_data->scc_offset;
1085 		host->check_retune = renesas_sdhi_check_scc_error;
1086 		host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1087 		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1088 		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1089 		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1090 	}
1091 
1092 	ret = tmio_mmc_host_probe(host);
1093 	if (ret < 0)
1094 		goto edisclk;
1095 
1096 	num_irqs = platform_irq_count(pdev);
1097 	if (num_irqs < 0) {
1098 		ret = num_irqs;
1099 		goto eirq;
1100 	}
1101 
1102 	/* There must be at least one IRQ source */
1103 	if (!num_irqs) {
1104 		ret = -ENXIO;
1105 		goto eirq;
1106 	}
1107 
1108 	for (i = 0; i < num_irqs; i++) {
1109 		irq = platform_get_irq(pdev, i);
1110 		if (irq < 0) {
1111 			ret = irq;
1112 			goto eirq;
1113 		}
1114 
1115 		ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1116 				       dev_name(&pdev->dev), host);
1117 		if (ret)
1118 			goto eirq;
1119 	}
1120 
1121 	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1122 		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1123 
1124 	return ret;
1125 
1126 eirq:
1127 	tmio_mmc_host_remove(host);
1128 edisclk:
1129 	renesas_sdhi_clk_disable(host);
1130 efree:
1131 	tmio_mmc_host_free(host);
1132 
1133 	return ret;
1134 }
1135 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1136 
1137 int renesas_sdhi_remove(struct platform_device *pdev)
1138 {
1139 	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1140 
1141 	tmio_mmc_host_remove(host);
1142 	renesas_sdhi_clk_disable(host);
1143 	tmio_mmc_host_free(host);
1144 
1145 	return 0;
1146 }
1147 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1148 
1149 MODULE_LICENSE("GPL v2");
1150