1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/tmio.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/module.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/pinctrl-state.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_domain.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/reset.h> 36 #include <linux/sh_dma.h> 37 #include <linux/slab.h> 38 39 #include "renesas_sdhi.h" 40 #include "tmio_mmc.h" 41 42 #define CTL_HOST_MODE 0xe4 43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 45 #define HOST_MODE_GEN3_WMODE BIT(0) 46 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 47 48 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 49 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 50 #define HOST_MODE_GEN3_64BIT 0 51 52 #define CTL_SDIF_MODE 0xe6 53 #define SDIF_MODE_HS400 BIT(0) 54 55 #define SDHI_VER_GEN2_SDR50 0x490c 56 #define SDHI_VER_RZ_A1 0x820b 57 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 58 #define SDHI_VER_GEN2_SDR104 0xcb0d 59 #define SDHI_VER_GEN3_SD 0xcc10 60 #define SDHI_VER_GEN3_SDMMC 0xcd10 61 62 #define SDHI_GEN3_MMC0_ADDR 0xee140000 63 64 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 65 { 66 u32 val; 67 68 /* 69 * see also 70 * renesas_sdhi_of_data :: dma_buswidth 71 */ 72 switch (sd_ctrl_read16(host, CTL_VERSION)) { 73 case SDHI_VER_GEN2_SDR50: 74 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 75 break; 76 case SDHI_VER_GEN2_SDR104: 77 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 78 break; 79 case SDHI_VER_GEN3_SD: 80 case SDHI_VER_GEN3_SDMMC: 81 if (width == 64) 82 val = HOST_MODE_GEN3_64BIT; 83 else if (width == 32) 84 val = HOST_MODE_GEN3_32BIT; 85 else 86 val = HOST_MODE_GEN3_16BIT; 87 break; 88 default: 89 /* nothing to do */ 90 return; 91 } 92 93 sd_ctrl_write16(host, CTL_HOST_MODE, val); 94 } 95 96 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 97 { 98 struct mmc_host *mmc = host->mmc; 99 struct renesas_sdhi *priv = host_to_priv(host); 100 int ret; 101 102 ret = clk_prepare_enable(priv->clk_cd); 103 if (ret < 0) 104 return ret; 105 106 /* 107 * The clock driver may not know what maximum frequency 108 * actually works, so it should be set with the max-frequency 109 * property which will already have been read to f_max. If it 110 * was missing, assume the current frequency is the maximum. 111 */ 112 if (!mmc->f_max) 113 mmc->f_max = clk_get_rate(priv->clk); 114 115 /* 116 * Minimum frequency is the minimum input clock frequency 117 * divided by our maximum divider. 118 */ 119 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 120 121 /* enable 16bit data access on SDBUF as default */ 122 renesas_sdhi_sdbuf_width(host, 16); 123 124 return 0; 125 } 126 127 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 128 unsigned int wanted_clock) 129 { 130 struct renesas_sdhi *priv = host_to_priv(host); 131 struct clk *ref_clk = priv->clk; 132 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 133 unsigned int new_clock, clkh_shift = 0; 134 int i; 135 136 /* 137 * We simply return the current rate if a) we are not on a R-Car Gen2+ 138 * SoC (may work for others, but untested) or b) if the SCC needs its 139 * clock during tuning, so we don't change the external clock setup. 140 */ 141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142 return clk_get_rate(priv->clk); 143 144 if (priv->clkh) { 145 /* HS400 with 4TAP needs different clock settings */ 146 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 147 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 148 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 149 ref_clk = priv->clkh; 150 } 151 152 new_clock = wanted_clock << clkh_shift; 153 154 /* 155 * We want the bus clock to be as close as possible to, but no 156 * greater than, new_clock. As we can divide by 1 << i for 157 * any i in [0, 9] we want the input clock to be as close as 158 * possible, but no greater than, new_clock << i. 159 */ 160 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 161 freq = clk_round_rate(ref_clk, new_clock << i); 162 if (freq > (new_clock << i)) { 163 /* Too fast; look for a slightly slower option */ 164 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 165 if (freq > (new_clock << i)) 166 continue; 167 } 168 169 diff = new_clock - (freq >> i); 170 if (diff <= diff_min) { 171 best_freq = freq; 172 diff_min = diff; 173 } 174 } 175 176 clk_set_rate(ref_clk, best_freq); 177 178 if (priv->clkh) 179 clk_set_rate(priv->clk, best_freq >> clkh_shift); 180 181 return clk_get_rate(priv->clk); 182 } 183 184 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 185 unsigned int new_clock) 186 { 187 u32 clk = 0, clock; 188 189 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 190 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 191 192 if (new_clock == 0) { 193 host->mmc->actual_clock = 0; 194 goto out; 195 } 196 197 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 198 clock = host->mmc->actual_clock / 512; 199 200 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 201 clock <<= 1; 202 203 /* 1/1 clock is option */ 204 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 205 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 206 clk |= 0xff; 207 else 208 clk &= ~0xff; 209 } 210 211 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 212 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 213 usleep_range(10000, 11000); 214 215 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 216 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 217 218 out: 219 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 220 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 221 usleep_range(10000, 11000); 222 } 223 224 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 225 { 226 struct renesas_sdhi *priv = host_to_priv(host); 227 228 clk_disable_unprepare(priv->clk_cd); 229 } 230 231 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 232 { 233 struct tmio_mmc_host *host = mmc_priv(mmc); 234 235 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 236 TMIO_STAT_DAT0); 237 } 238 239 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 240 struct mmc_ios *ios) 241 { 242 struct tmio_mmc_host *host = mmc_priv(mmc); 243 struct renesas_sdhi *priv = host_to_priv(host); 244 struct pinctrl_state *pin_state; 245 int ret; 246 247 switch (ios->signal_voltage) { 248 case MMC_SIGNAL_VOLTAGE_330: 249 pin_state = priv->pins_default; 250 break; 251 case MMC_SIGNAL_VOLTAGE_180: 252 pin_state = priv->pins_uhs; 253 break; 254 default: 255 return -EINVAL; 256 } 257 258 /* 259 * If anything is missing, assume signal voltage is fixed at 260 * 3.3V and succeed/fail accordingly. 261 */ 262 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 263 return ios->signal_voltage == 264 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 265 266 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 267 if (ret < 0) 268 return ret; 269 270 return pinctrl_select_state(priv->pinctrl, pin_state); 271 } 272 273 /* SCC registers */ 274 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 275 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 276 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 277 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 278 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 279 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 280 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 281 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 282 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 283 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 284 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 285 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 286 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 287 288 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 289 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 290 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 291 292 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 293 294 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 295 296 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 297 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 298 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 299 300 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 301 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 302 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 303 304 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 305 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 306 307 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 308 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 309 310 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 311 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 312 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 313 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 314 315 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 316 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 317 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 318 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 319 320 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 321 struct renesas_sdhi *priv, int addr) 322 { 323 return readl(priv->scc_ctl + (addr << host->bus_shift)); 324 } 325 326 static inline void sd_scc_write32(struct tmio_mmc_host *host, 327 struct renesas_sdhi *priv, 328 int addr, u32 val) 329 { 330 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 331 } 332 333 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 334 { 335 struct renesas_sdhi *priv; 336 337 priv = host_to_priv(host); 338 339 /* Initialize SCC */ 340 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 341 342 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 343 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 344 345 /* set sampling clock selection range */ 346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 347 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 348 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 349 350 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 351 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 352 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 353 354 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 355 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 356 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 357 358 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 359 360 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 361 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 362 363 /* Read TAPNUM */ 364 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 365 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 366 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 367 } 368 369 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 370 { 371 struct tmio_mmc_host *host = mmc_priv(mmc); 372 struct renesas_sdhi *priv = host_to_priv(host); 373 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 374 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 375 376 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 377 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 378 379 /* Set HS400 mode */ 380 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 381 sd_ctrl_read16(host, CTL_SDIF_MODE)); 382 383 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 384 priv->scc_tappos_hs400); 385 386 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 387 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 388 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 389 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 390 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 391 392 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 393 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 394 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 395 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 396 397 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 398 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 399 sd_scc_read32(host, priv, 400 SH_MOBILE_SDHI_SCC_DTCNTL)); 401 402 /* Avoid bad TAP */ 403 if (bad_taps & BIT(priv->tap_set)) { 404 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 405 406 if (bad_taps & BIT(new_tap)) 407 new_tap = (priv->tap_set - 1) % priv->tap_num; 408 409 if (bad_taps & BIT(new_tap)) { 410 new_tap = priv->tap_set; 411 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 412 } 413 414 priv->tap_set = new_tap; 415 } 416 417 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 418 priv->tap_set / (use_4tap ? 2 : 1)); 419 420 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 421 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 422 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 423 424 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 425 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 426 427 if (priv->adjust_hs400_calib_table) 428 priv->needs_adjust_hs400 = true; 429 } 430 431 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 432 { 433 struct tmio_mmc_host *host = mmc_priv(mmc); 434 struct renesas_sdhi *priv = host_to_priv(host); 435 436 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 437 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 438 439 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 440 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 441 sd_scc_read32(host, priv, 442 SH_MOBILE_SDHI_SCC_CKSEL)); 443 444 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 445 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 446 sd_scc_read32(host, priv, 447 SH_MOBILE_SDHI_SCC_DTCNTL)); 448 449 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 450 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 451 } 452 453 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 454 struct renesas_sdhi *priv, u32 addr) 455 { 456 /* read mode */ 457 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 458 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 459 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 460 461 /* access start and stop */ 462 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 463 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 465 466 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 467 } 468 469 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 470 struct renesas_sdhi *priv, u32 addr, u32 val) 471 { 472 /* write mode */ 473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 474 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 475 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 476 477 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 478 479 /* access start and stop */ 480 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 481 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 483 } 484 485 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 486 { 487 struct renesas_sdhi *priv = host_to_priv(host); 488 u32 calib_code; 489 490 /* disable write protect */ 491 sd_scc_tmpport_write32(host, priv, 0x00, 492 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 493 /* read calibration code and adjust */ 494 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 495 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 496 497 sd_scc_tmpport_write32(host, priv, 0x22, 498 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 499 priv->adjust_hs400_calib_table[calib_code]); 500 501 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 502 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 503 504 /* adjustment done, clear flag */ 505 priv->needs_adjust_hs400 = false; 506 } 507 508 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 509 { 510 struct renesas_sdhi *priv = host_to_priv(host); 511 512 /* disable write protect */ 513 sd_scc_tmpport_write32(host, priv, 0x00, 514 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 515 /* disable manual calibration */ 516 sd_scc_tmpport_write32(host, priv, 0x22, 0); 517 /* clear offset value of TMPPORT3 */ 518 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 519 } 520 521 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 522 struct renesas_sdhi *priv) 523 { 524 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 525 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 526 527 /* Reset HS400 mode */ 528 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 529 sd_ctrl_read16(host, CTL_SDIF_MODE)); 530 531 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 532 533 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 534 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 535 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 536 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 537 538 if (priv->adjust_hs400_calib_table) 539 renesas_sdhi_adjust_hs400_mode_disable(host); 540 541 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 542 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 543 } 544 545 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 546 { 547 struct tmio_mmc_host *host = mmc_priv(mmc); 548 549 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 550 return 0; 551 } 552 553 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 554 { 555 renesas_sdhi_disable_scc(host->mmc); 556 renesas_sdhi_reset_hs400_mode(host, priv); 557 priv->needs_adjust_hs400 = false; 558 559 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 560 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 561 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 562 } 563 564 /* only populated for TMIO_MMC_MIN_RCAR2 */ 565 static void renesas_sdhi_reset(struct tmio_mmc_host *host) 566 { 567 struct renesas_sdhi *priv = host_to_priv(host); 568 int ret; 569 u16 val; 570 571 if (priv->rstc) { 572 reset_control_reset(priv->rstc); 573 /* Unknown why but without polling reset status, it will hang */ 574 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 575 false, priv->rstc); 576 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 577 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 578 priv->needs_adjust_hs400 = false; 579 renesas_sdhi_set_clock(host, host->clk_cache); 580 } else if (priv->scc_ctl) { 581 renesas_sdhi_scc_reset(host, priv); 582 } 583 584 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 585 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 586 val |= CARD_OPT_EXTOP; 587 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 588 } 589 } 590 591 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 592 { 593 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 594 595 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 596 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 597 598 } 599 600 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 601 602 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 603 { 604 struct renesas_sdhi *priv = host_to_priv(host); 605 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 606 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 607 unsigned long *bitmap; 608 609 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 610 611 /* 612 * When tuning CMD19 is issued twice for each tap, merge the 613 * result requiring the tap to be good in both runs before 614 * considering it for tuning selection. 615 */ 616 for (i = 0; i < taps_size; i++) { 617 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 618 619 if (!test_bit(i, priv->taps)) 620 clear_bit(i + offset, priv->taps); 621 622 if (!test_bit(i, priv->smpcmp)) 623 clear_bit(i + offset, priv->smpcmp); 624 } 625 626 /* 627 * If all TAP are OK, the sampling clock position is selected by 628 * identifying the change point of data. 629 */ 630 if (bitmap_full(priv->taps, taps_size)) { 631 bitmap = priv->smpcmp; 632 min_tap_row = 1; 633 } else { 634 bitmap = priv->taps; 635 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 636 } 637 638 /* 639 * Find the longest consecutive run of successful probes. If that 640 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 641 * center index as the tap, otherwise bail out. 642 */ 643 for_each_set_bitrange(rs, re, bitmap, taps_size) { 644 if (re - rs > tap_cnt) { 645 tap_end = re; 646 tap_start = rs; 647 tap_cnt = tap_end - tap_start; 648 } 649 } 650 651 if (tap_cnt >= min_tap_row) 652 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 653 else 654 return -EIO; 655 656 /* Set SCC */ 657 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 658 659 /* Enable auto re-tuning */ 660 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 661 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 662 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 663 664 return 0; 665 } 666 667 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 668 { 669 struct tmio_mmc_host *host = mmc_priv(mmc); 670 struct renesas_sdhi *priv = host_to_priv(host); 671 int i, ret; 672 673 priv->tap_num = renesas_sdhi_init_tuning(host); 674 if (!priv->tap_num) 675 return 0; /* Tuning is not supported */ 676 677 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 678 dev_err(&host->pdev->dev, 679 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 680 return -EINVAL; 681 } 682 683 bitmap_zero(priv->taps, priv->tap_num * 2); 684 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 685 686 /* Issue CMD19 twice for each tap */ 687 for (i = 0; i < 2 * priv->tap_num; i++) { 688 int cmd_error = 0; 689 690 /* Set sampling clock position */ 691 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 692 693 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 694 set_bit(i, priv->taps); 695 696 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 697 set_bit(i, priv->smpcmp); 698 699 if (cmd_error) 700 mmc_send_abort_tuning(mmc, opcode); 701 } 702 703 ret = renesas_sdhi_select_tuning(host); 704 if (ret < 0) 705 renesas_sdhi_scc_reset(host, priv); 706 return ret; 707 } 708 709 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 710 { 711 struct renesas_sdhi *priv = host_to_priv(host); 712 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 713 u32 val; 714 715 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 716 if (!val) 717 return false; 718 719 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 720 721 /* Change TAP position according to correction status */ 722 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 723 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 724 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 725 /* 726 * With HS400, the DAT signal is based on DS, not CLK. 727 * Therefore, use only CMD status. 728 */ 729 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 730 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 731 if (!smpcmp) { 732 return false; /* no error in CMD signal */ 733 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 734 new_tap++; 735 error_tap--; 736 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 737 new_tap--; 738 error_tap++; 739 } else { 740 return true; /* need retune */ 741 } 742 743 /* 744 * When new_tap is a bad tap, we cannot change. Then, we compare 745 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 746 * we can at least retune. 747 */ 748 if (bad_taps & BIT(new_tap % priv->tap_num)) 749 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 750 } else { 751 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 752 return true; /* need retune */ 753 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 754 new_tap++; 755 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 756 new_tap--; 757 else 758 return false; 759 } 760 761 priv->tap_set = (new_tap % priv->tap_num); 762 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 763 priv->tap_set / (use_4tap ? 2 : 1)); 764 765 return false; 766 } 767 768 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 769 { 770 struct renesas_sdhi *priv = host_to_priv(host); 771 772 /* Check SCC error */ 773 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 774 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 775 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 776 return true; 777 } 778 779 return false; 780 } 781 782 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 783 struct mmc_request *mrq) 784 { 785 struct renesas_sdhi *priv = host_to_priv(host); 786 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 787 bool ret = false; 788 789 /* 790 * Skip checking SCC errors when running on 4 taps in HS400 mode as 791 * any retuning would still result in the same 4 taps being used. 792 */ 793 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 794 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 795 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 796 return false; 797 798 if (mmc_doing_tune(host->mmc)) 799 return false; 800 801 if (((mrq->cmd->error == -ETIMEDOUT) || 802 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 803 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 804 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 805 ret |= true; 806 807 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 808 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 809 ret |= renesas_sdhi_auto_correction(host); 810 else 811 ret |= renesas_sdhi_manual_correction(host, use_4tap); 812 813 return ret; 814 } 815 816 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 817 { 818 int timeout = 1000; 819 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 820 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 821 822 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 823 & bit) == wait_state) 824 udelay(1); 825 826 if (!timeout) { 827 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 828 return -EBUSY; 829 } 830 831 return 0; 832 } 833 834 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 835 { 836 u32 bit = TMIO_STAT_SCLKDIVEN; 837 838 switch (addr) { 839 case CTL_SD_CMD: 840 case CTL_STOP_INTERNAL_ACTION: 841 case CTL_XFER_BLK_COUNT: 842 case CTL_SD_XFER_LEN: 843 case CTL_SD_MEM_CARD_OPT: 844 case CTL_TRANSACTION_CTL: 845 case CTL_DMA_ENABLE: 846 case CTL_HOST_MODE: 847 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 848 bit = TMIO_STAT_CMD_BUSY; 849 fallthrough; 850 case CTL_SD_CARD_CLK_CTL: 851 return renesas_sdhi_wait_idle(host, bit); 852 } 853 854 return 0; 855 } 856 857 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 858 unsigned int direction, int blk_size) 859 { 860 /* 861 * In Renesas controllers, when performing a 862 * multiple block read of one or two blocks, 863 * depending on the timing with which the 864 * response register is read, the response 865 * value may not be read properly. 866 * Use single block read for this HW bug 867 */ 868 if ((direction == MMC_DATA_READ) && 869 blk_size == 2) 870 return 1; 871 872 return blk_size; 873 } 874 875 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 876 { 877 struct renesas_sdhi *priv = host_to_priv(host); 878 879 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 880 renesas_sdhi_adjust_hs400_mode_enable(host); 881 } 882 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 883 { 884 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 885 int width = (host->bus_shift == 2) ? 64 : 32; 886 887 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 888 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 889 } 890 891 int renesas_sdhi_probe(struct platform_device *pdev, 892 const struct tmio_mmc_dma_ops *dma_ops, 893 const struct renesas_sdhi_of_data *of_data, 894 const struct renesas_sdhi_quirks *quirks) 895 { 896 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 897 struct tmio_mmc_data *mmc_data; 898 struct tmio_mmc_dma *dma_priv; 899 struct tmio_mmc_host *host; 900 struct renesas_sdhi *priv; 901 int num_irqs, irq, ret, i; 902 struct resource *res; 903 u16 ver; 904 905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 906 if (!res) 907 return -EINVAL; 908 909 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 910 GFP_KERNEL); 911 if (!priv) 912 return -ENOMEM; 913 914 priv->quirks = quirks; 915 mmc_data = &priv->mmc_data; 916 dma_priv = &priv->dma_priv; 917 918 priv->clk = devm_clk_get(&pdev->dev, NULL); 919 if (IS_ERR(priv->clk)) 920 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 921 922 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 923 if (IS_ERR(priv->clkh)) 924 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 925 926 /* 927 * Some controllers provide a 2nd clock just to run the internal card 928 * detection logic. Unfortunately, the existing driver architecture does 929 * not support a separation of clocks for runtime PM usage. When 930 * native hotplug is used, the tmio driver assumes that the core 931 * must continue to run for card detect to stay active, so we cannot 932 * disable it. 933 * Additionally, it is prohibited to supply a clock to the core but not 934 * to the card detect circuit. That leaves us with if separate clocks 935 * are presented, we must treat them both as virtually 1 clock. 936 */ 937 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 938 if (IS_ERR(priv->clk_cd)) 939 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 940 941 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 942 if (!IS_ERR(priv->pinctrl)) { 943 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 944 PINCTRL_STATE_DEFAULT); 945 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 946 "state_uhs"); 947 } 948 949 host = tmio_mmc_host_alloc(pdev, mmc_data); 950 if (IS_ERR(host)) 951 return PTR_ERR(host); 952 953 if (of_data) { 954 mmc_data->flags |= of_data->tmio_flags; 955 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 956 mmc_data->capabilities |= of_data->capabilities; 957 mmc_data->capabilities2 |= of_data->capabilities2; 958 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 959 mmc_data->max_blk_count = of_data->max_blk_count; 960 mmc_data->max_segs = of_data->max_segs; 961 dma_priv->dma_buswidth = of_data->dma_buswidth; 962 host->bus_shift = of_data->bus_shift; 963 /* Fallback for old DTs */ 964 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 965 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 966 967 } 968 969 host->write16_hook = renesas_sdhi_write16_hook; 970 host->clk_enable = renesas_sdhi_clk_enable; 971 host->clk_disable = renesas_sdhi_clk_disable; 972 host->set_clock = renesas_sdhi_set_clock; 973 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 974 host->dma_ops = dma_ops; 975 976 if (quirks && quirks->hs400_disabled) 977 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 978 979 /* For some SoC, we disable internal WP. GPIO may override this */ 980 if (mmc_can_gpio_ro(host->mmc)) 981 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 982 983 /* SDR speeds are only available on Gen2+ */ 984 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 985 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 986 host->ops.card_busy = renesas_sdhi_card_busy; 987 host->ops.start_signal_voltage_switch = 988 renesas_sdhi_start_signal_voltage_switch; 989 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 990 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 991 host->reset = renesas_sdhi_reset; 992 } 993 994 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 995 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 996 host->bus_shift = 1; 997 998 if (mmd) 999 *mmc_data = *mmd; 1000 1001 dma_priv->filter = shdma_chan_filter; 1002 dma_priv->enable = renesas_sdhi_enable_dma; 1003 1004 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1005 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1006 1007 /* 1008 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1009 * bus width mode. 1010 */ 1011 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1012 1013 /* 1014 * All SDHI blocks support SDIO IRQ signalling. 1015 */ 1016 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1017 1018 /* All SDHI have CMD12 control bit */ 1019 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1020 1021 /* All SDHI have SDIO status bits which must be 1 */ 1022 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1023 1024 /* All SDHI support HW busy detection */ 1025 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1026 1027 dev_pm_domain_start(&pdev->dev); 1028 1029 ret = renesas_sdhi_clk_enable(host); 1030 if (ret) 1031 goto efree; 1032 1033 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1034 if (IS_ERR(priv->rstc)) 1035 return PTR_ERR(priv->rstc); 1036 1037 ver = sd_ctrl_read16(host, CTL_VERSION); 1038 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1039 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1040 mmc_data->max_blk_count = U16_MAX; 1041 1042 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1043 if (ver == SDHI_VER_GEN2_SDR50) 1044 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1045 1046 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1047 host->fixup_request = renesas_sdhi_fixup_request; 1048 priv->adjust_hs400_calib_table = *( 1049 res->start == SDHI_GEN3_MMC0_ADDR ? 1050 quirks->hs400_calib_table : 1051 quirks->hs400_calib_table + 1); 1052 } 1053 1054 /* these have an EXTOP bit */ 1055 if (ver >= SDHI_VER_GEN3_SD) 1056 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1057 1058 /* Enable tuning iff we have an SCC and a supported mode */ 1059 if (of_data && of_data->scc_offset && 1060 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1061 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1062 MMC_CAP2_HS400_1_8V))) { 1063 const struct renesas_sdhi_scc *taps = of_data->taps; 1064 bool use_4tap = quirks && quirks->hs400_4taps; 1065 bool hit = false; 1066 1067 for (i = 0; i < of_data->taps_num; i++) { 1068 if (taps[i].clk_rate == 0 || 1069 taps[i].clk_rate == host->mmc->f_max) { 1070 priv->scc_tappos = taps->tap; 1071 priv->scc_tappos_hs400 = use_4tap ? 1072 taps->tap_hs400_4tap : 1073 taps->tap; 1074 hit = true; 1075 break; 1076 } 1077 } 1078 1079 if (!hit) 1080 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1081 1082 priv->scc_ctl = host->ctl + of_data->scc_offset; 1083 host->check_retune = renesas_sdhi_check_scc_error; 1084 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1085 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1086 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1087 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1088 } 1089 1090 ret = tmio_mmc_host_probe(host); 1091 if (ret < 0) 1092 goto edisclk; 1093 1094 num_irqs = platform_irq_count(pdev); 1095 if (num_irqs < 0) { 1096 ret = num_irqs; 1097 goto eirq; 1098 } 1099 1100 /* There must be at least one IRQ source */ 1101 if (!num_irqs) { 1102 ret = -ENXIO; 1103 goto eirq; 1104 } 1105 1106 for (i = 0; i < num_irqs; i++) { 1107 irq = platform_get_irq(pdev, i); 1108 if (irq < 0) { 1109 ret = irq; 1110 goto eirq; 1111 } 1112 1113 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1114 dev_name(&pdev->dev), host); 1115 if (ret) 1116 goto eirq; 1117 } 1118 1119 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1120 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1121 1122 return ret; 1123 1124 eirq: 1125 tmio_mmc_host_remove(host); 1126 edisclk: 1127 renesas_sdhi_clk_disable(host); 1128 efree: 1129 tmio_mmc_host_free(host); 1130 1131 return ret; 1132 } 1133 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1134 1135 int renesas_sdhi_remove(struct platform_device *pdev) 1136 { 1137 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1138 1139 tmio_mmc_host_remove(host); 1140 renesas_sdhi_clk_disable(host); 1141 tmio_mmc_host_free(host); 1142 1143 return 0; 1144 } 1145 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1146 1147 MODULE_LICENSE("GPL v2"); 1148