1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas SDHI
4  *
5  * Copyright (C) 2015-19 Renesas Electronics Corporation
6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8  * Copyright (C) 2009 Magnus Damm
9  *
10  * Based on "Compaq ASIC3 support":
11  *
12  * Copyright 2001 Compaq Computer Corporation.
13  * Copyright 2004-2005 Phil Blundell
14  * Copyright 2007-2008 OpenedHand Ltd.
15  *
16  * Authors: Phil Blundell <pb@handhelds.org>,
17  *	    Samuel Ortiz <sameo@openedhand.com>
18  *
19  */
20 
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mfd/tmio.h>
31 #include <linux/sh_dma.h>
32 #include <linux/delay.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/pinctrl/pinctrl-state.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/sys_soc.h>
37 
38 #include "renesas_sdhi.h"
39 #include "tmio_mmc.h"
40 
41 #define HOST_MODE		0xe4
42 
43 #define SDHI_VER_GEN2_SDR50	0x490c
44 #define SDHI_VER_RZ_A1		0x820b
45 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
46 #define SDHI_VER_GEN2_SDR104	0xcb0d
47 #define SDHI_VER_GEN3_SD	0xcc10
48 #define SDHI_VER_GEN3_SDMMC	0xcd10
49 
50 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
51 {
52 	u32 val;
53 
54 	/*
55 	 * see also
56 	 *	renesas_sdhi_of_data :: dma_buswidth
57 	 */
58 	switch (sd_ctrl_read16(host, CTL_VERSION)) {
59 	case SDHI_VER_GEN2_SDR50:
60 		val = (width == 32) ? 0x0001 : 0x0000;
61 		break;
62 	case SDHI_VER_GEN2_SDR104:
63 		val = (width == 32) ? 0x0000 : 0x0001;
64 		break;
65 	case SDHI_VER_GEN3_SD:
66 	case SDHI_VER_GEN3_SDMMC:
67 		if (width == 64)
68 			val = 0x0000;
69 		else if (width == 32)
70 			val = 0x0101;
71 		else
72 			val = 0x0001;
73 		break;
74 	default:
75 		/* nothing to do */
76 		return;
77 	}
78 
79 	sd_ctrl_write16(host, HOST_MODE, val);
80 }
81 
82 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
83 {
84 	struct mmc_host *mmc = host->mmc;
85 	struct renesas_sdhi *priv = host_to_priv(host);
86 	int ret;
87 
88 	ret = clk_prepare_enable(priv->clk_cd);
89 	if (ret < 0)
90 		return ret;
91 
92 	/*
93 	 * The clock driver may not know what maximum frequency
94 	 * actually works, so it should be set with the max-frequency
95 	 * property which will already have been read to f_max.  If it
96 	 * was missing, assume the current frequency is the maximum.
97 	 */
98 	if (!mmc->f_max)
99 		mmc->f_max = clk_get_rate(priv->clk);
100 
101 	/*
102 	 * Minimum frequency is the minimum input clock frequency
103 	 * divided by our maximum divider.
104 	 */
105 	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
106 
107 	/* enable 16bit data access on SDBUF as default */
108 	renesas_sdhi_sdbuf_width(host, 16);
109 
110 	return 0;
111 }
112 
113 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
114 					    unsigned int new_clock)
115 {
116 	struct renesas_sdhi *priv = host_to_priv(host);
117 	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
118 	int i;
119 
120 	/* tested only on R-Car Gen2+ currently; may work for others */
121 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
122 		return clk_get_rate(priv->clk);
123 
124 	/*
125 	 * We want the bus clock to be as close as possible to, but no
126 	 * greater than, new_clock.  As we can divide by 1 << i for
127 	 * any i in [0, 9] we want the input clock to be as close as
128 	 * possible, but no greater than, new_clock << i.
129 	 */
130 	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
131 		freq = clk_round_rate(priv->clk, new_clock << i);
132 		if (freq > (new_clock << i)) {
133 			/* Too fast; look for a slightly slower option */
134 			freq = clk_round_rate(priv->clk,
135 					      (new_clock << i) / 4 * 3);
136 			if (freq > (new_clock << i))
137 				continue;
138 		}
139 
140 		diff = new_clock - (freq >> i);
141 		if (diff <= diff_min) {
142 			best_freq = freq;
143 			diff_min = diff;
144 		}
145 	}
146 
147 	clk_set_rate(priv->clk, best_freq);
148 
149 	return clk_get_rate(priv->clk);
150 }
151 
152 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
153 				   unsigned int new_clock)
154 {
155 	u32 clk = 0, clock;
156 
157 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
158 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
159 
160 	if (new_clock == 0) {
161 		host->mmc->actual_clock = 0;
162 		goto out;
163 	}
164 
165 	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
166 	clock = host->mmc->actual_clock / 512;
167 
168 	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
169 		clock <<= 1;
170 
171 	/* 1/1 clock is option */
172 	if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
173 		if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
174 			clk |= 0xff;
175 		else
176 			clk &= ~0xff;
177 	}
178 
179 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
180 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
181 		usleep_range(10000, 11000);
182 
183 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
184 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
185 
186 out:
187 	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
188 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
189 		usleep_range(10000, 11000);
190 }
191 
192 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
193 {
194 	struct renesas_sdhi *priv = host_to_priv(host);
195 
196 	clk_disable_unprepare(priv->clk_cd);
197 }
198 
199 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
200 {
201 	struct tmio_mmc_host *host = mmc_priv(mmc);
202 
203 	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
204 		 TMIO_STAT_DAT0);
205 }
206 
207 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
208 						    struct mmc_ios *ios)
209 {
210 	struct tmio_mmc_host *host = mmc_priv(mmc);
211 	struct renesas_sdhi *priv = host_to_priv(host);
212 	struct pinctrl_state *pin_state;
213 	int ret;
214 
215 	switch (ios->signal_voltage) {
216 	case MMC_SIGNAL_VOLTAGE_330:
217 		pin_state = priv->pins_default;
218 		break;
219 	case MMC_SIGNAL_VOLTAGE_180:
220 		pin_state = priv->pins_uhs;
221 		break;
222 	default:
223 		return -EINVAL;
224 	}
225 
226 	/*
227 	 * If anything is missing, assume signal voltage is fixed at
228 	 * 3.3V and succeed/fail accordingly.
229 	 */
230 	if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
231 		return ios->signal_voltage ==
232 			MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
233 
234 	ret = mmc_regulator_set_vqmmc(host->mmc, ios);
235 	if (ret < 0)
236 		return ret;
237 
238 	return pinctrl_select_state(priv->pinctrl, pin_state);
239 }
240 
241 /* SCC registers */
242 #define SH_MOBILE_SDHI_SCC_DTCNTL	0x000
243 #define SH_MOBILE_SDHI_SCC_TAPSET	0x002
244 #define SH_MOBILE_SDHI_SCC_DT2FF	0x004
245 #define SH_MOBILE_SDHI_SCC_CKSEL	0x006
246 #define SH_MOBILE_SDHI_SCC_RVSCNTL	0x008
247 #define SH_MOBILE_SDHI_SCC_RVSREQ	0x00A
248 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
249 #define SH_MOBILE_SDHI_SCC_TMPPORT2	0x00E
250 
251 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
252 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
253 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK	0xff
254 
255 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL		BIT(0)
256 
257 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN	BIT(0)
258 
259 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN	BIT(0)
260 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP	BIT(1)
261 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR	BIT(2)
262 
263 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN	BIT(8)
264 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP	BIT(24)
265 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR	(BIT(8) | BIT(24))
266 
267 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL	BIT(4)
268 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN	BIT(31)
269 
270 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
271 				struct renesas_sdhi *priv, int addr)
272 {
273 	return readl(priv->scc_ctl + (addr << host->bus_shift));
274 }
275 
276 static inline void sd_scc_write32(struct tmio_mmc_host *host,
277 				  struct renesas_sdhi *priv,
278 				  int addr, u32 val)
279 {
280 	writel(val, priv->scc_ctl + (addr << host->bus_shift));
281 }
282 
283 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
284 {
285 	struct renesas_sdhi *priv;
286 
287 	priv = host_to_priv(host);
288 
289 	/* Initialize SCC */
290 	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
291 
292 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
293 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
294 
295 	/* set sampling clock selection range */
296 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
297 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
298 		       0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
299 
300 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
301 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
302 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
303 
304 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
305 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
306 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
307 
308 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
309 
310 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
311 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
312 
313 	/* Read TAPNUM */
314 	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
315 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
316 		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
317 }
318 
319 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
320 {
321 	struct tmio_mmc_host *host = mmc_priv(mmc);
322 	struct renesas_sdhi *priv = host_to_priv(host);
323 	u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
324 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
325 
326 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
327 		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
328 
329 	/* Set HS400 mode */
330 	sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
331 			sd_ctrl_read16(host, CTL_SDIF_MODE));
332 
333 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
334 		       priv->scc_tappos_hs400);
335 
336 	/* Gen3 can't do automatic tap correction with HS400, so disable it */
337 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
338 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
339 			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
340 			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
341 
342 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
343 		       (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
344 			SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
345 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
346 
347 	/* Set the sampling clock selection range of HS400 mode */
348 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
349 		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
350 		       0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
351 
352 	/* Avoid bad TAP */
353 	if (bad_taps & BIT(priv->tap_set)) {
354 		u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
355 
356 		if (bad_taps & BIT(new_tap))
357 			new_tap = (priv->tap_set - 1) % priv->tap_num;
358 
359 		if (bad_taps & BIT(new_tap)) {
360 			new_tap = priv->tap_set;
361 			dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
362 		}
363 
364 		priv->tap_set = new_tap;
365 	}
366 
367 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
368 		       priv->tap_set / (use_4tap ? 2 : 1));
369 
370 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
371 		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
372 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
373 
374 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
375 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
376 }
377 
378 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
379 				   struct renesas_sdhi *priv)
380 {
381 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
382 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
383 
384 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
385 		       ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
386 		       sd_scc_read32(host, priv,
387 				     SH_MOBILE_SDHI_SCC_CKSEL));
388 }
389 
390 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
391 {
392 	struct tmio_mmc_host *host = mmc_priv(mmc);
393 	struct renesas_sdhi *priv = host_to_priv(host);
394 
395 	renesas_sdhi_reset_scc(host, priv);
396 
397 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
398 		       ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
399 		       sd_scc_read32(host, priv,
400 				     SH_MOBILE_SDHI_SCC_DTCNTL));
401 
402 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
403 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
404 }
405 
406 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
407 					  struct renesas_sdhi *priv)
408 {
409 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
410 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
411 
412 	/* Reset HS400 mode */
413 	sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
414 			sd_ctrl_read16(host, CTL_SDIF_MODE));
415 
416 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
417 
418 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
419 		       ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
420 			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
421 			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
422 
423 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
424 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
425 }
426 
427 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
428 {
429 	struct tmio_mmc_host *host = mmc_priv(mmc);
430 
431 	renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
432 	return 0;
433 }
434 
435 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
436 
437 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
438 {
439 	struct renesas_sdhi *priv = host_to_priv(host);
440 	unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
441 	unsigned int taps_size = priv->tap_num * 2, min_tap_row;
442 	unsigned long *bitmap;
443 
444 	priv->doing_tune = false;
445 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
446 
447 	/*
448 	 * When tuning CMD19 is issued twice for each tap, merge the
449 	 * result requiring the tap to be good in both runs before
450 	 * considering it for tuning selection.
451 	 */
452 	for (i = 0; i < taps_size; i++) {
453 		int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
454 
455 		if (!test_bit(i, priv->taps))
456 			clear_bit(i + offset, priv->taps);
457 
458 		if (!test_bit(i, priv->smpcmp))
459 			clear_bit(i + offset, priv->smpcmp);
460 	}
461 
462 	/*
463 	 * If all TAP are OK, the sampling clock position is selected by
464 	 * identifying the change point of data.
465 	 */
466 	if (bitmap_full(priv->taps, taps_size)) {
467 		bitmap = priv->smpcmp;
468 		min_tap_row = 1;
469 	} else {
470 		bitmap = priv->taps;
471 		min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
472 	}
473 
474 	/*
475 	 * Find the longest consecutive run of successful probes. If that
476 	 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
477 	 * center index as the tap, otherwise bail out.
478 	 */
479 	bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
480 		if (re - rs > tap_cnt) {
481 			tap_end = re;
482 			tap_start = rs;
483 			tap_cnt = tap_end - tap_start;
484 		}
485 	}
486 
487 	if (tap_cnt >= min_tap_row)
488 		priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
489 	else
490 		return -EIO;
491 
492 	/* Set SCC */
493 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
494 
495 	/* Enable auto re-tuning */
496 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
497 		       SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
498 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
499 
500 	return 0;
501 }
502 
503 static int renesas_sdhi_execute_tuning(struct tmio_mmc_host *host, u32 opcode)
504 {
505 	struct renesas_sdhi *priv = host_to_priv(host);
506 	int i;
507 
508 	priv->tap_num = renesas_sdhi_init_tuning(host);
509 	if (!priv->tap_num)
510 		return 0; /* Tuning is not supported */
511 
512 	if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
513 		dev_err(&host->pdev->dev,
514 			"Too many taps, please update 'taps' in tmio_mmc_host!\n");
515 		return -EINVAL;
516 	}
517 
518 	priv->doing_tune = true;
519 	bitmap_zero(priv->taps, priv->tap_num * 2);
520 	bitmap_zero(priv->smpcmp, priv->tap_num * 2);
521 
522 	/* Issue CMD19 twice for each tap */
523 	for (i = 0; i < 2 * priv->tap_num; i++) {
524 		/* Set sampling clock position */
525 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
526 
527 		if (mmc_send_tuning(host->mmc, opcode, NULL) == 0)
528 			set_bit(i, priv->taps);
529 
530 		if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
531 			set_bit(i, priv->smpcmp);
532 	}
533 
534 	return renesas_sdhi_select_tuning(host);
535 }
536 
537 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
538 {
539 	struct renesas_sdhi *priv = host_to_priv(host);
540 	unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
541 	u32 val;
542 
543 	val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
544 	if (!val)
545 		return false;
546 
547 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
548 
549 	/* Change TAP position according to correction status */
550 	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
551 	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
552 		u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
553 		/*
554 		 * With HS400, the DAT signal is based on DS, not CLK.
555 		 * Therefore, use only CMD status.
556 		 */
557 		u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
558 					   SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
559 		if (!smpcmp) {
560 			return false;	/* no error in CMD signal */
561 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
562 			new_tap++;
563 			error_tap--;
564 		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
565 			new_tap--;
566 			error_tap++;
567 		} else {
568 			return true;	/* need retune */
569 		}
570 
571 		/*
572 		 * When new_tap is a bad tap, we cannot change. Then, we compare
573 		 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
574 		 * we can at least retune.
575 		 */
576 		if (bad_taps & BIT(new_tap % priv->tap_num))
577 			return test_bit(error_tap % priv->tap_num, priv->smpcmp);
578 	} else {
579 		if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
580 			return true;    /* need retune */
581 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
582 			new_tap++;
583 		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
584 			new_tap--;
585 		else
586 			return false;
587 	}
588 
589 	priv->tap_set = (new_tap % priv->tap_num);
590 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
591 		       priv->tap_set / (use_4tap ? 2 : 1));
592 
593 	return false;
594 }
595 
596 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
597 {
598 	struct renesas_sdhi *priv = host_to_priv(host);
599 
600 	/* Check SCC error */
601 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
602 	    SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
603 		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
604 		return true;
605 	}
606 
607 	return false;
608 }
609 
610 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
611 {
612 	struct renesas_sdhi *priv = host_to_priv(host);
613 	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
614 
615 	/*
616 	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
617 	 * any retuning would still result in the same 4 taps being used.
618 	 */
619 	if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
620 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
621 	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
622 		return false;
623 
624 	if (mmc_doing_retune(host->mmc) || priv->doing_tune)
625 		return false;
626 
627 	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
628 	    SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
629 		return renesas_sdhi_auto_correction(host);
630 
631 	return renesas_sdhi_manual_correction(host, use_4tap);
632 }
633 
634 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
635 {
636 	struct renesas_sdhi *priv;
637 
638 	priv = host_to_priv(host);
639 
640 	renesas_sdhi_reset_scc(host, priv);
641 	renesas_sdhi_reset_hs400_mode(host, priv);
642 
643 	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
644 			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
645 
646 	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
647 		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
648 		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
649 
650 	if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
651 		sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
652 					     TMIO_MASK_INIT_RCAR2);
653 }
654 
655 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
656 {
657 	int timeout = 1000;
658 	/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
659 	u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
660 
661 	while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
662 			      & bit) == wait_state)
663 		udelay(1);
664 
665 	if (!timeout) {
666 		dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
667 		return -EBUSY;
668 	}
669 
670 	return 0;
671 }
672 
673 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
674 {
675 	u32 bit = TMIO_STAT_SCLKDIVEN;
676 
677 	switch (addr) {
678 	case CTL_SD_CMD:
679 	case CTL_STOP_INTERNAL_ACTION:
680 	case CTL_XFER_BLK_COUNT:
681 	case CTL_SD_XFER_LEN:
682 	case CTL_SD_MEM_CARD_OPT:
683 	case CTL_TRANSACTION_CTL:
684 	case CTL_DMA_ENABLE:
685 	case HOST_MODE:
686 		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
687 			bit = TMIO_STAT_CMD_BUSY;
688 		/* fallthrough */
689 	case CTL_SD_CARD_CLK_CTL:
690 		return renesas_sdhi_wait_idle(host, bit);
691 	}
692 
693 	return 0;
694 }
695 
696 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
697 				       unsigned int direction, int blk_size)
698 {
699 	/*
700 	 * In Renesas controllers, when performing a
701 	 * multiple block read of one or two blocks,
702 	 * depending on the timing with which the
703 	 * response register is read, the response
704 	 * value may not be read properly.
705 	 * Use single block read for this HW bug
706 	 */
707 	if ((direction == MMC_DATA_READ) &&
708 	    blk_size == 2)
709 		return 1;
710 
711 	return blk_size;
712 }
713 
714 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
715 {
716 	/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
717 	int width = (host->bus_shift == 2) ? 64 : 32;
718 
719 	sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
720 	renesas_sdhi_sdbuf_width(host, enable ? width : 16);
721 }
722 
723 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
724 	.hs400_disabled = true,
725 	.hs400_4taps = true,
726 };
727 
728 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
729 	.hs400_4taps = true,
730 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
731 };
732 
733 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
734 	.hs400_disabled = true,
735 };
736 
737 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
738 	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
739 };
740 
741 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
742 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
743 };
744 
745 /*
746  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
747  * So, we want to treat them equally and only have a match for ES1.2 to enforce
748  * this if there ever will be a way to distinguish ES1.2.
749  */
750 static const struct soc_device_attribute sdhi_quirks_match[]  = {
751 	{ .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
752 	{ .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
753 	{ .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
754 	{ .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
755 	{ .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
756 	{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_4tap },
757 	{ .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 },
758 	{ .soc_id = "r8a77965", .data = &sdhi_quirks_bad_taps2367 },
759 	{ .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
760 	{ /* Sentinel. */ },
761 };
762 
763 int renesas_sdhi_probe(struct platform_device *pdev,
764 		       const struct tmio_mmc_dma_ops *dma_ops)
765 {
766 	struct tmio_mmc_data *mmd = pdev->dev.platform_data;
767 	const struct renesas_sdhi_quirks *quirks = NULL;
768 	const struct renesas_sdhi_of_data *of_data;
769 	const struct soc_device_attribute *attr;
770 	struct tmio_mmc_data *mmc_data;
771 	struct tmio_mmc_dma *dma_priv;
772 	struct tmio_mmc_host *host;
773 	struct renesas_sdhi *priv;
774 	int num_irqs, irq, ret, i;
775 	struct resource *res;
776 	u16 ver;
777 
778 	of_data = of_device_get_match_data(&pdev->dev);
779 
780 	attr = soc_device_match(sdhi_quirks_match);
781 	if (attr)
782 		quirks = attr->data;
783 
784 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 	if (!res)
786 		return -EINVAL;
787 
788 	priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
789 			    GFP_KERNEL);
790 	if (!priv)
791 		return -ENOMEM;
792 
793 	priv->quirks = quirks;
794 	mmc_data = &priv->mmc_data;
795 	dma_priv = &priv->dma_priv;
796 
797 	priv->clk = devm_clk_get(&pdev->dev, NULL);
798 	if (IS_ERR(priv->clk)) {
799 		ret = PTR_ERR(priv->clk);
800 		dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
801 		return ret;
802 	}
803 
804 	/*
805 	 * Some controllers provide a 2nd clock just to run the internal card
806 	 * detection logic. Unfortunately, the existing driver architecture does
807 	 * not support a separation of clocks for runtime PM usage. When
808 	 * native hotplug is used, the tmio driver assumes that the core
809 	 * must continue to run for card detect to stay active, so we cannot
810 	 * disable it.
811 	 * Additionally, it is prohibited to supply a clock to the core but not
812 	 * to the card detect circuit. That leaves us with if separate clocks
813 	 * are presented, we must treat them both as virtually 1 clock.
814 	 */
815 	priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
816 	if (IS_ERR(priv->clk_cd))
817 		priv->clk_cd = NULL;
818 
819 	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
820 	if (!IS_ERR(priv->pinctrl)) {
821 		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
822 						PINCTRL_STATE_DEFAULT);
823 		priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
824 						"state_uhs");
825 	}
826 
827 	host = tmio_mmc_host_alloc(pdev, mmc_data);
828 	if (IS_ERR(host))
829 		return PTR_ERR(host);
830 
831 	if (of_data) {
832 		mmc_data->flags |= of_data->tmio_flags;
833 		mmc_data->ocr_mask = of_data->tmio_ocr_mask;
834 		mmc_data->capabilities |= of_data->capabilities;
835 		mmc_data->capabilities2 |= of_data->capabilities2;
836 		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
837 		mmc_data->max_blk_count = of_data->max_blk_count;
838 		mmc_data->max_segs = of_data->max_segs;
839 		dma_priv->dma_buswidth = of_data->dma_buswidth;
840 		host->bus_shift = of_data->bus_shift;
841 	}
842 
843 	host->write16_hook	= renesas_sdhi_write16_hook;
844 	host->clk_enable	= renesas_sdhi_clk_enable;
845 	host->clk_disable	= renesas_sdhi_clk_disable;
846 	host->set_clock		= renesas_sdhi_set_clock;
847 	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
848 	host->dma_ops		= dma_ops;
849 
850 	if (quirks && quirks->hs400_disabled)
851 		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
852 
853 	/* For some SoC, we disable internal WP. GPIO may override this */
854 	if (mmc_can_gpio_ro(host->mmc))
855 		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
856 
857 	/* SDR speeds are only available on Gen2+ */
858 	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
859 		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
860 		host->ops.card_busy = renesas_sdhi_card_busy;
861 		host->ops.start_signal_voltage_switch =
862 			renesas_sdhi_start_signal_voltage_switch;
863 		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
864 
865 		/* SDR and HS200/400 registers requires HW reset */
866 		if (of_data && of_data->scc_offset) {
867 			priv->scc_ctl = host->ctl + of_data->scc_offset;
868 			host->mmc->caps |= MMC_CAP_HW_RESET;
869 			host->hw_reset = renesas_sdhi_hw_reset;
870 		}
871 	}
872 
873 	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
874 	if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
875 		host->bus_shift = 1;
876 
877 	if (mmd)
878 		*mmc_data = *mmd;
879 
880 	dma_priv->filter = shdma_chan_filter;
881 	dma_priv->enable = renesas_sdhi_enable_dma;
882 
883 	mmc_data->alignment_shift = 1; /* 2-byte alignment */
884 	mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
885 
886 	/*
887 	 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
888 	 * bus width mode.
889 	 */
890 	mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
891 
892 	/*
893 	 * All SDHI blocks support SDIO IRQ signalling.
894 	 */
895 	mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
896 
897 	/* All SDHI have CMD12 control bit */
898 	mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
899 
900 	/* All SDHI have SDIO status bits which must be 1 */
901 	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
902 
903 	dev_pm_domain_start(&pdev->dev);
904 
905 	ret = renesas_sdhi_clk_enable(host);
906 	if (ret)
907 		goto efree;
908 
909 	ver = sd_ctrl_read16(host, CTL_VERSION);
910 	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
911 	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
912 		mmc_data->max_blk_count = U16_MAX;
913 
914 	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
915 	if (ver == SDHI_VER_GEN2_SDR50)
916 		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
917 
918 	ret = tmio_mmc_host_probe(host);
919 	if (ret < 0)
920 		goto edisclk;
921 
922 	/* Enable tuning iff we have an SCC and a supported mode */
923 	if (of_data && of_data->scc_offset &&
924 	    (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
925 	     host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
926 				 MMC_CAP2_HS400_1_8V))) {
927 		const struct renesas_sdhi_scc *taps = of_data->taps;
928 		bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
929 		bool hit = false;
930 
931 		for (i = 0; i < of_data->taps_num; i++) {
932 			if (taps[i].clk_rate == 0 ||
933 			    taps[i].clk_rate == host->mmc->f_max) {
934 				priv->scc_tappos = taps->tap;
935 				priv->scc_tappos_hs400 = use_4tap ?
936 							 taps->tap_hs400_4tap :
937 							 taps->tap;
938 				hit = true;
939 				break;
940 			}
941 		}
942 
943 		if (!hit)
944 			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
945 
946 		host->execute_tuning = renesas_sdhi_execute_tuning;
947 		host->check_retune = renesas_sdhi_check_scc_error;
948 		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
949 		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
950 		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
951 	}
952 
953 	num_irqs = platform_irq_count(pdev);
954 	if (num_irqs < 0) {
955 		ret = num_irqs;
956 		goto eirq;
957 	}
958 
959 	/* There must be at least one IRQ source */
960 	if (!num_irqs) {
961 		ret = -ENXIO;
962 		goto eirq;
963 	}
964 
965 	for (i = 0; i < num_irqs; i++) {
966 		irq = platform_get_irq(pdev, i);
967 		if (irq < 0) {
968 			ret = irq;
969 			goto eirq;
970 		}
971 
972 		ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
973 				       dev_name(&pdev->dev), host);
974 		if (ret)
975 			goto eirq;
976 	}
977 
978 	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
979 		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
980 
981 	return ret;
982 
983 eirq:
984 	tmio_mmc_host_remove(host);
985 edisclk:
986 	renesas_sdhi_clk_disable(host);
987 efree:
988 	tmio_mmc_host_free(host);
989 
990 	return ret;
991 }
992 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
993 
994 int renesas_sdhi_remove(struct platform_device *pdev)
995 {
996 	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
997 
998 	tmio_mmc_host_remove(host);
999 	renesas_sdhi_clk_disable(host);
1000 
1001 	return 0;
1002 }
1003 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1004 
1005 MODULE_LICENSE("GPL v2");
1006