1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/kernel.h> 24 #include <linux/mfd/tmio.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/pinctrl-state.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_domain.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/sh_dma.h> 36 #include <linux/slab.h> 37 #include <linux/sys_soc.h> 38 39 #include "renesas_sdhi.h" 40 #include "tmio_mmc.h" 41 42 #define CTL_HOST_MODE 0xe4 43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 45 #define HOST_MODE_GEN3_WMODE BIT(0) 46 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 47 48 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 49 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 50 #define HOST_MODE_GEN3_64BIT 0 51 52 #define CTL_SDIF_MODE 0xe6 53 #define SDIF_MODE_HS400 BIT(0) 54 55 #define SDHI_VER_GEN2_SDR50 0x490c 56 #define SDHI_VER_RZ_A1 0x820b 57 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 58 #define SDHI_VER_GEN2_SDR104 0xcb0d 59 #define SDHI_VER_GEN3_SD 0xcc10 60 #define SDHI_VER_GEN3_SDMMC 0xcd10 61 62 #define SDHI_GEN3_MMC0_ADDR 0xee140000 63 64 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 65 { 66 u32 val; 67 68 /* 69 * see also 70 * renesas_sdhi_of_data :: dma_buswidth 71 */ 72 switch (sd_ctrl_read16(host, CTL_VERSION)) { 73 case SDHI_VER_GEN2_SDR50: 74 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 75 break; 76 case SDHI_VER_GEN2_SDR104: 77 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 78 break; 79 case SDHI_VER_GEN3_SD: 80 case SDHI_VER_GEN3_SDMMC: 81 if (width == 64) 82 val = HOST_MODE_GEN3_64BIT; 83 else if (width == 32) 84 val = HOST_MODE_GEN3_32BIT; 85 else 86 val = HOST_MODE_GEN3_16BIT; 87 break; 88 default: 89 /* nothing to do */ 90 return; 91 } 92 93 sd_ctrl_write16(host, CTL_HOST_MODE, val); 94 } 95 96 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 97 { 98 struct mmc_host *mmc = host->mmc; 99 struct renesas_sdhi *priv = host_to_priv(host); 100 int ret; 101 102 ret = clk_prepare_enable(priv->clk_cd); 103 if (ret < 0) 104 return ret; 105 106 /* 107 * The clock driver may not know what maximum frequency 108 * actually works, so it should be set with the max-frequency 109 * property which will already have been read to f_max. If it 110 * was missing, assume the current frequency is the maximum. 111 */ 112 if (!mmc->f_max) 113 mmc->f_max = clk_get_rate(priv->clk); 114 115 /* 116 * Minimum frequency is the minimum input clock frequency 117 * divided by our maximum divider. 118 */ 119 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 120 121 /* enable 16bit data access on SDBUF as default */ 122 renesas_sdhi_sdbuf_width(host, 16); 123 124 return 0; 125 } 126 127 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 128 unsigned int new_clock) 129 { 130 struct renesas_sdhi *priv = host_to_priv(host); 131 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 132 int i; 133 134 /* 135 * We simply return the current rate if a) we are not on a R-Car Gen2+ 136 * SoC (may work for others, but untested) or b) if the SCC needs its 137 * clock during tuning, so we don't change the external clock setup. 138 */ 139 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 140 return clk_get_rate(priv->clk); 141 142 /* 143 * We want the bus clock to be as close as possible to, but no 144 * greater than, new_clock. As we can divide by 1 << i for 145 * any i in [0, 9] we want the input clock to be as close as 146 * possible, but no greater than, new_clock << i. 147 */ 148 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 149 freq = clk_round_rate(priv->clk, new_clock << i); 150 if (freq > (new_clock << i)) { 151 /* Too fast; look for a slightly slower option */ 152 freq = clk_round_rate(priv->clk, 153 (new_clock << i) / 4 * 3); 154 if (freq > (new_clock << i)) 155 continue; 156 } 157 158 diff = new_clock - (freq >> i); 159 if (diff <= diff_min) { 160 best_freq = freq; 161 diff_min = diff; 162 } 163 } 164 165 clk_set_rate(priv->clk, best_freq); 166 167 return clk_get_rate(priv->clk); 168 } 169 170 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 171 unsigned int new_clock) 172 { 173 u32 clk = 0, clock; 174 175 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 176 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 177 178 if (new_clock == 0) { 179 host->mmc->actual_clock = 0; 180 goto out; 181 } 182 183 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 184 clock = host->mmc->actual_clock / 512; 185 186 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 187 clock <<= 1; 188 189 /* 1/1 clock is option */ 190 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 191 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 192 clk |= 0xff; 193 else 194 clk &= ~0xff; 195 } 196 197 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 198 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 199 usleep_range(10000, 11000); 200 201 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 202 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 203 204 out: 205 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 206 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 207 usleep_range(10000, 11000); 208 } 209 210 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 211 { 212 struct renesas_sdhi *priv = host_to_priv(host); 213 214 clk_disable_unprepare(priv->clk_cd); 215 } 216 217 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 218 { 219 struct tmio_mmc_host *host = mmc_priv(mmc); 220 221 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 222 TMIO_STAT_DAT0); 223 } 224 225 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 226 struct mmc_ios *ios) 227 { 228 struct tmio_mmc_host *host = mmc_priv(mmc); 229 struct renesas_sdhi *priv = host_to_priv(host); 230 struct pinctrl_state *pin_state; 231 int ret; 232 233 switch (ios->signal_voltage) { 234 case MMC_SIGNAL_VOLTAGE_330: 235 pin_state = priv->pins_default; 236 break; 237 case MMC_SIGNAL_VOLTAGE_180: 238 pin_state = priv->pins_uhs; 239 break; 240 default: 241 return -EINVAL; 242 } 243 244 /* 245 * If anything is missing, assume signal voltage is fixed at 246 * 3.3V and succeed/fail accordingly. 247 */ 248 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 249 return ios->signal_voltage == 250 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 251 252 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 253 if (ret < 0) 254 return ret; 255 256 return pinctrl_select_state(priv->pinctrl, pin_state); 257 } 258 259 /* SCC registers */ 260 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 261 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 262 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 263 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 264 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 265 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 266 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 267 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 268 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 269 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 270 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 271 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 272 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 273 274 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 275 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 276 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 277 278 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 279 280 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 281 282 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 283 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 284 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 285 286 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 287 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 288 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 289 290 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 291 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 292 293 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 294 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 295 296 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 297 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 298 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 299 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 300 301 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 302 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 303 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 304 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 305 306 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 307 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 308 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 309 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 310 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 311 }; 312 313 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 314 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 315 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 316 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 317 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 318 }; 319 320 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 321 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 322 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 323 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 324 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 325 }; 326 327 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 328 struct renesas_sdhi *priv, int addr) 329 { 330 return readl(priv->scc_ctl + (addr << host->bus_shift)); 331 } 332 333 static inline void sd_scc_write32(struct tmio_mmc_host *host, 334 struct renesas_sdhi *priv, 335 int addr, u32 val) 336 { 337 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 338 } 339 340 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 341 { 342 struct renesas_sdhi *priv; 343 344 priv = host_to_priv(host); 345 346 /* Initialize SCC */ 347 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 348 349 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 350 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 351 352 /* set sampling clock selection range */ 353 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 354 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 355 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 356 357 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 358 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 359 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 360 361 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 362 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 363 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 364 365 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 366 367 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 368 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 369 370 /* Read TAPNUM */ 371 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 372 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 373 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 374 } 375 376 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 377 { 378 struct tmio_mmc_host *host = mmc_priv(mmc); 379 struct renesas_sdhi *priv = host_to_priv(host); 380 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 381 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 382 383 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 384 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 385 386 /* Set HS400 mode */ 387 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 388 sd_ctrl_read16(host, CTL_SDIF_MODE)); 389 390 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 391 priv->scc_tappos_hs400); 392 393 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 394 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 395 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 396 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 397 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 398 399 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 400 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 401 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 402 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 403 404 /* Set the sampling clock selection range of HS400 mode */ 405 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 406 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 407 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 408 409 /* Avoid bad TAP */ 410 if (bad_taps & BIT(priv->tap_set)) { 411 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 412 413 if (bad_taps & BIT(new_tap)) 414 new_tap = (priv->tap_set - 1) % priv->tap_num; 415 416 if (bad_taps & BIT(new_tap)) { 417 new_tap = priv->tap_set; 418 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 419 } 420 421 priv->tap_set = new_tap; 422 } 423 424 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 425 priv->tap_set / (use_4tap ? 2 : 1)); 426 427 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 428 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 429 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 430 431 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 432 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 433 434 if (priv->adjust_hs400_calib_table) 435 priv->needs_adjust_hs400 = true; 436 } 437 438 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 439 { 440 struct tmio_mmc_host *host = mmc_priv(mmc); 441 struct renesas_sdhi *priv = host_to_priv(host); 442 443 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 444 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 445 446 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 447 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 448 sd_scc_read32(host, priv, 449 SH_MOBILE_SDHI_SCC_CKSEL)); 450 451 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 452 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 453 sd_scc_read32(host, priv, 454 SH_MOBILE_SDHI_SCC_DTCNTL)); 455 456 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 457 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 458 } 459 460 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 461 struct renesas_sdhi *priv, u32 addr) 462 { 463 /* read mode */ 464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 465 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 466 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 467 468 /* access start and stop */ 469 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 470 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 471 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 472 473 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 474 } 475 476 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 477 struct renesas_sdhi *priv, u32 addr, u32 val) 478 { 479 /* write mode */ 480 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 481 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 482 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 483 484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 485 486 /* access start and stop */ 487 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 488 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 489 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 490 } 491 492 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 493 { 494 struct renesas_sdhi *priv = host_to_priv(host); 495 u32 calib_code; 496 497 /* disable write protect */ 498 sd_scc_tmpport_write32(host, priv, 0x00, 499 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 500 /* read calibration code and adjust */ 501 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 502 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 503 504 sd_scc_tmpport_write32(host, priv, 0x22, 505 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 506 priv->adjust_hs400_calib_table[calib_code]); 507 508 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 509 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 510 511 /* adjustment done, clear flag */ 512 priv->needs_adjust_hs400 = false; 513 } 514 515 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 516 { 517 struct renesas_sdhi *priv = host_to_priv(host); 518 519 /* disable write protect */ 520 sd_scc_tmpport_write32(host, priv, 0x00, 521 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 522 /* disable manual calibration */ 523 sd_scc_tmpport_write32(host, priv, 0x22, 0); 524 /* clear offset value of TMPPORT3 */ 525 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 526 } 527 528 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 529 struct renesas_sdhi *priv) 530 { 531 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 532 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 533 534 /* Reset HS400 mode */ 535 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 536 sd_ctrl_read16(host, CTL_SDIF_MODE)); 537 538 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 539 540 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 541 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 542 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 543 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 544 545 if (priv->adjust_hs400_calib_table) 546 renesas_sdhi_adjust_hs400_mode_disable(host); 547 548 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 549 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 550 } 551 552 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 553 { 554 struct tmio_mmc_host *host = mmc_priv(mmc); 555 556 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 557 return 0; 558 } 559 560 /* only populated for TMIO_MMC_MIN_RCAR2 */ 561 static void renesas_sdhi_reset(struct tmio_mmc_host *host) 562 { 563 struct renesas_sdhi *priv = host_to_priv(host); 564 565 if (priv->scc_ctl) { 566 renesas_sdhi_disable_scc(host->mmc); 567 renesas_sdhi_reset_hs400_mode(host, priv); 568 priv->needs_adjust_hs400 = false; 569 570 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 571 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 572 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 573 } 574 575 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_INIT_RCAR2); 576 } 577 578 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 579 580 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 581 { 582 struct renesas_sdhi *priv = host_to_priv(host); 583 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 584 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 585 unsigned long *bitmap; 586 587 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 588 589 /* 590 * When tuning CMD19 is issued twice for each tap, merge the 591 * result requiring the tap to be good in both runs before 592 * considering it for tuning selection. 593 */ 594 for (i = 0; i < taps_size; i++) { 595 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 596 597 if (!test_bit(i, priv->taps)) 598 clear_bit(i + offset, priv->taps); 599 600 if (!test_bit(i, priv->smpcmp)) 601 clear_bit(i + offset, priv->smpcmp); 602 } 603 604 /* 605 * If all TAP are OK, the sampling clock position is selected by 606 * identifying the change point of data. 607 */ 608 if (bitmap_full(priv->taps, taps_size)) { 609 bitmap = priv->smpcmp; 610 min_tap_row = 1; 611 } else { 612 bitmap = priv->taps; 613 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 614 } 615 616 /* 617 * Find the longest consecutive run of successful probes. If that 618 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 619 * center index as the tap, otherwise bail out. 620 */ 621 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 622 if (re - rs > tap_cnt) { 623 tap_end = re; 624 tap_start = rs; 625 tap_cnt = tap_end - tap_start; 626 } 627 } 628 629 if (tap_cnt >= min_tap_row) 630 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 631 else 632 return -EIO; 633 634 /* Set SCC */ 635 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 636 637 /* Enable auto re-tuning */ 638 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 639 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 640 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 641 642 return 0; 643 } 644 645 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 646 { 647 struct tmio_mmc_host *host = mmc_priv(mmc); 648 struct renesas_sdhi *priv = host_to_priv(host); 649 int i, ret; 650 651 priv->tap_num = renesas_sdhi_init_tuning(host); 652 if (!priv->tap_num) 653 return 0; /* Tuning is not supported */ 654 655 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 656 dev_err(&host->pdev->dev, 657 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 658 return -EINVAL; 659 } 660 661 bitmap_zero(priv->taps, priv->tap_num * 2); 662 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 663 664 /* Issue CMD19 twice for each tap */ 665 for (i = 0; i < 2 * priv->tap_num; i++) { 666 /* Set sampling clock position */ 667 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 668 669 if (mmc_send_tuning(mmc, opcode, NULL) == 0) 670 set_bit(i, priv->taps); 671 672 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 673 set_bit(i, priv->smpcmp); 674 } 675 676 ret = renesas_sdhi_select_tuning(host); 677 if (ret < 0) 678 renesas_sdhi_reset(host); 679 return ret; 680 } 681 682 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 683 { 684 struct renesas_sdhi *priv = host_to_priv(host); 685 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 686 u32 val; 687 688 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 689 if (!val) 690 return false; 691 692 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 693 694 /* Change TAP position according to correction status */ 695 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 696 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 697 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 698 /* 699 * With HS400, the DAT signal is based on DS, not CLK. 700 * Therefore, use only CMD status. 701 */ 702 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 703 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 704 if (!smpcmp) { 705 return false; /* no error in CMD signal */ 706 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 707 new_tap++; 708 error_tap--; 709 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 710 new_tap--; 711 error_tap++; 712 } else { 713 return true; /* need retune */ 714 } 715 716 /* 717 * When new_tap is a bad tap, we cannot change. Then, we compare 718 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 719 * we can at least retune. 720 */ 721 if (bad_taps & BIT(new_tap % priv->tap_num)) 722 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 723 } else { 724 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 725 return true; /* need retune */ 726 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 727 new_tap++; 728 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 729 new_tap--; 730 else 731 return false; 732 } 733 734 priv->tap_set = (new_tap % priv->tap_num); 735 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 736 priv->tap_set / (use_4tap ? 2 : 1)); 737 738 return false; 739 } 740 741 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 742 { 743 struct renesas_sdhi *priv = host_to_priv(host); 744 745 /* Check SCC error */ 746 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 747 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 748 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 749 return true; 750 } 751 752 return false; 753 } 754 755 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 756 { 757 struct renesas_sdhi *priv = host_to_priv(host); 758 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 759 760 /* 761 * Skip checking SCC errors when running on 4 taps in HS400 mode as 762 * any retuning would still result in the same 4 taps being used. 763 */ 764 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 765 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 766 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 767 return false; 768 769 if (mmc_doing_tune(host->mmc)) 770 return false; 771 772 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 773 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 774 return renesas_sdhi_auto_correction(host); 775 776 return renesas_sdhi_manual_correction(host, use_4tap); 777 } 778 779 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 780 { 781 int timeout = 1000; 782 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 783 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 784 785 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 786 & bit) == wait_state) 787 udelay(1); 788 789 if (!timeout) { 790 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 791 return -EBUSY; 792 } 793 794 return 0; 795 } 796 797 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 798 { 799 u32 bit = TMIO_STAT_SCLKDIVEN; 800 801 switch (addr) { 802 case CTL_SD_CMD: 803 case CTL_STOP_INTERNAL_ACTION: 804 case CTL_XFER_BLK_COUNT: 805 case CTL_SD_XFER_LEN: 806 case CTL_SD_MEM_CARD_OPT: 807 case CTL_TRANSACTION_CTL: 808 case CTL_DMA_ENABLE: 809 case CTL_HOST_MODE: 810 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 811 bit = TMIO_STAT_CMD_BUSY; 812 fallthrough; 813 case CTL_SD_CARD_CLK_CTL: 814 return renesas_sdhi_wait_idle(host, bit); 815 } 816 817 return 0; 818 } 819 820 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 821 unsigned int direction, int blk_size) 822 { 823 /* 824 * In Renesas controllers, when performing a 825 * multiple block read of one or two blocks, 826 * depending on the timing with which the 827 * response register is read, the response 828 * value may not be read properly. 829 * Use single block read for this HW bug 830 */ 831 if ((direction == MMC_DATA_READ) && 832 blk_size == 2) 833 return 1; 834 835 return blk_size; 836 } 837 838 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 839 { 840 struct renesas_sdhi *priv = host_to_priv(host); 841 842 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 843 renesas_sdhi_adjust_hs400_mode_enable(host); 844 } 845 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 846 { 847 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 848 int width = (host->bus_shift == 2) ? 64 : 32; 849 850 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 851 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 852 } 853 854 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 855 .hs400_disabled = true, 856 .hs400_4taps = true, 857 }; 858 859 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 860 .hs400_4taps = true, 861 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 862 }; 863 864 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 865 .hs400_disabled = true, 866 }; 867 868 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 869 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 870 }; 871 872 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 873 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 874 }; 875 876 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 877 .hs400_4taps = true, 878 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 879 .hs400_calib_table = r8a7796_es13_calib_table, 880 }; 881 882 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 883 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 884 .hs400_calib_table = r8a77965_calib_table, 885 }; 886 887 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 888 .hs400_calib_table = r8a77990_calib_table, 889 }; 890 891 /* 892 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 893 * So, we want to treat them equally and only have a match for ES1.2 to enforce 894 * this if there ever will be a way to distinguish ES1.2. 895 */ 896 static const struct soc_device_attribute sdhi_quirks_match[] = { 897 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 898 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 899 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 900 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 }, 901 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 902 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 903 { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 }, 904 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 }, 905 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 906 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 }, 907 { /* Sentinel. */ }, 908 }; 909 910 int renesas_sdhi_probe(struct platform_device *pdev, 911 const struct tmio_mmc_dma_ops *dma_ops) 912 { 913 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 914 const struct renesas_sdhi_quirks *quirks = NULL; 915 const struct renesas_sdhi_of_data *of_data; 916 const struct soc_device_attribute *attr; 917 struct tmio_mmc_data *mmc_data; 918 struct tmio_mmc_dma *dma_priv; 919 struct tmio_mmc_host *host; 920 struct renesas_sdhi *priv; 921 int num_irqs, irq, ret, i; 922 struct resource *res; 923 u16 ver; 924 925 of_data = of_device_get_match_data(&pdev->dev); 926 927 attr = soc_device_match(sdhi_quirks_match); 928 if (attr) 929 quirks = attr->data; 930 931 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 932 if (!res) 933 return -EINVAL; 934 935 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 936 GFP_KERNEL); 937 if (!priv) 938 return -ENOMEM; 939 940 priv->quirks = quirks; 941 mmc_data = &priv->mmc_data; 942 dma_priv = &priv->dma_priv; 943 944 priv->clk = devm_clk_get(&pdev->dev, NULL); 945 if (IS_ERR(priv->clk)) { 946 ret = PTR_ERR(priv->clk); 947 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 948 return ret; 949 } 950 951 /* 952 * Some controllers provide a 2nd clock just to run the internal card 953 * detection logic. Unfortunately, the existing driver architecture does 954 * not support a separation of clocks for runtime PM usage. When 955 * native hotplug is used, the tmio driver assumes that the core 956 * must continue to run for card detect to stay active, so we cannot 957 * disable it. 958 * Additionally, it is prohibited to supply a clock to the core but not 959 * to the card detect circuit. That leaves us with if separate clocks 960 * are presented, we must treat them both as virtually 1 clock. 961 */ 962 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 963 if (IS_ERR(priv->clk_cd)) 964 priv->clk_cd = NULL; 965 966 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 967 if (!IS_ERR(priv->pinctrl)) { 968 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 969 PINCTRL_STATE_DEFAULT); 970 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 971 "state_uhs"); 972 } 973 974 host = tmio_mmc_host_alloc(pdev, mmc_data); 975 if (IS_ERR(host)) 976 return PTR_ERR(host); 977 978 if (of_data) { 979 mmc_data->flags |= of_data->tmio_flags; 980 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 981 mmc_data->capabilities |= of_data->capabilities; 982 mmc_data->capabilities2 |= of_data->capabilities2; 983 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 984 mmc_data->max_blk_count = of_data->max_blk_count; 985 mmc_data->max_segs = of_data->max_segs; 986 dma_priv->dma_buswidth = of_data->dma_buswidth; 987 host->bus_shift = of_data->bus_shift; 988 } 989 990 host->write16_hook = renesas_sdhi_write16_hook; 991 host->clk_enable = renesas_sdhi_clk_enable; 992 host->clk_disable = renesas_sdhi_clk_disable; 993 host->set_clock = renesas_sdhi_set_clock; 994 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 995 host->dma_ops = dma_ops; 996 997 if (quirks && quirks->hs400_disabled) 998 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 999 1000 /* For some SoC, we disable internal WP. GPIO may override this */ 1001 if (mmc_can_gpio_ro(host->mmc)) 1002 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1003 1004 /* SDR speeds are only available on Gen2+ */ 1005 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1006 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1007 host->ops.card_busy = renesas_sdhi_card_busy; 1008 host->ops.start_signal_voltage_switch = 1009 renesas_sdhi_start_signal_voltage_switch; 1010 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1011 host->reset = renesas_sdhi_reset; 1012 } 1013 1014 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1015 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1016 host->bus_shift = 1; 1017 1018 if (mmd) 1019 *mmc_data = *mmd; 1020 1021 dma_priv->filter = shdma_chan_filter; 1022 dma_priv->enable = renesas_sdhi_enable_dma; 1023 1024 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1025 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1026 1027 /* 1028 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1029 * bus width mode. 1030 */ 1031 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1032 1033 /* 1034 * All SDHI blocks support SDIO IRQ signalling. 1035 */ 1036 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1037 1038 /* All SDHI have CMD12 control bit */ 1039 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1040 1041 /* All SDHI have SDIO status bits which must be 1 */ 1042 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1043 1044 /* All SDHI support HW busy detection */ 1045 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1046 1047 dev_pm_domain_start(&pdev->dev); 1048 1049 ret = renesas_sdhi_clk_enable(host); 1050 if (ret) 1051 goto efree; 1052 1053 ver = sd_ctrl_read16(host, CTL_VERSION); 1054 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1055 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1056 mmc_data->max_blk_count = U16_MAX; 1057 1058 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1059 if (ver == SDHI_VER_GEN2_SDR50) 1060 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1061 1062 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1063 host->fixup_request = renesas_sdhi_fixup_request; 1064 priv->adjust_hs400_calib_table = *( 1065 res->start == SDHI_GEN3_MMC0_ADDR ? 1066 quirks->hs400_calib_table : 1067 quirks->hs400_calib_table + 1); 1068 } 1069 1070 /* Enable tuning iff we have an SCC and a supported mode */ 1071 if (of_data && of_data->scc_offset && 1072 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1073 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1074 MMC_CAP2_HS400_1_8V))) { 1075 const struct renesas_sdhi_scc *taps = of_data->taps; 1076 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1077 bool hit = false; 1078 1079 for (i = 0; i < of_data->taps_num; i++) { 1080 if (taps[i].clk_rate == 0 || 1081 taps[i].clk_rate == host->mmc->f_max) { 1082 priv->scc_tappos = taps->tap; 1083 priv->scc_tappos_hs400 = use_4tap ? 1084 taps->tap_hs400_4tap : 1085 taps->tap; 1086 hit = true; 1087 break; 1088 } 1089 } 1090 1091 if (!hit) 1092 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1093 1094 priv->scc_ctl = host->ctl + of_data->scc_offset; 1095 host->check_retune = renesas_sdhi_check_scc_error; 1096 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1097 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1098 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1099 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1100 } 1101 1102 ret = tmio_mmc_host_probe(host); 1103 if (ret < 0) 1104 goto edisclk; 1105 1106 num_irqs = platform_irq_count(pdev); 1107 if (num_irqs < 0) { 1108 ret = num_irqs; 1109 goto eirq; 1110 } 1111 1112 /* There must be at least one IRQ source */ 1113 if (!num_irqs) { 1114 ret = -ENXIO; 1115 goto eirq; 1116 } 1117 1118 for (i = 0; i < num_irqs; i++) { 1119 irq = platform_get_irq(pdev, i); 1120 if (irq < 0) { 1121 ret = irq; 1122 goto eirq; 1123 } 1124 1125 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1126 dev_name(&pdev->dev), host); 1127 if (ret) 1128 goto eirq; 1129 } 1130 1131 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1132 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1133 1134 return ret; 1135 1136 eirq: 1137 tmio_mmc_host_remove(host); 1138 edisclk: 1139 renesas_sdhi_clk_disable(host); 1140 efree: 1141 tmio_mmc_host_free(host); 1142 1143 return ret; 1144 } 1145 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1146 1147 int renesas_sdhi_remove(struct platform_device *pdev) 1148 { 1149 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1150 1151 tmio_mmc_host_remove(host); 1152 renesas_sdhi_clk_disable(host); 1153 tmio_mmc_host_free(host); 1154 1155 return 0; 1156 } 1157 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1158 1159 MODULE_LICENSE("GPL v2"); 1160