1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-17 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/mmc/host.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mfd/tmio.h> 30 #include <linux/sh_dma.h> 31 #include <linux/delay.h> 32 #include <linux/pinctrl/consumer.h> 33 #include <linux/pinctrl/pinctrl-state.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/sys_soc.h> 36 37 #include "renesas_sdhi.h" 38 #include "tmio_mmc.h" 39 40 #define HOST_MODE 0xe4 41 42 #define SDHI_VER_GEN2_SDR50 0x490c 43 #define SDHI_VER_RZ_A1 0x820b 44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45 #define SDHI_VER_GEN2_SDR104 0xcb0d 46 #define SDHI_VER_GEN3_SD 0xcc10 47 #define SDHI_VER_GEN3_SDMMC 0xcd10 48 49 struct renesas_sdhi_quirks { 50 bool hs400_disabled; 51 bool hs400_4taps; 52 }; 53 54 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 55 { 56 u32 val; 57 58 /* 59 * see also 60 * renesas_sdhi_of_data :: dma_buswidth 61 */ 62 switch (sd_ctrl_read16(host, CTL_VERSION)) { 63 case SDHI_VER_GEN2_SDR50: 64 val = (width == 32) ? 0x0001 : 0x0000; 65 break; 66 case SDHI_VER_GEN2_SDR104: 67 val = (width == 32) ? 0x0000 : 0x0001; 68 break; 69 case SDHI_VER_GEN3_SD: 70 case SDHI_VER_GEN3_SDMMC: 71 if (width == 64) 72 val = 0x0000; 73 else if (width == 32) 74 val = 0x0101; 75 else 76 val = 0x0001; 77 break; 78 default: 79 /* nothing to do */ 80 return; 81 } 82 83 sd_ctrl_write16(host, HOST_MODE, val); 84 } 85 86 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 87 { 88 struct mmc_host *mmc = host->mmc; 89 struct renesas_sdhi *priv = host_to_priv(host); 90 int ret = clk_prepare_enable(priv->clk); 91 92 if (ret < 0) 93 return ret; 94 95 ret = clk_prepare_enable(priv->clk_cd); 96 if (ret < 0) { 97 clk_disable_unprepare(priv->clk); 98 return ret; 99 } 100 101 /* 102 * The clock driver may not know what maximum frequency 103 * actually works, so it should be set with the max-frequency 104 * property which will already have been read to f_max. If it 105 * was missing, assume the current frequency is the maximum. 106 */ 107 if (!mmc->f_max) 108 mmc->f_max = clk_get_rate(priv->clk); 109 110 /* 111 * Minimum frequency is the minimum input clock frequency 112 * divided by our maximum divider. 113 */ 114 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 115 116 /* enable 16bit data access on SDBUF as default */ 117 renesas_sdhi_sdbuf_width(host, 16); 118 119 return 0; 120 } 121 122 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 123 unsigned int new_clock) 124 { 125 struct renesas_sdhi *priv = host_to_priv(host); 126 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 127 int i, ret; 128 129 /* tested only on R-Car Gen2+ currently; may work for others */ 130 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 131 return clk_get_rate(priv->clk); 132 133 /* 134 * We want the bus clock to be as close as possible to, but no 135 * greater than, new_clock. As we can divide by 1 << i for 136 * any i in [0, 9] we want the input clock to be as close as 137 * possible, but no greater than, new_clock << i. 138 */ 139 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 140 freq = clk_round_rate(priv->clk, new_clock << i); 141 if (freq > (new_clock << i)) { 142 /* Too fast; look for a slightly slower option */ 143 freq = clk_round_rate(priv->clk, 144 (new_clock << i) / 4 * 3); 145 if (freq > (new_clock << i)) 146 continue; 147 } 148 149 diff = new_clock - (freq >> i); 150 if (diff <= diff_min) { 151 best_freq = freq; 152 diff_min = diff; 153 } 154 } 155 156 ret = clk_set_rate(priv->clk, best_freq); 157 158 return ret == 0 ? best_freq : clk_get_rate(priv->clk); 159 } 160 161 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 162 unsigned int new_clock) 163 { 164 u32 clk = 0, clock; 165 166 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 167 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 168 169 if (new_clock == 0) 170 goto out; 171 172 clock = renesas_sdhi_clk_update(host, new_clock) / 512; 173 174 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 175 clock <<= 1; 176 177 /* 1/1 clock is option */ 178 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 179 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 180 clk |= 0xff; 181 else 182 clk &= ~0xff; 183 } 184 185 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 186 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 187 usleep_range(10000, 11000); 188 189 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 190 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 191 192 out: 193 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 194 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 195 usleep_range(10000, 11000); 196 } 197 198 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 199 { 200 struct renesas_sdhi *priv = host_to_priv(host); 201 202 clk_disable_unprepare(priv->clk); 203 clk_disable_unprepare(priv->clk_cd); 204 } 205 206 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 207 { 208 struct tmio_mmc_host *host = mmc_priv(mmc); 209 210 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 211 TMIO_STAT_DAT0); 212 } 213 214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 215 struct mmc_ios *ios) 216 { 217 struct tmio_mmc_host *host = mmc_priv(mmc); 218 struct renesas_sdhi *priv = host_to_priv(host); 219 struct pinctrl_state *pin_state; 220 int ret; 221 222 switch (ios->signal_voltage) { 223 case MMC_SIGNAL_VOLTAGE_330: 224 pin_state = priv->pins_default; 225 break; 226 case MMC_SIGNAL_VOLTAGE_180: 227 pin_state = priv->pins_uhs; 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 /* 234 * If anything is missing, assume signal voltage is fixed at 235 * 3.3V and succeed/fail accordingly. 236 */ 237 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 238 return ios->signal_voltage == 239 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 240 241 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 242 if (ret) 243 return ret; 244 245 return pinctrl_select_state(priv->pinctrl, pin_state); 246 } 247 248 /* SCC registers */ 249 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 250 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 251 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 252 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 253 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 254 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 255 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 256 257 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 259 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 260 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 261 262 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 263 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 264 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 265 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 266 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 267 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 268 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */ 269 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 270 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 271 272 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 273 struct renesas_sdhi *priv, int addr) 274 { 275 return readl(priv->scc_ctl + (addr << host->bus_shift)); 276 } 277 278 static inline void sd_scc_write32(struct tmio_mmc_host *host, 279 struct renesas_sdhi *priv, 280 int addr, u32 val) 281 { 282 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 283 } 284 285 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 286 { 287 struct renesas_sdhi *priv; 288 289 priv = host_to_priv(host); 290 291 /* Initialize SCC */ 292 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 293 294 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 295 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 296 297 /* set sampling clock selection range */ 298 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 299 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 300 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 301 302 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 303 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 304 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 305 306 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 307 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 308 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 309 310 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 311 312 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 313 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 314 315 /* Read TAPNUM */ 316 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 317 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 318 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 319 } 320 321 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 322 unsigned long tap) 323 { 324 struct renesas_sdhi *priv = host_to_priv(host); 325 326 /* Set sampling clock position */ 327 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 328 } 329 330 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) 331 { 332 struct renesas_sdhi *priv = host_to_priv(host); 333 334 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 335 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 336 337 /* Set HS400 mode */ 338 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 339 sd_ctrl_read16(host, CTL_SDIF_MODE)); 340 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 341 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 342 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 343 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 344 345 /* Set the sampling clock selection range of HS400 mode */ 346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 347 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 348 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 349 350 351 if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400) 352 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 353 host->tap_set / 2); 354 355 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 356 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 357 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 358 359 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 360 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 361 } 362 363 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 364 struct renesas_sdhi *priv) 365 { 366 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 367 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 368 369 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 370 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 371 sd_scc_read32(host, priv, 372 SH_MOBILE_SDHI_SCC_CKSEL)); 373 } 374 375 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host) 376 { 377 struct renesas_sdhi *priv = host_to_priv(host); 378 379 renesas_sdhi_reset_scc(host, priv); 380 381 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 382 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 383 sd_scc_read32(host, priv, 384 SH_MOBILE_SDHI_SCC_DTCNTL)); 385 386 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 387 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 388 } 389 390 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 391 struct renesas_sdhi *priv) 392 { 393 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 394 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 395 396 /* Reset HS400 mode */ 397 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 398 sd_ctrl_read16(host, CTL_SDIF_MODE)); 399 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 400 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 401 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 402 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 403 404 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 405 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 406 } 407 408 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host) 409 { 410 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 411 } 412 413 #define SH_MOBILE_SDHI_MAX_TAP 3 414 415 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 416 { 417 struct renesas_sdhi *priv = host_to_priv(host); 418 unsigned long tap_cnt; /* counter of tuning success */ 419 unsigned long tap_start;/* start position of tuning success */ 420 unsigned long tap_end; /* end position of tuning success */ 421 unsigned long ntap; /* temporary counter of tuning success */ 422 unsigned long i; 423 424 /* Clear SCC_RVSREQ */ 425 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 426 427 /* 428 * When tuning CMD19 is issued twice for each tap, merge the 429 * result requiring the tap to be good in both runs before 430 * considering it for tuning selection. 431 */ 432 for (i = 0; i < host->tap_num * 2; i++) { 433 int offset = host->tap_num * (i < host->tap_num ? 1 : -1); 434 435 if (!test_bit(i, host->taps)) 436 clear_bit(i + offset, host->taps); 437 } 438 439 /* 440 * Find the longest consecutive run of successful probes. If that 441 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 442 * center index as the tap. 443 */ 444 tap_cnt = 0; 445 ntap = 0; 446 tap_start = 0; 447 tap_end = 0; 448 for (i = 0; i < host->tap_num * 2; i++) { 449 if (test_bit(i, host->taps)) { 450 ntap++; 451 } else { 452 if (ntap > tap_cnt) { 453 tap_start = i - ntap; 454 tap_end = i - 1; 455 tap_cnt = ntap; 456 } 457 ntap = 0; 458 } 459 } 460 461 if (ntap > tap_cnt) { 462 tap_start = i - ntap; 463 tap_end = i - 1; 464 tap_cnt = ntap; 465 } 466 467 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 468 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num; 469 else 470 return -EIO; 471 472 /* Set SCC */ 473 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set); 474 475 /* Enable auto re-tuning */ 476 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 477 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 478 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 479 480 return 0; 481 } 482 483 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 484 { 485 struct renesas_sdhi *priv = host_to_priv(host); 486 bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400; 487 488 /* 489 * Skip checking SCC errors when running on 4 taps in HS400 mode as 490 * any retuning would still result in the same 4 taps being used. 491 */ 492 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 493 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 494 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 495 return false; 496 497 if (mmc_doing_retune(host->mmc)) 498 return false; 499 500 /* Check SCC error */ 501 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 502 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 503 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 504 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 505 /* Clear SCC error */ 506 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 507 return true; 508 } 509 510 return false; 511 } 512 513 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 514 { 515 struct renesas_sdhi *priv; 516 517 priv = host_to_priv(host); 518 519 renesas_sdhi_reset_scc(host, priv); 520 renesas_sdhi_reset_hs400_mode(host, priv); 521 522 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 523 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 524 525 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 526 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 527 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 528 529 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 530 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 531 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 532 533 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) 534 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, 535 TMIO_MASK_INIT_RCAR2); 536 } 537 538 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 539 { 540 int timeout = 1000; 541 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 542 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 543 544 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 545 & bit) == wait_state) 546 udelay(1); 547 548 if (!timeout) { 549 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 550 return -EBUSY; 551 } 552 553 return 0; 554 } 555 556 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 557 { 558 u32 bit = TMIO_STAT_SCLKDIVEN; 559 560 switch (addr) { 561 case CTL_SD_CMD: 562 case CTL_STOP_INTERNAL_ACTION: 563 case CTL_XFER_BLK_COUNT: 564 case CTL_SD_XFER_LEN: 565 case CTL_SD_MEM_CARD_OPT: 566 case CTL_TRANSACTION_CTL: 567 case CTL_DMA_ENABLE: 568 case HOST_MODE: 569 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 570 bit = TMIO_STAT_CMD_BUSY; 571 /* fallthrough */ 572 case CTL_SD_CARD_CLK_CTL: 573 return renesas_sdhi_wait_idle(host, bit); 574 } 575 576 return 0; 577 } 578 579 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 580 unsigned int direction, int blk_size) 581 { 582 /* 583 * In Renesas controllers, when performing a 584 * multiple block read of one or two blocks, 585 * depending on the timing with which the 586 * response register is read, the response 587 * value may not be read properly. 588 * Use single block read for this HW bug 589 */ 590 if ((direction == MMC_DATA_READ) && 591 blk_size == 2) 592 return 1; 593 594 return blk_size; 595 } 596 597 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 598 { 599 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 600 int width = (host->bus_shift == 2) ? 64 : 32; 601 602 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 603 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 604 } 605 606 static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w_es1 = { 607 .hs400_disabled = true, 608 .hs400_4taps = true, 609 }; 610 611 static const struct renesas_sdhi_quirks sdhi_quirks_h3_es2 = { 612 .hs400_disabled = false, 613 .hs400_4taps = true, 614 }; 615 616 static const struct soc_device_attribute sdhi_quirks_match[] = { 617 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_h3_m3w_es1 }, 618 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_h3_es2 }, 619 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_h3_m3w_es1 }, 620 { .soc_id = "r8a7796", .revision = "ES1.1", .data = &sdhi_quirks_h3_m3w_es1 }, 621 { /* Sentinel. */ }, 622 }; 623 624 int renesas_sdhi_probe(struct platform_device *pdev, 625 const struct tmio_mmc_dma_ops *dma_ops) 626 { 627 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 628 const struct renesas_sdhi_quirks *quirks = NULL; 629 const struct renesas_sdhi_of_data *of_data; 630 const struct soc_device_attribute *attr; 631 struct tmio_mmc_data *mmc_data; 632 struct tmio_mmc_dma *dma_priv; 633 struct tmio_mmc_host *host; 634 struct renesas_sdhi *priv; 635 struct resource *res; 636 int irq, ret, i; 637 638 of_data = of_device_get_match_data(&pdev->dev); 639 640 attr = soc_device_match(sdhi_quirks_match); 641 if (attr) 642 quirks = attr->data; 643 644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645 if (!res) 646 return -EINVAL; 647 648 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 649 GFP_KERNEL); 650 if (!priv) 651 return -ENOMEM; 652 653 mmc_data = &priv->mmc_data; 654 dma_priv = &priv->dma_priv; 655 656 priv->clk = devm_clk_get(&pdev->dev, NULL); 657 if (IS_ERR(priv->clk)) { 658 ret = PTR_ERR(priv->clk); 659 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 660 return ret; 661 } 662 663 /* 664 * Some controllers provide a 2nd clock just to run the internal card 665 * detection logic. Unfortunately, the existing driver architecture does 666 * not support a separation of clocks for runtime PM usage. When 667 * native hotplug is used, the tmio driver assumes that the core 668 * must continue to run for card detect to stay active, so we cannot 669 * disable it. 670 * Additionally, it is prohibited to supply a clock to the core but not 671 * to the card detect circuit. That leaves us with if separate clocks 672 * are presented, we must treat them both as virtually 1 clock. 673 */ 674 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 675 if (IS_ERR(priv->clk_cd)) 676 priv->clk_cd = NULL; 677 678 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 679 if (!IS_ERR(priv->pinctrl)) { 680 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 681 PINCTRL_STATE_DEFAULT); 682 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 683 "state_uhs"); 684 } 685 686 host = tmio_mmc_host_alloc(pdev, mmc_data); 687 if (IS_ERR(host)) 688 return PTR_ERR(host); 689 690 if (of_data) { 691 mmc_data->flags |= of_data->tmio_flags; 692 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 693 mmc_data->capabilities |= of_data->capabilities; 694 mmc_data->capabilities2 |= of_data->capabilities2; 695 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 696 mmc_data->max_blk_count = of_data->max_blk_count; 697 mmc_data->max_segs = of_data->max_segs; 698 dma_priv->dma_buswidth = of_data->dma_buswidth; 699 host->bus_shift = of_data->bus_shift; 700 } 701 702 host->write16_hook = renesas_sdhi_write16_hook; 703 host->clk_enable = renesas_sdhi_clk_enable; 704 host->clk_disable = renesas_sdhi_clk_disable; 705 host->set_clock = renesas_sdhi_set_clock; 706 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 707 host->dma_ops = dma_ops; 708 709 if (quirks && quirks->hs400_disabled) 710 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 711 712 if (quirks && quirks->hs400_4taps) 713 mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400; 714 715 /* For some SoC, we disable internal WP. GPIO may override this */ 716 if (mmc_can_gpio_ro(host->mmc)) 717 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 718 719 /* SDR speeds are only available on Gen2+ */ 720 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 721 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 722 host->ops.card_busy = renesas_sdhi_card_busy; 723 host->ops.start_signal_voltage_switch = 724 renesas_sdhi_start_signal_voltage_switch; 725 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 726 } 727 728 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 729 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 730 host->bus_shift = 1; 731 732 if (mmd) 733 *mmc_data = *mmd; 734 735 dma_priv->filter = shdma_chan_filter; 736 dma_priv->enable = renesas_sdhi_enable_dma; 737 738 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 739 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 740 741 /* 742 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 743 * bus width mode. 744 */ 745 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 746 747 /* 748 * All SDHI blocks support SDIO IRQ signalling. 749 */ 750 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 751 752 /* All SDHI have CMD12 control bit */ 753 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 754 755 /* All SDHI have SDIO status bits which must be 1 */ 756 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 757 758 ret = renesas_sdhi_clk_enable(host); 759 if (ret) 760 goto efree; 761 762 ret = tmio_mmc_host_probe(host); 763 if (ret < 0) 764 goto edisclk; 765 766 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 767 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 768 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 769 770 /* Enable tuning iff we have an SCC and a supported mode */ 771 if (of_data && of_data->scc_offset && 772 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 773 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 774 MMC_CAP2_HS400_1_8V))) { 775 const struct renesas_sdhi_scc *taps = of_data->taps; 776 bool hit = false; 777 778 host->mmc->caps |= MMC_CAP_HW_RESET; 779 780 for (i = 0; i < of_data->taps_num; i++) { 781 if (taps[i].clk_rate == 0 || 782 taps[i].clk_rate == host->mmc->f_max) { 783 priv->scc_tappos = taps->tap; 784 hit = true; 785 break; 786 } 787 } 788 789 if (!hit) 790 dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 791 792 priv->scc_ctl = host->ctl + of_data->scc_offset; 793 host->init_tuning = renesas_sdhi_init_tuning; 794 host->prepare_tuning = renesas_sdhi_prepare_tuning; 795 host->select_tuning = renesas_sdhi_select_tuning; 796 host->check_scc_error = renesas_sdhi_check_scc_error; 797 host->hw_reset = renesas_sdhi_hw_reset; 798 host->prepare_hs400_tuning = 799 renesas_sdhi_prepare_hs400_tuning; 800 host->hs400_downgrade = renesas_sdhi_disable_scc; 801 host->hs400_complete = renesas_sdhi_hs400_complete; 802 } 803 804 i = 0; 805 while (1) { 806 irq = platform_get_irq(pdev, i); 807 if (irq < 0) 808 break; 809 i++; 810 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 811 dev_name(&pdev->dev), host); 812 if (ret) 813 goto eirq; 814 } 815 816 /* There must be at least one IRQ source */ 817 if (!i) { 818 ret = irq; 819 goto eirq; 820 } 821 822 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 823 mmc_hostname(host->mmc), (unsigned long) 824 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 825 host->mmc->f_max / 1000000); 826 827 return ret; 828 829 eirq: 830 tmio_mmc_host_remove(host); 831 edisclk: 832 renesas_sdhi_clk_disable(host); 833 efree: 834 tmio_mmc_host_free(host); 835 836 return ret; 837 } 838 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 839 840 int renesas_sdhi_remove(struct platform_device *pdev) 841 { 842 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 843 844 tmio_mmc_host_remove(host); 845 renesas_sdhi_clk_disable(host); 846 847 return 0; 848 } 849 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 850 851 MODULE_LICENSE("GPL v2"); 852