1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_domain.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/slot-gpio.h> 31 #include <linux/mfd/tmio.h> 32 #include <linux/sh_dma.h> 33 #include <linux/delay.h> 34 #include <linux/pinctrl/consumer.h> 35 #include <linux/pinctrl/pinctrl-state.h> 36 #include <linux/regulator/consumer.h> 37 #include <linux/sys_soc.h> 38 39 #include "renesas_sdhi.h" 40 #include "tmio_mmc.h" 41 42 #define HOST_MODE 0xe4 43 44 #define SDHI_VER_GEN2_SDR50 0x490c 45 #define SDHI_VER_RZ_A1 0x820b 46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 47 #define SDHI_VER_GEN2_SDR104 0xcb0d 48 #define SDHI_VER_GEN3_SD 0xcc10 49 #define SDHI_VER_GEN3_SDMMC 0xcd10 50 51 #define SDHI_GEN3_MMC0_ADDR 0xee140000 52 53 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 54 { 55 u32 val; 56 57 /* 58 * see also 59 * renesas_sdhi_of_data :: dma_buswidth 60 */ 61 switch (sd_ctrl_read16(host, CTL_VERSION)) { 62 case SDHI_VER_GEN2_SDR50: 63 val = (width == 32) ? 0x0001 : 0x0000; 64 break; 65 case SDHI_VER_GEN2_SDR104: 66 val = (width == 32) ? 0x0000 : 0x0001; 67 break; 68 case SDHI_VER_GEN3_SD: 69 case SDHI_VER_GEN3_SDMMC: 70 if (width == 64) 71 val = 0x0000; 72 else if (width == 32) 73 val = 0x0101; 74 else 75 val = 0x0001; 76 break; 77 default: 78 /* nothing to do */ 79 return; 80 } 81 82 sd_ctrl_write16(host, HOST_MODE, val); 83 } 84 85 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 86 { 87 struct mmc_host *mmc = host->mmc; 88 struct renesas_sdhi *priv = host_to_priv(host); 89 int ret; 90 91 ret = clk_prepare_enable(priv->clk_cd); 92 if (ret < 0) 93 return ret; 94 95 /* 96 * The clock driver may not know what maximum frequency 97 * actually works, so it should be set with the max-frequency 98 * property which will already have been read to f_max. If it 99 * was missing, assume the current frequency is the maximum. 100 */ 101 if (!mmc->f_max) 102 mmc->f_max = clk_get_rate(priv->clk); 103 104 /* 105 * Minimum frequency is the minimum input clock frequency 106 * divided by our maximum divider. 107 */ 108 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 109 110 /* enable 16bit data access on SDBUF as default */ 111 renesas_sdhi_sdbuf_width(host, 16); 112 113 return 0; 114 } 115 116 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 117 unsigned int new_clock) 118 { 119 struct renesas_sdhi *priv = host_to_priv(host); 120 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 121 int i; 122 123 /* 124 * We simply return the current rate if a) we are not on a R-Car Gen2+ 125 * SoC (may work for others, but untested) or b) if the SCC needs its 126 * clock during tuning, so we don't change the external clock setup. 127 */ 128 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 129 return clk_get_rate(priv->clk); 130 131 /* 132 * We want the bus clock to be as close as possible to, but no 133 * greater than, new_clock. As we can divide by 1 << i for 134 * any i in [0, 9] we want the input clock to be as close as 135 * possible, but no greater than, new_clock << i. 136 */ 137 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 138 freq = clk_round_rate(priv->clk, new_clock << i); 139 if (freq > (new_clock << i)) { 140 /* Too fast; look for a slightly slower option */ 141 freq = clk_round_rate(priv->clk, 142 (new_clock << i) / 4 * 3); 143 if (freq > (new_clock << i)) 144 continue; 145 } 146 147 diff = new_clock - (freq >> i); 148 if (diff <= diff_min) { 149 best_freq = freq; 150 diff_min = diff; 151 } 152 } 153 154 clk_set_rate(priv->clk, best_freq); 155 156 return clk_get_rate(priv->clk); 157 } 158 159 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 160 unsigned int new_clock) 161 { 162 u32 clk = 0, clock; 163 164 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 165 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 166 167 if (new_clock == 0) { 168 host->mmc->actual_clock = 0; 169 goto out; 170 } 171 172 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 173 clock = host->mmc->actual_clock / 512; 174 175 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 176 clock <<= 1; 177 178 /* 1/1 clock is option */ 179 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 180 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 181 clk |= 0xff; 182 else 183 clk &= ~0xff; 184 } 185 186 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 187 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 188 usleep_range(10000, 11000); 189 190 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 191 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 192 193 out: 194 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 195 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 196 usleep_range(10000, 11000); 197 } 198 199 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 200 { 201 struct renesas_sdhi *priv = host_to_priv(host); 202 203 clk_disable_unprepare(priv->clk_cd); 204 } 205 206 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 207 { 208 struct tmio_mmc_host *host = mmc_priv(mmc); 209 210 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 211 TMIO_STAT_DAT0); 212 } 213 214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 215 struct mmc_ios *ios) 216 { 217 struct tmio_mmc_host *host = mmc_priv(mmc); 218 struct renesas_sdhi *priv = host_to_priv(host); 219 struct pinctrl_state *pin_state; 220 int ret; 221 222 switch (ios->signal_voltage) { 223 case MMC_SIGNAL_VOLTAGE_330: 224 pin_state = priv->pins_default; 225 break; 226 case MMC_SIGNAL_VOLTAGE_180: 227 pin_state = priv->pins_uhs; 228 break; 229 default: 230 return -EINVAL; 231 } 232 233 /* 234 * If anything is missing, assume signal voltage is fixed at 235 * 3.3V and succeed/fail accordingly. 236 */ 237 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 238 return ios->signal_voltage == 239 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 240 241 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 242 if (ret < 0) 243 return ret; 244 245 return pinctrl_select_state(priv->pinctrl, pin_state); 246 } 247 248 /* SCC registers */ 249 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 250 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 251 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 252 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 253 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 254 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 255 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 256 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 257 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 258 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 259 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 260 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 261 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 262 263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 264 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 265 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 266 267 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 268 269 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 270 271 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 272 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 273 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 274 275 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 276 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 277 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 278 279 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 280 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 281 282 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 283 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 284 285 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 286 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 287 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 288 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 289 290 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 291 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 292 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 293 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 294 295 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 296 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 297 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 298 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 299 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 300 }; 301 302 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 303 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 304 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 305 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 306 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 307 }; 308 309 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 310 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 311 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 312 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 313 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 314 }; 315 316 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 317 struct renesas_sdhi *priv, int addr) 318 { 319 return readl(priv->scc_ctl + (addr << host->bus_shift)); 320 } 321 322 static inline void sd_scc_write32(struct tmio_mmc_host *host, 323 struct renesas_sdhi *priv, 324 int addr, u32 val) 325 { 326 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 327 } 328 329 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 330 { 331 struct renesas_sdhi *priv; 332 333 priv = host_to_priv(host); 334 335 /* Initialize SCC */ 336 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 337 338 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 339 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 340 341 /* set sampling clock selection range */ 342 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 343 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 344 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 345 346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 347 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 348 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 349 350 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 351 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 352 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 353 354 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 355 356 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 357 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 358 359 /* Read TAPNUM */ 360 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 361 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 362 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 363 } 364 365 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 366 { 367 struct tmio_mmc_host *host = mmc_priv(mmc); 368 struct renesas_sdhi *priv = host_to_priv(host); 369 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 370 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 371 372 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 373 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 374 375 /* Set HS400 mode */ 376 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 377 sd_ctrl_read16(host, CTL_SDIF_MODE)); 378 379 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 380 priv->scc_tappos_hs400); 381 382 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 383 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 384 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 385 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 386 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 387 388 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 389 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 390 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 391 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 392 393 /* Set the sampling clock selection range of HS400 mode */ 394 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 395 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 396 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 397 398 /* Avoid bad TAP */ 399 if (bad_taps & BIT(priv->tap_set)) { 400 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 401 402 if (bad_taps & BIT(new_tap)) 403 new_tap = (priv->tap_set - 1) % priv->tap_num; 404 405 if (bad_taps & BIT(new_tap)) { 406 new_tap = priv->tap_set; 407 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 408 } 409 410 priv->tap_set = new_tap; 411 } 412 413 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 414 priv->tap_set / (use_4tap ? 2 : 1)); 415 416 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 417 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 418 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 419 420 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 421 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 422 423 if (priv->adjust_hs400_calib_table) 424 priv->needs_adjust_hs400 = true; 425 } 426 427 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 428 struct renesas_sdhi *priv) 429 { 430 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 431 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 432 433 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 434 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 435 sd_scc_read32(host, priv, 436 SH_MOBILE_SDHI_SCC_CKSEL)); 437 } 438 439 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 440 { 441 struct tmio_mmc_host *host = mmc_priv(mmc); 442 struct renesas_sdhi *priv = host_to_priv(host); 443 444 renesas_sdhi_reset_scc(host, priv); 445 446 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 447 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 448 sd_scc_read32(host, priv, 449 SH_MOBILE_SDHI_SCC_DTCNTL)); 450 451 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 452 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 453 } 454 455 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 456 struct renesas_sdhi *priv, u32 addr) 457 { 458 /* read mode */ 459 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 460 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 461 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 462 463 /* access start and stop */ 464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 465 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 466 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 467 468 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 469 } 470 471 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 472 struct renesas_sdhi *priv, u32 addr, u32 val) 473 { 474 /* write mode */ 475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 476 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 477 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 478 479 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 480 481 /* access start and stop */ 482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 483 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 485 } 486 487 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 488 { 489 struct renesas_sdhi *priv = host_to_priv(host); 490 u32 calib_code; 491 492 /* disable write protect */ 493 sd_scc_tmpport_write32(host, priv, 0x00, 494 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 495 /* read calibration code and adjust */ 496 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 497 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 498 499 sd_scc_tmpport_write32(host, priv, 0x22, 500 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 501 priv->adjust_hs400_calib_table[calib_code]); 502 503 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 504 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 505 506 /* adjustment done, clear flag */ 507 priv->needs_adjust_hs400 = false; 508 } 509 510 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 511 { 512 struct renesas_sdhi *priv = host_to_priv(host); 513 514 /* disable write protect */ 515 sd_scc_tmpport_write32(host, priv, 0x00, 516 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 517 /* disable manual calibration */ 518 sd_scc_tmpport_write32(host, priv, 0x22, 0); 519 /* clear offset value of TMPPORT3 */ 520 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 521 } 522 523 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 524 struct renesas_sdhi *priv) 525 { 526 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 527 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 528 529 /* Reset HS400 mode */ 530 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 531 sd_ctrl_read16(host, CTL_SDIF_MODE)); 532 533 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 534 535 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 536 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 537 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 538 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 539 540 if (priv->adjust_hs400_calib_table) 541 renesas_sdhi_adjust_hs400_mode_disable(host); 542 543 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 544 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 545 } 546 547 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 548 { 549 struct tmio_mmc_host *host = mmc_priv(mmc); 550 551 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 552 return 0; 553 } 554 555 static void renesas_sdhi_reset(struct tmio_mmc_host *host) 556 { 557 struct renesas_sdhi *priv = host_to_priv(host); 558 559 renesas_sdhi_reset_scc(host, priv); 560 renesas_sdhi_reset_hs400_mode(host, priv); 561 priv->needs_adjust_hs400 = false; 562 563 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 564 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 565 566 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 567 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 568 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 569 570 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) 571 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, 572 TMIO_MASK_INIT_RCAR2); 573 } 574 575 /* 576 * This is a temporary workaround! This driver used 'hw_reset' wrongly and the 577 * fix for that showed a regression. So, we mimic the old behaviour until the 578 * proper solution is found. 579 */ 580 static void renesas_sdhi_hw_reset(struct mmc_host *mmc) 581 { 582 struct tmio_mmc_host *host = mmc_priv(mmc); 583 renesas_sdhi_reset(host); 584 } 585 586 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 587 588 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 589 { 590 struct renesas_sdhi *priv = host_to_priv(host); 591 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 592 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 593 unsigned long *bitmap; 594 595 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 596 597 /* 598 * When tuning CMD19 is issued twice for each tap, merge the 599 * result requiring the tap to be good in both runs before 600 * considering it for tuning selection. 601 */ 602 for (i = 0; i < taps_size; i++) { 603 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 604 605 if (!test_bit(i, priv->taps)) 606 clear_bit(i + offset, priv->taps); 607 608 if (!test_bit(i, priv->smpcmp)) 609 clear_bit(i + offset, priv->smpcmp); 610 } 611 612 /* 613 * If all TAP are OK, the sampling clock position is selected by 614 * identifying the change point of data. 615 */ 616 if (bitmap_full(priv->taps, taps_size)) { 617 bitmap = priv->smpcmp; 618 min_tap_row = 1; 619 } else { 620 bitmap = priv->taps; 621 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 622 } 623 624 /* 625 * Find the longest consecutive run of successful probes. If that 626 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 627 * center index as the tap, otherwise bail out. 628 */ 629 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 630 if (re - rs > tap_cnt) { 631 tap_end = re; 632 tap_start = rs; 633 tap_cnt = tap_end - tap_start; 634 } 635 } 636 637 if (tap_cnt >= min_tap_row) 638 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 639 else 640 return -EIO; 641 642 /* Set SCC */ 643 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 644 645 /* Enable auto re-tuning */ 646 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 647 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 648 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 649 650 return 0; 651 } 652 653 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 654 { 655 struct tmio_mmc_host *host = mmc_priv(mmc); 656 struct renesas_sdhi *priv = host_to_priv(host); 657 int i, ret; 658 659 priv->tap_num = renesas_sdhi_init_tuning(host); 660 if (!priv->tap_num) 661 return 0; /* Tuning is not supported */ 662 663 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 664 dev_err(&host->pdev->dev, 665 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 666 return -EINVAL; 667 } 668 669 bitmap_zero(priv->taps, priv->tap_num * 2); 670 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 671 672 /* Issue CMD19 twice for each tap */ 673 for (i = 0; i < 2 * priv->tap_num; i++) { 674 /* Set sampling clock position */ 675 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 676 677 if (mmc_send_tuning(mmc, opcode, NULL) == 0) 678 set_bit(i, priv->taps); 679 680 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 681 set_bit(i, priv->smpcmp); 682 } 683 684 ret = renesas_sdhi_select_tuning(host); 685 if (ret < 0) 686 renesas_sdhi_reset(host); 687 return ret; 688 } 689 690 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 691 { 692 struct renesas_sdhi *priv = host_to_priv(host); 693 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 694 u32 val; 695 696 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 697 if (!val) 698 return false; 699 700 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 701 702 /* Change TAP position according to correction status */ 703 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 704 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 705 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 706 /* 707 * With HS400, the DAT signal is based on DS, not CLK. 708 * Therefore, use only CMD status. 709 */ 710 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 711 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 712 if (!smpcmp) { 713 return false; /* no error in CMD signal */ 714 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 715 new_tap++; 716 error_tap--; 717 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 718 new_tap--; 719 error_tap++; 720 } else { 721 return true; /* need retune */ 722 } 723 724 /* 725 * When new_tap is a bad tap, we cannot change. Then, we compare 726 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 727 * we can at least retune. 728 */ 729 if (bad_taps & BIT(new_tap % priv->tap_num)) 730 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 731 } else { 732 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 733 return true; /* need retune */ 734 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 735 new_tap++; 736 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 737 new_tap--; 738 else 739 return false; 740 } 741 742 priv->tap_set = (new_tap % priv->tap_num); 743 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 744 priv->tap_set / (use_4tap ? 2 : 1)); 745 746 return false; 747 } 748 749 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 750 { 751 struct renesas_sdhi *priv = host_to_priv(host); 752 753 /* Check SCC error */ 754 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 755 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 756 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 757 return true; 758 } 759 760 return false; 761 } 762 763 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 764 { 765 struct renesas_sdhi *priv = host_to_priv(host); 766 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 767 768 /* 769 * Skip checking SCC errors when running on 4 taps in HS400 mode as 770 * any retuning would still result in the same 4 taps being used. 771 */ 772 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 773 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 774 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 775 return false; 776 777 if (mmc_doing_tune(host->mmc)) 778 return false; 779 780 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 781 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 782 return renesas_sdhi_auto_correction(host); 783 784 return renesas_sdhi_manual_correction(host, use_4tap); 785 } 786 787 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 788 { 789 int timeout = 1000; 790 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 791 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 792 793 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 794 & bit) == wait_state) 795 udelay(1); 796 797 if (!timeout) { 798 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 799 return -EBUSY; 800 } 801 802 return 0; 803 } 804 805 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 806 { 807 u32 bit = TMIO_STAT_SCLKDIVEN; 808 809 switch (addr) { 810 case CTL_SD_CMD: 811 case CTL_STOP_INTERNAL_ACTION: 812 case CTL_XFER_BLK_COUNT: 813 case CTL_SD_XFER_LEN: 814 case CTL_SD_MEM_CARD_OPT: 815 case CTL_TRANSACTION_CTL: 816 case CTL_DMA_ENABLE: 817 case HOST_MODE: 818 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 819 bit = TMIO_STAT_CMD_BUSY; 820 fallthrough; 821 case CTL_SD_CARD_CLK_CTL: 822 return renesas_sdhi_wait_idle(host, bit); 823 } 824 825 return 0; 826 } 827 828 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 829 unsigned int direction, int blk_size) 830 { 831 /* 832 * In Renesas controllers, when performing a 833 * multiple block read of one or two blocks, 834 * depending on the timing with which the 835 * response register is read, the response 836 * value may not be read properly. 837 * Use single block read for this HW bug 838 */ 839 if ((direction == MMC_DATA_READ) && 840 blk_size == 2) 841 return 1; 842 843 return blk_size; 844 } 845 846 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 847 { 848 struct renesas_sdhi *priv = host_to_priv(host); 849 850 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 851 renesas_sdhi_adjust_hs400_mode_enable(host); 852 } 853 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 854 { 855 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 856 int width = (host->bus_shift == 2) ? 64 : 32; 857 858 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 859 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 860 } 861 862 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 863 .hs400_disabled = true, 864 .hs400_4taps = true, 865 }; 866 867 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 868 .hs400_4taps = true, 869 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 870 }; 871 872 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 873 .hs400_disabled = true, 874 }; 875 876 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 877 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 878 }; 879 880 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 881 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 882 }; 883 884 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 885 .hs400_4taps = true, 886 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 887 .hs400_calib_table = r8a7796_es13_calib_table, 888 }; 889 890 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 891 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 892 .hs400_calib_table = r8a77965_calib_table, 893 }; 894 895 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 896 .hs400_calib_table = r8a77990_calib_table, 897 }; 898 899 /* 900 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 901 * So, we want to treat them equally and only have a match for ES1.2 to enforce 902 * this if there ever will be a way to distinguish ES1.2. 903 */ 904 static const struct soc_device_attribute sdhi_quirks_match[] = { 905 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 906 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 907 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 908 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 }, 909 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 910 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 911 { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 }, 912 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 }, 913 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 914 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 }, 915 { /* Sentinel. */ }, 916 }; 917 918 int renesas_sdhi_probe(struct platform_device *pdev, 919 const struct tmio_mmc_dma_ops *dma_ops) 920 { 921 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 922 const struct renesas_sdhi_quirks *quirks = NULL; 923 const struct renesas_sdhi_of_data *of_data; 924 const struct soc_device_attribute *attr; 925 struct tmio_mmc_data *mmc_data; 926 struct tmio_mmc_dma *dma_priv; 927 struct tmio_mmc_host *host; 928 struct renesas_sdhi *priv; 929 int num_irqs, irq, ret, i; 930 struct resource *res; 931 u16 ver; 932 933 of_data = of_device_get_match_data(&pdev->dev); 934 935 attr = soc_device_match(sdhi_quirks_match); 936 if (attr) 937 quirks = attr->data; 938 939 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 940 if (!res) 941 return -EINVAL; 942 943 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 944 GFP_KERNEL); 945 if (!priv) 946 return -ENOMEM; 947 948 priv->quirks = quirks; 949 mmc_data = &priv->mmc_data; 950 dma_priv = &priv->dma_priv; 951 952 priv->clk = devm_clk_get(&pdev->dev, NULL); 953 if (IS_ERR(priv->clk)) { 954 ret = PTR_ERR(priv->clk); 955 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 956 return ret; 957 } 958 959 /* 960 * Some controllers provide a 2nd clock just to run the internal card 961 * detection logic. Unfortunately, the existing driver architecture does 962 * not support a separation of clocks for runtime PM usage. When 963 * native hotplug is used, the tmio driver assumes that the core 964 * must continue to run for card detect to stay active, so we cannot 965 * disable it. 966 * Additionally, it is prohibited to supply a clock to the core but not 967 * to the card detect circuit. That leaves us with if separate clocks 968 * are presented, we must treat them both as virtually 1 clock. 969 */ 970 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 971 if (IS_ERR(priv->clk_cd)) 972 priv->clk_cd = NULL; 973 974 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 975 if (!IS_ERR(priv->pinctrl)) { 976 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 977 PINCTRL_STATE_DEFAULT); 978 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 979 "state_uhs"); 980 } 981 982 host = tmio_mmc_host_alloc(pdev, mmc_data); 983 if (IS_ERR(host)) 984 return PTR_ERR(host); 985 986 if (of_data) { 987 mmc_data->flags |= of_data->tmio_flags; 988 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 989 mmc_data->capabilities |= of_data->capabilities; 990 mmc_data->capabilities2 |= of_data->capabilities2; 991 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 992 mmc_data->max_blk_count = of_data->max_blk_count; 993 mmc_data->max_segs = of_data->max_segs; 994 dma_priv->dma_buswidth = of_data->dma_buswidth; 995 host->bus_shift = of_data->bus_shift; 996 } 997 998 host->write16_hook = renesas_sdhi_write16_hook; 999 host->clk_enable = renesas_sdhi_clk_enable; 1000 host->clk_disable = renesas_sdhi_clk_disable; 1001 host->set_clock = renesas_sdhi_set_clock; 1002 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1003 host->dma_ops = dma_ops; 1004 1005 if (quirks && quirks->hs400_disabled) 1006 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1007 1008 /* For some SoC, we disable internal WP. GPIO may override this */ 1009 if (mmc_can_gpio_ro(host->mmc)) 1010 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1011 1012 /* SDR speeds are only available on Gen2+ */ 1013 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1014 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1015 host->ops.card_busy = renesas_sdhi_card_busy; 1016 host->ops.start_signal_voltage_switch = 1017 renesas_sdhi_start_signal_voltage_switch; 1018 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1019 1020 if (of_data && of_data->scc_offset) { 1021 priv->scc_ctl = host->ctl + of_data->scc_offset; 1022 host->reset = renesas_sdhi_reset; 1023 host->ops.hw_reset = renesas_sdhi_hw_reset; 1024 host->mmc->caps |= MMC_CAP_HW_RESET; 1025 } 1026 } 1027 1028 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1029 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1030 host->bus_shift = 1; 1031 1032 if (mmd) 1033 *mmc_data = *mmd; 1034 1035 dma_priv->filter = shdma_chan_filter; 1036 dma_priv->enable = renesas_sdhi_enable_dma; 1037 1038 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1039 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1040 1041 /* 1042 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1043 * bus width mode. 1044 */ 1045 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1046 1047 /* 1048 * All SDHI blocks support SDIO IRQ signalling. 1049 */ 1050 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1051 1052 /* All SDHI have CMD12 control bit */ 1053 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1054 1055 /* All SDHI have SDIO status bits which must be 1 */ 1056 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1057 1058 dev_pm_domain_start(&pdev->dev); 1059 1060 ret = renesas_sdhi_clk_enable(host); 1061 if (ret) 1062 goto efree; 1063 1064 ver = sd_ctrl_read16(host, CTL_VERSION); 1065 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1066 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1067 mmc_data->max_blk_count = U16_MAX; 1068 1069 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1070 if (ver == SDHI_VER_GEN2_SDR50) 1071 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1072 1073 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1074 host->fixup_request = renesas_sdhi_fixup_request; 1075 priv->adjust_hs400_calib_table = *( 1076 res->start == SDHI_GEN3_MMC0_ADDR ? 1077 quirks->hs400_calib_table : 1078 quirks->hs400_calib_table + 1); 1079 } 1080 1081 ret = tmio_mmc_host_probe(host); 1082 if (ret < 0) 1083 goto edisclk; 1084 1085 /* Enable tuning iff we have an SCC and a supported mode */ 1086 if (of_data && of_data->scc_offset && 1087 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1088 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1089 MMC_CAP2_HS400_1_8V))) { 1090 const struct renesas_sdhi_scc *taps = of_data->taps; 1091 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1092 bool hit = false; 1093 1094 for (i = 0; i < of_data->taps_num; i++) { 1095 if (taps[i].clk_rate == 0 || 1096 taps[i].clk_rate == host->mmc->f_max) { 1097 priv->scc_tappos = taps->tap; 1098 priv->scc_tappos_hs400 = use_4tap ? 1099 taps->tap_hs400_4tap : 1100 taps->tap; 1101 hit = true; 1102 break; 1103 } 1104 } 1105 1106 if (!hit) 1107 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1108 1109 host->check_retune = renesas_sdhi_check_scc_error; 1110 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1111 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1112 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1113 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1114 } 1115 1116 num_irqs = platform_irq_count(pdev); 1117 if (num_irqs < 0) { 1118 ret = num_irqs; 1119 goto eirq; 1120 } 1121 1122 /* There must be at least one IRQ source */ 1123 if (!num_irqs) { 1124 ret = -ENXIO; 1125 goto eirq; 1126 } 1127 1128 for (i = 0; i < num_irqs; i++) { 1129 irq = platform_get_irq(pdev, i); 1130 if (irq < 0) { 1131 ret = irq; 1132 goto eirq; 1133 } 1134 1135 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1136 dev_name(&pdev->dev), host); 1137 if (ret) 1138 goto eirq; 1139 } 1140 1141 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1142 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1143 1144 return ret; 1145 1146 eirq: 1147 tmio_mmc_host_remove(host); 1148 edisclk: 1149 renesas_sdhi_clk_disable(host); 1150 efree: 1151 tmio_mmc_host_free(host); 1152 1153 return ret; 1154 } 1155 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1156 1157 int renesas_sdhi_remove(struct platform_device *pdev) 1158 { 1159 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1160 1161 tmio_mmc_host_remove(host); 1162 renesas_sdhi_clk_disable(host); 1163 1164 return 0; 1165 } 1166 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1167 1168 MODULE_LICENSE("GPL v2"); 1169