1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mfd/tmio.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/mmc.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/module.h> 30 #include <linux/of_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pinctrl/pinctrl-state.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_domain.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/reset.h> 37 #include <linux/sh_dma.h> 38 #include <linux/slab.h> 39 #include <linux/sys_soc.h> 40 41 #include "renesas_sdhi.h" 42 #include "tmio_mmc.h" 43 44 #define CTL_HOST_MODE 0xe4 45 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 46 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 47 #define HOST_MODE_GEN3_WMODE BIT(0) 48 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 49 50 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 51 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 52 #define HOST_MODE_GEN3_64BIT 0 53 54 #define CTL_SDIF_MODE 0xe6 55 #define SDIF_MODE_HS400 BIT(0) 56 57 #define SDHI_VER_GEN2_SDR50 0x490c 58 #define SDHI_VER_RZ_A1 0x820b 59 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 60 #define SDHI_VER_GEN2_SDR104 0xcb0d 61 #define SDHI_VER_GEN3_SD 0xcc10 62 #define SDHI_VER_GEN3_SDMMC 0xcd10 63 64 #define SDHI_GEN3_MMC0_ADDR 0xee140000 65 66 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 67 { 68 u32 val; 69 70 /* 71 * see also 72 * renesas_sdhi_of_data :: dma_buswidth 73 */ 74 switch (sd_ctrl_read16(host, CTL_VERSION)) { 75 case SDHI_VER_GEN2_SDR50: 76 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 77 break; 78 case SDHI_VER_GEN2_SDR104: 79 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 80 break; 81 case SDHI_VER_GEN3_SD: 82 case SDHI_VER_GEN3_SDMMC: 83 if (width == 64) 84 val = HOST_MODE_GEN3_64BIT; 85 else if (width == 32) 86 val = HOST_MODE_GEN3_32BIT; 87 else 88 val = HOST_MODE_GEN3_16BIT; 89 break; 90 default: 91 /* nothing to do */ 92 return; 93 } 94 95 sd_ctrl_write16(host, CTL_HOST_MODE, val); 96 } 97 98 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 99 { 100 struct mmc_host *mmc = host->mmc; 101 struct renesas_sdhi *priv = host_to_priv(host); 102 int ret; 103 104 ret = clk_prepare_enable(priv->clk_cd); 105 if (ret < 0) 106 return ret; 107 108 /* 109 * The clock driver may not know what maximum frequency 110 * actually works, so it should be set with the max-frequency 111 * property which will already have been read to f_max. If it 112 * was missing, assume the current frequency is the maximum. 113 */ 114 if (!mmc->f_max) 115 mmc->f_max = clk_get_rate(priv->clk); 116 117 /* 118 * Minimum frequency is the minimum input clock frequency 119 * divided by our maximum divider. 120 */ 121 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 122 123 /* enable 16bit data access on SDBUF as default */ 124 renesas_sdhi_sdbuf_width(host, 16); 125 126 return 0; 127 } 128 129 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 130 unsigned int new_clock) 131 { 132 struct renesas_sdhi *priv = host_to_priv(host); 133 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 134 int i; 135 136 /* 137 * We simply return the current rate if a) we are not on a R-Car Gen2+ 138 * SoC (may work for others, but untested) or b) if the SCC needs its 139 * clock during tuning, so we don't change the external clock setup. 140 */ 141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142 return clk_get_rate(priv->clk); 143 144 /* 145 * We want the bus clock to be as close as possible to, but no 146 * greater than, new_clock. As we can divide by 1 << i for 147 * any i in [0, 9] we want the input clock to be as close as 148 * possible, but no greater than, new_clock << i. 149 */ 150 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 151 freq = clk_round_rate(priv->clk, new_clock << i); 152 if (freq > (new_clock << i)) { 153 /* Too fast; look for a slightly slower option */ 154 freq = clk_round_rate(priv->clk, 155 (new_clock << i) / 4 * 3); 156 if (freq > (new_clock << i)) 157 continue; 158 } 159 160 diff = new_clock - (freq >> i); 161 if (diff <= diff_min) { 162 best_freq = freq; 163 diff_min = diff; 164 } 165 } 166 167 clk_set_rate(priv->clk, best_freq); 168 169 return clk_get_rate(priv->clk); 170 } 171 172 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 173 unsigned int new_clock) 174 { 175 u32 clk = 0, clock; 176 177 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 178 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 179 180 if (new_clock == 0) { 181 host->mmc->actual_clock = 0; 182 goto out; 183 } 184 185 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 186 clock = host->mmc->actual_clock / 512; 187 188 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 189 clock <<= 1; 190 191 /* 1/1 clock is option */ 192 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 193 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 194 clk |= 0xff; 195 else 196 clk &= ~0xff; 197 } 198 199 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 200 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 201 usleep_range(10000, 11000); 202 203 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 204 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 205 206 out: 207 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 209 usleep_range(10000, 11000); 210 } 211 212 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 213 { 214 struct renesas_sdhi *priv = host_to_priv(host); 215 216 clk_disable_unprepare(priv->clk_cd); 217 } 218 219 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 220 { 221 struct tmio_mmc_host *host = mmc_priv(mmc); 222 223 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 224 TMIO_STAT_DAT0); 225 } 226 227 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 228 struct mmc_ios *ios) 229 { 230 struct tmio_mmc_host *host = mmc_priv(mmc); 231 struct renesas_sdhi *priv = host_to_priv(host); 232 struct pinctrl_state *pin_state; 233 int ret; 234 235 switch (ios->signal_voltage) { 236 case MMC_SIGNAL_VOLTAGE_330: 237 pin_state = priv->pins_default; 238 break; 239 case MMC_SIGNAL_VOLTAGE_180: 240 pin_state = priv->pins_uhs; 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 /* 247 * If anything is missing, assume signal voltage is fixed at 248 * 3.3V and succeed/fail accordingly. 249 */ 250 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 251 return ios->signal_voltage == 252 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 253 254 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 255 if (ret < 0) 256 return ret; 257 258 return pinctrl_select_state(priv->pinctrl, pin_state); 259 } 260 261 /* SCC registers */ 262 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 263 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 264 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 265 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 266 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 267 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 268 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 269 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 270 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 271 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 272 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 273 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 274 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 275 276 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 277 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 278 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 279 280 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 281 282 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 283 284 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 285 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 286 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 287 288 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 289 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 290 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 291 292 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 293 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 294 295 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 296 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 297 298 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 299 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 300 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 301 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 302 303 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 304 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 305 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 306 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 307 308 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 309 struct renesas_sdhi *priv, int addr) 310 { 311 return readl(priv->scc_ctl + (addr << host->bus_shift)); 312 } 313 314 static inline void sd_scc_write32(struct tmio_mmc_host *host, 315 struct renesas_sdhi *priv, 316 int addr, u32 val) 317 { 318 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 319 } 320 321 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 322 { 323 struct renesas_sdhi *priv; 324 325 priv = host_to_priv(host); 326 327 /* Initialize SCC */ 328 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 329 330 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 331 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 332 333 /* set sampling clock selection range */ 334 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 335 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 336 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 337 338 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 339 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 340 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 341 342 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 343 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 344 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 345 346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 347 348 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 349 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 350 351 /* Read TAPNUM */ 352 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 353 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 354 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 355 } 356 357 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 358 { 359 struct tmio_mmc_host *host = mmc_priv(mmc); 360 struct renesas_sdhi *priv = host_to_priv(host); 361 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 362 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 363 364 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 365 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 366 367 /* Set HS400 mode */ 368 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 369 sd_ctrl_read16(host, CTL_SDIF_MODE)); 370 371 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 372 priv->scc_tappos_hs400); 373 374 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 375 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 376 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 377 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 378 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 379 380 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 381 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 382 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 383 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 384 385 /* Set the sampling clock selection range of HS400 mode */ 386 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 387 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 388 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 389 390 /* Avoid bad TAP */ 391 if (bad_taps & BIT(priv->tap_set)) { 392 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 393 394 if (bad_taps & BIT(new_tap)) 395 new_tap = (priv->tap_set - 1) % priv->tap_num; 396 397 if (bad_taps & BIT(new_tap)) { 398 new_tap = priv->tap_set; 399 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 400 } 401 402 priv->tap_set = new_tap; 403 } 404 405 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 406 priv->tap_set / (use_4tap ? 2 : 1)); 407 408 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 409 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 410 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 411 412 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 413 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 414 415 if (priv->adjust_hs400_calib_table) 416 priv->needs_adjust_hs400 = true; 417 } 418 419 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 420 { 421 struct tmio_mmc_host *host = mmc_priv(mmc); 422 struct renesas_sdhi *priv = host_to_priv(host); 423 424 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 425 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 426 427 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 428 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 429 sd_scc_read32(host, priv, 430 SH_MOBILE_SDHI_SCC_CKSEL)); 431 432 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 433 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 434 sd_scc_read32(host, priv, 435 SH_MOBILE_SDHI_SCC_DTCNTL)); 436 437 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 438 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 439 } 440 441 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 442 struct renesas_sdhi *priv, u32 addr) 443 { 444 /* read mode */ 445 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 446 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 447 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 448 449 /* access start and stop */ 450 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 451 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 452 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 453 454 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 455 } 456 457 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 458 struct renesas_sdhi *priv, u32 addr, u32 val) 459 { 460 /* write mode */ 461 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 462 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 463 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 464 465 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 466 467 /* access start and stop */ 468 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 469 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 470 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 471 } 472 473 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 474 { 475 struct renesas_sdhi *priv = host_to_priv(host); 476 u32 calib_code; 477 478 /* disable write protect */ 479 sd_scc_tmpport_write32(host, priv, 0x00, 480 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 481 /* read calibration code and adjust */ 482 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 483 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 484 485 sd_scc_tmpport_write32(host, priv, 0x22, 486 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 487 priv->adjust_hs400_calib_table[calib_code]); 488 489 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 490 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 491 492 /* adjustment done, clear flag */ 493 priv->needs_adjust_hs400 = false; 494 } 495 496 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 497 { 498 struct renesas_sdhi *priv = host_to_priv(host); 499 500 /* disable write protect */ 501 sd_scc_tmpport_write32(host, priv, 0x00, 502 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 503 /* disable manual calibration */ 504 sd_scc_tmpport_write32(host, priv, 0x22, 0); 505 /* clear offset value of TMPPORT3 */ 506 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 507 } 508 509 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 510 struct renesas_sdhi *priv) 511 { 512 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 513 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 514 515 /* Reset HS400 mode */ 516 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 517 sd_ctrl_read16(host, CTL_SDIF_MODE)); 518 519 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 520 521 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 522 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 523 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 524 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 525 526 if (priv->adjust_hs400_calib_table) 527 renesas_sdhi_adjust_hs400_mode_disable(host); 528 529 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 530 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 531 } 532 533 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 534 { 535 struct tmio_mmc_host *host = mmc_priv(mmc); 536 537 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 538 return 0; 539 } 540 541 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 542 { 543 renesas_sdhi_disable_scc(host->mmc); 544 renesas_sdhi_reset_hs400_mode(host, priv); 545 priv->needs_adjust_hs400 = false; 546 547 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 548 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 549 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 550 } 551 552 /* only populated for TMIO_MMC_MIN_RCAR2 */ 553 static void renesas_sdhi_reset(struct tmio_mmc_host *host) 554 { 555 struct renesas_sdhi *priv = host_to_priv(host); 556 int ret; 557 u16 val; 558 559 if (priv->rstc) { 560 reset_control_reset(priv->rstc); 561 /* Unknown why but without polling reset status, it will hang */ 562 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 563 false, priv->rstc); 564 priv->needs_adjust_hs400 = false; 565 renesas_sdhi_set_clock(host, host->clk_cache); 566 } else if (priv->scc_ctl) { 567 renesas_sdhi_scc_reset(host, priv); 568 } 569 570 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 571 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 572 val |= CARD_OPT_EXTOP; 573 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 574 } 575 } 576 577 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 578 { 579 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 580 581 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 582 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 583 584 } 585 586 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 587 588 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 589 { 590 struct renesas_sdhi *priv = host_to_priv(host); 591 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 592 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 593 unsigned long *bitmap; 594 595 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 596 597 /* 598 * When tuning CMD19 is issued twice for each tap, merge the 599 * result requiring the tap to be good in both runs before 600 * considering it for tuning selection. 601 */ 602 for (i = 0; i < taps_size; i++) { 603 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 604 605 if (!test_bit(i, priv->taps)) 606 clear_bit(i + offset, priv->taps); 607 608 if (!test_bit(i, priv->smpcmp)) 609 clear_bit(i + offset, priv->smpcmp); 610 } 611 612 /* 613 * If all TAP are OK, the sampling clock position is selected by 614 * identifying the change point of data. 615 */ 616 if (bitmap_full(priv->taps, taps_size)) { 617 bitmap = priv->smpcmp; 618 min_tap_row = 1; 619 } else { 620 bitmap = priv->taps; 621 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 622 } 623 624 /* 625 * Find the longest consecutive run of successful probes. If that 626 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 627 * center index as the tap, otherwise bail out. 628 */ 629 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 630 if (re - rs > tap_cnt) { 631 tap_end = re; 632 tap_start = rs; 633 tap_cnt = tap_end - tap_start; 634 } 635 } 636 637 if (tap_cnt >= min_tap_row) 638 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 639 else 640 return -EIO; 641 642 /* Set SCC */ 643 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 644 645 /* Enable auto re-tuning */ 646 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 647 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 648 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 649 650 return 0; 651 } 652 653 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 654 { 655 struct tmio_mmc_host *host = mmc_priv(mmc); 656 struct renesas_sdhi *priv = host_to_priv(host); 657 int i, ret; 658 659 priv->tap_num = renesas_sdhi_init_tuning(host); 660 if (!priv->tap_num) 661 return 0; /* Tuning is not supported */ 662 663 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 664 dev_err(&host->pdev->dev, 665 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 666 return -EINVAL; 667 } 668 669 bitmap_zero(priv->taps, priv->tap_num * 2); 670 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 671 672 /* Issue CMD19 twice for each tap */ 673 for (i = 0; i < 2 * priv->tap_num; i++) { 674 int cmd_error; 675 676 /* Set sampling clock position */ 677 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 678 679 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 680 set_bit(i, priv->taps); 681 682 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 683 set_bit(i, priv->smpcmp); 684 685 if (cmd_error) 686 mmc_send_abort_tuning(mmc, opcode); 687 } 688 689 ret = renesas_sdhi_select_tuning(host); 690 if (ret < 0) 691 renesas_sdhi_scc_reset(host, priv); 692 return ret; 693 } 694 695 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 696 { 697 struct renesas_sdhi *priv = host_to_priv(host); 698 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 699 u32 val; 700 701 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 702 if (!val) 703 return false; 704 705 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 706 707 /* Change TAP position according to correction status */ 708 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 709 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 710 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 711 /* 712 * With HS400, the DAT signal is based on DS, not CLK. 713 * Therefore, use only CMD status. 714 */ 715 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 716 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 717 if (!smpcmp) { 718 return false; /* no error in CMD signal */ 719 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 720 new_tap++; 721 error_tap--; 722 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 723 new_tap--; 724 error_tap++; 725 } else { 726 return true; /* need retune */ 727 } 728 729 /* 730 * When new_tap is a bad tap, we cannot change. Then, we compare 731 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 732 * we can at least retune. 733 */ 734 if (bad_taps & BIT(new_tap % priv->tap_num)) 735 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 736 } else { 737 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 738 return true; /* need retune */ 739 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 740 new_tap++; 741 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 742 new_tap--; 743 else 744 return false; 745 } 746 747 priv->tap_set = (new_tap % priv->tap_num); 748 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 749 priv->tap_set / (use_4tap ? 2 : 1)); 750 751 return false; 752 } 753 754 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 755 { 756 struct renesas_sdhi *priv = host_to_priv(host); 757 758 /* Check SCC error */ 759 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 760 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 761 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 762 return true; 763 } 764 765 return false; 766 } 767 768 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 769 struct mmc_request *mrq) 770 { 771 struct renesas_sdhi *priv = host_to_priv(host); 772 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 773 bool ret = false; 774 775 /* 776 * Skip checking SCC errors when running on 4 taps in HS400 mode as 777 * any retuning would still result in the same 4 taps being used. 778 */ 779 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 780 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 781 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 782 return false; 783 784 if (mmc_doing_tune(host->mmc)) 785 return false; 786 787 if (((mrq->cmd->error == -ETIMEDOUT) || 788 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 789 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 790 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 791 ret |= true; 792 793 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 794 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 795 ret |= renesas_sdhi_auto_correction(host); 796 else 797 ret |= renesas_sdhi_manual_correction(host, use_4tap); 798 799 return ret; 800 } 801 802 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 803 { 804 int timeout = 1000; 805 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 806 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 807 808 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 809 & bit) == wait_state) 810 udelay(1); 811 812 if (!timeout) { 813 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 814 return -EBUSY; 815 } 816 817 return 0; 818 } 819 820 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 821 { 822 u32 bit = TMIO_STAT_SCLKDIVEN; 823 824 switch (addr) { 825 case CTL_SD_CMD: 826 case CTL_STOP_INTERNAL_ACTION: 827 case CTL_XFER_BLK_COUNT: 828 case CTL_SD_XFER_LEN: 829 case CTL_SD_MEM_CARD_OPT: 830 case CTL_TRANSACTION_CTL: 831 case CTL_DMA_ENABLE: 832 case CTL_HOST_MODE: 833 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 834 bit = TMIO_STAT_CMD_BUSY; 835 fallthrough; 836 case CTL_SD_CARD_CLK_CTL: 837 return renesas_sdhi_wait_idle(host, bit); 838 } 839 840 return 0; 841 } 842 843 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 844 unsigned int direction, int blk_size) 845 { 846 /* 847 * In Renesas controllers, when performing a 848 * multiple block read of one or two blocks, 849 * depending on the timing with which the 850 * response register is read, the response 851 * value may not be read properly. 852 * Use single block read for this HW bug 853 */ 854 if ((direction == MMC_DATA_READ) && 855 blk_size == 2) 856 return 1; 857 858 return blk_size; 859 } 860 861 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 862 { 863 struct renesas_sdhi *priv = host_to_priv(host); 864 865 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 866 renesas_sdhi_adjust_hs400_mode_enable(host); 867 } 868 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 869 { 870 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 871 int width = (host->bus_shift == 2) ? 64 : 32; 872 873 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 874 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 875 } 876 877 int renesas_sdhi_probe(struct platform_device *pdev, 878 const struct tmio_mmc_dma_ops *dma_ops, 879 const struct renesas_sdhi_of_data *of_data, 880 const struct renesas_sdhi_quirks *quirks) 881 { 882 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 883 struct tmio_mmc_data *mmc_data; 884 struct tmio_mmc_dma *dma_priv; 885 struct tmio_mmc_host *host; 886 struct renesas_sdhi *priv; 887 int num_irqs, irq, ret, i; 888 struct resource *res; 889 u16 ver; 890 891 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 892 if (!res) 893 return -EINVAL; 894 895 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 896 GFP_KERNEL); 897 if (!priv) 898 return -ENOMEM; 899 900 priv->quirks = quirks; 901 mmc_data = &priv->mmc_data; 902 dma_priv = &priv->dma_priv; 903 904 priv->clk = devm_clk_get(&pdev->dev, NULL); 905 if (IS_ERR(priv->clk)) { 906 ret = PTR_ERR(priv->clk); 907 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 908 return ret; 909 } 910 911 /* 912 * Some controllers provide a 2nd clock just to run the internal card 913 * detection logic. Unfortunately, the existing driver architecture does 914 * not support a separation of clocks for runtime PM usage. When 915 * native hotplug is used, the tmio driver assumes that the core 916 * must continue to run for card detect to stay active, so we cannot 917 * disable it. 918 * Additionally, it is prohibited to supply a clock to the core but not 919 * to the card detect circuit. That leaves us with if separate clocks 920 * are presented, we must treat them both as virtually 1 clock. 921 */ 922 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 923 if (IS_ERR(priv->clk_cd)) 924 priv->clk_cd = NULL; 925 926 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 927 if (!IS_ERR(priv->pinctrl)) { 928 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 929 PINCTRL_STATE_DEFAULT); 930 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 931 "state_uhs"); 932 } 933 934 host = tmio_mmc_host_alloc(pdev, mmc_data); 935 if (IS_ERR(host)) 936 return PTR_ERR(host); 937 938 if (of_data) { 939 mmc_data->flags |= of_data->tmio_flags; 940 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 941 mmc_data->capabilities |= of_data->capabilities; 942 mmc_data->capabilities2 |= of_data->capabilities2; 943 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 944 mmc_data->max_blk_count = of_data->max_blk_count; 945 mmc_data->max_segs = of_data->max_segs; 946 dma_priv->dma_buswidth = of_data->dma_buswidth; 947 host->bus_shift = of_data->bus_shift; 948 } 949 950 host->write16_hook = renesas_sdhi_write16_hook; 951 host->clk_enable = renesas_sdhi_clk_enable; 952 host->clk_disable = renesas_sdhi_clk_disable; 953 host->set_clock = renesas_sdhi_set_clock; 954 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 955 host->dma_ops = dma_ops; 956 957 if (quirks && quirks->hs400_disabled) 958 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 959 960 /* For some SoC, we disable internal WP. GPIO may override this */ 961 if (mmc_can_gpio_ro(host->mmc)) 962 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 963 964 /* SDR speeds are only available on Gen2+ */ 965 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 966 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 967 host->ops.card_busy = renesas_sdhi_card_busy; 968 host->ops.start_signal_voltage_switch = 969 renesas_sdhi_start_signal_voltage_switch; 970 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 971 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 972 host->reset = renesas_sdhi_reset; 973 } 974 975 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 976 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 977 host->bus_shift = 1; 978 979 if (mmd) 980 *mmc_data = *mmd; 981 982 dma_priv->filter = shdma_chan_filter; 983 dma_priv->enable = renesas_sdhi_enable_dma; 984 985 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 986 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 987 988 /* 989 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 990 * bus width mode. 991 */ 992 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 993 994 /* 995 * All SDHI blocks support SDIO IRQ signalling. 996 */ 997 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 998 999 /* All SDHI have CMD12 control bit */ 1000 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1001 1002 /* All SDHI have SDIO status bits which must be 1 */ 1003 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1004 1005 /* All SDHI support HW busy detection */ 1006 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1007 1008 dev_pm_domain_start(&pdev->dev); 1009 1010 ret = renesas_sdhi_clk_enable(host); 1011 if (ret) 1012 goto efree; 1013 1014 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1015 if (IS_ERR(priv->rstc)) 1016 return PTR_ERR(priv->rstc); 1017 1018 ver = sd_ctrl_read16(host, CTL_VERSION); 1019 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1020 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1021 mmc_data->max_blk_count = U16_MAX; 1022 1023 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1024 if (ver == SDHI_VER_GEN2_SDR50) 1025 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1026 1027 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1028 host->fixup_request = renesas_sdhi_fixup_request; 1029 priv->adjust_hs400_calib_table = *( 1030 res->start == SDHI_GEN3_MMC0_ADDR ? 1031 quirks->hs400_calib_table : 1032 quirks->hs400_calib_table + 1); 1033 } 1034 1035 /* these have an EXTOP bit */ 1036 if (ver >= SDHI_VER_GEN3_SD) 1037 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1038 1039 /* Enable tuning iff we have an SCC and a supported mode */ 1040 if (of_data && of_data->scc_offset && 1041 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1042 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1043 MMC_CAP2_HS400_1_8V))) { 1044 const struct renesas_sdhi_scc *taps = of_data->taps; 1045 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1046 bool hit = false; 1047 1048 for (i = 0; i < of_data->taps_num; i++) { 1049 if (taps[i].clk_rate == 0 || 1050 taps[i].clk_rate == host->mmc->f_max) { 1051 priv->scc_tappos = taps->tap; 1052 priv->scc_tappos_hs400 = use_4tap ? 1053 taps->tap_hs400_4tap : 1054 taps->tap; 1055 hit = true; 1056 break; 1057 } 1058 } 1059 1060 if (!hit) 1061 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1062 1063 priv->scc_ctl = host->ctl + of_data->scc_offset; 1064 host->check_retune = renesas_sdhi_check_scc_error; 1065 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1066 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1067 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1068 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1069 } 1070 1071 ret = tmio_mmc_host_probe(host); 1072 if (ret < 0) 1073 goto edisclk; 1074 1075 num_irqs = platform_irq_count(pdev); 1076 if (num_irqs < 0) { 1077 ret = num_irqs; 1078 goto eirq; 1079 } 1080 1081 /* There must be at least one IRQ source */ 1082 if (!num_irqs) { 1083 ret = -ENXIO; 1084 goto eirq; 1085 } 1086 1087 for (i = 0; i < num_irqs; i++) { 1088 irq = platform_get_irq(pdev, i); 1089 if (irq < 0) { 1090 ret = irq; 1091 goto eirq; 1092 } 1093 1094 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1095 dev_name(&pdev->dev), host); 1096 if (ret) 1097 goto eirq; 1098 } 1099 1100 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1101 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1102 1103 return ret; 1104 1105 eirq: 1106 tmio_mmc_host_remove(host); 1107 edisclk: 1108 renesas_sdhi_clk_disable(host); 1109 efree: 1110 tmio_mmc_host_free(host); 1111 1112 return ret; 1113 } 1114 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1115 1116 int renesas_sdhi_remove(struct platform_device *pdev) 1117 { 1118 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1119 1120 tmio_mmc_host_remove(host); 1121 renesas_sdhi_clk_disable(host); 1122 tmio_mmc_host_free(host); 1123 1124 return 0; 1125 } 1126 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1127 1128 MODULE_LICENSE("GPL v2"); 1129