1b5b6a5f4SSimon Horman /* 29d08428aSSimon Horman * Renesas SDHI 3b5b6a5f4SSimon Horman * 487317c4dSSimon Horman * Copyright (C) 2015-17 Renesas Electronics Corporation 587317c4dSSimon Horman * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 687317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 8b5b6a5f4SSimon Horman * 9b5b6a5f4SSimon Horman * This program is free software; you can redistribute it and/or modify 10b5b6a5f4SSimon Horman * it under the terms of the GNU General Public License version 2 as 11b5b6a5f4SSimon Horman * published by the Free Software Foundation. 12b5b6a5f4SSimon Horman * 13b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 14b5b6a5f4SSimon Horman * 15b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 16b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 17b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 20b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 21b5b6a5f4SSimon Horman * 22b5b6a5f4SSimon Horman */ 23b5b6a5f4SSimon Horman 24b5b6a5f4SSimon Horman #include <linux/kernel.h> 25b5b6a5f4SSimon Horman #include <linux/clk.h> 26b5b6a5f4SSimon Horman #include <linux/slab.h> 27b5b6a5f4SSimon Horman #include <linux/of_device.h> 28b5b6a5f4SSimon Horman #include <linux/platform_device.h> 29b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 30b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 31b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 32b5b6a5f4SSimon Horman #include <linux/delay.h> 33b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 34b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 35b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 36b5b6a5f4SSimon Horman 37b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 38b5b6a5f4SSimon Horman #include "tmio_mmc.h" 39b5b6a5f4SSimon Horman 40b5b6a5f4SSimon Horman #define EXT_ACC 0xe4 41b5b6a5f4SSimon Horman 42b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 43c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 44b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 46b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 47b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 48b5b6a5f4SSimon Horman 492fe35968SSimon Horman #define host_to_priv(host) \ 502fe35968SSimon Horman container_of((host)->pdata, struct renesas_sdhi, mmc_data) 51b5b6a5f4SSimon Horman 52b5b6a5f4SSimon Horman struct renesas_sdhi { 53b5b6a5f4SSimon Horman struct clk *clk; 54b5b6a5f4SSimon Horman struct clk *clk_cd; 55b5b6a5f4SSimon Horman struct tmio_mmc_data mmc_data; 56b5b6a5f4SSimon Horman struct tmio_mmc_dma dma_priv; 57b5b6a5f4SSimon Horman struct pinctrl *pinctrl; 58b5b6a5f4SSimon Horman struct pinctrl_state *pins_default, *pins_uhs; 59b5b6a5f4SSimon Horman void __iomem *scc_ctl; 60b5b6a5f4SSimon Horman }; 61b5b6a5f4SSimon Horman 62b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 63b5b6a5f4SSimon Horman { 64b5b6a5f4SSimon Horman u32 val; 65b5b6a5f4SSimon Horman 66b5b6a5f4SSimon Horman /* 67b5b6a5f4SSimon Horman * see also 68b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 69b5b6a5f4SSimon Horman */ 70b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 71b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 72b5b6a5f4SSimon Horman val = (width == 32) ? 0x0001 : 0x0000; 73b5b6a5f4SSimon Horman break; 74b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 75b5b6a5f4SSimon Horman val = (width == 32) ? 0x0000 : 0x0001; 76b5b6a5f4SSimon Horman break; 77b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 78b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 79b5b6a5f4SSimon Horman if (width == 64) 80b5b6a5f4SSimon Horman val = 0x0000; 81b5b6a5f4SSimon Horman else if (width == 32) 82b5b6a5f4SSimon Horman val = 0x0101; 83b5b6a5f4SSimon Horman else 84b5b6a5f4SSimon Horman val = 0x0001; 85b5b6a5f4SSimon Horman break; 86b5b6a5f4SSimon Horman default: 87b5b6a5f4SSimon Horman /* nothing to do */ 88b5b6a5f4SSimon Horman return; 89b5b6a5f4SSimon Horman } 90b5b6a5f4SSimon Horman 91b5b6a5f4SSimon Horman sd_ctrl_write16(host, EXT_ACC, val); 92b5b6a5f4SSimon Horman } 93b5b6a5f4SSimon Horman 94b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 95b5b6a5f4SSimon Horman { 96b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 97b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 98b5b6a5f4SSimon Horman int ret = clk_prepare_enable(priv->clk); 992fe35968SSimon Horman 100b5b6a5f4SSimon Horman if (ret < 0) 101b5b6a5f4SSimon Horman return ret; 102b5b6a5f4SSimon Horman 103b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 104b5b6a5f4SSimon Horman if (ret < 0) { 105b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 106b5b6a5f4SSimon Horman return ret; 107b5b6a5f4SSimon Horman } 108b5b6a5f4SSimon Horman 109b5b6a5f4SSimon Horman /* 110b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 111b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 112b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 113b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 114b5b6a5f4SSimon Horman */ 115b5b6a5f4SSimon Horman if (!mmc->f_max) 116b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 117b5b6a5f4SSimon Horman 118b5b6a5f4SSimon Horman /* 119b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 120b5b6a5f4SSimon Horman * divided by our maximum divider. 121b5b6a5f4SSimon Horman */ 122b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 123b5b6a5f4SSimon Horman 124b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 125b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 126b5b6a5f4SSimon Horman 127b5b6a5f4SSimon Horman return 0; 128b5b6a5f4SSimon Horman } 129b5b6a5f4SSimon Horman 130b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 131b5b6a5f4SSimon Horman unsigned int new_clock) 132b5b6a5f4SSimon Horman { 133b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 134b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 135b5b6a5f4SSimon Horman int i, ret; 136b5b6a5f4SSimon Horman 137d63c2bf4SWolfram Sang /* tested only on R-Car Gen2+ currently; may work for others */ 138b5b6a5f4SSimon Horman if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 139b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 140b5b6a5f4SSimon Horman 141b5b6a5f4SSimon Horman /* 142b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 143b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 144b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 145b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 146b5b6a5f4SSimon Horman */ 147b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 148b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 149b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 150b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 151b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 152b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 153b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 154b5b6a5f4SSimon Horman continue; 155b5b6a5f4SSimon Horman } 156b5b6a5f4SSimon Horman 157b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 158b5b6a5f4SSimon Horman if (diff <= diff_min) { 159b5b6a5f4SSimon Horman best_freq = freq; 160b5b6a5f4SSimon Horman diff_min = diff; 161b5b6a5f4SSimon Horman } 162b5b6a5f4SSimon Horman } 163b5b6a5f4SSimon Horman 164b5b6a5f4SSimon Horman ret = clk_set_rate(priv->clk, best_freq); 165b5b6a5f4SSimon Horman 166b5b6a5f4SSimon Horman return ret == 0 ? best_freq : clk_get_rate(priv->clk); 167b5b6a5f4SSimon Horman } 168b5b6a5f4SSimon Horman 169b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 170b5b6a5f4SSimon Horman { 171b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 172b5b6a5f4SSimon Horman 173b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 174b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 175b5b6a5f4SSimon Horman } 176b5b6a5f4SSimon Horman 177b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 178b5b6a5f4SSimon Horman { 179b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 180b5b6a5f4SSimon Horman 1812fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 1822fe35968SSimon Horman TMIO_STAT_DAT0); 183b5b6a5f4SSimon Horman } 184b5b6a5f4SSimon Horman 185b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 186b5b6a5f4SSimon Horman struct mmc_ios *ios) 187b5b6a5f4SSimon Horman { 188b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 189b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 190b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 191b5b6a5f4SSimon Horman int ret; 192b5b6a5f4SSimon Horman 193b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 194b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 195b5b6a5f4SSimon Horman pin_state = priv->pins_default; 196b5b6a5f4SSimon Horman break; 197b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 198b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 199b5b6a5f4SSimon Horman break; 200b5b6a5f4SSimon Horman default: 201b5b6a5f4SSimon Horman return -EINVAL; 202b5b6a5f4SSimon Horman } 203b5b6a5f4SSimon Horman 204b5b6a5f4SSimon Horman /* 205b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 206b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 207b5b6a5f4SSimon Horman */ 208b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 209b5b6a5f4SSimon Horman return ios->signal_voltage == 210b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 211b5b6a5f4SSimon Horman 212b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 213b5b6a5f4SSimon Horman if (ret) 214b5b6a5f4SSimon Horman return ret; 215b5b6a5f4SSimon Horman 216b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 217b5b6a5f4SSimon Horman } 218b5b6a5f4SSimon Horman 219b5b6a5f4SSimon Horman /* SCC registers */ 220b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 221b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 222b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 223b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 224b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 225b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 226b5b6a5f4SSimon Horman 227b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 228b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 229b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 230b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 231b5b6a5f4SSimon Horman 232b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 233b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 234b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 235b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 236b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 237b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 238b5b6a5f4SSimon Horman 239b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 240b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 241b5b6a5f4SSimon Horman { 242b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 243b5b6a5f4SSimon Horman } 244b5b6a5f4SSimon Horman 245b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 246b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 247b5b6a5f4SSimon Horman int addr, u32 val) 248b5b6a5f4SSimon Horman { 249b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 250b5b6a5f4SSimon Horman } 251b5b6a5f4SSimon Horman 252b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 253b5b6a5f4SSimon Horman { 254b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 255b5b6a5f4SSimon Horman 256b5b6a5f4SSimon Horman priv = host_to_priv(host); 257b5b6a5f4SSimon Horman 258b5b6a5f4SSimon Horman /* set sampling clock selection range */ 259b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 260b5b6a5f4SSimon Horman 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 261b5b6a5f4SSimon Horman 262b5b6a5f4SSimon Horman /* Initialize SCC */ 263b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 264b5b6a5f4SSimon Horman 265b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 266b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 267b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); 268b5b6a5f4SSimon Horman 269b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 270b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 271b5b6a5f4SSimon Horman 272b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 273b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 274b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 275b5b6a5f4SSimon Horman 276b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 277b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 278b5b6a5f4SSimon Horman 279b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 280b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 281b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 282b5b6a5f4SSimon Horman 283b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos); 284b5b6a5f4SSimon Horman 285b5b6a5f4SSimon Horman /* Read TAPNUM */ 286b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 287b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 288b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 289b5b6a5f4SSimon Horman } 290b5b6a5f4SSimon Horman 291b5b6a5f4SSimon Horman static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 292b5b6a5f4SSimon Horman unsigned long tap) 293b5b6a5f4SSimon Horman { 294b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 295b5b6a5f4SSimon Horman 296b5b6a5f4SSimon Horman /* Set sampling clock position */ 297b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 298b5b6a5f4SSimon Horman } 299b5b6a5f4SSimon Horman 300b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_MAX_TAP 3 301b5b6a5f4SSimon Horman 302b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 303b5b6a5f4SSimon Horman { 304b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 305b5b6a5f4SSimon Horman unsigned long tap_cnt; /* counter of tuning success */ 306b5b6a5f4SSimon Horman unsigned long tap_set; /* tap position */ 307b5b6a5f4SSimon Horman unsigned long tap_start;/* start position of tuning success */ 308b5b6a5f4SSimon Horman unsigned long tap_end; /* end position of tuning success */ 309b5b6a5f4SSimon Horman unsigned long ntap; /* temporary counter of tuning success */ 310b5b6a5f4SSimon Horman unsigned long i; 311b5b6a5f4SSimon Horman 312b5b6a5f4SSimon Horman /* Clear SCC_RVSREQ */ 313b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 314b5b6a5f4SSimon Horman 315b5b6a5f4SSimon Horman /* 316b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 317b5b6a5f4SSimon Horman * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 318b5b6a5f4SSimon Horman * center index as the tap. 319b5b6a5f4SSimon Horman */ 320b5b6a5f4SSimon Horman tap_cnt = 0; 321b5b6a5f4SSimon Horman ntap = 0; 322b5b6a5f4SSimon Horman tap_start = 0; 323b5b6a5f4SSimon Horman tap_end = 0; 324b5b6a5f4SSimon Horman for (i = 0; i < host->tap_num * 2; i++) { 3252fe35968SSimon Horman if (test_bit(i, host->taps)) { 326b5b6a5f4SSimon Horman ntap++; 3272fe35968SSimon Horman } else { 328b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 329b5b6a5f4SSimon Horman tap_start = i - ntap; 330b5b6a5f4SSimon Horman tap_end = i - 1; 331b5b6a5f4SSimon Horman tap_cnt = ntap; 332b5b6a5f4SSimon Horman } 333b5b6a5f4SSimon Horman ntap = 0; 334b5b6a5f4SSimon Horman } 335b5b6a5f4SSimon Horman } 336b5b6a5f4SSimon Horman 337b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 338b5b6a5f4SSimon Horman tap_start = i - ntap; 339b5b6a5f4SSimon Horman tap_end = i - 1; 340b5b6a5f4SSimon Horman tap_cnt = ntap; 341b5b6a5f4SSimon Horman } 342b5b6a5f4SSimon Horman 343b5b6a5f4SSimon Horman if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 344b5b6a5f4SSimon Horman tap_set = (tap_start + tap_end) / 2 % host->tap_num; 345b5b6a5f4SSimon Horman else 346b5b6a5f4SSimon Horman return -EIO; 347b5b6a5f4SSimon Horman 348b5b6a5f4SSimon Horman /* Set SCC */ 349b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); 350b5b6a5f4SSimon Horman 351b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 352b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 353b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 354b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 355b5b6a5f4SSimon Horman 356b5b6a5f4SSimon Horman return 0; 357b5b6a5f4SSimon Horman } 358b5b6a5f4SSimon Horman 359b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 360b5b6a5f4SSimon Horman { 361b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 362b5b6a5f4SSimon Horman 363b5b6a5f4SSimon Horman /* Check SCC error */ 364b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 365b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 366b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 367b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 368b5b6a5f4SSimon Horman /* Clear SCC error */ 369b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 370b5b6a5f4SSimon Horman return true; 371b5b6a5f4SSimon Horman } 372b5b6a5f4SSimon Horman 373b5b6a5f4SSimon Horman return false; 374b5b6a5f4SSimon Horman } 375b5b6a5f4SSimon Horman 376b5b6a5f4SSimon Horman static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 377b5b6a5f4SSimon Horman { 378b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 379b5b6a5f4SSimon Horman 380b5b6a5f4SSimon Horman priv = host_to_priv(host); 381b5b6a5f4SSimon Horman 382b5b6a5f4SSimon Horman /* Reset SCC */ 383b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 384b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 385b5b6a5f4SSimon Horman 386b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 387b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 388b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 389b5b6a5f4SSimon Horman 390b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 391b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 392b5b6a5f4SSimon Horman 393b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 394b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 395b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 396b5b6a5f4SSimon Horman 397b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 398b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 399b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 400b5b6a5f4SSimon Horman } 401b5b6a5f4SSimon Horman 4024dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 403b5b6a5f4SSimon Horman { 404b5b6a5f4SSimon Horman int timeout = 1000; 4054dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 4064dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 407b5b6a5f4SSimon Horman 4084dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 4094dc48a95SWolfram Sang & bit) == wait_state) 410b5b6a5f4SSimon Horman udelay(1); 411b5b6a5f4SSimon Horman 412b5b6a5f4SSimon Horman if (!timeout) { 413b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 414b5b6a5f4SSimon Horman return -EBUSY; 415b5b6a5f4SSimon Horman } 416b5b6a5f4SSimon Horman 417b5b6a5f4SSimon Horman return 0; 418b5b6a5f4SSimon Horman } 419b5b6a5f4SSimon Horman 420b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 421b5b6a5f4SSimon Horman { 4224dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 4234dc48a95SWolfram Sang 4242fe35968SSimon Horman switch (addr) { 425b5b6a5f4SSimon Horman case CTL_SD_CMD: 426b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 427b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 428b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 429b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 430b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 431b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 432b5b6a5f4SSimon Horman case EXT_ACC: 4335124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 4344dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 4354dc48a95SWolfram Sang /* fallthrough */ 4364dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 4374dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 438b5b6a5f4SSimon Horman } 439b5b6a5f4SSimon Horman 440b5b6a5f4SSimon Horman return 0; 441b5b6a5f4SSimon Horman } 442b5b6a5f4SSimon Horman 443b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 444b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 445b5b6a5f4SSimon Horman { 446b5b6a5f4SSimon Horman /* 447b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 448b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 449b5b6a5f4SSimon Horman * depending on the timing with which the 450b5b6a5f4SSimon Horman * response register is read, the response 451b5b6a5f4SSimon Horman * value may not be read properly. 452b5b6a5f4SSimon Horman * Use single block read for this HW bug 453b5b6a5f4SSimon Horman */ 454b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 455b5b6a5f4SSimon Horman blk_size == 2) 456b5b6a5f4SSimon Horman return 1; 457b5b6a5f4SSimon Horman 458b5b6a5f4SSimon Horman return blk_size; 459b5b6a5f4SSimon Horman } 460b5b6a5f4SSimon Horman 461b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 462b5b6a5f4SSimon Horman { 4635af02d32SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 464b5b6a5f4SSimon Horman 465b5b6a5f4SSimon Horman /* enable 32bit access if DMA mode if possibile */ 466b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, enable ? 32 : 16); 467b5b6a5f4SSimon Horman } 468b5b6a5f4SSimon Horman 4699d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 4709d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 471b5b6a5f4SSimon Horman { 472b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 4732fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 4742fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 4752fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 476b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 4772fe35968SSimon Horman struct renesas_sdhi *priv; 478b5b6a5f4SSimon Horman struct resource *res; 479b5b6a5f4SSimon Horman int irq, ret, i; 4802fe35968SSimon Horman 4812fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 482b5b6a5f4SSimon Horman 483b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 484b5b6a5f4SSimon Horman if (!res) 485b5b6a5f4SSimon Horman return -EINVAL; 486b5b6a5f4SSimon Horman 4872fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 4882fe35968SSimon Horman GFP_KERNEL); 489b5b6a5f4SSimon Horman if (!priv) 490b5b6a5f4SSimon Horman return -ENOMEM; 491b5b6a5f4SSimon Horman 492b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 493b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 494b5b6a5f4SSimon Horman 495b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 496b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 497b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 498b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 499b5b6a5f4SSimon Horman goto eprobe; 500b5b6a5f4SSimon Horman } 501b5b6a5f4SSimon Horman 502b5b6a5f4SSimon Horman /* 503b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 504b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 505b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 506b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 507b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 508b5b6a5f4SSimon Horman * disable it. 509b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 510b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 511b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 512b5b6a5f4SSimon Horman */ 513b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 514b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 515b5b6a5f4SSimon Horman priv->clk_cd = NULL; 516b5b6a5f4SSimon Horman 517b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 518b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 519b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 520b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 521b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 522b5b6a5f4SSimon Horman "state_uhs"); 523b5b6a5f4SSimon Horman } 524b5b6a5f4SSimon Horman 525b5b6a5f4SSimon Horman host = tmio_mmc_host_alloc(pdev); 526b5b6a5f4SSimon Horman if (!host) { 527b5b6a5f4SSimon Horman ret = -ENOMEM; 528b5b6a5f4SSimon Horman goto eprobe; 529b5b6a5f4SSimon Horman } 530b5b6a5f4SSimon Horman 531b5b6a5f4SSimon Horman if (of_data) { 532b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 533b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 534b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 535b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 536b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 537603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 538603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 539b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 540b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 541b5b6a5f4SSimon Horman } 542b5b6a5f4SSimon Horman 543b5b6a5f4SSimon Horman host->dma = dma_priv; 544b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 545b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 546b5b6a5f4SSimon Horman host->clk_update = renesas_sdhi_clk_update; 547b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 548b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 549b5b6a5f4SSimon Horman 550b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 551b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 552b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 553b5b6a5f4SSimon Horman host->card_busy = renesas_sdhi_card_busy; 554b5b6a5f4SSimon Horman host->start_signal_voltage_switch = 555b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 556b5b6a5f4SSimon Horman } 557b5b6a5f4SSimon Horman 558b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 559b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 560b5b6a5f4SSimon Horman host->bus_shift = 1; 561b5b6a5f4SSimon Horman 562b5b6a5f4SSimon Horman if (mmd) 563b5b6a5f4SSimon Horman *mmc_data = *mmd; 564b5b6a5f4SSimon Horman 565b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 566b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 567b5b6a5f4SSimon Horman 568b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 569b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 570b5b6a5f4SSimon Horman 571b5b6a5f4SSimon Horman /* 572b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 573b5b6a5f4SSimon Horman * bus width mode. 574b5b6a5f4SSimon Horman */ 575b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 576b5b6a5f4SSimon Horman 577b5b6a5f4SSimon Horman /* 578b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 579b5b6a5f4SSimon Horman */ 580b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 581b5b6a5f4SSimon Horman 5822fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 583b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 584b5b6a5f4SSimon Horman 585b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 586b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 587b5b6a5f4SSimon Horman 5889d08428aSSimon Horman ret = tmio_mmc_host_probe(host, mmc_data, dma_ops); 589b5b6a5f4SSimon Horman if (ret < 0) 590b5b6a5f4SSimon Horman goto efree; 591b5b6a5f4SSimon Horman 5925124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 5935124b592SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 5945124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 5955124b592SWolfram Sang 596b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 597b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 598b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 599b5b6a5f4SSimon Horman host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { 600b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 601b5b6a5f4SSimon Horman bool hit = false; 602b5b6a5f4SSimon Horman 603b5b6a5f4SSimon Horman host->mmc->caps |= MMC_CAP_HW_RESET; 604b5b6a5f4SSimon Horman 605b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 606b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 607b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 608b5b6a5f4SSimon Horman host->scc_tappos = taps->tap; 609b5b6a5f4SSimon Horman hit = true; 610b5b6a5f4SSimon Horman break; 611b5b6a5f4SSimon Horman } 612b5b6a5f4SSimon Horman } 613b5b6a5f4SSimon Horman 614b5b6a5f4SSimon Horman if (!hit) 615b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 616b5b6a5f4SSimon Horman 617b5b6a5f4SSimon Horman priv->scc_ctl = host->ctl + of_data->scc_offset; 618b5b6a5f4SSimon Horman host->init_tuning = renesas_sdhi_init_tuning; 619b5b6a5f4SSimon Horman host->prepare_tuning = renesas_sdhi_prepare_tuning; 620b5b6a5f4SSimon Horman host->select_tuning = renesas_sdhi_select_tuning; 621b5b6a5f4SSimon Horman host->check_scc_error = renesas_sdhi_check_scc_error; 622b5b6a5f4SSimon Horman host->hw_reset = renesas_sdhi_hw_reset; 623b5b6a5f4SSimon Horman } 624b5b6a5f4SSimon Horman 625b5b6a5f4SSimon Horman i = 0; 626b5b6a5f4SSimon Horman while (1) { 627b5b6a5f4SSimon Horman irq = platform_get_irq(pdev, i); 628b5b6a5f4SSimon Horman if (irq < 0) 629b5b6a5f4SSimon Horman break; 630b5b6a5f4SSimon Horman i++; 631b5b6a5f4SSimon Horman ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 632b5b6a5f4SSimon Horman dev_name(&pdev->dev), host); 633b5b6a5f4SSimon Horman if (ret) 634b5b6a5f4SSimon Horman goto eirq; 635b5b6a5f4SSimon Horman } 636b5b6a5f4SSimon Horman 637b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 638b5b6a5f4SSimon Horman if (!i) { 639b5b6a5f4SSimon Horman ret = irq; 640b5b6a5f4SSimon Horman goto eirq; 641b5b6a5f4SSimon Horman } 642b5b6a5f4SSimon Horman 643b5b6a5f4SSimon Horman dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 644b5b6a5f4SSimon Horman mmc_hostname(host->mmc), (unsigned long) 645b5b6a5f4SSimon Horman (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 646b5b6a5f4SSimon Horman host->mmc->f_max / 1000000); 647b5b6a5f4SSimon Horman 648b5b6a5f4SSimon Horman return ret; 649b5b6a5f4SSimon Horman 650b5b6a5f4SSimon Horman eirq: 651b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 652b5b6a5f4SSimon Horman efree: 653b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 654b5b6a5f4SSimon Horman eprobe: 655b5b6a5f4SSimon Horman return ret; 656b5b6a5f4SSimon Horman } 6579d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 658b5b6a5f4SSimon Horman 6599d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 660b5b6a5f4SSimon Horman { 661b5b6a5f4SSimon Horman struct mmc_host *mmc = platform_get_drvdata(pdev); 662b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 663b5b6a5f4SSimon Horman 664b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 665b5b6a5f4SSimon Horman 666b5b6a5f4SSimon Horman return 0; 667b5b6a5f4SSimon Horman } 6689d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 669