1b5b6a5f4SSimon Horman /* 29d08428aSSimon Horman * Renesas SDHI 3b5b6a5f4SSimon Horman * 487317c4dSSimon Horman * Copyright (C) 2015-17 Renesas Electronics Corporation 587317c4dSSimon Horman * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 687317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 8b5b6a5f4SSimon Horman * 9b5b6a5f4SSimon Horman * This program is free software; you can redistribute it and/or modify 10b5b6a5f4SSimon Horman * it under the terms of the GNU General Public License version 2 as 11b5b6a5f4SSimon Horman * published by the Free Software Foundation. 12b5b6a5f4SSimon Horman * 13b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 14b5b6a5f4SSimon Horman * 15b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 16b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 17b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 20b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 21b5b6a5f4SSimon Horman * 22b5b6a5f4SSimon Horman */ 23b5b6a5f4SSimon Horman 24b5b6a5f4SSimon Horman #include <linux/kernel.h> 25b5b6a5f4SSimon Horman #include <linux/clk.h> 26b5b6a5f4SSimon Horman #include <linux/slab.h> 27967a6a07SMasaharu Hayakawa #include <linux/module.h> 28b5b6a5f4SSimon Horman #include <linux/of_device.h> 29b5b6a5f4SSimon Horman #include <linux/platform_device.h> 30b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 31b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 32b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 33b5b6a5f4SSimon Horman #include <linux/delay.h> 34b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 35b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 36b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 37b5b6a5f4SSimon Horman 38b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 39b5b6a5f4SSimon Horman #include "tmio_mmc.h" 40b5b6a5f4SSimon Horman 41b5b6a5f4SSimon Horman #define EXT_ACC 0xe4 42b5b6a5f4SSimon Horman 43b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 44c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 45b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 46b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 47b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 48b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 49b5b6a5f4SSimon Horman 50b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 51b5b6a5f4SSimon Horman { 52b5b6a5f4SSimon Horman u32 val; 53b5b6a5f4SSimon Horman 54b5b6a5f4SSimon Horman /* 55b5b6a5f4SSimon Horman * see also 56b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 57b5b6a5f4SSimon Horman */ 58b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 59b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 60b5b6a5f4SSimon Horman val = (width == 32) ? 0x0001 : 0x0000; 61b5b6a5f4SSimon Horman break; 62b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 63b5b6a5f4SSimon Horman val = (width == 32) ? 0x0000 : 0x0001; 64b5b6a5f4SSimon Horman break; 65b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 66b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 67b5b6a5f4SSimon Horman if (width == 64) 68b5b6a5f4SSimon Horman val = 0x0000; 69b5b6a5f4SSimon Horman else if (width == 32) 70b5b6a5f4SSimon Horman val = 0x0101; 71b5b6a5f4SSimon Horman else 72b5b6a5f4SSimon Horman val = 0x0001; 73b5b6a5f4SSimon Horman break; 74b5b6a5f4SSimon Horman default: 75b5b6a5f4SSimon Horman /* nothing to do */ 76b5b6a5f4SSimon Horman return; 77b5b6a5f4SSimon Horman } 78b5b6a5f4SSimon Horman 79b5b6a5f4SSimon Horman sd_ctrl_write16(host, EXT_ACC, val); 80b5b6a5f4SSimon Horman } 81b5b6a5f4SSimon Horman 82b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 83b5b6a5f4SSimon Horman { 84b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 85b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 86b5b6a5f4SSimon Horman int ret = clk_prepare_enable(priv->clk); 872fe35968SSimon Horman 88b5b6a5f4SSimon Horman if (ret < 0) 89b5b6a5f4SSimon Horman return ret; 90b5b6a5f4SSimon Horman 91b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 92b5b6a5f4SSimon Horman if (ret < 0) { 93b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 94b5b6a5f4SSimon Horman return ret; 95b5b6a5f4SSimon Horman } 96b5b6a5f4SSimon Horman 97b5b6a5f4SSimon Horman /* 98b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 99b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 100b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 101b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 102b5b6a5f4SSimon Horman */ 103b5b6a5f4SSimon Horman if (!mmc->f_max) 104b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 105b5b6a5f4SSimon Horman 106b5b6a5f4SSimon Horman /* 107b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 108b5b6a5f4SSimon Horman * divided by our maximum divider. 109b5b6a5f4SSimon Horman */ 110b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 111b5b6a5f4SSimon Horman 112b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 113b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 114b5b6a5f4SSimon Horman 115b5b6a5f4SSimon Horman return 0; 116b5b6a5f4SSimon Horman } 117b5b6a5f4SSimon Horman 118b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 119b5b6a5f4SSimon Horman unsigned int new_clock) 120b5b6a5f4SSimon Horman { 121b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 122b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 123b5b6a5f4SSimon Horman int i, ret; 124b5b6a5f4SSimon Horman 125d63c2bf4SWolfram Sang /* tested only on R-Car Gen2+ currently; may work for others */ 126b5b6a5f4SSimon Horman if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 127b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 128b5b6a5f4SSimon Horman 129b5b6a5f4SSimon Horman /* 130b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 131b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 132b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 133b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 134b5b6a5f4SSimon Horman */ 135b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 136b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 137b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 138b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 139b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 140b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 141b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 142b5b6a5f4SSimon Horman continue; 143b5b6a5f4SSimon Horman } 144b5b6a5f4SSimon Horman 145b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 146b5b6a5f4SSimon Horman if (diff <= diff_min) { 147b5b6a5f4SSimon Horman best_freq = freq; 148b5b6a5f4SSimon Horman diff_min = diff; 149b5b6a5f4SSimon Horman } 150b5b6a5f4SSimon Horman } 151b5b6a5f4SSimon Horman 152b5b6a5f4SSimon Horman ret = clk_set_rate(priv->clk, best_freq); 153b5b6a5f4SSimon Horman 154b5b6a5f4SSimon Horman return ret == 0 ? best_freq : clk_get_rate(priv->clk); 155b5b6a5f4SSimon Horman } 156b5b6a5f4SSimon Horman 157b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 158b5b6a5f4SSimon Horman { 159b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 160b5b6a5f4SSimon Horman 161b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 162b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 163b5b6a5f4SSimon Horman } 164b5b6a5f4SSimon Horman 165b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 166b5b6a5f4SSimon Horman { 167b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 168b5b6a5f4SSimon Horman 1692fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 1702fe35968SSimon Horman TMIO_STAT_DAT0); 171b5b6a5f4SSimon Horman } 172b5b6a5f4SSimon Horman 173b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 174b5b6a5f4SSimon Horman struct mmc_ios *ios) 175b5b6a5f4SSimon Horman { 176b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 177b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 178b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 179b5b6a5f4SSimon Horman int ret; 180b5b6a5f4SSimon Horman 181b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 182b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 183b5b6a5f4SSimon Horman pin_state = priv->pins_default; 184b5b6a5f4SSimon Horman break; 185b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 186b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 187b5b6a5f4SSimon Horman break; 188b5b6a5f4SSimon Horman default: 189b5b6a5f4SSimon Horman return -EINVAL; 190b5b6a5f4SSimon Horman } 191b5b6a5f4SSimon Horman 192b5b6a5f4SSimon Horman /* 193b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 194b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 195b5b6a5f4SSimon Horman */ 196b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 197b5b6a5f4SSimon Horman return ios->signal_voltage == 198b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 199b5b6a5f4SSimon Horman 200b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 201b5b6a5f4SSimon Horman if (ret) 202b5b6a5f4SSimon Horman return ret; 203b5b6a5f4SSimon Horman 204b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 205b5b6a5f4SSimon Horman } 206b5b6a5f4SSimon Horman 207b5b6a5f4SSimon Horman /* SCC registers */ 208b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 209b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 210b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 211b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 212b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 213b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 214b5b6a5f4SSimon Horman 215b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 216b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 217b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 218b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 219b5b6a5f4SSimon Horman 220b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 221b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 222b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 223b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 224b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 225b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 226b5b6a5f4SSimon Horman 227b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 228b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 229b5b6a5f4SSimon Horman { 230b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 231b5b6a5f4SSimon Horman } 232b5b6a5f4SSimon Horman 233b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 234b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 235b5b6a5f4SSimon Horman int addr, u32 val) 236b5b6a5f4SSimon Horman { 237b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 238b5b6a5f4SSimon Horman } 239b5b6a5f4SSimon Horman 240b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 241b5b6a5f4SSimon Horman { 242b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 243b5b6a5f4SSimon Horman 244b5b6a5f4SSimon Horman priv = host_to_priv(host); 245b5b6a5f4SSimon Horman 246b5b6a5f4SSimon Horman /* set sampling clock selection range */ 247b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 248b5b6a5f4SSimon Horman 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 249b5b6a5f4SSimon Horman 250b5b6a5f4SSimon Horman /* Initialize SCC */ 251b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 252b5b6a5f4SSimon Horman 253b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 254b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 255b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); 256b5b6a5f4SSimon Horman 257b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 258b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 259b5b6a5f4SSimon Horman 260b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 261b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 262b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 263b5b6a5f4SSimon Horman 264b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 265b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 266b5b6a5f4SSimon Horman 267b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 268b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 269b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 270b5b6a5f4SSimon Horman 271852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 272b5b6a5f4SSimon Horman 273b5b6a5f4SSimon Horman /* Read TAPNUM */ 274b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 275b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 276b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 277b5b6a5f4SSimon Horman } 278b5b6a5f4SSimon Horman 279b5b6a5f4SSimon Horman static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 280b5b6a5f4SSimon Horman unsigned long tap) 281b5b6a5f4SSimon Horman { 282b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 283b5b6a5f4SSimon Horman 284b5b6a5f4SSimon Horman /* Set sampling clock position */ 285b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 286b5b6a5f4SSimon Horman } 287b5b6a5f4SSimon Horman 288b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_MAX_TAP 3 289b5b6a5f4SSimon Horman 290b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 291b5b6a5f4SSimon Horman { 292b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 293b5b6a5f4SSimon Horman unsigned long tap_cnt; /* counter of tuning success */ 294b5b6a5f4SSimon Horman unsigned long tap_set; /* tap position */ 295b5b6a5f4SSimon Horman unsigned long tap_start;/* start position of tuning success */ 296b5b6a5f4SSimon Horman unsigned long tap_end; /* end position of tuning success */ 297b5b6a5f4SSimon Horman unsigned long ntap; /* temporary counter of tuning success */ 298b5b6a5f4SSimon Horman unsigned long i; 299b5b6a5f4SSimon Horman 300b5b6a5f4SSimon Horman /* Clear SCC_RVSREQ */ 301b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 302b5b6a5f4SSimon Horman 303b5b6a5f4SSimon Horman /* 304b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 305b5b6a5f4SSimon Horman * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 306b5b6a5f4SSimon Horman * center index as the tap. 307b5b6a5f4SSimon Horman */ 308b5b6a5f4SSimon Horman tap_cnt = 0; 309b5b6a5f4SSimon Horman ntap = 0; 310b5b6a5f4SSimon Horman tap_start = 0; 311b5b6a5f4SSimon Horman tap_end = 0; 312b5b6a5f4SSimon Horman for (i = 0; i < host->tap_num * 2; i++) { 3132fe35968SSimon Horman if (test_bit(i, host->taps)) { 314b5b6a5f4SSimon Horman ntap++; 3152fe35968SSimon Horman } else { 316b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 317b5b6a5f4SSimon Horman tap_start = i - ntap; 318b5b6a5f4SSimon Horman tap_end = i - 1; 319b5b6a5f4SSimon Horman tap_cnt = ntap; 320b5b6a5f4SSimon Horman } 321b5b6a5f4SSimon Horman ntap = 0; 322b5b6a5f4SSimon Horman } 323b5b6a5f4SSimon Horman } 324b5b6a5f4SSimon Horman 325b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 326b5b6a5f4SSimon Horman tap_start = i - ntap; 327b5b6a5f4SSimon Horman tap_end = i - 1; 328b5b6a5f4SSimon Horman tap_cnt = ntap; 329b5b6a5f4SSimon Horman } 330b5b6a5f4SSimon Horman 331b5b6a5f4SSimon Horman if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 332b5b6a5f4SSimon Horman tap_set = (tap_start + tap_end) / 2 % host->tap_num; 333b5b6a5f4SSimon Horman else 334b5b6a5f4SSimon Horman return -EIO; 335b5b6a5f4SSimon Horman 336b5b6a5f4SSimon Horman /* Set SCC */ 337b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set); 338b5b6a5f4SSimon Horman 339b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 340b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 341b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 342b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 343b5b6a5f4SSimon Horman 344b5b6a5f4SSimon Horman return 0; 345b5b6a5f4SSimon Horman } 346b5b6a5f4SSimon Horman 347b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 348b5b6a5f4SSimon Horman { 349b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 350b5b6a5f4SSimon Horman 351b5b6a5f4SSimon Horman /* Check SCC error */ 352b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 353b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 354b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 355b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 356b5b6a5f4SSimon Horman /* Clear SCC error */ 357b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 358b5b6a5f4SSimon Horman return true; 359b5b6a5f4SSimon Horman } 360b5b6a5f4SSimon Horman 361b5b6a5f4SSimon Horman return false; 362b5b6a5f4SSimon Horman } 363b5b6a5f4SSimon Horman 364b5b6a5f4SSimon Horman static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 365b5b6a5f4SSimon Horman { 366b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 367b5b6a5f4SSimon Horman 368b5b6a5f4SSimon Horman priv = host_to_priv(host); 369b5b6a5f4SSimon Horman 370b5b6a5f4SSimon Horman /* Reset SCC */ 371b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 372b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 373b5b6a5f4SSimon Horman 374b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 375b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 376b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 377b5b6a5f4SSimon Horman 378b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 379b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 380b5b6a5f4SSimon Horman 381b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 382b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 383b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 384b5b6a5f4SSimon Horman 385b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 386b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 387b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 388b5b6a5f4SSimon Horman } 389b5b6a5f4SSimon Horman 3904dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 391b5b6a5f4SSimon Horman { 392b5b6a5f4SSimon Horman int timeout = 1000; 3934dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 3944dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 395b5b6a5f4SSimon Horman 3964dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 3974dc48a95SWolfram Sang & bit) == wait_state) 398b5b6a5f4SSimon Horman udelay(1); 399b5b6a5f4SSimon Horman 400b5b6a5f4SSimon Horman if (!timeout) { 401b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 402b5b6a5f4SSimon Horman return -EBUSY; 403b5b6a5f4SSimon Horman } 404b5b6a5f4SSimon Horman 405b5b6a5f4SSimon Horman return 0; 406b5b6a5f4SSimon Horman } 407b5b6a5f4SSimon Horman 408b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 409b5b6a5f4SSimon Horman { 4104dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 4114dc48a95SWolfram Sang 4122fe35968SSimon Horman switch (addr) { 413b5b6a5f4SSimon Horman case CTL_SD_CMD: 414b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 415b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 416b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 417b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 418b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 419b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 420b5b6a5f4SSimon Horman case EXT_ACC: 4215124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 4224dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 4234dc48a95SWolfram Sang /* fallthrough */ 4244dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 4254dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 426b5b6a5f4SSimon Horman } 427b5b6a5f4SSimon Horman 428b5b6a5f4SSimon Horman return 0; 429b5b6a5f4SSimon Horman } 430b5b6a5f4SSimon Horman 431b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 432b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 433b5b6a5f4SSimon Horman { 434b5b6a5f4SSimon Horman /* 435b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 436b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 437b5b6a5f4SSimon Horman * depending on the timing with which the 438b5b6a5f4SSimon Horman * response register is read, the response 439b5b6a5f4SSimon Horman * value may not be read properly. 440b5b6a5f4SSimon Horman * Use single block read for this HW bug 441b5b6a5f4SSimon Horman */ 442b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 443b5b6a5f4SSimon Horman blk_size == 2) 444b5b6a5f4SSimon Horman return 1; 445b5b6a5f4SSimon Horman 446b5b6a5f4SSimon Horman return blk_size; 447b5b6a5f4SSimon Horman } 448b5b6a5f4SSimon Horman 449b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 450b5b6a5f4SSimon Horman { 45141279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 45241279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 453b5b6a5f4SSimon Horman 45441279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 45541279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 456b5b6a5f4SSimon Horman } 457b5b6a5f4SSimon Horman 4589d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 4599d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 460b5b6a5f4SSimon Horman { 461b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 4622fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 4632fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 4642fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 465b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 4662fe35968SSimon Horman struct renesas_sdhi *priv; 467b5b6a5f4SSimon Horman struct resource *res; 468b5b6a5f4SSimon Horman int irq, ret, i; 4692fe35968SSimon Horman 4702fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 471b5b6a5f4SSimon Horman 472b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 473b5b6a5f4SSimon Horman if (!res) 474b5b6a5f4SSimon Horman return -EINVAL; 475b5b6a5f4SSimon Horman 4762fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 4772fe35968SSimon Horman GFP_KERNEL); 478b5b6a5f4SSimon Horman if (!priv) 479b5b6a5f4SSimon Horman return -ENOMEM; 480b5b6a5f4SSimon Horman 481b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 482b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 483b5b6a5f4SSimon Horman 484b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 485b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 486b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 487b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 4884ce62817SMasahiro Yamada return ret; 489b5b6a5f4SSimon Horman } 490b5b6a5f4SSimon Horman 491b5b6a5f4SSimon Horman /* 492b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 493b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 494b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 495b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 496b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 497b5b6a5f4SSimon Horman * disable it. 498b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 499b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 500b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 501b5b6a5f4SSimon Horman */ 502b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 503b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 504b5b6a5f4SSimon Horman priv->clk_cd = NULL; 505b5b6a5f4SSimon Horman 506b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 507b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 508b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 509b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 510b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 511b5b6a5f4SSimon Horman "state_uhs"); 512b5b6a5f4SSimon Horman } 513b5b6a5f4SSimon Horman 514b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 5158d09a133SMasahiro Yamada if (IS_ERR(host)) 5168d09a133SMasahiro Yamada return PTR_ERR(host); 517b5b6a5f4SSimon Horman 518b5b6a5f4SSimon Horman if (of_data) { 519b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 520b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 521b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 522b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 523b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 524603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 525603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 526b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 527b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 528b5b6a5f4SSimon Horman } 529b5b6a5f4SSimon Horman 530b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 531b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 532b5b6a5f4SSimon Horman host->clk_update = renesas_sdhi_clk_update; 533b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 534b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 535bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 536b5b6a5f4SSimon Horman 537b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 538b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 539b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 5402aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 5412aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 542b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 543b5b6a5f4SSimon Horman } 544b5b6a5f4SSimon Horman 545b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 546b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 547b5b6a5f4SSimon Horman host->bus_shift = 1; 548b5b6a5f4SSimon Horman 549b5b6a5f4SSimon Horman if (mmd) 550b5b6a5f4SSimon Horman *mmc_data = *mmd; 551b5b6a5f4SSimon Horman 552b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 553b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 554b5b6a5f4SSimon Horman 555b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 556b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 557b5b6a5f4SSimon Horman 558b5b6a5f4SSimon Horman /* 559b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 560b5b6a5f4SSimon Horman * bus width mode. 561b5b6a5f4SSimon Horman */ 562b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 563b5b6a5f4SSimon Horman 564b5b6a5f4SSimon Horman /* 565b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 566b5b6a5f4SSimon Horman */ 567b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 568b5b6a5f4SSimon Horman 5692fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 570b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 571b5b6a5f4SSimon Horman 572b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 573b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 574b5b6a5f4SSimon Horman 575b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 576b21fc294SMasahiro Yamada if (ret) 577b5b6a5f4SSimon Horman goto efree; 578b5b6a5f4SSimon Horman 579bc45719cSMasahiro Yamada ret = tmio_mmc_host_probe(host); 580b21fc294SMasahiro Yamada if (ret < 0) 581b21fc294SMasahiro Yamada goto edisclk; 582b21fc294SMasahiro Yamada 5835124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 5845124b592SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 5855124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 5865124b592SWolfram Sang 587b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 588b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 589b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 590b5b6a5f4SSimon Horman host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) { 591b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 592b5b6a5f4SSimon Horman bool hit = false; 593b5b6a5f4SSimon Horman 594b5b6a5f4SSimon Horman host->mmc->caps |= MMC_CAP_HW_RESET; 595b5b6a5f4SSimon Horman 596b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 597b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 598b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 599852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 600b5b6a5f4SSimon Horman hit = true; 601b5b6a5f4SSimon Horman break; 602b5b6a5f4SSimon Horman } 603b5b6a5f4SSimon Horman } 604b5b6a5f4SSimon Horman 605b5b6a5f4SSimon Horman if (!hit) 606b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 607b5b6a5f4SSimon Horman 608b5b6a5f4SSimon Horman priv->scc_ctl = host->ctl + of_data->scc_offset; 609b5b6a5f4SSimon Horman host->init_tuning = renesas_sdhi_init_tuning; 610b5b6a5f4SSimon Horman host->prepare_tuning = renesas_sdhi_prepare_tuning; 611b5b6a5f4SSimon Horman host->select_tuning = renesas_sdhi_select_tuning; 612b5b6a5f4SSimon Horman host->check_scc_error = renesas_sdhi_check_scc_error; 613b5b6a5f4SSimon Horman host->hw_reset = renesas_sdhi_hw_reset; 614b5b6a5f4SSimon Horman } 615b5b6a5f4SSimon Horman 616b5b6a5f4SSimon Horman i = 0; 617b5b6a5f4SSimon Horman while (1) { 618b5b6a5f4SSimon Horman irq = platform_get_irq(pdev, i); 619b5b6a5f4SSimon Horman if (irq < 0) 620b5b6a5f4SSimon Horman break; 621b5b6a5f4SSimon Horman i++; 622b5b6a5f4SSimon Horman ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 623b5b6a5f4SSimon Horman dev_name(&pdev->dev), host); 624b5b6a5f4SSimon Horman if (ret) 625b5b6a5f4SSimon Horman goto eirq; 626b5b6a5f4SSimon Horman } 627b5b6a5f4SSimon Horman 628b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 629b5b6a5f4SSimon Horman if (!i) { 630b5b6a5f4SSimon Horman ret = irq; 631b5b6a5f4SSimon Horman goto eirq; 632b5b6a5f4SSimon Horman } 633b5b6a5f4SSimon Horman 634b5b6a5f4SSimon Horman dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 635b5b6a5f4SSimon Horman mmc_hostname(host->mmc), (unsigned long) 636b5b6a5f4SSimon Horman (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 637b5b6a5f4SSimon Horman host->mmc->f_max / 1000000); 638b5b6a5f4SSimon Horman 639b5b6a5f4SSimon Horman return ret; 640b5b6a5f4SSimon Horman 641b5b6a5f4SSimon Horman eirq: 642b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 643b21fc294SMasahiro Yamada edisclk: 644b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 645b5b6a5f4SSimon Horman efree: 646b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 6474ce62817SMasahiro Yamada 648b5b6a5f4SSimon Horman return ret; 649b5b6a5f4SSimon Horman } 6509d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 651b5b6a5f4SSimon Horman 6529d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 653b5b6a5f4SSimon Horman { 654a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 655b5b6a5f4SSimon Horman 656b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 657b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 658b5b6a5f4SSimon Horman 659b5b6a5f4SSimon Horman return 0; 660b5b6a5f4SSimon Horman } 6619d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 662967a6a07SMasaharu Hayakawa 663967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 664