1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/clk.h> 22ab07a135SWolfram Sang #include <linux/delay.h> 23b4d86f37SWolfram Sang #include <linux/iopoll.h> 24ab07a135SWolfram Sang #include <linux/kernel.h> 25ab07a135SWolfram Sang #include <linux/mfd/tmio.h> 26b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 27ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h> 28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 29ab07a135SWolfram Sang #include <linux/module.h> 30ab07a135SWolfram Sang #include <linux/of_device.h> 31b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 32b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 33ab07a135SWolfram Sang #include <linux/platform_device.h> 34ab07a135SWolfram Sang #include <linux/pm_domain.h> 35b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 36b4d86f37SWolfram Sang #include <linux/reset.h> 37ab07a135SWolfram Sang #include <linux/sh_dma.h> 38ab07a135SWolfram Sang #include <linux/slab.h> 39164691aaSNiklas Söderlund #include <linux/sys_soc.h> 40b5b6a5f4SSimon Horman 41b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 42b5b6a5f4SSimon Horman #include "tmio_mmc.h" 43b5b6a5f4SSimon Horman 444533c3ebSWolfram Sang #define CTL_HOST_MODE 0xe4 454533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 464533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 474533c3ebSWolfram Sang #define HOST_MODE_GEN3_WMODE BIT(0) 484533c3ebSWolfram Sang #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 494533c3ebSWolfram Sang 504533c3ebSWolfram Sang #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 514533c3ebSWolfram Sang #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 524533c3ebSWolfram Sang #define HOST_MODE_GEN3_64BIT 0 53b5b6a5f4SSimon Horman 540e08a411SWolfram Sang #define CTL_SDIF_MODE 0xe6 550e08a411SWolfram Sang #define SDIF_MODE_HS400 BIT(0) 560e08a411SWolfram Sang 57b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 58c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 59b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 60b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 61b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 62b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 63b5b6a5f4SSimon Horman 64ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000 65ce6f92c2SWolfram Sang 66b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 67b5b6a5f4SSimon Horman { 68b5b6a5f4SSimon Horman u32 val; 69b5b6a5f4SSimon Horman 70b5b6a5f4SSimon Horman /* 71b5b6a5f4SSimon Horman * see also 72b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 73b5b6a5f4SSimon Horman */ 74b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 75b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 764533c3ebSWolfram Sang val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 77b5b6a5f4SSimon Horman break; 78b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 794533c3ebSWolfram Sang val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 80b5b6a5f4SSimon Horman break; 81b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 82b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 83b5b6a5f4SSimon Horman if (width == 64) 844533c3ebSWolfram Sang val = HOST_MODE_GEN3_64BIT; 85b5b6a5f4SSimon Horman else if (width == 32) 864533c3ebSWolfram Sang val = HOST_MODE_GEN3_32BIT; 87b5b6a5f4SSimon Horman else 884533c3ebSWolfram Sang val = HOST_MODE_GEN3_16BIT; 89b5b6a5f4SSimon Horman break; 90b5b6a5f4SSimon Horman default: 91b5b6a5f4SSimon Horman /* nothing to do */ 92b5b6a5f4SSimon Horman return; 93b5b6a5f4SSimon Horman } 94b5b6a5f4SSimon Horman 954533c3ebSWolfram Sang sd_ctrl_write16(host, CTL_HOST_MODE, val); 96b5b6a5f4SSimon Horman } 97b5b6a5f4SSimon Horman 98b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 99b5b6a5f4SSimon Horman { 100b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 101b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 102d42c9fffSWolfram Sang int ret; 103b5b6a5f4SSimon Horman 104b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 105d42c9fffSWolfram Sang if (ret < 0) 106b5b6a5f4SSimon Horman return ret; 107b5b6a5f4SSimon Horman 108b5b6a5f4SSimon Horman /* 109b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 110b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 111b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 112b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 113b5b6a5f4SSimon Horman */ 114b5b6a5f4SSimon Horman if (!mmc->f_max) 115b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 116b5b6a5f4SSimon Horman 117b5b6a5f4SSimon Horman /* 118b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 119b5b6a5f4SSimon Horman * divided by our maximum divider. 120b5b6a5f4SSimon Horman */ 121b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 122b5b6a5f4SSimon Horman 123b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 124b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 125b5b6a5f4SSimon Horman 126b5b6a5f4SSimon Horman return 0; 127b5b6a5f4SSimon Horman } 128b5b6a5f4SSimon Horman 129b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 130*bb6d3fa9SWolfram Sang unsigned int wanted_clock) 131b5b6a5f4SSimon Horman { 132b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 133*bb6d3fa9SWolfram Sang struct clk *ref_clk = priv->clk; 134b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 135*bb6d3fa9SWolfram Sang unsigned int new_clock, clkh_shift = 0; 13675eaf49fSTamás Szűcs int i; 137b5b6a5f4SSimon Horman 1380f93db65SWolfram Sang /* 1390f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+ 1400f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its 1410f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup. 1420f93db65SWolfram Sang */ 1430f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 144b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 145b5b6a5f4SSimon Horman 146*bb6d3fa9SWolfram Sang if (priv->clkh) { 147*bb6d3fa9SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 148*bb6d3fa9SWolfram Sang bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 149*bb6d3fa9SWolfram Sang (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); 150*bb6d3fa9SWolfram Sang clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 151*bb6d3fa9SWolfram Sang ref_clk = priv->clkh; 152*bb6d3fa9SWolfram Sang } 153*bb6d3fa9SWolfram Sang 154*bb6d3fa9SWolfram Sang new_clock = wanted_clock << clkh_shift; 155*bb6d3fa9SWolfram Sang 156b5b6a5f4SSimon Horman /* 157b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 158b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 159b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 160b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 161b5b6a5f4SSimon Horman */ 162b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 163*bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, new_clock << i); 164b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 165b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 166*bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 167b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 168b5b6a5f4SSimon Horman continue; 169b5b6a5f4SSimon Horman } 170b5b6a5f4SSimon Horman 171b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 172b5b6a5f4SSimon Horman if (diff <= diff_min) { 173b5b6a5f4SSimon Horman best_freq = freq; 174b5b6a5f4SSimon Horman diff_min = diff; 175b5b6a5f4SSimon Horman } 176b5b6a5f4SSimon Horman } 177b5b6a5f4SSimon Horman 178*bb6d3fa9SWolfram Sang clk_set_rate(ref_clk, best_freq); 179*bb6d3fa9SWolfram Sang 180*bb6d3fa9SWolfram Sang if (priv->clkh) 181*bb6d3fa9SWolfram Sang clk_set_rate(priv->clk, best_freq >> clkh_shift); 182b5b6a5f4SSimon Horman 18375eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 184b5b6a5f4SSimon Horman } 185b5b6a5f4SSimon Horman 1860196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1870196c8dbSMasahiro Yamada unsigned int new_clock) 1880196c8dbSMasahiro Yamada { 1890196c8dbSMasahiro Yamada u32 clk = 0, clock; 1900196c8dbSMasahiro Yamada 19168f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 19268f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 19368f83127SMasahiro Yamada 19475eaf49fSTamás Szűcs if (new_clock == 0) { 19575eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 19668f83127SMasahiro Yamada goto out; 19775eaf49fSTamás Szűcs } 19868f83127SMasahiro Yamada 19975eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 20075eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 2010196c8dbSMasahiro Yamada 2020196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 2030196c8dbSMasahiro Yamada clock <<= 1; 2040196c8dbSMasahiro Yamada 2050196c8dbSMasahiro Yamada /* 1/1 clock is option */ 2060196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 2070196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 2080196c8dbSMasahiro Yamada clk |= 0xff; 2090196c8dbSMasahiro Yamada else 2100196c8dbSMasahiro Yamada clk &= ~0xff; 2110196c8dbSMasahiro Yamada } 2120196c8dbSMasahiro Yamada 2130196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 2140196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 2150196c8dbSMasahiro Yamada usleep_range(10000, 11000); 2160196c8dbSMasahiro Yamada 21768f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 21868f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 21968f83127SMasahiro Yamada 22068f83127SMasahiro Yamada out: 22168f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 22268f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 22368f83127SMasahiro Yamada usleep_range(10000, 11000); 2240196c8dbSMasahiro Yamada } 2250196c8dbSMasahiro Yamada 226b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 227b5b6a5f4SSimon Horman { 228b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 229b5b6a5f4SSimon Horman 230b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 231b5b6a5f4SSimon Horman } 232b5b6a5f4SSimon Horman 233b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 234b5b6a5f4SSimon Horman { 235b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 236b5b6a5f4SSimon Horman 2372fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2382fe35968SSimon Horman TMIO_STAT_DAT0); 239b5b6a5f4SSimon Horman } 240b5b6a5f4SSimon Horman 241b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 242b5b6a5f4SSimon Horman struct mmc_ios *ios) 243b5b6a5f4SSimon Horman { 244b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 245b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 246b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 247b5b6a5f4SSimon Horman int ret; 248b5b6a5f4SSimon Horman 249b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 250b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 251b5b6a5f4SSimon Horman pin_state = priv->pins_default; 252b5b6a5f4SSimon Horman break; 253b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 254b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 255b5b6a5f4SSimon Horman break; 256b5b6a5f4SSimon Horman default: 257b5b6a5f4SSimon Horman return -EINVAL; 258b5b6a5f4SSimon Horman } 259b5b6a5f4SSimon Horman 260b5b6a5f4SSimon Horman /* 261b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 262b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 263b5b6a5f4SSimon Horman */ 264b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 265b5b6a5f4SSimon Horman return ios->signal_voltage == 266b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 267b5b6a5f4SSimon Horman 268b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 2699cbe0fc8SMarek Vasut if (ret < 0) 270b5b6a5f4SSimon Horman return ret; 271b5b6a5f4SSimon Horman 272b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 273b5b6a5f4SSimon Horman } 274b5b6a5f4SSimon Horman 275b5b6a5f4SSimon Horman /* SCC registers */ 276b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 277b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 278b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 279b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 280b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 281b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 28271cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 28326eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 284ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 285ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 286ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 287ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 288ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 289b5b6a5f4SSimon Horman 290b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 291b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 292b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 293b5b6a5f4SSimon Horman 294b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2956199a10eSWolfram Sang 296b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2976199a10eSWolfram Sang 29811a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2996199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 3006199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 3016199a10eSWolfram Sang 30271cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 3036199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 3046199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 3056199a10eSWolfram Sang 30626eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 30726eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 308b5b6a5f4SSimon Horman 309ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 310ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 311ce6f92c2SWolfram Sang 312ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 313ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 314ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 315ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 316ce6f92c2SWolfram Sang 317ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 318ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 319ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 320ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 321ce6f92c2SWolfram Sang 322b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 323b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 324b5b6a5f4SSimon Horman { 325b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 326b5b6a5f4SSimon Horman } 327b5b6a5f4SSimon Horman 328b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 329b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 330b5b6a5f4SSimon Horman int addr, u32 val) 331b5b6a5f4SSimon Horman { 332b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 333b5b6a5f4SSimon Horman } 334b5b6a5f4SSimon Horman 335b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 336b5b6a5f4SSimon Horman { 337b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 338b5b6a5f4SSimon Horman 339b5b6a5f4SSimon Horman priv = host_to_priv(host); 340b5b6a5f4SSimon Horman 341b5b6a5f4SSimon Horman /* Initialize SCC */ 342b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 343b5b6a5f4SSimon Horman 344b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 345b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 346b5b6a5f4SSimon Horman 34726eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 34826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 34926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 35026eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 35126eb2607SMasaharu Hayakawa 352b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 353b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 354b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 355b5b6a5f4SSimon Horman 356b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 357b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 358b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 359b5b6a5f4SSimon Horman 360852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 361b5b6a5f4SSimon Horman 36226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 36326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36426eb2607SMasaharu Hayakawa 365b5b6a5f4SSimon Horman /* Read TAPNUM */ 366b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 367b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 368b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 369b5b6a5f4SSimon Horman } 370b5b6a5f4SSimon Horman 371f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 37226eb2607SMasaharu Hayakawa { 373f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 37426eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 375a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 376a38c078fSTakeshi Saito bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 37726eb2607SMasaharu Hayakawa 37826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 37926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 38026eb2607SMasaharu Hayakawa 38126eb2607SMasaharu Hayakawa /* Set HS400 mode */ 3820e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 38326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 384f0c8234cSTakeshi Saito 385f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 386f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 387f0c8234cSTakeshi Saito 3889b0d6855SWolfram Sang /* Gen3 can't do automatic tap correction with HS400, so disable it */ 3899b0d6855SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 3909b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3919b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3929b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3939b0d6855SWolfram Sang 39426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 39526eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 39626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 39726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 39826eb2607SMasaharu Hayakawa 39926eb2607SMasaharu Hayakawa /* Set the sampling clock selection range of HS400 mode */ 40026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 40126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 40226eb2607SMasaharu Hayakawa 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 40326eb2607SMasaharu Hayakawa 404a38c078fSTakeshi Saito /* Avoid bad TAP */ 405a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) { 406a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 40726eb2607SMasaharu Hayakawa 408a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) 409a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num; 410a38c078fSTakeshi Saito 411a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) { 412a38c078fSTakeshi Saito new_tap = priv->tap_set; 413a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 414a38c078fSTakeshi Saito } 415a38c078fSTakeshi Saito 416a38c078fSTakeshi Saito priv->tap_set = new_tap; 417a38c078fSTakeshi Saito } 418a38c078fSTakeshi Saito 41926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 420a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1)); 42126eb2607SMasaharu Hayakawa 42226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 42326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 42426eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 42526eb2607SMasaharu Hayakawa 42626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 42726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 428ce6f92c2SWolfram Sang 429ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 430ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true; 43126eb2607SMasaharu Hayakawa } 43226eb2607SMasaharu Hayakawa 43380d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 43426eb2607SMasaharu Hayakawa { 43580d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 43680d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 43780d0be81SWolfram Sang 43826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 43926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 44026eb2607SMasaharu Hayakawa 44126eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 44226eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 44326eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44426eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 44526eb2607SMasaharu Hayakawa 44626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 44726eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 44826eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 45026eb2607SMasaharu Hayakawa 45126eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 45226eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 45326eb2607SMasaharu Hayakawa } 45426eb2607SMasaharu Hayakawa 455ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 456ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr) 457ce6f92c2SWolfram Sang { 458ce6f92c2SWolfram Sang /* read mode */ 459ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 460ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 461ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 462ce6f92c2SWolfram Sang 463ce6f92c2SWolfram Sang /* access start and stop */ 464ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 465ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 466ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 467ce6f92c2SWolfram Sang 468ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 469ce6f92c2SWolfram Sang } 470ce6f92c2SWolfram Sang 471ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 472ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val) 473ce6f92c2SWolfram Sang { 474ce6f92c2SWolfram Sang /* write mode */ 475ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 476ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 477ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 478ce6f92c2SWolfram Sang 479ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 480ce6f92c2SWolfram Sang 481ce6f92c2SWolfram Sang /* access start and stop */ 482ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 483ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 484ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 485ce6f92c2SWolfram Sang } 486ce6f92c2SWolfram Sang 487ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 488ce6f92c2SWolfram Sang { 489ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 490ce6f92c2SWolfram Sang u32 calib_code; 491ce6f92c2SWolfram Sang 492ce6f92c2SWolfram Sang /* disable write protect */ 493ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 494ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 495ce6f92c2SWolfram Sang /* read calibration code and adjust */ 496ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 497ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 498ce6f92c2SWolfram Sang 499ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 500ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 501ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]); 502ce6f92c2SWolfram Sang 503ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 504ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 505ce6f92c2SWolfram Sang 506ce6f92c2SWolfram Sang /* adjustment done, clear flag */ 507ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 508ce6f92c2SWolfram Sang } 509ce6f92c2SWolfram Sang 510ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 511ce6f92c2SWolfram Sang { 512ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 513ce6f92c2SWolfram Sang 514ce6f92c2SWolfram Sang /* disable write protect */ 515ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 516ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 517ce6f92c2SWolfram Sang /* disable manual calibration */ 518ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0); 519ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */ 520ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 521ce6f92c2SWolfram Sang } 522ce6f92c2SWolfram Sang 52326eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 52426eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 52526eb2607SMasaharu Hayakawa { 52626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 52726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 52826eb2607SMasaharu Hayakawa 52926eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 5300e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 53126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 532f0c8234cSTakeshi Saito 533f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 534f0c8234cSTakeshi Saito 53526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 53626eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 53726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 53826eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 53926eb2607SMasaharu Hayakawa 540ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 541ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host); 542ce6f92c2SWolfram Sang 54326eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 54426eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 54526eb2607SMasaharu Hayakawa } 54626eb2607SMasaharu Hayakawa 547f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 54826eb2607SMasaharu Hayakawa { 549f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 550f22084b6SWolfram Sang 55126eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 552f22084b6SWolfram Sang return 0; 55326eb2607SMasaharu Hayakawa } 55426eb2607SMasaharu Hayakawa 5550e587014SWolfram Sang static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 5565b0739d7SWolfram Sang { 557183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc); 5585b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv); 559ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 5605b0739d7SWolfram Sang 5615b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 5625b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 5635b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 56445bffc37SWolfram Sang } 5655b0739d7SWolfram Sang 5660e587014SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */ 5670e587014SWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host) 5680e587014SWolfram Sang { 5690e587014SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 570b4d86f37SWolfram Sang int ret; 5710e587014SWolfram Sang u16 val; 5720e587014SWolfram Sang 573b4d86f37SWolfram Sang if (priv->rstc) { 574b4d86f37SWolfram Sang reset_control_reset(priv->rstc); 575b4d86f37SWolfram Sang /* Unknown why but without polling reset status, it will hang */ 576b4d86f37SWolfram Sang read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 577b4d86f37SWolfram Sang false, priv->rstc); 578b81bede4SWolfram Sang /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 579b81bede4SWolfram Sang sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 580b4d86f37SWolfram Sang priv->needs_adjust_hs400 = false; 581b4d86f37SWolfram Sang renesas_sdhi_set_clock(host, host->clk_cache); 582b4d86f37SWolfram Sang } else if (priv->scc_ctl) { 5830e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 584b4d86f37SWolfram Sang } 5850e587014SWolfram Sang 586b191deceSWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 587b191deceSWolfram Sang val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 588b191deceSWolfram Sang val |= CARD_OPT_EXTOP; 589b191deceSWolfram Sang sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 590b191deceSWolfram Sang } 591b191deceSWolfram Sang } 592b191deceSWolfram Sang 593b191deceSWolfram Sang static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 594b191deceSWolfram Sang { 595b191deceSWolfram Sang u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 596b191deceSWolfram Sang 597b191deceSWolfram Sang num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 598b191deceSWolfram Sang return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 599b191deceSWolfram Sang 6005b0739d7SWolfram Sang } 6015b0739d7SWolfram Sang 602ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 603b5b6a5f4SSimon Horman 604b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 605b5b6a5f4SSimon Horman { 606b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 60792fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 6085fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row; 6095fb6bf51SWolfram Sang unsigned long *bitmap; 610b5b6a5f4SSimon Horman 611b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 612b5b6a5f4SSimon Horman 613b5b6a5f4SSimon Horman /* 6145c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 6155c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 6165c99826bSNiklas Söderlund * considering it for tuning selection. 6175c99826bSNiklas Söderlund */ 61892fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) { 619b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 6205c99826bSNiklas Söderlund 621b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps)) 622b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps); 6235fb6bf51SWolfram Sang 6245fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp)) 6255fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp); 6265fb6bf51SWolfram Sang } 6275fb6bf51SWolfram Sang 6285fb6bf51SWolfram Sang /* 6295fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by 6305fb6bf51SWolfram Sang * identifying the change point of data. 6315fb6bf51SWolfram Sang */ 6325fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) { 6335fb6bf51SWolfram Sang bitmap = priv->smpcmp; 6345fb6bf51SWolfram Sang min_tap_row = 1; 6355fb6bf51SWolfram Sang } else { 6365fb6bf51SWolfram Sang bitmap = priv->taps; 6375fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 6385c99826bSNiklas Söderlund } 6395c99826bSNiklas Söderlund 6405c99826bSNiklas Söderlund /* 641b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 642ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 643ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out. 644b5b6a5f4SSimon Horman */ 6455fb6bf51SWolfram Sang bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 64692fa2a56SWolfram Sang if (re - rs > tap_cnt) { 64792fa2a56SWolfram Sang tap_end = re; 64892fa2a56SWolfram Sang tap_start = rs; 64992fa2a56SWolfram Sang tap_cnt = tap_end - tap_start; 650b5b6a5f4SSimon Horman } 651b5b6a5f4SSimon Horman } 652b5b6a5f4SSimon Horman 6535fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row) 654b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 655b5b6a5f4SSimon Horman else 656b5b6a5f4SSimon Horman return -EIO; 657b5b6a5f4SSimon Horman 658b5b6a5f4SSimon Horman /* Set SCC */ 659b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 660b5b6a5f4SSimon Horman 661b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 662b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 663b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 664b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 665b5b6a5f4SSimon Horman 666b5b6a5f4SSimon Horman return 0; 667b5b6a5f4SSimon Horman } 668b5b6a5f4SSimon Horman 669510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 6700c482d82SWolfram Sang { 671510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 6720c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 6735b0739d7SWolfram Sang int i, ret; 6740c482d82SWolfram Sang 675b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host); 676b2dd9a13SWolfram Sang if (!priv->tap_num) 6770c482d82SWolfram Sang return 0; /* Tuning is not supported */ 6780c482d82SWolfram Sang 679b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 6803a821a82SWolfram Sang dev_err(&host->pdev->dev, 6813a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 6823a821a82SWolfram Sang return -EINVAL; 6830c482d82SWolfram Sang } 6840c482d82SWolfram Sang 685b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2); 6865fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2); 6870c482d82SWolfram Sang 6880c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 689b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) { 6902c9017d0SWolfram Sang int cmd_error; 6912c9017d0SWolfram Sang 6920c482d82SWolfram Sang /* Set sampling clock position */ 693b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 6940c482d82SWolfram Sang 6952c9017d0SWolfram Sang if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 696b2dd9a13SWolfram Sang set_bit(i, priv->taps); 6975fb6bf51SWolfram Sang 6985fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 6995fb6bf51SWolfram Sang set_bit(i, priv->smpcmp); 7002c9017d0SWolfram Sang 7012c9017d0SWolfram Sang if (cmd_error) 70221adc2e4SWolfram Sang mmc_send_abort_tuning(mmc, opcode); 7030c482d82SWolfram Sang } 7040c482d82SWolfram Sang 7055b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host); 7065b0739d7SWolfram Sang if (ret < 0) 7070e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 7085b0739d7SWolfram Sang return ret; 7090c482d82SWolfram Sang } 7100c482d82SWolfram Sang 71111a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 71211a21960STakeshi Saito { 71311a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 714a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 71511a21960STakeshi Saito u32 val; 71611a21960STakeshi Saito 71711a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 71811a21960STakeshi Saito if (!val) 71911a21960STakeshi Saito return false; 72011a21960STakeshi Saito 72111a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 72211a21960STakeshi Saito 72311a21960STakeshi Saito /* Change TAP position according to correction status */ 72471cfc927STakeshi Saito if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 72571cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 726a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 72771cfc927STakeshi Saito /* 72871cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 72971cfc927STakeshi Saito * Therefore, use only CMD status. 73071cfc927STakeshi Saito */ 73171cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 73271cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 733a38c078fSTakeshi Saito if (!smpcmp) { 73471cfc927STakeshi Saito return false; /* no error in CMD signal */ 735a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 73671cfc927STakeshi Saito new_tap++; 737a38c078fSTakeshi Saito error_tap--; 738a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 73971cfc927STakeshi Saito new_tap--; 740a38c078fSTakeshi Saito error_tap++; 741a38c078fSTakeshi Saito } else { 74271cfc927STakeshi Saito return true; /* need retune */ 743a38c078fSTakeshi Saito } 744a38c078fSTakeshi Saito 745a38c078fSTakeshi Saito /* 746a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare 747a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK, 748a38c078fSTakeshi Saito * we can at least retune. 749a38c078fSTakeshi Saito */ 750a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num)) 751a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp); 75271cfc927STakeshi Saito } else { 75311a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 75471cfc927STakeshi Saito return true; /* need retune */ 75511a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 75671cfc927STakeshi Saito new_tap++; 75711a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 75871cfc927STakeshi Saito new_tap--; 75911a21960STakeshi Saito else 76011a21960STakeshi Saito return false; 76171cfc927STakeshi Saito } 76211a21960STakeshi Saito 763b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num); 76411a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 765b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1)); 76611a21960STakeshi Saito 76711a21960STakeshi Saito return false; 76811a21960STakeshi Saito } 76911a21960STakeshi Saito 77011a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 77111a21960STakeshi Saito { 77211a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 77311a21960STakeshi Saito 77411a21960STakeshi Saito /* Check SCC error */ 77511a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 77611a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 77711a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 77811a21960STakeshi Saito return true; 77911a21960STakeshi Saito } 78011a21960STakeshi Saito 78111a21960STakeshi Saito return false; 78211a21960STakeshi Saito } 78311a21960STakeshi Saito 784ed2fab9aSYoshihiro Shimoda static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 785ed2fab9aSYoshihiro Shimoda struct mmc_request *mrq) 786b5b6a5f4SSimon Horman { 787b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 78812e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 789ed2fab9aSYoshihiro Shimoda bool ret = false; 79075f349a1SMasaharu Hayakawa 79175f349a1SMasaharu Hayakawa /* 79275f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 79375f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 79475f349a1SMasaharu Hayakawa */ 79575f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 79675f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 79775f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 79875f349a1SMasaharu Hayakawa return false; 79975f349a1SMasaharu Hayakawa 800fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc)) 80175f349a1SMasaharu Hayakawa return false; 802b5b6a5f4SSimon Horman 803ed2fab9aSYoshihiro Shimoda if (((mrq->cmd->error == -ETIMEDOUT) || 804ed2fab9aSYoshihiro Shimoda (mrq->data && mrq->data->error == -ETIMEDOUT)) && 805ed2fab9aSYoshihiro Shimoda ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 806ed2fab9aSYoshihiro Shimoda (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 807ed2fab9aSYoshihiro Shimoda ret |= true; 808ed2fab9aSYoshihiro Shimoda 809b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 81011a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 811ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_auto_correction(host); 812ed2fab9aSYoshihiro Shimoda else 813ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_manual_correction(host, use_4tap); 814b5b6a5f4SSimon Horman 815ed2fab9aSYoshihiro Shimoda return ret; 816b5b6a5f4SSimon Horman } 817b5b6a5f4SSimon Horman 8184dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 819b5b6a5f4SSimon Horman { 820b5b6a5f4SSimon Horman int timeout = 1000; 8214dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 8224dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 823b5b6a5f4SSimon Horman 8244dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 8254dc48a95SWolfram Sang & bit) == wait_state) 826b5b6a5f4SSimon Horman udelay(1); 827b5b6a5f4SSimon Horman 828b5b6a5f4SSimon Horman if (!timeout) { 829b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 830b5b6a5f4SSimon Horman return -EBUSY; 831b5b6a5f4SSimon Horman } 832b5b6a5f4SSimon Horman 833b5b6a5f4SSimon Horman return 0; 834b5b6a5f4SSimon Horman } 835b5b6a5f4SSimon Horman 836b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 837b5b6a5f4SSimon Horman { 8384dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 8394dc48a95SWolfram Sang 8402fe35968SSimon Horman switch (addr) { 841b5b6a5f4SSimon Horman case CTL_SD_CMD: 842b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 843b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 844b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 845b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 846b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 847b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 8484533c3ebSWolfram Sang case CTL_HOST_MODE: 8495124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 8504dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 851df561f66SGustavo A. R. Silva fallthrough; 8524dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 8534dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 854b5b6a5f4SSimon Horman } 855b5b6a5f4SSimon Horman 856b5b6a5f4SSimon Horman return 0; 857b5b6a5f4SSimon Horman } 858b5b6a5f4SSimon Horman 859b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 860b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 861b5b6a5f4SSimon Horman { 862b5b6a5f4SSimon Horman /* 863b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 864b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 865b5b6a5f4SSimon Horman * depending on the timing with which the 866b5b6a5f4SSimon Horman * response register is read, the response 867b5b6a5f4SSimon Horman * value may not be read properly. 868b5b6a5f4SSimon Horman * Use single block read for this HW bug 869b5b6a5f4SSimon Horman */ 870b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 871b5b6a5f4SSimon Horman blk_size == 2) 872b5b6a5f4SSimon Horman return 1; 873b5b6a5f4SSimon Horman 874b5b6a5f4SSimon Horman return blk_size; 875b5b6a5f4SSimon Horman } 876b5b6a5f4SSimon Horman 877ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 878ce6f92c2SWolfram Sang { 879ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 880ce6f92c2SWolfram Sang 881ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 882ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host); 883ce6f92c2SWolfram Sang } 884b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 885b5b6a5f4SSimon Horman { 88641279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 88741279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 888b5b6a5f4SSimon Horman 88941279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 89041279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 891b5b6a5f4SSimon Horman } 892b5b6a5f4SSimon Horman 8939d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 89471b7597cSYoshihiro Shimoda const struct tmio_mmc_dma_ops *dma_ops, 89571b7597cSYoshihiro Shimoda const struct renesas_sdhi_of_data *of_data, 89671b7597cSYoshihiro Shimoda const struct renesas_sdhi_quirks *quirks) 897b5b6a5f4SSimon Horman { 898b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 8992fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 9002fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 901b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 9022fe35968SSimon Horman struct renesas_sdhi *priv; 903e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 904b5b6a5f4SSimon Horman struct resource *res; 905c9a9497cSWolfram Sang u16 ver; 9062fe35968SSimon Horman 907b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 908b5b6a5f4SSimon Horman if (!res) 909b5b6a5f4SSimon Horman return -EINVAL; 910b5b6a5f4SSimon Horman 9112fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 9122fe35968SSimon Horman GFP_KERNEL); 913b5b6a5f4SSimon Horman if (!priv) 914b5b6a5f4SSimon Horman return -ENOMEM; 915b5b6a5f4SSimon Horman 9167af08206SWolfram Sang priv->quirks = quirks; 917b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 918b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 919b5b6a5f4SSimon Horman 920b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 921b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 922b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 923b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 9244ce62817SMasahiro Yamada return ret; 925b5b6a5f4SSimon Horman } 926b5b6a5f4SSimon Horman 927b5b6a5f4SSimon Horman /* 928b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 929b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 930b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 931b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 932b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 933b5b6a5f4SSimon Horman * disable it. 934b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 935b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 936b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 937b5b6a5f4SSimon Horman */ 938b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 939b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 940b5b6a5f4SSimon Horman priv->clk_cd = NULL; 941b5b6a5f4SSimon Horman 942b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 943b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 944b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 945b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 946b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 947b5b6a5f4SSimon Horman "state_uhs"); 948b5b6a5f4SSimon Horman } 949b5b6a5f4SSimon Horman 950b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 9518d09a133SMasahiro Yamada if (IS_ERR(host)) 9528d09a133SMasahiro Yamada return PTR_ERR(host); 953b5b6a5f4SSimon Horman 954b5b6a5f4SSimon Horman if (of_data) { 955b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 956b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 957b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 958b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 959b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 960603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 961603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 962b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 963b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 964*bb6d3fa9SWolfram Sang /* Fallback for old DTs */ 965*bb6d3fa9SWolfram Sang if (of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 966*bb6d3fa9SWolfram Sang priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 967*bb6d3fa9SWolfram Sang 968b5b6a5f4SSimon Horman } 969b5b6a5f4SSimon Horman 970b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 971b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 972b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 9730196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 974b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 975bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 976b5b6a5f4SSimon Horman 9770f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 9780f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 9790f4e2054SNiklas Söderlund 980ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 981ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 982ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 983ef5332c1SWolfram Sang 984b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 985b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 986b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 9872aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 9882aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 989b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 9901970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 9919f12cac1SWolfram Sang host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 9926e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset; 993d30ae056STakeshi Saito } 994b5b6a5f4SSimon Horman 995b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 996b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 997b5b6a5f4SSimon Horman host->bus_shift = 1; 998b5b6a5f4SSimon Horman 999b5b6a5f4SSimon Horman if (mmd) 1000b5b6a5f4SSimon Horman *mmc_data = *mmd; 1001b5b6a5f4SSimon Horman 1002b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 1003b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 1004b5b6a5f4SSimon Horman 1005b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1006b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1007b5b6a5f4SSimon Horman 1008b5b6a5f4SSimon Horman /* 1009b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1010b5b6a5f4SSimon Horman * bus width mode. 1011b5b6a5f4SSimon Horman */ 1012b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1013b5b6a5f4SSimon Horman 1014b5b6a5f4SSimon Horman /* 1015b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 1016b5b6a5f4SSimon Horman */ 1017b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1018b5b6a5f4SSimon Horman 10192fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 1020b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1021b5b6a5f4SSimon Horman 1022b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 1023b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1024b5b6a5f4SSimon Horman 102530ae3e13SWolfram Sang /* All SDHI support HW busy detection */ 102630ae3e13SWolfram Sang mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 102730ae3e13SWolfram Sang 102863fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev); 102963fd8ef3SUlf Hansson 1030b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 1031b21fc294SMasahiro Yamada if (ret) 1032b5b6a5f4SSimon Horman goto efree; 1033b5b6a5f4SSimon Horman 1034b4d86f37SWolfram Sang priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1035b4d86f37SWolfram Sang if (IS_ERR(priv->rstc)) 1036b4d86f37SWolfram Sang return PTR_ERR(priv->rstc); 1037b4d86f37SWolfram Sang 1038c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 1039c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1040c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1041c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 1042c9a9497cSWolfram Sang 10435124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1044c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 10455124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 10465124b592SWolfram Sang 1047ce6f92c2SWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1048ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request; 1049ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *( 1050ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ? 1051ce6f92c2SWolfram Sang quirks->hs400_calib_table : 1052ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1); 1053ce6f92c2SWolfram Sang } 1054ce6f92c2SWolfram Sang 1055b191deceSWolfram Sang /* these have an EXTOP bit */ 1056b191deceSWolfram Sang if (ver >= SDHI_VER_GEN3_SD) 1057b191deceSWolfram Sang host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1058b191deceSWolfram Sang 1059b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 1060b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 1061b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 106226eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 106326eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 1064b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 1065c1a49782SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1066b5b6a5f4SSimon Horman bool hit = false; 1067b5b6a5f4SSimon Horman 1068b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 1069b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 1070b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 1071852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 1072c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 1073c1a49782SWolfram Sang taps->tap_hs400_4tap : 1074c1a49782SWolfram Sang taps->tap; 1075b5b6a5f4SSimon Horman hit = true; 1076b5b6a5f4SSimon Horman break; 1077b5b6a5f4SSimon Horman } 1078b5b6a5f4SSimon Horman } 1079b5b6a5f4SSimon Horman 1080b5b6a5f4SSimon Horman if (!hit) 1081e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1082b5b6a5f4SSimon Horman 1083d14ac691SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset; 108464982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error; 1085510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1086f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1087f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1088f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1089b5b6a5f4SSimon Horman } 1090b5b6a5f4SSimon Horman 1091b161d87dSWolfram Sang ret = tmio_mmc_host_probe(host); 1092b161d87dSWolfram Sang if (ret < 0) 1093b161d87dSWolfram Sang goto edisclk; 1094b161d87dSWolfram Sang 1095e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 1096e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 1097e8307ec5SGeert Uytterhoeven ret = num_irqs; 1098b5b6a5f4SSimon Horman goto eirq; 1099b5b6a5f4SSimon Horman } 1100b5b6a5f4SSimon Horman 1101b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 1102e8307ec5SGeert Uytterhoeven if (!num_irqs) { 1103e8307ec5SGeert Uytterhoeven ret = -ENXIO; 1104e8307ec5SGeert Uytterhoeven goto eirq; 1105e8307ec5SGeert Uytterhoeven } 1106e8307ec5SGeert Uytterhoeven 1107e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 1108e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 1109e8307ec5SGeert Uytterhoeven if (irq < 0) { 1110b5b6a5f4SSimon Horman ret = irq; 1111b5b6a5f4SSimon Horman goto eirq; 1112b5b6a5f4SSimon Horman } 1113b5b6a5f4SSimon Horman 1114e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1115e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 1116e8307ec5SGeert Uytterhoeven if (ret) 1117e8307ec5SGeert Uytterhoeven goto eirq; 1118e8307ec5SGeert Uytterhoeven } 1119e8307ec5SGeert Uytterhoeven 1120bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1121bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1122b5b6a5f4SSimon Horman 1123b5b6a5f4SSimon Horman return ret; 1124b5b6a5f4SSimon Horman 1125b5b6a5f4SSimon Horman eirq: 1126b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1127b21fc294SMasahiro Yamada edisclk: 1128b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1129b5b6a5f4SSimon Horman efree: 1130b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 11314ce62817SMasahiro Yamada 1132b5b6a5f4SSimon Horman return ret; 1133b5b6a5f4SSimon Horman } 11349d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1135b5b6a5f4SSimon Horman 11369d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 1137b5b6a5f4SSimon Horman { 1138a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1139b5b6a5f4SSimon Horman 1140b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1141b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1142e8973201SYoshihiro Shimoda tmio_mmc_host_free(host); 1143b5b6a5f4SSimon Horman 1144b5b6a5f4SSimon Horman return 0; 1145b5b6a5f4SSimon Horman } 11469d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1147967a6a07SMasaharu Hayakawa 1148967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 1149