1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/kernel.h> 22b5b6a5f4SSimon Horman #include <linux/clk.h> 23b5b6a5f4SSimon Horman #include <linux/slab.h> 24967a6a07SMasaharu Hayakawa #include <linux/module.h> 25b5b6a5f4SSimon Horman #include <linux/of_device.h> 26b5b6a5f4SSimon Horman #include <linux/platform_device.h> 2763fd8ef3SUlf Hansson #include <linux/pm_domain.h> 28b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 29ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h> 30ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 31b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 32b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 33b5b6a5f4SSimon Horman #include <linux/delay.h> 34b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 35b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 36b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 37164691aaSNiklas Söderlund #include <linux/sys_soc.h> 38b5b6a5f4SSimon Horman 39b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 40b5b6a5f4SSimon Horman #include "tmio_mmc.h" 41b5b6a5f4SSimon Horman 424472f0fcSMasaharu Hayakawa #define HOST_MODE 0xe4 43b5b6a5f4SSimon Horman 44b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 45c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 46b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 47b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 48b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 49b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 50b5b6a5f4SSimon Horman 51ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000 52ce6f92c2SWolfram Sang 53b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 54b5b6a5f4SSimon Horman { 55b5b6a5f4SSimon Horman u32 val; 56b5b6a5f4SSimon Horman 57b5b6a5f4SSimon Horman /* 58b5b6a5f4SSimon Horman * see also 59b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 60b5b6a5f4SSimon Horman */ 61b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 62b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 63b5b6a5f4SSimon Horman val = (width == 32) ? 0x0001 : 0x0000; 64b5b6a5f4SSimon Horman break; 65b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 66b5b6a5f4SSimon Horman val = (width == 32) ? 0x0000 : 0x0001; 67b5b6a5f4SSimon Horman break; 68b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 69b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 70b5b6a5f4SSimon Horman if (width == 64) 71b5b6a5f4SSimon Horman val = 0x0000; 72b5b6a5f4SSimon Horman else if (width == 32) 73b5b6a5f4SSimon Horman val = 0x0101; 74b5b6a5f4SSimon Horman else 75b5b6a5f4SSimon Horman val = 0x0001; 76b5b6a5f4SSimon Horman break; 77b5b6a5f4SSimon Horman default: 78b5b6a5f4SSimon Horman /* nothing to do */ 79b5b6a5f4SSimon Horman return; 80b5b6a5f4SSimon Horman } 81b5b6a5f4SSimon Horman 824472f0fcSMasaharu Hayakawa sd_ctrl_write16(host, HOST_MODE, val); 83b5b6a5f4SSimon Horman } 84b5b6a5f4SSimon Horman 85b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 86b5b6a5f4SSimon Horman { 87b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 88b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 89d42c9fffSWolfram Sang int ret; 90b5b6a5f4SSimon Horman 91b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 92d42c9fffSWolfram Sang if (ret < 0) 93b5b6a5f4SSimon Horman return ret; 94b5b6a5f4SSimon Horman 95b5b6a5f4SSimon Horman /* 96b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 97b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 98b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 99b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 100b5b6a5f4SSimon Horman */ 101b5b6a5f4SSimon Horman if (!mmc->f_max) 102b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 103b5b6a5f4SSimon Horman 104b5b6a5f4SSimon Horman /* 105b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 106b5b6a5f4SSimon Horman * divided by our maximum divider. 107b5b6a5f4SSimon Horman */ 108b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 109b5b6a5f4SSimon Horman 110b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 111b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 112b5b6a5f4SSimon Horman 113b5b6a5f4SSimon Horman return 0; 114b5b6a5f4SSimon Horman } 115b5b6a5f4SSimon Horman 116b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 117b5b6a5f4SSimon Horman unsigned int new_clock) 118b5b6a5f4SSimon Horman { 119b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 120b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 12175eaf49fSTamás Szűcs int i; 122b5b6a5f4SSimon Horman 1230f93db65SWolfram Sang /* 1240f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+ 1250f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its 1260f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup. 1270f93db65SWolfram Sang */ 1280f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 129b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 130b5b6a5f4SSimon Horman 131b5b6a5f4SSimon Horman /* 132b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 133b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 134b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 135b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 136b5b6a5f4SSimon Horman */ 137b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 138b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 139b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 140b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 141b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 142b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 143b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 144b5b6a5f4SSimon Horman continue; 145b5b6a5f4SSimon Horman } 146b5b6a5f4SSimon Horman 147b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 148b5b6a5f4SSimon Horman if (diff <= diff_min) { 149b5b6a5f4SSimon Horman best_freq = freq; 150b5b6a5f4SSimon Horman diff_min = diff; 151b5b6a5f4SSimon Horman } 152b5b6a5f4SSimon Horman } 153b5b6a5f4SSimon Horman 15475eaf49fSTamás Szűcs clk_set_rate(priv->clk, best_freq); 155b5b6a5f4SSimon Horman 15675eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 157b5b6a5f4SSimon Horman } 158b5b6a5f4SSimon Horman 1590196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1600196c8dbSMasahiro Yamada unsigned int new_clock) 1610196c8dbSMasahiro Yamada { 1620196c8dbSMasahiro Yamada u32 clk = 0, clock; 1630196c8dbSMasahiro Yamada 16468f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 16568f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 16668f83127SMasahiro Yamada 16775eaf49fSTamás Szűcs if (new_clock == 0) { 16875eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 16968f83127SMasahiro Yamada goto out; 17075eaf49fSTamás Szűcs } 17168f83127SMasahiro Yamada 17275eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 17375eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 1740196c8dbSMasahiro Yamada 1750196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 1760196c8dbSMasahiro Yamada clock <<= 1; 1770196c8dbSMasahiro Yamada 1780196c8dbSMasahiro Yamada /* 1/1 clock is option */ 1790196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 1800196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 1810196c8dbSMasahiro Yamada clk |= 0xff; 1820196c8dbSMasahiro Yamada else 1830196c8dbSMasahiro Yamada clk &= ~0xff; 1840196c8dbSMasahiro Yamada } 1850196c8dbSMasahiro Yamada 1860196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 1870196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 1880196c8dbSMasahiro Yamada usleep_range(10000, 11000); 1890196c8dbSMasahiro Yamada 19068f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 19168f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 19268f83127SMasahiro Yamada 19368f83127SMasahiro Yamada out: 19468f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 19568f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 19668f83127SMasahiro Yamada usleep_range(10000, 11000); 1970196c8dbSMasahiro Yamada } 1980196c8dbSMasahiro Yamada 199b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 200b5b6a5f4SSimon Horman { 201b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 202b5b6a5f4SSimon Horman 203b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 204b5b6a5f4SSimon Horman } 205b5b6a5f4SSimon Horman 206b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 207b5b6a5f4SSimon Horman { 208b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 209b5b6a5f4SSimon Horman 2102fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2112fe35968SSimon Horman TMIO_STAT_DAT0); 212b5b6a5f4SSimon Horman } 213b5b6a5f4SSimon Horman 214b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 215b5b6a5f4SSimon Horman struct mmc_ios *ios) 216b5b6a5f4SSimon Horman { 217b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 218b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 219b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 220b5b6a5f4SSimon Horman int ret; 221b5b6a5f4SSimon Horman 222b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 223b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 224b5b6a5f4SSimon Horman pin_state = priv->pins_default; 225b5b6a5f4SSimon Horman break; 226b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 227b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 228b5b6a5f4SSimon Horman break; 229b5b6a5f4SSimon Horman default: 230b5b6a5f4SSimon Horman return -EINVAL; 231b5b6a5f4SSimon Horman } 232b5b6a5f4SSimon Horman 233b5b6a5f4SSimon Horman /* 234b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 235b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 236b5b6a5f4SSimon Horman */ 237b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 238b5b6a5f4SSimon Horman return ios->signal_voltage == 239b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 240b5b6a5f4SSimon Horman 241b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 2429cbe0fc8SMarek Vasut if (ret < 0) 243b5b6a5f4SSimon Horman return ret; 244b5b6a5f4SSimon Horman 245b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 246b5b6a5f4SSimon Horman } 247b5b6a5f4SSimon Horman 248b5b6a5f4SSimon Horman /* SCC registers */ 249b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 250b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 251b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 252b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 253b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 254b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 25571cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 25626eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 257ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 258ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 259ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 260ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 261ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 262b5b6a5f4SSimon Horman 263b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 264b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 265b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 266b5b6a5f4SSimon Horman 267b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2686199a10eSWolfram Sang 269b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2706199a10eSWolfram Sang 27111a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2726199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 2736199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 2746199a10eSWolfram Sang 27571cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 2766199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 2776199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 2786199a10eSWolfram Sang 27926eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 28026eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 281b5b6a5f4SSimon Horman 282ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 283ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 284ce6f92c2SWolfram Sang 285ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 286ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 287ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 288ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 289ce6f92c2SWolfram Sang 290ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 291ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 292ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 293ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 294ce6f92c2SWolfram Sang 295ce6f92c2SWolfram Sang static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 296ce6f92c2SWolfram Sang { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 297ce6f92c2SWolfram Sang 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 298ce6f92c2SWolfram Sang { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 299ce6f92c2SWolfram Sang 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 300ce6f92c2SWolfram Sang }; 301ce6f92c2SWolfram Sang 302ce6f92c2SWolfram Sang static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 303ce6f92c2SWolfram Sang { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 304ce6f92c2SWolfram Sang 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 305ce6f92c2SWolfram Sang { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 306ce6f92c2SWolfram Sang 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 307ce6f92c2SWolfram Sang }; 308ce6f92c2SWolfram Sang 309ce6f92c2SWolfram Sang static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 310ce6f92c2SWolfram Sang { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 311ce6f92c2SWolfram Sang 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 312ce6f92c2SWolfram Sang { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 313ce6f92c2SWolfram Sang 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 314ce6f92c2SWolfram Sang }; 315ce6f92c2SWolfram Sang 316b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 317b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 318b5b6a5f4SSimon Horman { 319b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 320b5b6a5f4SSimon Horman } 321b5b6a5f4SSimon Horman 322b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 323b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 324b5b6a5f4SSimon Horman int addr, u32 val) 325b5b6a5f4SSimon Horman { 326b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 327b5b6a5f4SSimon Horman } 328b5b6a5f4SSimon Horman 329b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 330b5b6a5f4SSimon Horman { 331b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 332b5b6a5f4SSimon Horman 333b5b6a5f4SSimon Horman priv = host_to_priv(host); 334b5b6a5f4SSimon Horman 335b5b6a5f4SSimon Horman /* Initialize SCC */ 336b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 337b5b6a5f4SSimon Horman 338b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 339b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 340b5b6a5f4SSimon Horman 34126eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 34226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 34326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 34426eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 34526eb2607SMasaharu Hayakawa 346b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 347b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 348b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 349b5b6a5f4SSimon Horman 350b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 351b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 352b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 353b5b6a5f4SSimon Horman 354852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 355b5b6a5f4SSimon Horman 35626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 35726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 35826eb2607SMasaharu Hayakawa 359b5b6a5f4SSimon Horman /* Read TAPNUM */ 360b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 361b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 362b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 363b5b6a5f4SSimon Horman } 364b5b6a5f4SSimon Horman 365f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 36626eb2607SMasaharu Hayakawa { 367f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 36826eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 369a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 370a38c078fSTakeshi Saito bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 37126eb2607SMasaharu Hayakawa 37226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 37326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 37426eb2607SMasaharu Hayakawa 37526eb2607SMasaharu Hayakawa /* Set HS400 mode */ 37626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 37726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 378f0c8234cSTakeshi Saito 379f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 380f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 381f0c8234cSTakeshi Saito 3829b0d6855SWolfram Sang /* Gen3 can't do automatic tap correction with HS400, so disable it */ 3839b0d6855SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 3849b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3859b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3869b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3879b0d6855SWolfram Sang 38826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 38926eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 39026eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 39126eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 39226eb2607SMasaharu Hayakawa 39326eb2607SMasaharu Hayakawa /* Set the sampling clock selection range of HS400 mode */ 39426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 39526eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 39626eb2607SMasaharu Hayakawa 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 39726eb2607SMasaharu Hayakawa 398a38c078fSTakeshi Saito /* Avoid bad TAP */ 399a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) { 400a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 40126eb2607SMasaharu Hayakawa 402a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) 403a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num; 404a38c078fSTakeshi Saito 405a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) { 406a38c078fSTakeshi Saito new_tap = priv->tap_set; 407a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 408a38c078fSTakeshi Saito } 409a38c078fSTakeshi Saito 410a38c078fSTakeshi Saito priv->tap_set = new_tap; 411a38c078fSTakeshi Saito } 412a38c078fSTakeshi Saito 41326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 414a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1)); 41526eb2607SMasaharu Hayakawa 41626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 41726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 41826eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 41926eb2607SMasaharu Hayakawa 42026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 42126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 422ce6f92c2SWolfram Sang 423ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 424ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true; 42526eb2607SMasaharu Hayakawa } 42626eb2607SMasaharu Hayakawa 427*80d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 42826eb2607SMasaharu Hayakawa { 429*80d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 430*80d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 431*80d0be81SWolfram Sang 43226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 43326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 43426eb2607SMasaharu Hayakawa 43526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 43626eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 43726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 43826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 43926eb2607SMasaharu Hayakawa 44026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 44126eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 44226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 44426eb2607SMasaharu Hayakawa 44526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 44626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 44726eb2607SMasaharu Hayakawa } 44826eb2607SMasaharu Hayakawa 449ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 450ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr) 451ce6f92c2SWolfram Sang { 452ce6f92c2SWolfram Sang /* read mode */ 453ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 454ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 455ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 456ce6f92c2SWolfram Sang 457ce6f92c2SWolfram Sang /* access start and stop */ 458ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 459ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 460ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 461ce6f92c2SWolfram Sang 462ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 463ce6f92c2SWolfram Sang } 464ce6f92c2SWolfram Sang 465ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 466ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val) 467ce6f92c2SWolfram Sang { 468ce6f92c2SWolfram Sang /* write mode */ 469ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 470ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 471ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 472ce6f92c2SWolfram Sang 473ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 474ce6f92c2SWolfram Sang 475ce6f92c2SWolfram Sang /* access start and stop */ 476ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 477ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 478ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 479ce6f92c2SWolfram Sang } 480ce6f92c2SWolfram Sang 481ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 482ce6f92c2SWolfram Sang { 483ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 484ce6f92c2SWolfram Sang u32 calib_code; 485ce6f92c2SWolfram Sang 486ce6f92c2SWolfram Sang /* disable write protect */ 487ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 488ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 489ce6f92c2SWolfram Sang /* read calibration code and adjust */ 490ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 491ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 492ce6f92c2SWolfram Sang 493ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 494ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 495ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]); 496ce6f92c2SWolfram Sang 497ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 498ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 499ce6f92c2SWolfram Sang 500ce6f92c2SWolfram Sang /* adjustment done, clear flag */ 501ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 502ce6f92c2SWolfram Sang } 503ce6f92c2SWolfram Sang 504ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 505ce6f92c2SWolfram Sang { 506ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 507ce6f92c2SWolfram Sang 508ce6f92c2SWolfram Sang /* disable write protect */ 509ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 510ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 511ce6f92c2SWolfram Sang /* disable manual calibration */ 512ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0); 513ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */ 514ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 515ce6f92c2SWolfram Sang } 516ce6f92c2SWolfram Sang 51726eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 51826eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 51926eb2607SMasaharu Hayakawa { 52026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 52126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 52226eb2607SMasaharu Hayakawa 52326eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 52426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 52526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 526f0c8234cSTakeshi Saito 527f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 528f0c8234cSTakeshi Saito 52926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 53026eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 53126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 53226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 53326eb2607SMasaharu Hayakawa 534ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 535ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host); 536ce6f92c2SWolfram Sang 53726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 53826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 53926eb2607SMasaharu Hayakawa } 54026eb2607SMasaharu Hayakawa 541f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 54226eb2607SMasaharu Hayakawa { 543f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 544f22084b6SWolfram Sang 54526eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 546f22084b6SWolfram Sang return 0; 54726eb2607SMasaharu Hayakawa } 54826eb2607SMasaharu Hayakawa 5499f809065SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */ 5505b0739d7SWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host) 5515b0739d7SWolfram Sang { 5525b0739d7SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 5535b0739d7SWolfram Sang 55445bffc37SWolfram Sang if (priv->scc_ctl) { 555183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc); 5565b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv); 557ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 5585b0739d7SWolfram Sang 5595b0739d7SWolfram Sang sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 5605b0739d7SWolfram Sang sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 5615b0739d7SWolfram Sang 5625b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 5635b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 5645b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 56545bffc37SWolfram Sang } 5665b0739d7SWolfram Sang 5679f809065SWolfram Sang sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_INIT_RCAR2); 5685b0739d7SWolfram Sang } 5695b0739d7SWolfram Sang 570ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 571b5b6a5f4SSimon Horman 572b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 573b5b6a5f4SSimon Horman { 574b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 57592fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 5765fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row; 5775fb6bf51SWolfram Sang unsigned long *bitmap; 578b5b6a5f4SSimon Horman 579b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 580b5b6a5f4SSimon Horman 581b5b6a5f4SSimon Horman /* 5825c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 5835c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 5845c99826bSNiklas Söderlund * considering it for tuning selection. 5855c99826bSNiklas Söderlund */ 58692fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) { 587b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 5885c99826bSNiklas Söderlund 589b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps)) 590b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps); 5915fb6bf51SWolfram Sang 5925fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp)) 5935fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp); 5945fb6bf51SWolfram Sang } 5955fb6bf51SWolfram Sang 5965fb6bf51SWolfram Sang /* 5975fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by 5985fb6bf51SWolfram Sang * identifying the change point of data. 5995fb6bf51SWolfram Sang */ 6005fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) { 6015fb6bf51SWolfram Sang bitmap = priv->smpcmp; 6025fb6bf51SWolfram Sang min_tap_row = 1; 6035fb6bf51SWolfram Sang } else { 6045fb6bf51SWolfram Sang bitmap = priv->taps; 6055fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 6065c99826bSNiklas Söderlund } 6075c99826bSNiklas Söderlund 6085c99826bSNiklas Söderlund /* 609b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 610ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 611ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out. 612b5b6a5f4SSimon Horman */ 6135fb6bf51SWolfram Sang bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 61492fa2a56SWolfram Sang if (re - rs > tap_cnt) { 61592fa2a56SWolfram Sang tap_end = re; 61692fa2a56SWolfram Sang tap_start = rs; 61792fa2a56SWolfram Sang tap_cnt = tap_end - tap_start; 618b5b6a5f4SSimon Horman } 619b5b6a5f4SSimon Horman } 620b5b6a5f4SSimon Horman 6215fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row) 622b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 623b5b6a5f4SSimon Horman else 624b5b6a5f4SSimon Horman return -EIO; 625b5b6a5f4SSimon Horman 626b5b6a5f4SSimon Horman /* Set SCC */ 627b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 628b5b6a5f4SSimon Horman 629b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 630b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 631b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 632b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 633b5b6a5f4SSimon Horman 634b5b6a5f4SSimon Horman return 0; 635b5b6a5f4SSimon Horman } 636b5b6a5f4SSimon Horman 637510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 6380c482d82SWolfram Sang { 639510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 6400c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 6415b0739d7SWolfram Sang int i, ret; 6420c482d82SWolfram Sang 643b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host); 644b2dd9a13SWolfram Sang if (!priv->tap_num) 6450c482d82SWolfram Sang return 0; /* Tuning is not supported */ 6460c482d82SWolfram Sang 647b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 6483a821a82SWolfram Sang dev_err(&host->pdev->dev, 6493a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 6503a821a82SWolfram Sang return -EINVAL; 6510c482d82SWolfram Sang } 6520c482d82SWolfram Sang 653b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2); 6545fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2); 6550c482d82SWolfram Sang 6560c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 657b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) { 6580c482d82SWolfram Sang /* Set sampling clock position */ 659b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 6600c482d82SWolfram Sang 661510bfe58SWolfram Sang if (mmc_send_tuning(mmc, opcode, NULL) == 0) 662b2dd9a13SWolfram Sang set_bit(i, priv->taps); 6635fb6bf51SWolfram Sang 6645fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 6655fb6bf51SWolfram Sang set_bit(i, priv->smpcmp); 6660c482d82SWolfram Sang } 6670c482d82SWolfram Sang 6685b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host); 6695b0739d7SWolfram Sang if (ret < 0) 6705b0739d7SWolfram Sang renesas_sdhi_reset(host); 6715b0739d7SWolfram Sang return ret; 6720c482d82SWolfram Sang } 6730c482d82SWolfram Sang 67411a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 67511a21960STakeshi Saito { 67611a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 677a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 67811a21960STakeshi Saito u32 val; 67911a21960STakeshi Saito 68011a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 68111a21960STakeshi Saito if (!val) 68211a21960STakeshi Saito return false; 68311a21960STakeshi Saito 68411a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 68511a21960STakeshi Saito 68611a21960STakeshi Saito /* Change TAP position according to correction status */ 68771cfc927STakeshi Saito if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 68871cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 689a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 69071cfc927STakeshi Saito /* 69171cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 69271cfc927STakeshi Saito * Therefore, use only CMD status. 69371cfc927STakeshi Saito */ 69471cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 69571cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 696a38c078fSTakeshi Saito if (!smpcmp) { 69771cfc927STakeshi Saito return false; /* no error in CMD signal */ 698a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 69971cfc927STakeshi Saito new_tap++; 700a38c078fSTakeshi Saito error_tap--; 701a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 70271cfc927STakeshi Saito new_tap--; 703a38c078fSTakeshi Saito error_tap++; 704a38c078fSTakeshi Saito } else { 70571cfc927STakeshi Saito return true; /* need retune */ 706a38c078fSTakeshi Saito } 707a38c078fSTakeshi Saito 708a38c078fSTakeshi Saito /* 709a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare 710a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK, 711a38c078fSTakeshi Saito * we can at least retune. 712a38c078fSTakeshi Saito */ 713a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num)) 714a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp); 71571cfc927STakeshi Saito } else { 71611a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 71771cfc927STakeshi Saito return true; /* need retune */ 71811a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 71971cfc927STakeshi Saito new_tap++; 72011a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 72171cfc927STakeshi Saito new_tap--; 72211a21960STakeshi Saito else 72311a21960STakeshi Saito return false; 72471cfc927STakeshi Saito } 72511a21960STakeshi Saito 726b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num); 72711a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 728b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1)); 72911a21960STakeshi Saito 73011a21960STakeshi Saito return false; 73111a21960STakeshi Saito } 73211a21960STakeshi Saito 73311a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 73411a21960STakeshi Saito { 73511a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 73611a21960STakeshi Saito 73711a21960STakeshi Saito /* Check SCC error */ 73811a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 73911a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 74011a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 74111a21960STakeshi Saito return true; 74211a21960STakeshi Saito } 74311a21960STakeshi Saito 74411a21960STakeshi Saito return false; 74511a21960STakeshi Saito } 74611a21960STakeshi Saito 747b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 748b5b6a5f4SSimon Horman { 749b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 75012e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 75175f349a1SMasaharu Hayakawa 75275f349a1SMasaharu Hayakawa /* 75375f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 75475f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 75575f349a1SMasaharu Hayakawa */ 75675f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 75775f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 75875f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 75975f349a1SMasaharu Hayakawa return false; 76075f349a1SMasaharu Hayakawa 761fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc)) 76275f349a1SMasaharu Hayakawa return false; 763b5b6a5f4SSimon Horman 764b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 76511a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 76611a21960STakeshi Saito return renesas_sdhi_auto_correction(host); 767b5b6a5f4SSimon Horman 76811a21960STakeshi Saito return renesas_sdhi_manual_correction(host, use_4tap); 769b5b6a5f4SSimon Horman } 770b5b6a5f4SSimon Horman 7714dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 772b5b6a5f4SSimon Horman { 773b5b6a5f4SSimon Horman int timeout = 1000; 7744dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 7754dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 776b5b6a5f4SSimon Horman 7774dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 7784dc48a95SWolfram Sang & bit) == wait_state) 779b5b6a5f4SSimon Horman udelay(1); 780b5b6a5f4SSimon Horman 781b5b6a5f4SSimon Horman if (!timeout) { 782b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 783b5b6a5f4SSimon Horman return -EBUSY; 784b5b6a5f4SSimon Horman } 785b5b6a5f4SSimon Horman 786b5b6a5f4SSimon Horman return 0; 787b5b6a5f4SSimon Horman } 788b5b6a5f4SSimon Horman 789b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 790b5b6a5f4SSimon Horman { 7914dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 7924dc48a95SWolfram Sang 7932fe35968SSimon Horman switch (addr) { 794b5b6a5f4SSimon Horman case CTL_SD_CMD: 795b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 796b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 797b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 798b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 799b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 800b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 8014472f0fcSMasaharu Hayakawa case HOST_MODE: 8025124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 8034dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 804df561f66SGustavo A. R. Silva fallthrough; 8054dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 8064dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 807b5b6a5f4SSimon Horman } 808b5b6a5f4SSimon Horman 809b5b6a5f4SSimon Horman return 0; 810b5b6a5f4SSimon Horman } 811b5b6a5f4SSimon Horman 812b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 813b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 814b5b6a5f4SSimon Horman { 815b5b6a5f4SSimon Horman /* 816b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 817b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 818b5b6a5f4SSimon Horman * depending on the timing with which the 819b5b6a5f4SSimon Horman * response register is read, the response 820b5b6a5f4SSimon Horman * value may not be read properly. 821b5b6a5f4SSimon Horman * Use single block read for this HW bug 822b5b6a5f4SSimon Horman */ 823b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 824b5b6a5f4SSimon Horman blk_size == 2) 825b5b6a5f4SSimon Horman return 1; 826b5b6a5f4SSimon Horman 827b5b6a5f4SSimon Horman return blk_size; 828b5b6a5f4SSimon Horman } 829b5b6a5f4SSimon Horman 830ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 831ce6f92c2SWolfram Sang { 832ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 833ce6f92c2SWolfram Sang 834ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 835ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host); 836ce6f92c2SWolfram Sang } 837b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 838b5b6a5f4SSimon Horman { 83941279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 84041279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 841b5b6a5f4SSimon Horman 84241279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 84341279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 844b5b6a5f4SSimon Horman } 845b5b6a5f4SSimon Horman 8466a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 8470f4e2054SNiklas Söderlund .hs400_disabled = true, 8480f4e2054SNiklas Söderlund .hs400_4taps = true, 8490f4e2054SNiklas Söderlund }; 8500f4e2054SNiklas Söderlund 8516a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 852164691aaSNiklas Söderlund .hs400_4taps = true, 853a38c078fSTakeshi Saito .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 854164691aaSNiklas Söderlund }; 855164691aaSNiklas Söderlund 85697bf85b6SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 85797bf85b6SWolfram Sang .hs400_disabled = true, 85897bf85b6SWolfram Sang }; 85997bf85b6SWolfram Sang 860a38c078fSTakeshi Saito static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 861a38c078fSTakeshi Saito .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 862a38c078fSTakeshi Saito }; 863a38c078fSTakeshi Saito 864a38c078fSTakeshi Saito static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 865a38c078fSTakeshi Saito .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 866a38c078fSTakeshi Saito }; 867a38c078fSTakeshi Saito 868ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 869ce6f92c2SWolfram Sang .hs400_4taps = true, 870ce6f92c2SWolfram Sang .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 871ce6f92c2SWolfram Sang .hs400_calib_table = r8a7796_es13_calib_table, 872ce6f92c2SWolfram Sang }; 873ce6f92c2SWolfram Sang 874ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 875ce6f92c2SWolfram Sang .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 876ce6f92c2SWolfram Sang .hs400_calib_table = r8a77965_calib_table, 877ce6f92c2SWolfram Sang }; 878ce6f92c2SWolfram Sang 879ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 880ce6f92c2SWolfram Sang .hs400_calib_table = r8a77990_calib_table, 881ce6f92c2SWolfram Sang }; 882ce6f92c2SWolfram Sang 883f583da40SWolfram Sang /* 884f583da40SWolfram Sang * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 885f583da40SWolfram Sang * So, we want to treat them equally and only have a match for ES1.2 to enforce 886f583da40SWolfram Sang * this if there ever will be a way to distinguish ES1.2. 887f583da40SWolfram Sang */ 888164691aaSNiklas Söderlund static const struct soc_device_attribute sdhi_quirks_match[] = { 8896e3cbb05SWolfram Sang { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 8906a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 8916a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 892a38c078fSTakeshi Saito { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 }, 8936a686986SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 894ce6f92c2SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 895a38c078fSTakeshi Saito { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 }, 896ce6f92c2SWolfram Sang { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 }, 89797bf85b6SWolfram Sang { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 898ce6f92c2SWolfram Sang { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 }, 899164691aaSNiklas Söderlund { /* Sentinel. */ }, 900164691aaSNiklas Söderlund }; 901164691aaSNiklas Söderlund 9029d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 9039d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 904b5b6a5f4SSimon Horman { 905b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 906164691aaSNiklas Söderlund const struct renesas_sdhi_quirks *quirks = NULL; 9072fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 908164691aaSNiklas Söderlund const struct soc_device_attribute *attr; 9092fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 9102fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 911b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 9122fe35968SSimon Horman struct renesas_sdhi *priv; 913e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 914b5b6a5f4SSimon Horman struct resource *res; 915c9a9497cSWolfram Sang u16 ver; 9162fe35968SSimon Horman 9172fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 918b5b6a5f4SSimon Horman 919164691aaSNiklas Söderlund attr = soc_device_match(sdhi_quirks_match); 920164691aaSNiklas Söderlund if (attr) 921164691aaSNiklas Söderlund quirks = attr->data; 922164691aaSNiklas Söderlund 923b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 924b5b6a5f4SSimon Horman if (!res) 925b5b6a5f4SSimon Horman return -EINVAL; 926b5b6a5f4SSimon Horman 9272fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 9282fe35968SSimon Horman GFP_KERNEL); 929b5b6a5f4SSimon Horman if (!priv) 930b5b6a5f4SSimon Horman return -ENOMEM; 931b5b6a5f4SSimon Horman 9327af08206SWolfram Sang priv->quirks = quirks; 933b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 934b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 935b5b6a5f4SSimon Horman 936b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 937b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 938b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 939b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 9404ce62817SMasahiro Yamada return ret; 941b5b6a5f4SSimon Horman } 942b5b6a5f4SSimon Horman 943b5b6a5f4SSimon Horman /* 944b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 945b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 946b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 947b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 948b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 949b5b6a5f4SSimon Horman * disable it. 950b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 951b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 952b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 953b5b6a5f4SSimon Horman */ 954b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 955b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 956b5b6a5f4SSimon Horman priv->clk_cd = NULL; 957b5b6a5f4SSimon Horman 958b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 959b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 960b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 961b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 962b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 963b5b6a5f4SSimon Horman "state_uhs"); 964b5b6a5f4SSimon Horman } 965b5b6a5f4SSimon Horman 966b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 9678d09a133SMasahiro Yamada if (IS_ERR(host)) 9688d09a133SMasahiro Yamada return PTR_ERR(host); 969b5b6a5f4SSimon Horman 970b5b6a5f4SSimon Horman if (of_data) { 971b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 972b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 973b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 974b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 975b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 976603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 977603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 978b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 979b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 980b5b6a5f4SSimon Horman } 981b5b6a5f4SSimon Horman 982b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 983b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 984b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 9850196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 986b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 987bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 988b5b6a5f4SSimon Horman 9890f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 9900f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 9910f4e2054SNiklas Söderlund 992ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 993ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 994ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 995ef5332c1SWolfram Sang 996b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 997b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 998b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 9992aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 10002aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 1001b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 10021970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 10036e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset; 1004d30ae056STakeshi Saito } 1005b5b6a5f4SSimon Horman 1006b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1007b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1008b5b6a5f4SSimon Horman host->bus_shift = 1; 1009b5b6a5f4SSimon Horman 1010b5b6a5f4SSimon Horman if (mmd) 1011b5b6a5f4SSimon Horman *mmc_data = *mmd; 1012b5b6a5f4SSimon Horman 1013b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 1014b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 1015b5b6a5f4SSimon Horman 1016b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1017b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1018b5b6a5f4SSimon Horman 1019b5b6a5f4SSimon Horman /* 1020b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1021b5b6a5f4SSimon Horman * bus width mode. 1022b5b6a5f4SSimon Horman */ 1023b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1024b5b6a5f4SSimon Horman 1025b5b6a5f4SSimon Horman /* 1026b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 1027b5b6a5f4SSimon Horman */ 1028b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1029b5b6a5f4SSimon Horman 10302fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 1031b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1032b5b6a5f4SSimon Horman 1033b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 1034b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1035b5b6a5f4SSimon Horman 103663fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev); 103763fd8ef3SUlf Hansson 1038b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 1039b21fc294SMasahiro Yamada if (ret) 1040b5b6a5f4SSimon Horman goto efree; 1041b5b6a5f4SSimon Horman 1042c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 1043c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1044c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1045c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 1046c9a9497cSWolfram Sang 10475124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1048c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 10495124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 10505124b592SWolfram Sang 1051ce6f92c2SWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1052ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request; 1053ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *( 1054ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ? 1055ce6f92c2SWolfram Sang quirks->hs400_calib_table : 1056ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1); 1057ce6f92c2SWolfram Sang } 1058ce6f92c2SWolfram Sang 1059b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 1060b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 1061b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 106226eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 106326eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 1064b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 1065c1a49782SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1066b5b6a5f4SSimon Horman bool hit = false; 1067b5b6a5f4SSimon Horman 1068b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 1069b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 1070b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 1071852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 1072c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 1073c1a49782SWolfram Sang taps->tap_hs400_4tap : 1074c1a49782SWolfram Sang taps->tap; 1075b5b6a5f4SSimon Horman hit = true; 1076b5b6a5f4SSimon Horman break; 1077b5b6a5f4SSimon Horman } 1078b5b6a5f4SSimon Horman } 1079b5b6a5f4SSimon Horman 1080b5b6a5f4SSimon Horman if (!hit) 1081e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1082b5b6a5f4SSimon Horman 1083d14ac691SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset; 108464982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error; 1085510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1086f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1087f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1088f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1089b5b6a5f4SSimon Horman } 1090b5b6a5f4SSimon Horman 1091b161d87dSWolfram Sang ret = tmio_mmc_host_probe(host); 1092b161d87dSWolfram Sang if (ret < 0) 1093b161d87dSWolfram Sang goto edisclk; 1094b161d87dSWolfram Sang 1095e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 1096e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 1097e8307ec5SGeert Uytterhoeven ret = num_irqs; 1098b5b6a5f4SSimon Horman goto eirq; 1099b5b6a5f4SSimon Horman } 1100b5b6a5f4SSimon Horman 1101b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 1102e8307ec5SGeert Uytterhoeven if (!num_irqs) { 1103e8307ec5SGeert Uytterhoeven ret = -ENXIO; 1104e8307ec5SGeert Uytterhoeven goto eirq; 1105e8307ec5SGeert Uytterhoeven } 1106e8307ec5SGeert Uytterhoeven 1107e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 1108e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 1109e8307ec5SGeert Uytterhoeven if (irq < 0) { 1110b5b6a5f4SSimon Horman ret = irq; 1111b5b6a5f4SSimon Horman goto eirq; 1112b5b6a5f4SSimon Horman } 1113b5b6a5f4SSimon Horman 1114e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1115e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 1116e8307ec5SGeert Uytterhoeven if (ret) 1117e8307ec5SGeert Uytterhoeven goto eirq; 1118e8307ec5SGeert Uytterhoeven } 1119e8307ec5SGeert Uytterhoeven 1120bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1121bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1122b5b6a5f4SSimon Horman 1123b5b6a5f4SSimon Horman return ret; 1124b5b6a5f4SSimon Horman 1125b5b6a5f4SSimon Horman eirq: 1126b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1127b21fc294SMasahiro Yamada edisclk: 1128b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1129b5b6a5f4SSimon Horman efree: 1130b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 11314ce62817SMasahiro Yamada 1132b5b6a5f4SSimon Horman return ret; 1133b5b6a5f4SSimon Horman } 11349d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1135b5b6a5f4SSimon Horman 11369d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 1137b5b6a5f4SSimon Horman { 1138a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1139b5b6a5f4SSimon Horman 1140b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1141b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1142e8973201SYoshihiro Shimoda tmio_mmc_host_free(host); 1143b5b6a5f4SSimon Horman 1144b5b6a5f4SSimon Horman return 0; 1145b5b6a5f4SSimon Horman } 11469d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1147967a6a07SMasaharu Hayakawa 1148967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 1149