1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/kernel.h> 22b5b6a5f4SSimon Horman #include <linux/clk.h> 23b5b6a5f4SSimon Horman #include <linux/slab.h> 24967a6a07SMasaharu Hayakawa #include <linux/module.h> 25b5b6a5f4SSimon Horman #include <linux/of_device.h> 26b5b6a5f4SSimon Horman #include <linux/platform_device.h> 2763fd8ef3SUlf Hansson #include <linux/pm_domain.h> 28b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 29ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h> 30ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 31b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 32b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 33b5b6a5f4SSimon Horman #include <linux/delay.h> 34b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 35b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 36b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 37164691aaSNiklas Söderlund #include <linux/sys_soc.h> 38b5b6a5f4SSimon Horman 39b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 40b5b6a5f4SSimon Horman #include "tmio_mmc.h" 41b5b6a5f4SSimon Horman 42*4533c3ebSWolfram Sang #define CTL_HOST_MODE 0xe4 43*4533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 44*4533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 45*4533c3ebSWolfram Sang #define HOST_MODE_GEN3_WMODE BIT(0) 46*4533c3ebSWolfram Sang #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 47*4533c3ebSWolfram Sang 48*4533c3ebSWolfram Sang #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 49*4533c3ebSWolfram Sang #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 50*4533c3ebSWolfram Sang #define HOST_MODE_GEN3_64BIT 0 51b5b6a5f4SSimon Horman 52b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 53c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 54b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 55b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 56b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 57b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 58b5b6a5f4SSimon Horman 59ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000 60ce6f92c2SWolfram Sang 61b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 62b5b6a5f4SSimon Horman { 63b5b6a5f4SSimon Horman u32 val; 64b5b6a5f4SSimon Horman 65b5b6a5f4SSimon Horman /* 66b5b6a5f4SSimon Horman * see also 67b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 68b5b6a5f4SSimon Horman */ 69b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 70b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 71*4533c3ebSWolfram Sang val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 72b5b6a5f4SSimon Horman break; 73b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 74*4533c3ebSWolfram Sang val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 75b5b6a5f4SSimon Horman break; 76b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 77b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 78b5b6a5f4SSimon Horman if (width == 64) 79*4533c3ebSWolfram Sang val = HOST_MODE_GEN3_64BIT; 80b5b6a5f4SSimon Horman else if (width == 32) 81*4533c3ebSWolfram Sang val = HOST_MODE_GEN3_32BIT; 82b5b6a5f4SSimon Horman else 83*4533c3ebSWolfram Sang val = HOST_MODE_GEN3_16BIT; 84b5b6a5f4SSimon Horman break; 85b5b6a5f4SSimon Horman default: 86b5b6a5f4SSimon Horman /* nothing to do */ 87b5b6a5f4SSimon Horman return; 88b5b6a5f4SSimon Horman } 89b5b6a5f4SSimon Horman 90*4533c3ebSWolfram Sang sd_ctrl_write16(host, CTL_HOST_MODE, val); 91b5b6a5f4SSimon Horman } 92b5b6a5f4SSimon Horman 93b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 94b5b6a5f4SSimon Horman { 95b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 96b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 97d42c9fffSWolfram Sang int ret; 98b5b6a5f4SSimon Horman 99b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 100d42c9fffSWolfram Sang if (ret < 0) 101b5b6a5f4SSimon Horman return ret; 102b5b6a5f4SSimon Horman 103b5b6a5f4SSimon Horman /* 104b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 105b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 106b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 107b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 108b5b6a5f4SSimon Horman */ 109b5b6a5f4SSimon Horman if (!mmc->f_max) 110b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 111b5b6a5f4SSimon Horman 112b5b6a5f4SSimon Horman /* 113b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 114b5b6a5f4SSimon Horman * divided by our maximum divider. 115b5b6a5f4SSimon Horman */ 116b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 117b5b6a5f4SSimon Horman 118b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 119b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 120b5b6a5f4SSimon Horman 121b5b6a5f4SSimon Horman return 0; 122b5b6a5f4SSimon Horman } 123b5b6a5f4SSimon Horman 124b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 125b5b6a5f4SSimon Horman unsigned int new_clock) 126b5b6a5f4SSimon Horman { 127b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 128b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 12975eaf49fSTamás Szűcs int i; 130b5b6a5f4SSimon Horman 1310f93db65SWolfram Sang /* 1320f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+ 1330f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its 1340f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup. 1350f93db65SWolfram Sang */ 1360f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 137b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 138b5b6a5f4SSimon Horman 139b5b6a5f4SSimon Horman /* 140b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 141b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 142b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 143b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 144b5b6a5f4SSimon Horman */ 145b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 146b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 147b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 148b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 149b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 150b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 151b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 152b5b6a5f4SSimon Horman continue; 153b5b6a5f4SSimon Horman } 154b5b6a5f4SSimon Horman 155b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 156b5b6a5f4SSimon Horman if (diff <= diff_min) { 157b5b6a5f4SSimon Horman best_freq = freq; 158b5b6a5f4SSimon Horman diff_min = diff; 159b5b6a5f4SSimon Horman } 160b5b6a5f4SSimon Horman } 161b5b6a5f4SSimon Horman 16275eaf49fSTamás Szűcs clk_set_rate(priv->clk, best_freq); 163b5b6a5f4SSimon Horman 16475eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 165b5b6a5f4SSimon Horman } 166b5b6a5f4SSimon Horman 1670196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1680196c8dbSMasahiro Yamada unsigned int new_clock) 1690196c8dbSMasahiro Yamada { 1700196c8dbSMasahiro Yamada u32 clk = 0, clock; 1710196c8dbSMasahiro Yamada 17268f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 17368f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 17468f83127SMasahiro Yamada 17575eaf49fSTamás Szűcs if (new_clock == 0) { 17675eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 17768f83127SMasahiro Yamada goto out; 17875eaf49fSTamás Szűcs } 17968f83127SMasahiro Yamada 18075eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 18175eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 1820196c8dbSMasahiro Yamada 1830196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 1840196c8dbSMasahiro Yamada clock <<= 1; 1850196c8dbSMasahiro Yamada 1860196c8dbSMasahiro Yamada /* 1/1 clock is option */ 1870196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 1880196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 1890196c8dbSMasahiro Yamada clk |= 0xff; 1900196c8dbSMasahiro Yamada else 1910196c8dbSMasahiro Yamada clk &= ~0xff; 1920196c8dbSMasahiro Yamada } 1930196c8dbSMasahiro Yamada 1940196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 1950196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 1960196c8dbSMasahiro Yamada usleep_range(10000, 11000); 1970196c8dbSMasahiro Yamada 19868f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 19968f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 20068f83127SMasahiro Yamada 20168f83127SMasahiro Yamada out: 20268f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 20368f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 20468f83127SMasahiro Yamada usleep_range(10000, 11000); 2050196c8dbSMasahiro Yamada } 2060196c8dbSMasahiro Yamada 207b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 208b5b6a5f4SSimon Horman { 209b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 210b5b6a5f4SSimon Horman 211b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 212b5b6a5f4SSimon Horman } 213b5b6a5f4SSimon Horman 214b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 215b5b6a5f4SSimon Horman { 216b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 217b5b6a5f4SSimon Horman 2182fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2192fe35968SSimon Horman TMIO_STAT_DAT0); 220b5b6a5f4SSimon Horman } 221b5b6a5f4SSimon Horman 222b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 223b5b6a5f4SSimon Horman struct mmc_ios *ios) 224b5b6a5f4SSimon Horman { 225b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 226b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 227b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 228b5b6a5f4SSimon Horman int ret; 229b5b6a5f4SSimon Horman 230b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 231b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 232b5b6a5f4SSimon Horman pin_state = priv->pins_default; 233b5b6a5f4SSimon Horman break; 234b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 235b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 236b5b6a5f4SSimon Horman break; 237b5b6a5f4SSimon Horman default: 238b5b6a5f4SSimon Horman return -EINVAL; 239b5b6a5f4SSimon Horman } 240b5b6a5f4SSimon Horman 241b5b6a5f4SSimon Horman /* 242b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 243b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 244b5b6a5f4SSimon Horman */ 245b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 246b5b6a5f4SSimon Horman return ios->signal_voltage == 247b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 248b5b6a5f4SSimon Horman 249b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 2509cbe0fc8SMarek Vasut if (ret < 0) 251b5b6a5f4SSimon Horman return ret; 252b5b6a5f4SSimon Horman 253b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 254b5b6a5f4SSimon Horman } 255b5b6a5f4SSimon Horman 256b5b6a5f4SSimon Horman /* SCC registers */ 257b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 258b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 259b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 260b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 261b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 262b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 26371cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 26426eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 265ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 266ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 267ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 268ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 269ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 270b5b6a5f4SSimon Horman 271b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 272b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 273b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 274b5b6a5f4SSimon Horman 275b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2766199a10eSWolfram Sang 277b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2786199a10eSWolfram Sang 27911a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2806199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 2816199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 2826199a10eSWolfram Sang 28371cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 2846199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 2856199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 2866199a10eSWolfram Sang 28726eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 28826eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 289b5b6a5f4SSimon Horman 290ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 291ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 292ce6f92c2SWolfram Sang 293ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 294ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 295ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 296ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 297ce6f92c2SWolfram Sang 298ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 299ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 300ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 301ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 302ce6f92c2SWolfram Sang 303ce6f92c2SWolfram Sang static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 304ce6f92c2SWolfram Sang { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 305ce6f92c2SWolfram Sang 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 306ce6f92c2SWolfram Sang { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 307ce6f92c2SWolfram Sang 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 308ce6f92c2SWolfram Sang }; 309ce6f92c2SWolfram Sang 310ce6f92c2SWolfram Sang static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 311ce6f92c2SWolfram Sang { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 312ce6f92c2SWolfram Sang 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 313ce6f92c2SWolfram Sang { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 314ce6f92c2SWolfram Sang 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 315ce6f92c2SWolfram Sang }; 316ce6f92c2SWolfram Sang 317ce6f92c2SWolfram Sang static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 318ce6f92c2SWolfram Sang { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 319ce6f92c2SWolfram Sang 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 320ce6f92c2SWolfram Sang { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 321ce6f92c2SWolfram Sang 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 322ce6f92c2SWolfram Sang }; 323ce6f92c2SWolfram Sang 324b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 325b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 326b5b6a5f4SSimon Horman { 327b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 328b5b6a5f4SSimon Horman } 329b5b6a5f4SSimon Horman 330b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 331b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 332b5b6a5f4SSimon Horman int addr, u32 val) 333b5b6a5f4SSimon Horman { 334b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 335b5b6a5f4SSimon Horman } 336b5b6a5f4SSimon Horman 337b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 338b5b6a5f4SSimon Horman { 339b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 340b5b6a5f4SSimon Horman 341b5b6a5f4SSimon Horman priv = host_to_priv(host); 342b5b6a5f4SSimon Horman 343b5b6a5f4SSimon Horman /* Initialize SCC */ 344b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 345b5b6a5f4SSimon Horman 346b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 347b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 348b5b6a5f4SSimon Horman 34926eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 35026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 35126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 35226eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 35326eb2607SMasaharu Hayakawa 354b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 355b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 356b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 357b5b6a5f4SSimon Horman 358b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 359b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 360b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 361b5b6a5f4SSimon Horman 362852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 363b5b6a5f4SSimon Horman 36426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 36526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36626eb2607SMasaharu Hayakawa 367b5b6a5f4SSimon Horman /* Read TAPNUM */ 368b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 369b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 370b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 371b5b6a5f4SSimon Horman } 372b5b6a5f4SSimon Horman 373f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 37426eb2607SMasaharu Hayakawa { 375f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 37626eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 377a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 378a38c078fSTakeshi Saito bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 37926eb2607SMasaharu Hayakawa 38026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 38126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 38226eb2607SMasaharu Hayakawa 38326eb2607SMasaharu Hayakawa /* Set HS400 mode */ 38426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 38526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 386f0c8234cSTakeshi Saito 387f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 388f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 389f0c8234cSTakeshi Saito 3909b0d6855SWolfram Sang /* Gen3 can't do automatic tap correction with HS400, so disable it */ 3919b0d6855SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 3929b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3939b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3949b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3959b0d6855SWolfram Sang 39626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 39726eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 39826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 39926eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 40026eb2607SMasaharu Hayakawa 40126eb2607SMasaharu Hayakawa /* Set the sampling clock selection range of HS400 mode */ 40226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 40326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 40426eb2607SMasaharu Hayakawa 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 40526eb2607SMasaharu Hayakawa 406a38c078fSTakeshi Saito /* Avoid bad TAP */ 407a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) { 408a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 40926eb2607SMasaharu Hayakawa 410a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) 411a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num; 412a38c078fSTakeshi Saito 413a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) { 414a38c078fSTakeshi Saito new_tap = priv->tap_set; 415a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 416a38c078fSTakeshi Saito } 417a38c078fSTakeshi Saito 418a38c078fSTakeshi Saito priv->tap_set = new_tap; 419a38c078fSTakeshi Saito } 420a38c078fSTakeshi Saito 42126eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 422a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1)); 42326eb2607SMasaharu Hayakawa 42426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 42526eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 42626eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 42726eb2607SMasaharu Hayakawa 42826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 42926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 430ce6f92c2SWolfram Sang 431ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 432ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true; 43326eb2607SMasaharu Hayakawa } 43426eb2607SMasaharu Hayakawa 43580d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 43626eb2607SMasaharu Hayakawa { 43780d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 43880d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 43980d0be81SWolfram Sang 44026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 44126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 44226eb2607SMasaharu Hayakawa 44326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 44426eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 44526eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 44726eb2607SMasaharu Hayakawa 44826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 44926eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 45026eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 45126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 45226eb2607SMasaharu Hayakawa 45326eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 45426eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 45526eb2607SMasaharu Hayakawa } 45626eb2607SMasaharu Hayakawa 457ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 458ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr) 459ce6f92c2SWolfram Sang { 460ce6f92c2SWolfram Sang /* read mode */ 461ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 462ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 463ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 464ce6f92c2SWolfram Sang 465ce6f92c2SWolfram Sang /* access start and stop */ 466ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 467ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 468ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 469ce6f92c2SWolfram Sang 470ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 471ce6f92c2SWolfram Sang } 472ce6f92c2SWolfram Sang 473ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 474ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val) 475ce6f92c2SWolfram Sang { 476ce6f92c2SWolfram Sang /* write mode */ 477ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 478ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 479ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 480ce6f92c2SWolfram Sang 481ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 482ce6f92c2SWolfram Sang 483ce6f92c2SWolfram Sang /* access start and stop */ 484ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 485ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 486ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 487ce6f92c2SWolfram Sang } 488ce6f92c2SWolfram Sang 489ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 490ce6f92c2SWolfram Sang { 491ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 492ce6f92c2SWolfram Sang u32 calib_code; 493ce6f92c2SWolfram Sang 494ce6f92c2SWolfram Sang /* disable write protect */ 495ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 496ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 497ce6f92c2SWolfram Sang /* read calibration code and adjust */ 498ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 499ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 500ce6f92c2SWolfram Sang 501ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 502ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 503ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]); 504ce6f92c2SWolfram Sang 505ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 506ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 507ce6f92c2SWolfram Sang 508ce6f92c2SWolfram Sang /* adjustment done, clear flag */ 509ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 510ce6f92c2SWolfram Sang } 511ce6f92c2SWolfram Sang 512ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 513ce6f92c2SWolfram Sang { 514ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 515ce6f92c2SWolfram Sang 516ce6f92c2SWolfram Sang /* disable write protect */ 517ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 518ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 519ce6f92c2SWolfram Sang /* disable manual calibration */ 520ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0); 521ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */ 522ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 523ce6f92c2SWolfram Sang } 524ce6f92c2SWolfram Sang 52526eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 52626eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 52726eb2607SMasaharu Hayakawa { 52826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 52926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 53026eb2607SMasaharu Hayakawa 53126eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 53226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 53326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 534f0c8234cSTakeshi Saito 535f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 536f0c8234cSTakeshi Saito 53726eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 53826eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 53926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 54026eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 54126eb2607SMasaharu Hayakawa 542ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 543ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host); 544ce6f92c2SWolfram Sang 54526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 54626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 54726eb2607SMasaharu Hayakawa } 54826eb2607SMasaharu Hayakawa 549f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 55026eb2607SMasaharu Hayakawa { 551f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 552f22084b6SWolfram Sang 55326eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 554f22084b6SWolfram Sang return 0; 55526eb2607SMasaharu Hayakawa } 55626eb2607SMasaharu Hayakawa 5579f809065SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */ 5585b0739d7SWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host) 5595b0739d7SWolfram Sang { 5605b0739d7SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 5615b0739d7SWolfram Sang 56245bffc37SWolfram Sang if (priv->scc_ctl) { 563183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc); 5645b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv); 565ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 5665b0739d7SWolfram Sang 5675b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 5685b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 5695b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 57045bffc37SWolfram Sang } 5715b0739d7SWolfram Sang 5729f809065SWolfram Sang sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_INIT_RCAR2); 5735b0739d7SWolfram Sang } 5745b0739d7SWolfram Sang 575ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 576b5b6a5f4SSimon Horman 577b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 578b5b6a5f4SSimon Horman { 579b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 58092fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 5815fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row; 5825fb6bf51SWolfram Sang unsigned long *bitmap; 583b5b6a5f4SSimon Horman 584b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 585b5b6a5f4SSimon Horman 586b5b6a5f4SSimon Horman /* 5875c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 5885c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 5895c99826bSNiklas Söderlund * considering it for tuning selection. 5905c99826bSNiklas Söderlund */ 59192fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) { 592b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 5935c99826bSNiklas Söderlund 594b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps)) 595b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps); 5965fb6bf51SWolfram Sang 5975fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp)) 5985fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp); 5995fb6bf51SWolfram Sang } 6005fb6bf51SWolfram Sang 6015fb6bf51SWolfram Sang /* 6025fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by 6035fb6bf51SWolfram Sang * identifying the change point of data. 6045fb6bf51SWolfram Sang */ 6055fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) { 6065fb6bf51SWolfram Sang bitmap = priv->smpcmp; 6075fb6bf51SWolfram Sang min_tap_row = 1; 6085fb6bf51SWolfram Sang } else { 6095fb6bf51SWolfram Sang bitmap = priv->taps; 6105fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 6115c99826bSNiklas Söderlund } 6125c99826bSNiklas Söderlund 6135c99826bSNiklas Söderlund /* 614b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 615ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 616ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out. 617b5b6a5f4SSimon Horman */ 6185fb6bf51SWolfram Sang bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { 61992fa2a56SWolfram Sang if (re - rs > tap_cnt) { 62092fa2a56SWolfram Sang tap_end = re; 62192fa2a56SWolfram Sang tap_start = rs; 62292fa2a56SWolfram Sang tap_cnt = tap_end - tap_start; 623b5b6a5f4SSimon Horman } 624b5b6a5f4SSimon Horman } 625b5b6a5f4SSimon Horman 6265fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row) 627b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 628b5b6a5f4SSimon Horman else 629b5b6a5f4SSimon Horman return -EIO; 630b5b6a5f4SSimon Horman 631b5b6a5f4SSimon Horman /* Set SCC */ 632b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 633b5b6a5f4SSimon Horman 634b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 635b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 636b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 637b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 638b5b6a5f4SSimon Horman 639b5b6a5f4SSimon Horman return 0; 640b5b6a5f4SSimon Horman } 641b5b6a5f4SSimon Horman 642510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 6430c482d82SWolfram Sang { 644510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 6450c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 6465b0739d7SWolfram Sang int i, ret; 6470c482d82SWolfram Sang 648b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host); 649b2dd9a13SWolfram Sang if (!priv->tap_num) 6500c482d82SWolfram Sang return 0; /* Tuning is not supported */ 6510c482d82SWolfram Sang 652b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 6533a821a82SWolfram Sang dev_err(&host->pdev->dev, 6543a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 6553a821a82SWolfram Sang return -EINVAL; 6560c482d82SWolfram Sang } 6570c482d82SWolfram Sang 658b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2); 6595fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2); 6600c482d82SWolfram Sang 6610c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 662b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) { 6630c482d82SWolfram Sang /* Set sampling clock position */ 664b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 6650c482d82SWolfram Sang 666510bfe58SWolfram Sang if (mmc_send_tuning(mmc, opcode, NULL) == 0) 667b2dd9a13SWolfram Sang set_bit(i, priv->taps); 6685fb6bf51SWolfram Sang 6695fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 6705fb6bf51SWolfram Sang set_bit(i, priv->smpcmp); 6710c482d82SWolfram Sang } 6720c482d82SWolfram Sang 6735b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host); 6745b0739d7SWolfram Sang if (ret < 0) 6755b0739d7SWolfram Sang renesas_sdhi_reset(host); 6765b0739d7SWolfram Sang return ret; 6770c482d82SWolfram Sang } 6780c482d82SWolfram Sang 67911a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 68011a21960STakeshi Saito { 68111a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 682a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 68311a21960STakeshi Saito u32 val; 68411a21960STakeshi Saito 68511a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 68611a21960STakeshi Saito if (!val) 68711a21960STakeshi Saito return false; 68811a21960STakeshi Saito 68911a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 69011a21960STakeshi Saito 69111a21960STakeshi Saito /* Change TAP position according to correction status */ 69271cfc927STakeshi Saito if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 69371cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 694a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 69571cfc927STakeshi Saito /* 69671cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 69771cfc927STakeshi Saito * Therefore, use only CMD status. 69871cfc927STakeshi Saito */ 69971cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 70071cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 701a38c078fSTakeshi Saito if (!smpcmp) { 70271cfc927STakeshi Saito return false; /* no error in CMD signal */ 703a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 70471cfc927STakeshi Saito new_tap++; 705a38c078fSTakeshi Saito error_tap--; 706a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 70771cfc927STakeshi Saito new_tap--; 708a38c078fSTakeshi Saito error_tap++; 709a38c078fSTakeshi Saito } else { 71071cfc927STakeshi Saito return true; /* need retune */ 711a38c078fSTakeshi Saito } 712a38c078fSTakeshi Saito 713a38c078fSTakeshi Saito /* 714a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare 715a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK, 716a38c078fSTakeshi Saito * we can at least retune. 717a38c078fSTakeshi Saito */ 718a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num)) 719a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp); 72071cfc927STakeshi Saito } else { 72111a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 72271cfc927STakeshi Saito return true; /* need retune */ 72311a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 72471cfc927STakeshi Saito new_tap++; 72511a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 72671cfc927STakeshi Saito new_tap--; 72711a21960STakeshi Saito else 72811a21960STakeshi Saito return false; 72971cfc927STakeshi Saito } 73011a21960STakeshi Saito 731b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num); 73211a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 733b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1)); 73411a21960STakeshi Saito 73511a21960STakeshi Saito return false; 73611a21960STakeshi Saito } 73711a21960STakeshi Saito 73811a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 73911a21960STakeshi Saito { 74011a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 74111a21960STakeshi Saito 74211a21960STakeshi Saito /* Check SCC error */ 74311a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 74411a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 74511a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 74611a21960STakeshi Saito return true; 74711a21960STakeshi Saito } 74811a21960STakeshi Saito 74911a21960STakeshi Saito return false; 75011a21960STakeshi Saito } 75111a21960STakeshi Saito 752b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 753b5b6a5f4SSimon Horman { 754b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 75512e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 75675f349a1SMasaharu Hayakawa 75775f349a1SMasaharu Hayakawa /* 75875f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 75975f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 76075f349a1SMasaharu Hayakawa */ 76175f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 76275f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 76375f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 76475f349a1SMasaharu Hayakawa return false; 76575f349a1SMasaharu Hayakawa 766fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc)) 76775f349a1SMasaharu Hayakawa return false; 768b5b6a5f4SSimon Horman 769b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 77011a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 77111a21960STakeshi Saito return renesas_sdhi_auto_correction(host); 772b5b6a5f4SSimon Horman 77311a21960STakeshi Saito return renesas_sdhi_manual_correction(host, use_4tap); 774b5b6a5f4SSimon Horman } 775b5b6a5f4SSimon Horman 7764dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 777b5b6a5f4SSimon Horman { 778b5b6a5f4SSimon Horman int timeout = 1000; 7794dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 7804dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 781b5b6a5f4SSimon Horman 7824dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 7834dc48a95SWolfram Sang & bit) == wait_state) 784b5b6a5f4SSimon Horman udelay(1); 785b5b6a5f4SSimon Horman 786b5b6a5f4SSimon Horman if (!timeout) { 787b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 788b5b6a5f4SSimon Horman return -EBUSY; 789b5b6a5f4SSimon Horman } 790b5b6a5f4SSimon Horman 791b5b6a5f4SSimon Horman return 0; 792b5b6a5f4SSimon Horman } 793b5b6a5f4SSimon Horman 794b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 795b5b6a5f4SSimon Horman { 7964dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 7974dc48a95SWolfram Sang 7982fe35968SSimon Horman switch (addr) { 799b5b6a5f4SSimon Horman case CTL_SD_CMD: 800b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 801b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 802b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 803b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 804b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 805b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 806*4533c3ebSWolfram Sang case CTL_HOST_MODE: 8075124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 8084dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 809df561f66SGustavo A. R. Silva fallthrough; 8104dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 8114dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 812b5b6a5f4SSimon Horman } 813b5b6a5f4SSimon Horman 814b5b6a5f4SSimon Horman return 0; 815b5b6a5f4SSimon Horman } 816b5b6a5f4SSimon Horman 817b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 818b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 819b5b6a5f4SSimon Horman { 820b5b6a5f4SSimon Horman /* 821b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 822b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 823b5b6a5f4SSimon Horman * depending on the timing with which the 824b5b6a5f4SSimon Horman * response register is read, the response 825b5b6a5f4SSimon Horman * value may not be read properly. 826b5b6a5f4SSimon Horman * Use single block read for this HW bug 827b5b6a5f4SSimon Horman */ 828b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 829b5b6a5f4SSimon Horman blk_size == 2) 830b5b6a5f4SSimon Horman return 1; 831b5b6a5f4SSimon Horman 832b5b6a5f4SSimon Horman return blk_size; 833b5b6a5f4SSimon Horman } 834b5b6a5f4SSimon Horman 835ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 836ce6f92c2SWolfram Sang { 837ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 838ce6f92c2SWolfram Sang 839ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 840ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host); 841ce6f92c2SWolfram Sang } 842b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 843b5b6a5f4SSimon Horman { 84441279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 84541279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 846b5b6a5f4SSimon Horman 84741279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 84841279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 849b5b6a5f4SSimon Horman } 850b5b6a5f4SSimon Horman 8516a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 8520f4e2054SNiklas Söderlund .hs400_disabled = true, 8530f4e2054SNiklas Söderlund .hs400_4taps = true, 8540f4e2054SNiklas Söderlund }; 8550f4e2054SNiklas Söderlund 8566a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 857164691aaSNiklas Söderlund .hs400_4taps = true, 858a38c078fSTakeshi Saito .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 859164691aaSNiklas Söderlund }; 860164691aaSNiklas Söderlund 86197bf85b6SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 86297bf85b6SWolfram Sang .hs400_disabled = true, 86397bf85b6SWolfram Sang }; 86497bf85b6SWolfram Sang 865a38c078fSTakeshi Saito static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 866a38c078fSTakeshi Saito .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 867a38c078fSTakeshi Saito }; 868a38c078fSTakeshi Saito 869a38c078fSTakeshi Saito static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 870a38c078fSTakeshi Saito .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 871a38c078fSTakeshi Saito }; 872a38c078fSTakeshi Saito 873ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 874ce6f92c2SWolfram Sang .hs400_4taps = true, 875ce6f92c2SWolfram Sang .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 876ce6f92c2SWolfram Sang .hs400_calib_table = r8a7796_es13_calib_table, 877ce6f92c2SWolfram Sang }; 878ce6f92c2SWolfram Sang 879ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 880ce6f92c2SWolfram Sang .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 881ce6f92c2SWolfram Sang .hs400_calib_table = r8a77965_calib_table, 882ce6f92c2SWolfram Sang }; 883ce6f92c2SWolfram Sang 884ce6f92c2SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 885ce6f92c2SWolfram Sang .hs400_calib_table = r8a77990_calib_table, 886ce6f92c2SWolfram Sang }; 887ce6f92c2SWolfram Sang 888f583da40SWolfram Sang /* 889f583da40SWolfram Sang * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 890f583da40SWolfram Sang * So, we want to treat them equally and only have a match for ES1.2 to enforce 891f583da40SWolfram Sang * this if there ever will be a way to distinguish ES1.2. 892f583da40SWolfram Sang */ 893164691aaSNiklas Söderlund static const struct soc_device_attribute sdhi_quirks_match[] = { 8946e3cbb05SWolfram Sang { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 8956a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 8966a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 897a38c078fSTakeshi Saito { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 }, 8986a686986SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 899ce6f92c2SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 900a38c078fSTakeshi Saito { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 }, 901ce6f92c2SWolfram Sang { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 }, 90297bf85b6SWolfram Sang { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 903ce6f92c2SWolfram Sang { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 }, 904164691aaSNiklas Söderlund { /* Sentinel. */ }, 905164691aaSNiklas Söderlund }; 906164691aaSNiklas Söderlund 9079d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 9089d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 909b5b6a5f4SSimon Horman { 910b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 911164691aaSNiklas Söderlund const struct renesas_sdhi_quirks *quirks = NULL; 9122fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 913164691aaSNiklas Söderlund const struct soc_device_attribute *attr; 9142fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 9152fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 916b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 9172fe35968SSimon Horman struct renesas_sdhi *priv; 918e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 919b5b6a5f4SSimon Horman struct resource *res; 920c9a9497cSWolfram Sang u16 ver; 9212fe35968SSimon Horman 9222fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 923b5b6a5f4SSimon Horman 924164691aaSNiklas Söderlund attr = soc_device_match(sdhi_quirks_match); 925164691aaSNiklas Söderlund if (attr) 926164691aaSNiklas Söderlund quirks = attr->data; 927164691aaSNiklas Söderlund 928b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 929b5b6a5f4SSimon Horman if (!res) 930b5b6a5f4SSimon Horman return -EINVAL; 931b5b6a5f4SSimon Horman 9322fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 9332fe35968SSimon Horman GFP_KERNEL); 934b5b6a5f4SSimon Horman if (!priv) 935b5b6a5f4SSimon Horman return -ENOMEM; 936b5b6a5f4SSimon Horman 9377af08206SWolfram Sang priv->quirks = quirks; 938b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 939b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 940b5b6a5f4SSimon Horman 941b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 942b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 943b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 944b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 9454ce62817SMasahiro Yamada return ret; 946b5b6a5f4SSimon Horman } 947b5b6a5f4SSimon Horman 948b5b6a5f4SSimon Horman /* 949b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 950b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 951b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 952b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 953b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 954b5b6a5f4SSimon Horman * disable it. 955b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 956b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 957b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 958b5b6a5f4SSimon Horman */ 959b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 960b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 961b5b6a5f4SSimon Horman priv->clk_cd = NULL; 962b5b6a5f4SSimon Horman 963b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 964b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 965b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 966b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 967b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 968b5b6a5f4SSimon Horman "state_uhs"); 969b5b6a5f4SSimon Horman } 970b5b6a5f4SSimon Horman 971b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 9728d09a133SMasahiro Yamada if (IS_ERR(host)) 9738d09a133SMasahiro Yamada return PTR_ERR(host); 974b5b6a5f4SSimon Horman 975b5b6a5f4SSimon Horman if (of_data) { 976b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 977b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 978b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 979b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 980b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 981603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 982603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 983b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 984b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 985b5b6a5f4SSimon Horman } 986b5b6a5f4SSimon Horman 987b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 988b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 989b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 9900196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 991b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 992bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 993b5b6a5f4SSimon Horman 9940f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 9950f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 9960f4e2054SNiklas Söderlund 997ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 998ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 999ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1000ef5332c1SWolfram Sang 1001b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 1002b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1003b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 10042aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 10052aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 1006b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 10071970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 10086e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset; 1009d30ae056STakeshi Saito } 1010b5b6a5f4SSimon Horman 1011b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1012b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1013b5b6a5f4SSimon Horman host->bus_shift = 1; 1014b5b6a5f4SSimon Horman 1015b5b6a5f4SSimon Horman if (mmd) 1016b5b6a5f4SSimon Horman *mmc_data = *mmd; 1017b5b6a5f4SSimon Horman 1018b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 1019b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 1020b5b6a5f4SSimon Horman 1021b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1022b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1023b5b6a5f4SSimon Horman 1024b5b6a5f4SSimon Horman /* 1025b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1026b5b6a5f4SSimon Horman * bus width mode. 1027b5b6a5f4SSimon Horman */ 1028b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1029b5b6a5f4SSimon Horman 1030b5b6a5f4SSimon Horman /* 1031b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 1032b5b6a5f4SSimon Horman */ 1033b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1034b5b6a5f4SSimon Horman 10352fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 1036b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1037b5b6a5f4SSimon Horman 1038b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 1039b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1040b5b6a5f4SSimon Horman 104163fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev); 104263fd8ef3SUlf Hansson 1043b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 1044b21fc294SMasahiro Yamada if (ret) 1045b5b6a5f4SSimon Horman goto efree; 1046b5b6a5f4SSimon Horman 1047c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 1048c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1049c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1050c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 1051c9a9497cSWolfram Sang 10525124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1053c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 10545124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 10555124b592SWolfram Sang 1056ce6f92c2SWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1057ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request; 1058ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *( 1059ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ? 1060ce6f92c2SWolfram Sang quirks->hs400_calib_table : 1061ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1); 1062ce6f92c2SWolfram Sang } 1063ce6f92c2SWolfram Sang 1064b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 1065b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 1066b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 106726eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 106826eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 1069b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 1070c1a49782SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 1071b5b6a5f4SSimon Horman bool hit = false; 1072b5b6a5f4SSimon Horman 1073b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 1074b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 1075b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 1076852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 1077c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 1078c1a49782SWolfram Sang taps->tap_hs400_4tap : 1079c1a49782SWolfram Sang taps->tap; 1080b5b6a5f4SSimon Horman hit = true; 1081b5b6a5f4SSimon Horman break; 1082b5b6a5f4SSimon Horman } 1083b5b6a5f4SSimon Horman } 1084b5b6a5f4SSimon Horman 1085b5b6a5f4SSimon Horman if (!hit) 1086e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1087b5b6a5f4SSimon Horman 1088d14ac691SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset; 108964982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error; 1090510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1091f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1092f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1093f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1094b5b6a5f4SSimon Horman } 1095b5b6a5f4SSimon Horman 1096b161d87dSWolfram Sang ret = tmio_mmc_host_probe(host); 1097b161d87dSWolfram Sang if (ret < 0) 1098b161d87dSWolfram Sang goto edisclk; 1099b161d87dSWolfram Sang 1100e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 1101e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 1102e8307ec5SGeert Uytterhoeven ret = num_irqs; 1103b5b6a5f4SSimon Horman goto eirq; 1104b5b6a5f4SSimon Horman } 1105b5b6a5f4SSimon Horman 1106b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 1107e8307ec5SGeert Uytterhoeven if (!num_irqs) { 1108e8307ec5SGeert Uytterhoeven ret = -ENXIO; 1109e8307ec5SGeert Uytterhoeven goto eirq; 1110e8307ec5SGeert Uytterhoeven } 1111e8307ec5SGeert Uytterhoeven 1112e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 1113e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 1114e8307ec5SGeert Uytterhoeven if (irq < 0) { 1115b5b6a5f4SSimon Horman ret = irq; 1116b5b6a5f4SSimon Horman goto eirq; 1117b5b6a5f4SSimon Horman } 1118b5b6a5f4SSimon Horman 1119e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1120e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 1121e8307ec5SGeert Uytterhoeven if (ret) 1122e8307ec5SGeert Uytterhoeven goto eirq; 1123e8307ec5SGeert Uytterhoeven } 1124e8307ec5SGeert Uytterhoeven 1125bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1126bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1127b5b6a5f4SSimon Horman 1128b5b6a5f4SSimon Horman return ret; 1129b5b6a5f4SSimon Horman 1130b5b6a5f4SSimon Horman eirq: 1131b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1132b21fc294SMasahiro Yamada edisclk: 1133b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1134b5b6a5f4SSimon Horman efree: 1135b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 11364ce62817SMasahiro Yamada 1137b5b6a5f4SSimon Horman return ret; 1138b5b6a5f4SSimon Horman } 11399d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1140b5b6a5f4SSimon Horman 11419d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 1142b5b6a5f4SSimon Horman { 1143a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1144b5b6a5f4SSimon Horman 1145b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1146b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1147e8973201SYoshihiro Shimoda tmio_mmc_host_free(host); 1148b5b6a5f4SSimon Horman 1149b5b6a5f4SSimon Horman return 0; 1150b5b6a5f4SSimon Horman } 11519d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1152967a6a07SMasaharu Hayakawa 1153967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 1154