1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/kernel.h> 22b5b6a5f4SSimon Horman #include <linux/clk.h> 23b5b6a5f4SSimon Horman #include <linux/slab.h> 24967a6a07SMasaharu Hayakawa #include <linux/module.h> 25b5b6a5f4SSimon Horman #include <linux/of_device.h> 26b5b6a5f4SSimon Horman #include <linux/platform_device.h> 27b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 29b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 30b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 31b5b6a5f4SSimon Horman #include <linux/delay.h> 32b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 33b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 34b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 35164691aaSNiklas Söderlund #include <linux/sys_soc.h> 36b5b6a5f4SSimon Horman 37b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 38b5b6a5f4SSimon Horman #include "tmio_mmc.h" 39b5b6a5f4SSimon Horman 404472f0fcSMasaharu Hayakawa #define HOST_MODE 0xe4 41b5b6a5f4SSimon Horman 42b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 43c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 44b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 46b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 47b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 48b5b6a5f4SSimon Horman 49b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 50b5b6a5f4SSimon Horman { 51b5b6a5f4SSimon Horman u32 val; 52b5b6a5f4SSimon Horman 53b5b6a5f4SSimon Horman /* 54b5b6a5f4SSimon Horman * see also 55b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 56b5b6a5f4SSimon Horman */ 57b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 58b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 59b5b6a5f4SSimon Horman val = (width == 32) ? 0x0001 : 0x0000; 60b5b6a5f4SSimon Horman break; 61b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 62b5b6a5f4SSimon Horman val = (width == 32) ? 0x0000 : 0x0001; 63b5b6a5f4SSimon Horman break; 64b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 65b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 66b5b6a5f4SSimon Horman if (width == 64) 67b5b6a5f4SSimon Horman val = 0x0000; 68b5b6a5f4SSimon Horman else if (width == 32) 69b5b6a5f4SSimon Horman val = 0x0101; 70b5b6a5f4SSimon Horman else 71b5b6a5f4SSimon Horman val = 0x0001; 72b5b6a5f4SSimon Horman break; 73b5b6a5f4SSimon Horman default: 74b5b6a5f4SSimon Horman /* nothing to do */ 75b5b6a5f4SSimon Horman return; 76b5b6a5f4SSimon Horman } 77b5b6a5f4SSimon Horman 784472f0fcSMasaharu Hayakawa sd_ctrl_write16(host, HOST_MODE, val); 79b5b6a5f4SSimon Horman } 80b5b6a5f4SSimon Horman 81b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 82b5b6a5f4SSimon Horman { 83b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 84b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 85b5b6a5f4SSimon Horman int ret = clk_prepare_enable(priv->clk); 862fe35968SSimon Horman 87b5b6a5f4SSimon Horman if (ret < 0) 88b5b6a5f4SSimon Horman return ret; 89b5b6a5f4SSimon Horman 90b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 91b5b6a5f4SSimon Horman if (ret < 0) { 92b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 93b5b6a5f4SSimon Horman return ret; 94b5b6a5f4SSimon Horman } 95b5b6a5f4SSimon Horman 96b5b6a5f4SSimon Horman /* 97b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 98b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 99b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 100b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 101b5b6a5f4SSimon Horman */ 102b5b6a5f4SSimon Horman if (!mmc->f_max) 103b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 104b5b6a5f4SSimon Horman 105b5b6a5f4SSimon Horman /* 106b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 107b5b6a5f4SSimon Horman * divided by our maximum divider. 108b5b6a5f4SSimon Horman */ 109b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 110b5b6a5f4SSimon Horman 111b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 112b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 113b5b6a5f4SSimon Horman 114b5b6a5f4SSimon Horman return 0; 115b5b6a5f4SSimon Horman } 116b5b6a5f4SSimon Horman 117b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 118b5b6a5f4SSimon Horman unsigned int new_clock) 119b5b6a5f4SSimon Horman { 120b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 121b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 12275eaf49fSTamás Szűcs int i; 123b5b6a5f4SSimon Horman 124d63c2bf4SWolfram Sang /* tested only on R-Car Gen2+ currently; may work for others */ 125b5b6a5f4SSimon Horman if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 126b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 127b5b6a5f4SSimon Horman 128b5b6a5f4SSimon Horman /* 129b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 130b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 131b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 132b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 133b5b6a5f4SSimon Horman */ 134b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 135b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 136b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 137b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 138b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 139b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 140b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 141b5b6a5f4SSimon Horman continue; 142b5b6a5f4SSimon Horman } 143b5b6a5f4SSimon Horman 144b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 145b5b6a5f4SSimon Horman if (diff <= diff_min) { 146b5b6a5f4SSimon Horman best_freq = freq; 147b5b6a5f4SSimon Horman diff_min = diff; 148b5b6a5f4SSimon Horman } 149b5b6a5f4SSimon Horman } 150b5b6a5f4SSimon Horman 15175eaf49fSTamás Szűcs clk_set_rate(priv->clk, best_freq); 152b5b6a5f4SSimon Horman 15375eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 154b5b6a5f4SSimon Horman } 155b5b6a5f4SSimon Horman 1560196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1570196c8dbSMasahiro Yamada unsigned int new_clock) 1580196c8dbSMasahiro Yamada { 1590196c8dbSMasahiro Yamada u32 clk = 0, clock; 1600196c8dbSMasahiro Yamada 16168f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 16268f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 16368f83127SMasahiro Yamada 16475eaf49fSTamás Szűcs if (new_clock == 0) { 16575eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 16668f83127SMasahiro Yamada goto out; 16775eaf49fSTamás Szűcs } 16868f83127SMasahiro Yamada 16975eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 17075eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 1710196c8dbSMasahiro Yamada 1720196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 1730196c8dbSMasahiro Yamada clock <<= 1; 1740196c8dbSMasahiro Yamada 1750196c8dbSMasahiro Yamada /* 1/1 clock is option */ 1760196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 1770196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 1780196c8dbSMasahiro Yamada clk |= 0xff; 1790196c8dbSMasahiro Yamada else 1800196c8dbSMasahiro Yamada clk &= ~0xff; 1810196c8dbSMasahiro Yamada } 1820196c8dbSMasahiro Yamada 1830196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 1840196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 1850196c8dbSMasahiro Yamada usleep_range(10000, 11000); 1860196c8dbSMasahiro Yamada 18768f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 18868f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 18968f83127SMasahiro Yamada 19068f83127SMasahiro Yamada out: 19168f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 19268f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 19368f83127SMasahiro Yamada usleep_range(10000, 11000); 1940196c8dbSMasahiro Yamada } 1950196c8dbSMasahiro Yamada 196b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 197b5b6a5f4SSimon Horman { 198b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 199b5b6a5f4SSimon Horman 200b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 201b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 202b5b6a5f4SSimon Horman } 203b5b6a5f4SSimon Horman 204b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 205b5b6a5f4SSimon Horman { 206b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 207b5b6a5f4SSimon Horman 2082fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2092fe35968SSimon Horman TMIO_STAT_DAT0); 210b5b6a5f4SSimon Horman } 211b5b6a5f4SSimon Horman 212b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 213b5b6a5f4SSimon Horman struct mmc_ios *ios) 214b5b6a5f4SSimon Horman { 215b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 216b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 217b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 218b5b6a5f4SSimon Horman int ret; 219b5b6a5f4SSimon Horman 220b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 221b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 222b5b6a5f4SSimon Horman pin_state = priv->pins_default; 223b5b6a5f4SSimon Horman break; 224b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 225b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 226b5b6a5f4SSimon Horman break; 227b5b6a5f4SSimon Horman default: 228b5b6a5f4SSimon Horman return -EINVAL; 229b5b6a5f4SSimon Horman } 230b5b6a5f4SSimon Horman 231b5b6a5f4SSimon Horman /* 232b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 233b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 234b5b6a5f4SSimon Horman */ 235b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 236b5b6a5f4SSimon Horman return ios->signal_voltage == 237b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 238b5b6a5f4SSimon Horman 239b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 240b5b6a5f4SSimon Horman if (ret) 241b5b6a5f4SSimon Horman return ret; 242b5b6a5f4SSimon Horman 243b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 244b5b6a5f4SSimon Horman } 245b5b6a5f4SSimon Horman 246b5b6a5f4SSimon Horman /* SCC registers */ 247b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 248b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 249b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 250b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 251b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 252b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 25371cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 25426eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 255b5b6a5f4SSimon Horman 256b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 257b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 258b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 259b5b6a5f4SSimon Horman 260b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2616199a10eSWolfram Sang 262b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2636199a10eSWolfram Sang 26411a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2656199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 2666199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 2676199a10eSWolfram Sang 26871cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 2696199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 2706199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 2716199a10eSWolfram Sang 27226eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 27326eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 274b5b6a5f4SSimon Horman 275b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 276b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 277b5b6a5f4SSimon Horman { 278b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 279b5b6a5f4SSimon Horman } 280b5b6a5f4SSimon Horman 281b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 282b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 283b5b6a5f4SSimon Horman int addr, u32 val) 284b5b6a5f4SSimon Horman { 285b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 286b5b6a5f4SSimon Horman } 287b5b6a5f4SSimon Horman 288b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 289b5b6a5f4SSimon Horman { 290b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 291b5b6a5f4SSimon Horman 292b5b6a5f4SSimon Horman priv = host_to_priv(host); 293b5b6a5f4SSimon Horman 294b5b6a5f4SSimon Horman /* Initialize SCC */ 295b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 296b5b6a5f4SSimon Horman 297b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 298b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 299b5b6a5f4SSimon Horman 30026eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 30126eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 30226eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 30326eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 30426eb2607SMasaharu Hayakawa 305b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 306b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 307b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 308b5b6a5f4SSimon Horman 309b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 310b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 311b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 312b5b6a5f4SSimon Horman 313852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 314b5b6a5f4SSimon Horman 31526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 31626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 31726eb2607SMasaharu Hayakawa 318b5b6a5f4SSimon Horman /* Read TAPNUM */ 319b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 320b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 321b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 322b5b6a5f4SSimon Horman } 323b5b6a5f4SSimon Horman 32426eb2607SMasaharu Hayakawa static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) 32526eb2607SMasaharu Hayakawa { 32626eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 32726eb2607SMasaharu Hayakawa 32826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 32926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 33026eb2607SMasaharu Hayakawa 33126eb2607SMasaharu Hayakawa /* Set HS400 mode */ 33226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 33326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 334f0c8234cSTakeshi Saito 335f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 336f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 337f0c8234cSTakeshi Saito 3389b0d6855SWolfram Sang /* Gen3 can't do automatic tap correction with HS400, so disable it */ 3399b0d6855SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 3409b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3419b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3429b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3439b0d6855SWolfram Sang 34426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 34526eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 34626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 34726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 34826eb2607SMasaharu Hayakawa 34926eb2607SMasaharu Hayakawa /* Set the sampling clock selection range of HS400 mode */ 35026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 35126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 35226eb2607SMasaharu Hayakawa 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 35326eb2607SMasaharu Hayakawa 35426eb2607SMasaharu Hayakawa 35512e3c55dSWolfram Sang if (priv->quirks && priv->quirks->hs400_4taps) 35626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 35726eb2607SMasaharu Hayakawa host->tap_set / 2); 35826eb2607SMasaharu Hayakawa 35926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 36026eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 36126eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 36226eb2607SMasaharu Hayakawa 36326eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 36426eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36526eb2607SMasaharu Hayakawa } 36626eb2607SMasaharu Hayakawa 36726eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 36826eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 36926eb2607SMasaharu Hayakawa { 37026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 37126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 37226eb2607SMasaharu Hayakawa 37326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 37426eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 37526eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 37626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 37726eb2607SMasaharu Hayakawa } 37826eb2607SMasaharu Hayakawa 37926eb2607SMasaharu Hayakawa static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host) 38026eb2607SMasaharu Hayakawa { 38126eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 38226eb2607SMasaharu Hayakawa 38326eb2607SMasaharu Hayakawa renesas_sdhi_reset_scc(host, priv); 38426eb2607SMasaharu Hayakawa 38526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 38626eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 38726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 38826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 38926eb2607SMasaharu Hayakawa 39026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 39126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 39226eb2607SMasaharu Hayakawa } 39326eb2607SMasaharu Hayakawa 39426eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 39526eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 39626eb2607SMasaharu Hayakawa { 39726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 39826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 39926eb2607SMasaharu Hayakawa 40026eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 40126eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 40226eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 403f0c8234cSTakeshi Saito 404f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 405f0c8234cSTakeshi Saito 40626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 40726eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 40826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 40926eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 41026eb2607SMasaharu Hayakawa 41126eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 41226eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 41326eb2607SMasaharu Hayakawa } 41426eb2607SMasaharu Hayakawa 41526eb2607SMasaharu Hayakawa static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host) 41626eb2607SMasaharu Hayakawa { 41726eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 41826eb2607SMasaharu Hayakawa } 41926eb2607SMasaharu Hayakawa 420b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_MAX_TAP 3 421b5b6a5f4SSimon Horman 422b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 423b5b6a5f4SSimon Horman { 424b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 425b5b6a5f4SSimon Horman unsigned long tap_cnt; /* counter of tuning success */ 426b5b6a5f4SSimon Horman unsigned long tap_start;/* start position of tuning success */ 427b5b6a5f4SSimon Horman unsigned long tap_end; /* end position of tuning success */ 428b5b6a5f4SSimon Horman unsigned long ntap; /* temporary counter of tuning success */ 429b5b6a5f4SSimon Horman unsigned long i; 430b5b6a5f4SSimon Horman 43111a21960STakeshi Saito priv->doing_tune = false; 43211a21960STakeshi Saito 433b5b6a5f4SSimon Horman /* Clear SCC_RVSREQ */ 434b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 435b5b6a5f4SSimon Horman 436b5b6a5f4SSimon Horman /* 4375c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 4385c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 4395c99826bSNiklas Söderlund * considering it for tuning selection. 4405c99826bSNiklas Söderlund */ 4415c99826bSNiklas Söderlund for (i = 0; i < host->tap_num * 2; i++) { 4425c99826bSNiklas Söderlund int offset = host->tap_num * (i < host->tap_num ? 1 : -1); 4435c99826bSNiklas Söderlund 4445c99826bSNiklas Söderlund if (!test_bit(i, host->taps)) 4455c99826bSNiklas Söderlund clear_bit(i + offset, host->taps); 4465c99826bSNiklas Söderlund } 4475c99826bSNiklas Söderlund 4485c99826bSNiklas Söderlund /* 449b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 450b5b6a5f4SSimon Horman * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 451b5b6a5f4SSimon Horman * center index as the tap. 452b5b6a5f4SSimon Horman */ 453b5b6a5f4SSimon Horman tap_cnt = 0; 454b5b6a5f4SSimon Horman ntap = 0; 455b5b6a5f4SSimon Horman tap_start = 0; 456b5b6a5f4SSimon Horman tap_end = 0; 457b5b6a5f4SSimon Horman for (i = 0; i < host->tap_num * 2; i++) { 4582fe35968SSimon Horman if (test_bit(i, host->taps)) { 459b5b6a5f4SSimon Horman ntap++; 4602fe35968SSimon Horman } else { 461b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 462b5b6a5f4SSimon Horman tap_start = i - ntap; 463b5b6a5f4SSimon Horman tap_end = i - 1; 464b5b6a5f4SSimon Horman tap_cnt = ntap; 465b5b6a5f4SSimon Horman } 466b5b6a5f4SSimon Horman ntap = 0; 467b5b6a5f4SSimon Horman } 468b5b6a5f4SSimon Horman } 469b5b6a5f4SSimon Horman 470b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 471b5b6a5f4SSimon Horman tap_start = i - ntap; 472b5b6a5f4SSimon Horman tap_end = i - 1; 473b5b6a5f4SSimon Horman tap_cnt = ntap; 474b5b6a5f4SSimon Horman } 475b5b6a5f4SSimon Horman 476b5b6a5f4SSimon Horman if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 47726eb2607SMasaharu Hayakawa host->tap_set = (tap_start + tap_end) / 2 % host->tap_num; 478b5b6a5f4SSimon Horman else 479b5b6a5f4SSimon Horman return -EIO; 480b5b6a5f4SSimon Horman 481b5b6a5f4SSimon Horman /* Set SCC */ 48226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set); 483b5b6a5f4SSimon Horman 484b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 485b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 486b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 487b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 488b5b6a5f4SSimon Horman 489b5b6a5f4SSimon Horman return 0; 490b5b6a5f4SSimon Horman } 491b5b6a5f4SSimon Horman 4920c482d82SWolfram Sang static int renesas_sdhi_execute_tuning(struct tmio_mmc_host *host, u32 opcode) 4930c482d82SWolfram Sang { 4940c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 4950c482d82SWolfram Sang int i, ret; 4960c482d82SWolfram Sang 4970c482d82SWolfram Sang host->tap_num = renesas_sdhi_init_tuning(host); 4980c482d82SWolfram Sang if (!host->tap_num) 4990c482d82SWolfram Sang return 0; /* Tuning is not supported */ 5000c482d82SWolfram Sang 5010c482d82SWolfram Sang if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) { 5023a821a82SWolfram Sang dev_err(&host->pdev->dev, 5033a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 5043a821a82SWolfram Sang return -EINVAL; 5050c482d82SWolfram Sang } 5060c482d82SWolfram Sang 5070c482d82SWolfram Sang priv->doing_tune = true; 5080c482d82SWolfram Sang bitmap_zero(host->taps, host->tap_num * 2); 5090c482d82SWolfram Sang 5100c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 5110c482d82SWolfram Sang for (i = 0; i < 2 * host->tap_num; i++) { 5120c482d82SWolfram Sang /* Set sampling clock position */ 5130c482d82SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % host->tap_num); 5140c482d82SWolfram Sang 5150c482d82SWolfram Sang ret = mmc_send_tuning(host->mmc, opcode, NULL); 5160c482d82SWolfram Sang if (ret == 0) 5170c482d82SWolfram Sang set_bit(i, host->taps); 5180c482d82SWolfram Sang } 5190c482d82SWolfram Sang 5200c482d82SWolfram Sang return renesas_sdhi_select_tuning(host); 5210c482d82SWolfram Sang } 5220c482d82SWolfram Sang 52311a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 52411a21960STakeshi Saito { 52511a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 52671cfc927STakeshi Saito unsigned long new_tap = host->tap_set; 52711a21960STakeshi Saito u32 val; 52811a21960STakeshi Saito 52911a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 53011a21960STakeshi Saito if (!val) 53111a21960STakeshi Saito return false; 53211a21960STakeshi Saito 53311a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 53411a21960STakeshi Saito 53511a21960STakeshi Saito /* Change TAP position according to correction status */ 53671cfc927STakeshi Saito if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 53771cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 53871cfc927STakeshi Saito /* 53971cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 54071cfc927STakeshi Saito * Therefore, use only CMD status. 54171cfc927STakeshi Saito */ 54271cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 54371cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 54471cfc927STakeshi Saito if (!smpcmp) 54571cfc927STakeshi Saito return false; /* no error in CMD signal */ 54671cfc927STakeshi Saito else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) 54771cfc927STakeshi Saito new_tap++; 54871cfc927STakeshi Saito else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) 54971cfc927STakeshi Saito new_tap--; 55071cfc927STakeshi Saito else 55171cfc927STakeshi Saito return true; /* need retune */ 55271cfc927STakeshi Saito } else { 55311a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 55471cfc927STakeshi Saito return true; /* need retune */ 55511a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 55671cfc927STakeshi Saito new_tap++; 55711a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 55871cfc927STakeshi Saito new_tap--; 55911a21960STakeshi Saito else 56011a21960STakeshi Saito return false; 56171cfc927STakeshi Saito } 56211a21960STakeshi Saito 56371cfc927STakeshi Saito host->tap_set = (new_tap % host->tap_num); 56411a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 56511a21960STakeshi Saito host->tap_set / (use_4tap ? 2 : 1)); 56611a21960STakeshi Saito 56711a21960STakeshi Saito return false; 56811a21960STakeshi Saito } 56911a21960STakeshi Saito 57011a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 57111a21960STakeshi Saito { 57211a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 57311a21960STakeshi Saito 57411a21960STakeshi Saito /* Check SCC error */ 57511a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 57611a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 57711a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 57811a21960STakeshi Saito return true; 57911a21960STakeshi Saito } 58011a21960STakeshi Saito 58111a21960STakeshi Saito return false; 58211a21960STakeshi Saito } 58311a21960STakeshi Saito 584b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 585b5b6a5f4SSimon Horman { 586b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 58712e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 58875f349a1SMasaharu Hayakawa 58975f349a1SMasaharu Hayakawa /* 59075f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 59175f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 59275f349a1SMasaharu Hayakawa */ 59375f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 59475f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 59575f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 59675f349a1SMasaharu Hayakawa return false; 59775f349a1SMasaharu Hayakawa 59811a21960STakeshi Saito if (mmc_doing_retune(host->mmc) || priv->doing_tune) 59975f349a1SMasaharu Hayakawa return false; 600b5b6a5f4SSimon Horman 601b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 60211a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 60311a21960STakeshi Saito return renesas_sdhi_auto_correction(host); 604b5b6a5f4SSimon Horman 60511a21960STakeshi Saito return renesas_sdhi_manual_correction(host, use_4tap); 606b5b6a5f4SSimon Horman } 607b5b6a5f4SSimon Horman 608b5b6a5f4SSimon Horman static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 609b5b6a5f4SSimon Horman { 610b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 611b5b6a5f4SSimon Horman 612b5b6a5f4SSimon Horman priv = host_to_priv(host); 613b5b6a5f4SSimon Horman 61426eb2607SMasaharu Hayakawa renesas_sdhi_reset_scc(host, priv); 61526eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, priv); 616b5b6a5f4SSimon Horman 617b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 618b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 619b5b6a5f4SSimon Horman 620b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 621b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 622b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 623b5b6a5f4SSimon Horman 624202367cbSNiklas Söderlund if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) 625202367cbSNiklas Söderlund sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, 626202367cbSNiklas Söderlund TMIO_MASK_INIT_RCAR2); 627b5b6a5f4SSimon Horman } 628b5b6a5f4SSimon Horman 6294dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 630b5b6a5f4SSimon Horman { 631b5b6a5f4SSimon Horman int timeout = 1000; 6324dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 6334dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 634b5b6a5f4SSimon Horman 6354dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 6364dc48a95SWolfram Sang & bit) == wait_state) 637b5b6a5f4SSimon Horman udelay(1); 638b5b6a5f4SSimon Horman 639b5b6a5f4SSimon Horman if (!timeout) { 640b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 641b5b6a5f4SSimon Horman return -EBUSY; 642b5b6a5f4SSimon Horman } 643b5b6a5f4SSimon Horman 644b5b6a5f4SSimon Horman return 0; 645b5b6a5f4SSimon Horman } 646b5b6a5f4SSimon Horman 647b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 648b5b6a5f4SSimon Horman { 6494dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 6504dc48a95SWolfram Sang 6512fe35968SSimon Horman switch (addr) { 652b5b6a5f4SSimon Horman case CTL_SD_CMD: 653b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 654b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 655b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 656b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 657b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 658b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 6594472f0fcSMasaharu Hayakawa case HOST_MODE: 6605124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 6614dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 6624dc48a95SWolfram Sang /* fallthrough */ 6634dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 6644dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 665b5b6a5f4SSimon Horman } 666b5b6a5f4SSimon Horman 667b5b6a5f4SSimon Horman return 0; 668b5b6a5f4SSimon Horman } 669b5b6a5f4SSimon Horman 670b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 671b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 672b5b6a5f4SSimon Horman { 673b5b6a5f4SSimon Horman /* 674b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 675b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 676b5b6a5f4SSimon Horman * depending on the timing with which the 677b5b6a5f4SSimon Horman * response register is read, the response 678b5b6a5f4SSimon Horman * value may not be read properly. 679b5b6a5f4SSimon Horman * Use single block read for this HW bug 680b5b6a5f4SSimon Horman */ 681b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 682b5b6a5f4SSimon Horman blk_size == 2) 683b5b6a5f4SSimon Horman return 1; 684b5b6a5f4SSimon Horman 685b5b6a5f4SSimon Horman return blk_size; 686b5b6a5f4SSimon Horman } 687b5b6a5f4SSimon Horman 688b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 689b5b6a5f4SSimon Horman { 69041279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 69141279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 692b5b6a5f4SSimon Horman 69341279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 69441279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 695b5b6a5f4SSimon Horman } 696b5b6a5f4SSimon Horman 6976a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 6980f4e2054SNiklas Söderlund .hs400_disabled = true, 6990f4e2054SNiklas Söderlund .hs400_4taps = true, 7000f4e2054SNiklas Söderlund }; 7010f4e2054SNiklas Söderlund 7026a686986SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 703164691aaSNiklas Söderlund .hs400_4taps = true, 704164691aaSNiklas Söderlund }; 705164691aaSNiklas Söderlund 70697bf85b6SWolfram Sang static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 70797bf85b6SWolfram Sang .hs400_disabled = true, 70897bf85b6SWolfram Sang }; 70997bf85b6SWolfram Sang 710164691aaSNiklas Söderlund static const struct soc_device_attribute sdhi_quirks_match[] = { 7116e3cbb05SWolfram Sang { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 7126a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 7136a686986SWolfram Sang { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 7146a686986SWolfram Sang { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 71597bf85b6SWolfram Sang { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 716164691aaSNiklas Söderlund { /* Sentinel. */ }, 717164691aaSNiklas Söderlund }; 718164691aaSNiklas Söderlund 7199d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 7209d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 721b5b6a5f4SSimon Horman { 722b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 723164691aaSNiklas Söderlund const struct renesas_sdhi_quirks *quirks = NULL; 7242fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 725164691aaSNiklas Söderlund const struct soc_device_attribute *attr; 7262fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 7272fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 728b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 7292fe35968SSimon Horman struct renesas_sdhi *priv; 730e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 731b5b6a5f4SSimon Horman struct resource *res; 732c9a9497cSWolfram Sang u16 ver; 7332fe35968SSimon Horman 7342fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 735b5b6a5f4SSimon Horman 736164691aaSNiklas Söderlund attr = soc_device_match(sdhi_quirks_match); 737164691aaSNiklas Söderlund if (attr) 738164691aaSNiklas Söderlund quirks = attr->data; 739164691aaSNiklas Söderlund 740b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 741b5b6a5f4SSimon Horman if (!res) 742b5b6a5f4SSimon Horman return -EINVAL; 743b5b6a5f4SSimon Horman 7442fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 7452fe35968SSimon Horman GFP_KERNEL); 746b5b6a5f4SSimon Horman if (!priv) 747b5b6a5f4SSimon Horman return -ENOMEM; 748b5b6a5f4SSimon Horman 7497af08206SWolfram Sang priv->quirks = quirks; 750b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 751b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 752b5b6a5f4SSimon Horman 753b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 754b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 755b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 756b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 7574ce62817SMasahiro Yamada return ret; 758b5b6a5f4SSimon Horman } 759b5b6a5f4SSimon Horman 760b5b6a5f4SSimon Horman /* 761b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 762b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 763b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 764b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 765b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 766b5b6a5f4SSimon Horman * disable it. 767b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 768b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 769b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 770b5b6a5f4SSimon Horman */ 771b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 772b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 773b5b6a5f4SSimon Horman priv->clk_cd = NULL; 774b5b6a5f4SSimon Horman 775b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 776b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 777b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 778b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 779b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 780b5b6a5f4SSimon Horman "state_uhs"); 781b5b6a5f4SSimon Horman } 782b5b6a5f4SSimon Horman 783b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 7848d09a133SMasahiro Yamada if (IS_ERR(host)) 7858d09a133SMasahiro Yamada return PTR_ERR(host); 786b5b6a5f4SSimon Horman 787b5b6a5f4SSimon Horman if (of_data) { 788b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 789b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 790b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 791b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 792b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 793603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 794603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 795b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 796b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 797b5b6a5f4SSimon Horman } 798b5b6a5f4SSimon Horman 799b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 800b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 801b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 8020196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 803b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 804bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 805b5b6a5f4SSimon Horman 8060f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 8070f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 8080f4e2054SNiklas Söderlund 809ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 810ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 811ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 812ef5332c1SWolfram Sang 813b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 814b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 815b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 8162aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 8172aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 818b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 8191970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 820d30ae056STakeshi Saito 821d30ae056STakeshi Saito /* SDR and HS200/400 registers requires HW reset */ 822d30ae056STakeshi Saito if (of_data && of_data->scc_offset) { 823d30ae056STakeshi Saito priv->scc_ctl = host->ctl + of_data->scc_offset; 824d30ae056STakeshi Saito host->mmc->caps |= MMC_CAP_HW_RESET; 825d30ae056STakeshi Saito host->hw_reset = renesas_sdhi_hw_reset; 826d30ae056STakeshi Saito } 827b5b6a5f4SSimon Horman } 828b5b6a5f4SSimon Horman 829b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 830b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 831b5b6a5f4SSimon Horman host->bus_shift = 1; 832b5b6a5f4SSimon Horman 833b5b6a5f4SSimon Horman if (mmd) 834b5b6a5f4SSimon Horman *mmc_data = *mmd; 835b5b6a5f4SSimon Horman 836b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 837b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 838b5b6a5f4SSimon Horman 839b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 840b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 841b5b6a5f4SSimon Horman 842b5b6a5f4SSimon Horman /* 843b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 844b5b6a5f4SSimon Horman * bus width mode. 845b5b6a5f4SSimon Horman */ 846b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 847b5b6a5f4SSimon Horman 848b5b6a5f4SSimon Horman /* 849b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 850b5b6a5f4SSimon Horman */ 851b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 852b5b6a5f4SSimon Horman 8532fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 854b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 855b5b6a5f4SSimon Horman 856b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 857b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 858b5b6a5f4SSimon Horman 859b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 860b21fc294SMasahiro Yamada if (ret) 861b5b6a5f4SSimon Horman goto efree; 862b5b6a5f4SSimon Horman 863c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 864c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 865c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 866c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 867c9a9497cSWolfram Sang 8685124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 869c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 8705124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 8715124b592SWolfram Sang 87291ecbe50SWolfram Sang ret = tmio_mmc_host_probe(host); 87391ecbe50SWolfram Sang if (ret < 0) 87491ecbe50SWolfram Sang goto edisclk; 87591ecbe50SWolfram Sang 876b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 877b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 878b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 87926eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 88026eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 881b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 882c1a49782SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 883b5b6a5f4SSimon Horman bool hit = false; 884b5b6a5f4SSimon Horman 885b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 886b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 887b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 888852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 889c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 890c1a49782SWolfram Sang taps->tap_hs400_4tap : 891c1a49782SWolfram Sang taps->tap; 892b5b6a5f4SSimon Horman hit = true; 893b5b6a5f4SSimon Horman break; 894b5b6a5f4SSimon Horman } 895b5b6a5f4SSimon Horman } 896b5b6a5f4SSimon Horman 897b5b6a5f4SSimon Horman if (!hit) 898e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 899b5b6a5f4SSimon Horman 9000c482d82SWolfram Sang host->execute_tuning = renesas_sdhi_execute_tuning; 901b5b6a5f4SSimon Horman host->select_tuning = renesas_sdhi_select_tuning; 902b5b6a5f4SSimon Horman host->check_scc_error = renesas_sdhi_check_scc_error; 90326eb2607SMasaharu Hayakawa host->prepare_hs400_tuning = 90426eb2607SMasaharu Hayakawa renesas_sdhi_prepare_hs400_tuning; 90526eb2607SMasaharu Hayakawa host->hs400_downgrade = renesas_sdhi_disable_scc; 90626eb2607SMasaharu Hayakawa host->hs400_complete = renesas_sdhi_hs400_complete; 907b5b6a5f4SSimon Horman } 908b5b6a5f4SSimon Horman 909e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 910e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 911e8307ec5SGeert Uytterhoeven ret = num_irqs; 912b5b6a5f4SSimon Horman goto eirq; 913b5b6a5f4SSimon Horman } 914b5b6a5f4SSimon Horman 915b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 916e8307ec5SGeert Uytterhoeven if (!num_irqs) { 917e8307ec5SGeert Uytterhoeven ret = -ENXIO; 918e8307ec5SGeert Uytterhoeven goto eirq; 919e8307ec5SGeert Uytterhoeven } 920e8307ec5SGeert Uytterhoeven 921e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 922e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 923e8307ec5SGeert Uytterhoeven if (irq < 0) { 924b5b6a5f4SSimon Horman ret = irq; 925b5b6a5f4SSimon Horman goto eirq; 926b5b6a5f4SSimon Horman } 927b5b6a5f4SSimon Horman 928e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 929e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 930e8307ec5SGeert Uytterhoeven if (ret) 931e8307ec5SGeert Uytterhoeven goto eirq; 932e8307ec5SGeert Uytterhoeven } 933e8307ec5SGeert Uytterhoeven 934b5b6a5f4SSimon Horman dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 935b5b6a5f4SSimon Horman mmc_hostname(host->mmc), (unsigned long) 936b5b6a5f4SSimon Horman (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 937b5b6a5f4SSimon Horman host->mmc->f_max / 1000000); 938b5b6a5f4SSimon Horman 939b5b6a5f4SSimon Horman return ret; 940b5b6a5f4SSimon Horman 941b5b6a5f4SSimon Horman eirq: 942b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 943b21fc294SMasahiro Yamada edisclk: 944b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 945b5b6a5f4SSimon Horman efree: 946b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 9474ce62817SMasahiro Yamada 948b5b6a5f4SSimon Horman return ret; 949b5b6a5f4SSimon Horman } 9509d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 951b5b6a5f4SSimon Horman 9529d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 953b5b6a5f4SSimon Horman { 954a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 955b5b6a5f4SSimon Horman 956b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 957b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 958b5b6a5f4SSimon Horman 959b5b6a5f4SSimon Horman return 0; 960b5b6a5f4SSimon Horman } 9619d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 962967a6a07SMasaharu Hayakawa 963967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 964