1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 587317c4dSSimon Horman * Copyright (C) 2015-17 Renesas Electronics Corporation 687317c4dSSimon Horman * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/kernel.h> 22b5b6a5f4SSimon Horman #include <linux/clk.h> 23b5b6a5f4SSimon Horman #include <linux/slab.h> 24967a6a07SMasaharu Hayakawa #include <linux/module.h> 25b5b6a5f4SSimon Horman #include <linux/of_device.h> 26b5b6a5f4SSimon Horman #include <linux/platform_device.h> 27b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 29b5b6a5f4SSimon Horman #include <linux/mfd/tmio.h> 30b5b6a5f4SSimon Horman #include <linux/sh_dma.h> 31b5b6a5f4SSimon Horman #include <linux/delay.h> 32b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 33b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 34b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 35164691aaSNiklas Söderlund #include <linux/sys_soc.h> 36b5b6a5f4SSimon Horman 37b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 38b5b6a5f4SSimon Horman #include "tmio_mmc.h" 39b5b6a5f4SSimon Horman 404472f0fcSMasaharu Hayakawa #define HOST_MODE 0xe4 41b5b6a5f4SSimon Horman 42b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 43c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 44b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 46b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 47b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 48b5b6a5f4SSimon Horman 49164691aaSNiklas Söderlund struct renesas_sdhi_quirks { 500f4e2054SNiklas Söderlund bool hs400_disabled; 51164691aaSNiklas Söderlund bool hs400_4taps; 52164691aaSNiklas Söderlund }; 53164691aaSNiklas Söderlund 54b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 55b5b6a5f4SSimon Horman { 56b5b6a5f4SSimon Horman u32 val; 57b5b6a5f4SSimon Horman 58b5b6a5f4SSimon Horman /* 59b5b6a5f4SSimon Horman * see also 60b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 61b5b6a5f4SSimon Horman */ 62b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 63b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 64b5b6a5f4SSimon Horman val = (width == 32) ? 0x0001 : 0x0000; 65b5b6a5f4SSimon Horman break; 66b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 67b5b6a5f4SSimon Horman val = (width == 32) ? 0x0000 : 0x0001; 68b5b6a5f4SSimon Horman break; 69b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 70b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 71b5b6a5f4SSimon Horman if (width == 64) 72b5b6a5f4SSimon Horman val = 0x0000; 73b5b6a5f4SSimon Horman else if (width == 32) 74b5b6a5f4SSimon Horman val = 0x0101; 75b5b6a5f4SSimon Horman else 76b5b6a5f4SSimon Horman val = 0x0001; 77b5b6a5f4SSimon Horman break; 78b5b6a5f4SSimon Horman default: 79b5b6a5f4SSimon Horman /* nothing to do */ 80b5b6a5f4SSimon Horman return; 81b5b6a5f4SSimon Horman } 82b5b6a5f4SSimon Horman 834472f0fcSMasaharu Hayakawa sd_ctrl_write16(host, HOST_MODE, val); 84b5b6a5f4SSimon Horman } 85b5b6a5f4SSimon Horman 86b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 87b5b6a5f4SSimon Horman { 88b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 89b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 90b5b6a5f4SSimon Horman int ret = clk_prepare_enable(priv->clk); 912fe35968SSimon Horman 92b5b6a5f4SSimon Horman if (ret < 0) 93b5b6a5f4SSimon Horman return ret; 94b5b6a5f4SSimon Horman 95b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 96b5b6a5f4SSimon Horman if (ret < 0) { 97b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 98b5b6a5f4SSimon Horman return ret; 99b5b6a5f4SSimon Horman } 100b5b6a5f4SSimon Horman 101b5b6a5f4SSimon Horman /* 102b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 103b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 104b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 105b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 106b5b6a5f4SSimon Horman */ 107b5b6a5f4SSimon Horman if (!mmc->f_max) 108b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 109b5b6a5f4SSimon Horman 110b5b6a5f4SSimon Horman /* 111b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 112b5b6a5f4SSimon Horman * divided by our maximum divider. 113b5b6a5f4SSimon Horman */ 114b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 115b5b6a5f4SSimon Horman 116b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 117b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 118b5b6a5f4SSimon Horman 119b5b6a5f4SSimon Horman return 0; 120b5b6a5f4SSimon Horman } 121b5b6a5f4SSimon Horman 122b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 123b5b6a5f4SSimon Horman unsigned int new_clock) 124b5b6a5f4SSimon Horman { 125b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 126b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 127b5b6a5f4SSimon Horman int i, ret; 128b5b6a5f4SSimon Horman 129d63c2bf4SWolfram Sang /* tested only on R-Car Gen2+ currently; may work for others */ 130b5b6a5f4SSimon Horman if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 131b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 132b5b6a5f4SSimon Horman 133b5b6a5f4SSimon Horman /* 134b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 135b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 136b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 137b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 138b5b6a5f4SSimon Horman */ 139b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 140b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, new_clock << i); 141b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 142b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 143b5b6a5f4SSimon Horman freq = clk_round_rate(priv->clk, 144b5b6a5f4SSimon Horman (new_clock << i) / 4 * 3); 145b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 146b5b6a5f4SSimon Horman continue; 147b5b6a5f4SSimon Horman } 148b5b6a5f4SSimon Horman 149b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 150b5b6a5f4SSimon Horman if (diff <= diff_min) { 151b5b6a5f4SSimon Horman best_freq = freq; 152b5b6a5f4SSimon Horman diff_min = diff; 153b5b6a5f4SSimon Horman } 154b5b6a5f4SSimon Horman } 155b5b6a5f4SSimon Horman 156b5b6a5f4SSimon Horman ret = clk_set_rate(priv->clk, best_freq); 157b5b6a5f4SSimon Horman 158b5b6a5f4SSimon Horman return ret == 0 ? best_freq : clk_get_rate(priv->clk); 159b5b6a5f4SSimon Horman } 160b5b6a5f4SSimon Horman 1610196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1620196c8dbSMasahiro Yamada unsigned int new_clock) 1630196c8dbSMasahiro Yamada { 1640196c8dbSMasahiro Yamada u32 clk = 0, clock; 1650196c8dbSMasahiro Yamada 16668f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 16768f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 16868f83127SMasahiro Yamada 16968f83127SMasahiro Yamada if (new_clock == 0) 17068f83127SMasahiro Yamada goto out; 17168f83127SMasahiro Yamada 1720196c8dbSMasahiro Yamada clock = renesas_sdhi_clk_update(host, new_clock) / 512; 1730196c8dbSMasahiro Yamada 1740196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 1750196c8dbSMasahiro Yamada clock <<= 1; 1760196c8dbSMasahiro Yamada 1770196c8dbSMasahiro Yamada /* 1/1 clock is option */ 1780196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 1790196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 1800196c8dbSMasahiro Yamada clk |= 0xff; 1810196c8dbSMasahiro Yamada else 1820196c8dbSMasahiro Yamada clk &= ~0xff; 1830196c8dbSMasahiro Yamada } 1840196c8dbSMasahiro Yamada 1850196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 1860196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 1870196c8dbSMasahiro Yamada usleep_range(10000, 11000); 1880196c8dbSMasahiro Yamada 18968f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 19068f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 19168f83127SMasahiro Yamada 19268f83127SMasahiro Yamada out: 19368f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 19468f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 19568f83127SMasahiro Yamada usleep_range(10000, 11000); 1960196c8dbSMasahiro Yamada } 1970196c8dbSMasahiro Yamada 198b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 199b5b6a5f4SSimon Horman { 200b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 201b5b6a5f4SSimon Horman 202b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk); 203b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 204b5b6a5f4SSimon Horman } 205b5b6a5f4SSimon Horman 206b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 207b5b6a5f4SSimon Horman { 208b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 209b5b6a5f4SSimon Horman 2102fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2112fe35968SSimon Horman TMIO_STAT_DAT0); 212b5b6a5f4SSimon Horman } 213b5b6a5f4SSimon Horman 214b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 215b5b6a5f4SSimon Horman struct mmc_ios *ios) 216b5b6a5f4SSimon Horman { 217b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 218b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 219b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 220b5b6a5f4SSimon Horman int ret; 221b5b6a5f4SSimon Horman 222b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 223b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 224b5b6a5f4SSimon Horman pin_state = priv->pins_default; 225b5b6a5f4SSimon Horman break; 226b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 227b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 228b5b6a5f4SSimon Horman break; 229b5b6a5f4SSimon Horman default: 230b5b6a5f4SSimon Horman return -EINVAL; 231b5b6a5f4SSimon Horman } 232b5b6a5f4SSimon Horman 233b5b6a5f4SSimon Horman /* 234b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 235b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 236b5b6a5f4SSimon Horman */ 237b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 238b5b6a5f4SSimon Horman return ios->signal_voltage == 239b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 240b5b6a5f4SSimon Horman 241b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 242b5b6a5f4SSimon Horman if (ret) 243b5b6a5f4SSimon Horman return ret; 244b5b6a5f4SSimon Horman 245b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 246b5b6a5f4SSimon Horman } 247b5b6a5f4SSimon Horman 248b5b6a5f4SSimon Horman /* SCC registers */ 249b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 250b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 251b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 252b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 253b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 254b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 25526eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 256b5b6a5f4SSimon Horman 257b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */ 258b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 259b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 260b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 261b5b6a5f4SSimon Horman 262b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */ 263b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 264b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */ 265b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 266b5b6a5f4SSimon Horman /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */ 267b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 26826eb2607SMasaharu Hayakawa /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */ 26926eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 27026eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 271b5b6a5f4SSimon Horman 272b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 273b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 274b5b6a5f4SSimon Horman { 275b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 276b5b6a5f4SSimon Horman } 277b5b6a5f4SSimon Horman 278b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 279b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 280b5b6a5f4SSimon Horman int addr, u32 val) 281b5b6a5f4SSimon Horman { 282b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 283b5b6a5f4SSimon Horman } 284b5b6a5f4SSimon Horman 285b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 286b5b6a5f4SSimon Horman { 287b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 288b5b6a5f4SSimon Horman 289b5b6a5f4SSimon Horman priv = host_to_priv(host); 290b5b6a5f4SSimon Horman 291b5b6a5f4SSimon Horman /* Initialize SCC */ 292b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 293b5b6a5f4SSimon Horman 294b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 295b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 296b5b6a5f4SSimon Horman 29726eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 29826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 29926eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 30026eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 30126eb2607SMasaharu Hayakawa 302b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 303b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 304b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 305b5b6a5f4SSimon Horman 306b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 307b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 308b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 309b5b6a5f4SSimon Horman 310852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 311b5b6a5f4SSimon Horman 31226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 31326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 31426eb2607SMasaharu Hayakawa 315b5b6a5f4SSimon Horman /* Read TAPNUM */ 316b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 317b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 318b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 319b5b6a5f4SSimon Horman } 320b5b6a5f4SSimon Horman 321b5b6a5f4SSimon Horman static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host, 322b5b6a5f4SSimon Horman unsigned long tap) 323b5b6a5f4SSimon Horman { 324b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 325b5b6a5f4SSimon Horman 326b5b6a5f4SSimon Horman /* Set sampling clock position */ 327b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap); 328b5b6a5f4SSimon Horman } 329b5b6a5f4SSimon Horman 33026eb2607SMasaharu Hayakawa static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host) 33126eb2607SMasaharu Hayakawa { 33226eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 33326eb2607SMasaharu Hayakawa 33426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 33526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 33626eb2607SMasaharu Hayakawa 33726eb2607SMasaharu Hayakawa /* Set HS400 mode */ 33826eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 33926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 34026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 34126eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 34226eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 34326eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 34426eb2607SMasaharu Hayakawa 34526eb2607SMasaharu Hayakawa /* Set the sampling clock selection range of HS400 mode */ 34626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 34726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 34826eb2607SMasaharu Hayakawa 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 34926eb2607SMasaharu Hayakawa 35026eb2607SMasaharu Hayakawa 35126eb2607SMasaharu Hayakawa if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400) 35226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 35326eb2607SMasaharu Hayakawa host->tap_set / 2); 35426eb2607SMasaharu Hayakawa 35526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 35626eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 35726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 35826eb2607SMasaharu Hayakawa 35926eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 36026eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36126eb2607SMasaharu Hayakawa } 36226eb2607SMasaharu Hayakawa 36326eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 36426eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 36526eb2607SMasaharu Hayakawa { 36626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 36726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36826eb2607SMasaharu Hayakawa 36926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 37026eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 37126eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 37226eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 37326eb2607SMasaharu Hayakawa } 37426eb2607SMasaharu Hayakawa 37526eb2607SMasaharu Hayakawa static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host) 37626eb2607SMasaharu Hayakawa { 37726eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 37826eb2607SMasaharu Hayakawa 37926eb2607SMasaharu Hayakawa renesas_sdhi_reset_scc(host, priv); 38026eb2607SMasaharu Hayakawa 38126eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 38226eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 38326eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 38426eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 38526eb2607SMasaharu Hayakawa 38626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 38726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 38826eb2607SMasaharu Hayakawa } 38926eb2607SMasaharu Hayakawa 39026eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 39126eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 39226eb2607SMasaharu Hayakawa { 39326eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 39426eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 39526eb2607SMasaharu Hayakawa 39626eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 39726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 39826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 39926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 40026eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 40126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 40226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 40326eb2607SMasaharu Hayakawa 40426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 40526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 40626eb2607SMasaharu Hayakawa } 40726eb2607SMasaharu Hayakawa 40826eb2607SMasaharu Hayakawa static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host) 40926eb2607SMasaharu Hayakawa { 41026eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 41126eb2607SMasaharu Hayakawa } 41226eb2607SMasaharu Hayakawa 413b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_MAX_TAP 3 414b5b6a5f4SSimon Horman 415b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 416b5b6a5f4SSimon Horman { 417b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 418b5b6a5f4SSimon Horman unsigned long tap_cnt; /* counter of tuning success */ 419b5b6a5f4SSimon Horman unsigned long tap_start;/* start position of tuning success */ 420b5b6a5f4SSimon Horman unsigned long tap_end; /* end position of tuning success */ 421b5b6a5f4SSimon Horman unsigned long ntap; /* temporary counter of tuning success */ 422b5b6a5f4SSimon Horman unsigned long i; 423b5b6a5f4SSimon Horman 424b5b6a5f4SSimon Horman /* Clear SCC_RVSREQ */ 425b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 426b5b6a5f4SSimon Horman 427b5b6a5f4SSimon Horman /* 4285c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 4295c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 4305c99826bSNiklas Söderlund * considering it for tuning selection. 4315c99826bSNiklas Söderlund */ 4325c99826bSNiklas Söderlund for (i = 0; i < host->tap_num * 2; i++) { 4335c99826bSNiklas Söderlund int offset = host->tap_num * (i < host->tap_num ? 1 : -1); 4345c99826bSNiklas Söderlund 4355c99826bSNiklas Söderlund if (!test_bit(i, host->taps)) 4365c99826bSNiklas Söderlund clear_bit(i + offset, host->taps); 4375c99826bSNiklas Söderlund } 4385c99826bSNiklas Söderlund 4395c99826bSNiklas Söderlund /* 440b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 441b5b6a5f4SSimon Horman * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 442b5b6a5f4SSimon Horman * center index as the tap. 443b5b6a5f4SSimon Horman */ 444b5b6a5f4SSimon Horman tap_cnt = 0; 445b5b6a5f4SSimon Horman ntap = 0; 446b5b6a5f4SSimon Horman tap_start = 0; 447b5b6a5f4SSimon Horman tap_end = 0; 448b5b6a5f4SSimon Horman for (i = 0; i < host->tap_num * 2; i++) { 4492fe35968SSimon Horman if (test_bit(i, host->taps)) { 450b5b6a5f4SSimon Horman ntap++; 4512fe35968SSimon Horman } else { 452b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 453b5b6a5f4SSimon Horman tap_start = i - ntap; 454b5b6a5f4SSimon Horman tap_end = i - 1; 455b5b6a5f4SSimon Horman tap_cnt = ntap; 456b5b6a5f4SSimon Horman } 457b5b6a5f4SSimon Horman ntap = 0; 458b5b6a5f4SSimon Horman } 459b5b6a5f4SSimon Horman } 460b5b6a5f4SSimon Horman 461b5b6a5f4SSimon Horman if (ntap > tap_cnt) { 462b5b6a5f4SSimon Horman tap_start = i - ntap; 463b5b6a5f4SSimon Horman tap_end = i - 1; 464b5b6a5f4SSimon Horman tap_cnt = ntap; 465b5b6a5f4SSimon Horman } 466b5b6a5f4SSimon Horman 467b5b6a5f4SSimon Horman if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 46826eb2607SMasaharu Hayakawa host->tap_set = (tap_start + tap_end) / 2 % host->tap_num; 469b5b6a5f4SSimon Horman else 470b5b6a5f4SSimon Horman return -EIO; 471b5b6a5f4SSimon Horman 472b5b6a5f4SSimon Horman /* Set SCC */ 47326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set); 474b5b6a5f4SSimon Horman 475b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 476b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 477b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 478b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 479b5b6a5f4SSimon Horman 480b5b6a5f4SSimon Horman return 0; 481b5b6a5f4SSimon Horman } 482b5b6a5f4SSimon Horman 483b5b6a5f4SSimon Horman static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 484b5b6a5f4SSimon Horman { 485b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 48675f349a1SMasaharu Hayakawa bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400; 48775f349a1SMasaharu Hayakawa 48875f349a1SMasaharu Hayakawa /* 48975f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 49075f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 49175f349a1SMasaharu Hayakawa */ 49275f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 49375f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 49475f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 49575f349a1SMasaharu Hayakawa return false; 49675f349a1SMasaharu Hayakawa 49775f349a1SMasaharu Hayakawa if (mmc_doing_retune(host->mmc)) 49875f349a1SMasaharu Hayakawa return false; 499b5b6a5f4SSimon Horman 500b5b6a5f4SSimon Horman /* Check SCC error */ 501b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 502b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN && 503b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 504b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 505b5b6a5f4SSimon Horman /* Clear SCC error */ 506b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 507b5b6a5f4SSimon Horman return true; 508b5b6a5f4SSimon Horman } 509b5b6a5f4SSimon Horman 510b5b6a5f4SSimon Horman return false; 511b5b6a5f4SSimon Horman } 512b5b6a5f4SSimon Horman 513b5b6a5f4SSimon Horman static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 514b5b6a5f4SSimon Horman { 515b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 516b5b6a5f4SSimon Horman 517b5b6a5f4SSimon Horman priv = host_to_priv(host); 518b5b6a5f4SSimon Horman 51926eb2607SMasaharu Hayakawa renesas_sdhi_reset_scc(host, priv); 52026eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, priv); 521b5b6a5f4SSimon Horman 522b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 523b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 524b5b6a5f4SSimon Horman 525b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 526b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 527b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 528b5b6a5f4SSimon Horman 529b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 530b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 531b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 532202367cbSNiklas Söderlund 533202367cbSNiklas Söderlund if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) 534202367cbSNiklas Söderlund sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, 535202367cbSNiklas Söderlund TMIO_MASK_INIT_RCAR2); 536b5b6a5f4SSimon Horman } 537b5b6a5f4SSimon Horman 5384dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 539b5b6a5f4SSimon Horman { 540b5b6a5f4SSimon Horman int timeout = 1000; 5414dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 5424dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 543b5b6a5f4SSimon Horman 5444dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 5454dc48a95SWolfram Sang & bit) == wait_state) 546b5b6a5f4SSimon Horman udelay(1); 547b5b6a5f4SSimon Horman 548b5b6a5f4SSimon Horman if (!timeout) { 549b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 550b5b6a5f4SSimon Horman return -EBUSY; 551b5b6a5f4SSimon Horman } 552b5b6a5f4SSimon Horman 553b5b6a5f4SSimon Horman return 0; 554b5b6a5f4SSimon Horman } 555b5b6a5f4SSimon Horman 556b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 557b5b6a5f4SSimon Horman { 5584dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 5594dc48a95SWolfram Sang 5602fe35968SSimon Horman switch (addr) { 561b5b6a5f4SSimon Horman case CTL_SD_CMD: 562b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 563b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 564b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 565b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 566b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 567b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 5684472f0fcSMasaharu Hayakawa case HOST_MODE: 5695124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 5704dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 5714dc48a95SWolfram Sang /* fallthrough */ 5724dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 5734dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 574b5b6a5f4SSimon Horman } 575b5b6a5f4SSimon Horman 576b5b6a5f4SSimon Horman return 0; 577b5b6a5f4SSimon Horman } 578b5b6a5f4SSimon Horman 579b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 580b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 581b5b6a5f4SSimon Horman { 582b5b6a5f4SSimon Horman /* 583b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 584b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 585b5b6a5f4SSimon Horman * depending on the timing with which the 586b5b6a5f4SSimon Horman * response register is read, the response 587b5b6a5f4SSimon Horman * value may not be read properly. 588b5b6a5f4SSimon Horman * Use single block read for this HW bug 589b5b6a5f4SSimon Horman */ 590b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 591b5b6a5f4SSimon Horman blk_size == 2) 592b5b6a5f4SSimon Horman return 1; 593b5b6a5f4SSimon Horman 594b5b6a5f4SSimon Horman return blk_size; 595b5b6a5f4SSimon Horman } 596b5b6a5f4SSimon Horman 597b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 598b5b6a5f4SSimon Horman { 59941279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 60041279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 601b5b6a5f4SSimon Horman 60241279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 60341279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 604b5b6a5f4SSimon Horman } 605b5b6a5f4SSimon Horman 6060f4e2054SNiklas Söderlund static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w_es1 = { 6070f4e2054SNiklas Söderlund .hs400_disabled = true, 6080f4e2054SNiklas Söderlund .hs400_4taps = true, 6090f4e2054SNiklas Söderlund }; 6100f4e2054SNiklas Söderlund 6110f4e2054SNiklas Söderlund static const struct renesas_sdhi_quirks sdhi_quirks_h3_es2 = { 6120f4e2054SNiklas Söderlund .hs400_disabled = false, 613164691aaSNiklas Söderlund .hs400_4taps = true, 614164691aaSNiklas Söderlund }; 615164691aaSNiklas Söderlund 616164691aaSNiklas Söderlund static const struct soc_device_attribute sdhi_quirks_match[] = { 6170f4e2054SNiklas Söderlund { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_h3_m3w_es1 }, 6180f4e2054SNiklas Söderlund { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_h3_es2 }, 6190f4e2054SNiklas Söderlund { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_h3_m3w_es1 }, 6200f4e2054SNiklas Söderlund { .soc_id = "r8a7796", .revision = "ES1.1", .data = &sdhi_quirks_h3_m3w_es1 }, 621164691aaSNiklas Söderlund { /* Sentinel. */ }, 622164691aaSNiklas Söderlund }; 623164691aaSNiklas Söderlund 6249d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 6259d08428aSSimon Horman const struct tmio_mmc_dma_ops *dma_ops) 626b5b6a5f4SSimon Horman { 627b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 628164691aaSNiklas Söderlund const struct renesas_sdhi_quirks *quirks = NULL; 6292fe35968SSimon Horman const struct renesas_sdhi_of_data *of_data; 630164691aaSNiklas Söderlund const struct soc_device_attribute *attr; 6312fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 6322fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 633b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 6342fe35968SSimon Horman struct renesas_sdhi *priv; 635b5b6a5f4SSimon Horman struct resource *res; 636b5b6a5f4SSimon Horman int irq, ret, i; 6372fe35968SSimon Horman 6382fe35968SSimon Horman of_data = of_device_get_match_data(&pdev->dev); 639b5b6a5f4SSimon Horman 640164691aaSNiklas Söderlund attr = soc_device_match(sdhi_quirks_match); 641164691aaSNiklas Söderlund if (attr) 642164691aaSNiklas Söderlund quirks = attr->data; 643164691aaSNiklas Söderlund 644b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645b5b6a5f4SSimon Horman if (!res) 646b5b6a5f4SSimon Horman return -EINVAL; 647b5b6a5f4SSimon Horman 6482fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 6492fe35968SSimon Horman GFP_KERNEL); 650b5b6a5f4SSimon Horman if (!priv) 651b5b6a5f4SSimon Horman return -ENOMEM; 652b5b6a5f4SSimon Horman 653b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 654b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 655b5b6a5f4SSimon Horman 656b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 657b5b6a5f4SSimon Horman if (IS_ERR(priv->clk)) { 658b5b6a5f4SSimon Horman ret = PTR_ERR(priv->clk); 659b5b6a5f4SSimon Horman dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 6604ce62817SMasahiro Yamada return ret; 661b5b6a5f4SSimon Horman } 662b5b6a5f4SSimon Horman 663b5b6a5f4SSimon Horman /* 664b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 665b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 666b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 667b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 668b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 669b5b6a5f4SSimon Horman * disable it. 670b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 671b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 672b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 673b5b6a5f4SSimon Horman */ 674b5b6a5f4SSimon Horman priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 675b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 676b5b6a5f4SSimon Horman priv->clk_cd = NULL; 677b5b6a5f4SSimon Horman 678b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 679b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 680b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 681b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 682b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 683b5b6a5f4SSimon Horman "state_uhs"); 684b5b6a5f4SSimon Horman } 685b5b6a5f4SSimon Horman 686b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 6878d09a133SMasahiro Yamada if (IS_ERR(host)) 6888d09a133SMasahiro Yamada return PTR_ERR(host); 689b5b6a5f4SSimon Horman 690b5b6a5f4SSimon Horman if (of_data) { 691b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 692b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 693b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 694b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 695b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 696603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 697603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 698b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 699b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 700b5b6a5f4SSimon Horman } 701b5b6a5f4SSimon Horman 702b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 703b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 704b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 7050196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 706b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 707bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 708b5b6a5f4SSimon Horman 7090f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 7100f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 7110f4e2054SNiklas Söderlund 712164691aaSNiklas Söderlund if (quirks && quirks->hs400_4taps) 713164691aaSNiklas Söderlund mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400; 714164691aaSNiklas Söderlund 715ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 716ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 717ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 718ef5332c1SWolfram Sang 719b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 720b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 721b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 7222aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 7232aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 724b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 725b5b6a5f4SSimon Horman } 726b5b6a5f4SSimon Horman 727b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 728b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 729b5b6a5f4SSimon Horman host->bus_shift = 1; 730b5b6a5f4SSimon Horman 731b5b6a5f4SSimon Horman if (mmd) 732b5b6a5f4SSimon Horman *mmc_data = *mmd; 733b5b6a5f4SSimon Horman 734b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 735b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 736b5b6a5f4SSimon Horman 737b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 738b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 739b5b6a5f4SSimon Horman 740b5b6a5f4SSimon Horman /* 741b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 742b5b6a5f4SSimon Horman * bus width mode. 743b5b6a5f4SSimon Horman */ 744b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 745b5b6a5f4SSimon Horman 746b5b6a5f4SSimon Horman /* 747b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 748b5b6a5f4SSimon Horman */ 749b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 750b5b6a5f4SSimon Horman 7512fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 752b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 753b5b6a5f4SSimon Horman 754b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 755b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 756b5b6a5f4SSimon Horman 757b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 758b21fc294SMasahiro Yamada if (ret) 759b5b6a5f4SSimon Horman goto efree; 760b5b6a5f4SSimon Horman 761bc45719cSMasahiro Yamada ret = tmio_mmc_host_probe(host); 762b21fc294SMasahiro Yamada if (ret < 0) 763b21fc294SMasahiro Yamada goto edisclk; 764b21fc294SMasahiro Yamada 7655124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 7665124b592SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50) 7675124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 7685124b592SWolfram Sang 769b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 770b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 771b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 77226eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 77326eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 774b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 775b5b6a5f4SSimon Horman bool hit = false; 776b5b6a5f4SSimon Horman 777b5b6a5f4SSimon Horman host->mmc->caps |= MMC_CAP_HW_RESET; 778b5b6a5f4SSimon Horman 779b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 780b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 781b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 782852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 783b5b6a5f4SSimon Horman hit = true; 784b5b6a5f4SSimon Horman break; 785b5b6a5f4SSimon Horman } 786b5b6a5f4SSimon Horman } 787b5b6a5f4SSimon Horman 788b5b6a5f4SSimon Horman if (!hit) 789b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n"); 790b5b6a5f4SSimon Horman 791b5b6a5f4SSimon Horman priv->scc_ctl = host->ctl + of_data->scc_offset; 792b5b6a5f4SSimon Horman host->init_tuning = renesas_sdhi_init_tuning; 793b5b6a5f4SSimon Horman host->prepare_tuning = renesas_sdhi_prepare_tuning; 794b5b6a5f4SSimon Horman host->select_tuning = renesas_sdhi_select_tuning; 795b5b6a5f4SSimon Horman host->check_scc_error = renesas_sdhi_check_scc_error; 796b5b6a5f4SSimon Horman host->hw_reset = renesas_sdhi_hw_reset; 79726eb2607SMasaharu Hayakawa host->prepare_hs400_tuning = 79826eb2607SMasaharu Hayakawa renesas_sdhi_prepare_hs400_tuning; 79926eb2607SMasaharu Hayakawa host->hs400_downgrade = renesas_sdhi_disable_scc; 80026eb2607SMasaharu Hayakawa host->hs400_complete = renesas_sdhi_hs400_complete; 801b5b6a5f4SSimon Horman } 802b5b6a5f4SSimon Horman 803b5b6a5f4SSimon Horman i = 0; 804b5b6a5f4SSimon Horman while (1) { 805b5b6a5f4SSimon Horman irq = platform_get_irq(pdev, i); 806b5b6a5f4SSimon Horman if (irq < 0) 807b5b6a5f4SSimon Horman break; 808b5b6a5f4SSimon Horman i++; 809b5b6a5f4SSimon Horman ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 810b5b6a5f4SSimon Horman dev_name(&pdev->dev), host); 811b5b6a5f4SSimon Horman if (ret) 812b5b6a5f4SSimon Horman goto eirq; 813b5b6a5f4SSimon Horman } 814b5b6a5f4SSimon Horman 815b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 816b5b6a5f4SSimon Horman if (!i) { 817b5b6a5f4SSimon Horman ret = irq; 818b5b6a5f4SSimon Horman goto eirq; 819b5b6a5f4SSimon Horman } 820b5b6a5f4SSimon Horman 821b5b6a5f4SSimon Horman dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 822b5b6a5f4SSimon Horman mmc_hostname(host->mmc), (unsigned long) 823b5b6a5f4SSimon Horman (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 824b5b6a5f4SSimon Horman host->mmc->f_max / 1000000); 825b5b6a5f4SSimon Horman 826b5b6a5f4SSimon Horman return ret; 827b5b6a5f4SSimon Horman 828b5b6a5f4SSimon Horman eirq: 829b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 830b21fc294SMasahiro Yamada edisclk: 831b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 832b5b6a5f4SSimon Horman efree: 833b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 8344ce62817SMasahiro Yamada 835b5b6a5f4SSimon Horman return ret; 836b5b6a5f4SSimon Horman } 8379d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 838b5b6a5f4SSimon Horman 8399d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 840b5b6a5f4SSimon Horman { 841a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 842b5b6a5f4SSimon Horman 843b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 844b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 845b5b6a5f4SSimon Horman 846b5b6a5f4SSimon Horman return 0; 847b5b6a5f4SSimon Horman } 8489d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 849967a6a07SMasaharu Hayakawa 850967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 851