1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/clk.h> 22ab07a135SWolfram Sang #include <linux/delay.h> 23b4d86f37SWolfram Sang #include <linux/iopoll.h> 24ab07a135SWolfram Sang #include <linux/kernel.h> 25ab07a135SWolfram Sang #include <linux/mfd/tmio.h> 26b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 27ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h> 28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 29ab07a135SWolfram Sang #include <linux/module.h> 30b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 31b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 32ab07a135SWolfram Sang #include <linux/platform_device.h> 33ab07a135SWolfram Sang #include <linux/pm_domain.h> 34b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 35b4d86f37SWolfram Sang #include <linux/reset.h> 36ab07a135SWolfram Sang #include <linux/sh_dma.h> 37ab07a135SWolfram Sang #include <linux/slab.h> 38b5b6a5f4SSimon Horman 39b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 40b5b6a5f4SSimon Horman #include "tmio_mmc.h" 41b5b6a5f4SSimon Horman 424533c3ebSWolfram Sang #define CTL_HOST_MODE 0xe4 434533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 444533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 454533c3ebSWolfram Sang #define HOST_MODE_GEN3_WMODE BIT(0) 464533c3ebSWolfram Sang #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 474533c3ebSWolfram Sang 484533c3ebSWolfram Sang #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 494533c3ebSWolfram Sang #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 504533c3ebSWolfram Sang #define HOST_MODE_GEN3_64BIT 0 51b5b6a5f4SSimon Horman 520e08a411SWolfram Sang #define CTL_SDIF_MODE 0xe6 530e08a411SWolfram Sang #define SDIF_MODE_HS400 BIT(0) 540e08a411SWolfram Sang 55b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 56c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 57b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 58b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 59b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 60b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 61b5b6a5f4SSimon Horman 62ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000 63ce6f92c2SWolfram Sang 64b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 65b5b6a5f4SSimon Horman { 66b5b6a5f4SSimon Horman u32 val; 67b5b6a5f4SSimon Horman 68b5b6a5f4SSimon Horman /* 69b5b6a5f4SSimon Horman * see also 70b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 71b5b6a5f4SSimon Horman */ 72b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 73b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 744533c3ebSWolfram Sang val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 75b5b6a5f4SSimon Horman break; 76b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 774533c3ebSWolfram Sang val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 78b5b6a5f4SSimon Horman break; 79b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 80b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 81b5b6a5f4SSimon Horman if (width == 64) 824533c3ebSWolfram Sang val = HOST_MODE_GEN3_64BIT; 83b5b6a5f4SSimon Horman else if (width == 32) 844533c3ebSWolfram Sang val = HOST_MODE_GEN3_32BIT; 85b5b6a5f4SSimon Horman else 864533c3ebSWolfram Sang val = HOST_MODE_GEN3_16BIT; 87b5b6a5f4SSimon Horman break; 88b5b6a5f4SSimon Horman default: 89b5b6a5f4SSimon Horman /* nothing to do */ 90b5b6a5f4SSimon Horman return; 91b5b6a5f4SSimon Horman } 92b5b6a5f4SSimon Horman 934533c3ebSWolfram Sang sd_ctrl_write16(host, CTL_HOST_MODE, val); 94b5b6a5f4SSimon Horman } 95b5b6a5f4SSimon Horman 96b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 97b5b6a5f4SSimon Horman { 98b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 99b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 100d42c9fffSWolfram Sang int ret; 101b5b6a5f4SSimon Horman 102b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 103d42c9fffSWolfram Sang if (ret < 0) 104b5b6a5f4SSimon Horman return ret; 105b5b6a5f4SSimon Horman 106b5b6a5f4SSimon Horman /* 107b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 108b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 109b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 110b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 111b5b6a5f4SSimon Horman */ 112b5b6a5f4SSimon Horman if (!mmc->f_max) 113b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 114b5b6a5f4SSimon Horman 115b5b6a5f4SSimon Horman /* 116b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 117b5b6a5f4SSimon Horman * divided by our maximum divider. 118b5b6a5f4SSimon Horman */ 119b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 120b5b6a5f4SSimon Horman 121b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 122b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 123b5b6a5f4SSimon Horman 124b5b6a5f4SSimon Horman return 0; 125b5b6a5f4SSimon Horman } 126b5b6a5f4SSimon Horman 127b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 128bb6d3fa9SWolfram Sang unsigned int wanted_clock) 129b5b6a5f4SSimon Horman { 130b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 131bb6d3fa9SWolfram Sang struct clk *ref_clk = priv->clk; 132b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 133bb6d3fa9SWolfram Sang unsigned int new_clock, clkh_shift = 0; 13475eaf49fSTamás Szűcs int i; 135b5b6a5f4SSimon Horman 1360f93db65SWolfram Sang /* 1370f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+ 1380f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its 1390f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup. 1400f93db65SWolfram Sang */ 1410f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 143b5b6a5f4SSimon Horman 144bb6d3fa9SWolfram Sang if (priv->clkh) { 14546d4820fSWolfram Sang /* HS400 with 4TAP needs different clock settings */ 146bb6d3fa9SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 14746d4820fSWolfram Sang bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 148bb6d3fa9SWolfram Sang clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 149bb6d3fa9SWolfram Sang ref_clk = priv->clkh; 150bb6d3fa9SWolfram Sang } 151bb6d3fa9SWolfram Sang 152bb6d3fa9SWolfram Sang new_clock = wanted_clock << clkh_shift; 153bb6d3fa9SWolfram Sang 154b5b6a5f4SSimon Horman /* 155b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 156b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 157b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 158b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 159b5b6a5f4SSimon Horman */ 160b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 161bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, new_clock << i); 162b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 163b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 164bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 165b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 166b5b6a5f4SSimon Horman continue; 167b5b6a5f4SSimon Horman } 168b5b6a5f4SSimon Horman 169b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 170b5b6a5f4SSimon Horman if (diff <= diff_min) { 171b5b6a5f4SSimon Horman best_freq = freq; 172b5b6a5f4SSimon Horman diff_min = diff; 173b5b6a5f4SSimon Horman } 174b5b6a5f4SSimon Horman } 175b5b6a5f4SSimon Horman 176bb6d3fa9SWolfram Sang clk_set_rate(ref_clk, best_freq); 177bb6d3fa9SWolfram Sang 178bb6d3fa9SWolfram Sang if (priv->clkh) 179bb6d3fa9SWolfram Sang clk_set_rate(priv->clk, best_freq >> clkh_shift); 180b5b6a5f4SSimon Horman 18175eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 182b5b6a5f4SSimon Horman } 183b5b6a5f4SSimon Horman 1840196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1850196c8dbSMasahiro Yamada unsigned int new_clock) 1860196c8dbSMasahiro Yamada { 1870196c8dbSMasahiro Yamada u32 clk = 0, clock; 1880196c8dbSMasahiro Yamada 18968f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 19068f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 19168f83127SMasahiro Yamada 19275eaf49fSTamás Szűcs if (new_clock == 0) { 19375eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 19468f83127SMasahiro Yamada goto out; 19575eaf49fSTamás Szűcs } 19668f83127SMasahiro Yamada 19775eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 19875eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 1990196c8dbSMasahiro Yamada 2000196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 2010196c8dbSMasahiro Yamada clock <<= 1; 2020196c8dbSMasahiro Yamada 2030196c8dbSMasahiro Yamada /* 1/1 clock is option */ 2040196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 2050196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 2060196c8dbSMasahiro Yamada clk |= 0xff; 2070196c8dbSMasahiro Yamada else 2080196c8dbSMasahiro Yamada clk &= ~0xff; 2090196c8dbSMasahiro Yamada } 2100196c8dbSMasahiro Yamada 2110196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 2120196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 2130196c8dbSMasahiro Yamada usleep_range(10000, 11000); 2140196c8dbSMasahiro Yamada 21568f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 21668f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 21768f83127SMasahiro Yamada 21868f83127SMasahiro Yamada out: 21968f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 22068f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 22168f83127SMasahiro Yamada usleep_range(10000, 11000); 2220196c8dbSMasahiro Yamada } 2230196c8dbSMasahiro Yamada 224b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 225b5b6a5f4SSimon Horman { 226b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 227b5b6a5f4SSimon Horman 228b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 229b5b6a5f4SSimon Horman } 230b5b6a5f4SSimon Horman 231b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 232b5b6a5f4SSimon Horman { 233b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 234b5b6a5f4SSimon Horman 2352fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2362fe35968SSimon Horman TMIO_STAT_DAT0); 237b5b6a5f4SSimon Horman } 238b5b6a5f4SSimon Horman 239b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 240b5b6a5f4SSimon Horman struct mmc_ios *ios) 241b5b6a5f4SSimon Horman { 242b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 243b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 244b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 245b5b6a5f4SSimon Horman int ret; 246b5b6a5f4SSimon Horman 247b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 248b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 249b5b6a5f4SSimon Horman pin_state = priv->pins_default; 250b5b6a5f4SSimon Horman break; 251b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 252b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 253b5b6a5f4SSimon Horman break; 254b5b6a5f4SSimon Horman default: 255b5b6a5f4SSimon Horman return -EINVAL; 256b5b6a5f4SSimon Horman } 257b5b6a5f4SSimon Horman 258b5b6a5f4SSimon Horman /* 259b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 260b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 261b5b6a5f4SSimon Horman */ 262b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 263b5b6a5f4SSimon Horman return ios->signal_voltage == 264b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 265b5b6a5f4SSimon Horman 266b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 2679cbe0fc8SMarek Vasut if (ret < 0) 268b5b6a5f4SSimon Horman return ret; 269b5b6a5f4SSimon Horman 270b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 271b5b6a5f4SSimon Horman } 272b5b6a5f4SSimon Horman 273b5b6a5f4SSimon Horman /* SCC registers */ 274b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 275b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 276b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 277b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 278b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 279b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 28071cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 28126eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 282ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 283ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 284ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 285ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 286ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 287b5b6a5f4SSimon Horman 288b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 289b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 290b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 291b5b6a5f4SSimon Horman 292b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2936199a10eSWolfram Sang 294b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2956199a10eSWolfram Sang 29611a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2976199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 2986199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 2996199a10eSWolfram Sang 30071cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 3016199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 3026199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 3036199a10eSWolfram Sang 30426eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 30526eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 306b5b6a5f4SSimon Horman 307ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 308ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 309ce6f92c2SWolfram Sang 310ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 311ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 312ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 313ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 314ce6f92c2SWolfram Sang 315ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 316ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 317ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 318ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 319ce6f92c2SWolfram Sang 320b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 321b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 322b5b6a5f4SSimon Horman { 323b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 324b5b6a5f4SSimon Horman } 325b5b6a5f4SSimon Horman 326b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 327b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 328b5b6a5f4SSimon Horman int addr, u32 val) 329b5b6a5f4SSimon Horman { 330b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 331b5b6a5f4SSimon Horman } 332b5b6a5f4SSimon Horman 333b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 334b5b6a5f4SSimon Horman { 335b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 336b5b6a5f4SSimon Horman 337b5b6a5f4SSimon Horman priv = host_to_priv(host); 338b5b6a5f4SSimon Horman 339b5b6a5f4SSimon Horman /* Initialize SCC */ 340b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 341b5b6a5f4SSimon Horman 342b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 343b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 344b5b6a5f4SSimon Horman 34526eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 34626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 34726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 34826eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 34926eb2607SMasaharu Hayakawa 350b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 351b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 352b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 353b5b6a5f4SSimon Horman 354b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 355b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 356b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 357b5b6a5f4SSimon Horman 358852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 359b5b6a5f4SSimon Horman 36026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 36126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 36226eb2607SMasaharu Hayakawa 363b5b6a5f4SSimon Horman /* Read TAPNUM */ 364b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 365b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 366b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 367b5b6a5f4SSimon Horman } 368b5b6a5f4SSimon Horman 369f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 37026eb2607SMasaharu Hayakawa { 371f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 37226eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 373a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 374a38c078fSTakeshi Saito bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 37526eb2607SMasaharu Hayakawa 37626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 37726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 37826eb2607SMasaharu Hayakawa 37926eb2607SMasaharu Hayakawa /* Set HS400 mode */ 3800e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 38126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 382f0c8234cSTakeshi Saito 383f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 384f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 385f0c8234cSTakeshi Saito 3869b0d6855SWolfram Sang /* Gen3 can't do automatic tap correction with HS400, so disable it */ 3879b0d6855SWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 3889b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3899b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3909b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3919b0d6855SWolfram Sang 39226eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 39326eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 39426eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 39526eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 39626eb2607SMasaharu Hayakawa 39726eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 39826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 39903e59b1eSWolfram Sang sd_scc_read32(host, priv, 40003e59b1eSWolfram Sang SH_MOBILE_SDHI_SCC_DTCNTL)); 40126eb2607SMasaharu Hayakawa 402a38c078fSTakeshi Saito /* Avoid bad TAP */ 403a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) { 404a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 40526eb2607SMasaharu Hayakawa 406a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) 407a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num; 408a38c078fSTakeshi Saito 409a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) { 410a38c078fSTakeshi Saito new_tap = priv->tap_set; 411a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 412a38c078fSTakeshi Saito } 413a38c078fSTakeshi Saito 414a38c078fSTakeshi Saito priv->tap_set = new_tap; 415a38c078fSTakeshi Saito } 416a38c078fSTakeshi Saito 41726eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 418a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1)); 41926eb2607SMasaharu Hayakawa 42026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 42126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 42226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 42326eb2607SMasaharu Hayakawa 42426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 42526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 426ce6f92c2SWolfram Sang 427ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 428ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true; 42926eb2607SMasaharu Hayakawa } 43026eb2607SMasaharu Hayakawa 43180d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 43226eb2607SMasaharu Hayakawa { 43380d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 43480d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 43580d0be81SWolfram Sang 43626eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 43726eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 43826eb2607SMasaharu Hayakawa 43926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 44026eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 44126eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44226eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 44326eb2607SMasaharu Hayakawa 44426eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 44526eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 44626eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 44826eb2607SMasaharu Hayakawa 44926eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 45026eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 45126eb2607SMasaharu Hayakawa } 45226eb2607SMasaharu Hayakawa 453ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 454ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr) 455ce6f92c2SWolfram Sang { 456ce6f92c2SWolfram Sang /* read mode */ 457ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 458ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 459ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 460ce6f92c2SWolfram Sang 461ce6f92c2SWolfram Sang /* access start and stop */ 462ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 463ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 464ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 465ce6f92c2SWolfram Sang 466ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 467ce6f92c2SWolfram Sang } 468ce6f92c2SWolfram Sang 469ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 470ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val) 471ce6f92c2SWolfram Sang { 472ce6f92c2SWolfram Sang /* write mode */ 473ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 474ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 475ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 476ce6f92c2SWolfram Sang 477ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 478ce6f92c2SWolfram Sang 479ce6f92c2SWolfram Sang /* access start and stop */ 480ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 481ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 482ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 483ce6f92c2SWolfram Sang } 484ce6f92c2SWolfram Sang 485ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 486ce6f92c2SWolfram Sang { 487ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 488ce6f92c2SWolfram Sang u32 calib_code; 489ce6f92c2SWolfram Sang 490ce6f92c2SWolfram Sang /* disable write protect */ 491ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 492ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 493ce6f92c2SWolfram Sang /* read calibration code and adjust */ 494ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 495ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 496ce6f92c2SWolfram Sang 497ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 498ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 499ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]); 500ce6f92c2SWolfram Sang 501ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 502ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 503ce6f92c2SWolfram Sang 504ce6f92c2SWolfram Sang /* adjustment done, clear flag */ 505ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 506ce6f92c2SWolfram Sang } 507ce6f92c2SWolfram Sang 508ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 509ce6f92c2SWolfram Sang { 510ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 511ce6f92c2SWolfram Sang 512ce6f92c2SWolfram Sang /* disable write protect */ 513ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 514ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 515ce6f92c2SWolfram Sang /* disable manual calibration */ 516ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0); 517ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */ 518ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 519ce6f92c2SWolfram Sang } 520ce6f92c2SWolfram Sang 52126eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 52226eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 52326eb2607SMasaharu Hayakawa { 52426eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 52526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 52626eb2607SMasaharu Hayakawa 52726eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 5280e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 52926eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 530f0c8234cSTakeshi Saito 531f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 532f0c8234cSTakeshi Saito 53326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 53426eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 53526eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 53626eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 53726eb2607SMasaharu Hayakawa 538ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 539ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host); 540ce6f92c2SWolfram Sang 54126eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 54226eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 54326eb2607SMasaharu Hayakawa } 54426eb2607SMasaharu Hayakawa 545f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 54626eb2607SMasaharu Hayakawa { 547f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 548f22084b6SWolfram Sang 54926eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 550f22084b6SWolfram Sang return 0; 55126eb2607SMasaharu Hayakawa } 55226eb2607SMasaharu Hayakawa 5530e587014SWolfram Sang static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 5545b0739d7SWolfram Sang { 555183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc); 5565b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv); 557ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 5585b0739d7SWolfram Sang 5595b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 5605b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 5615b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 56245bffc37SWolfram Sang } 5635b0739d7SWolfram Sang 5640e587014SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */ 5650e587014SWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host) 5660e587014SWolfram Sang { 5670e587014SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 568b4d86f37SWolfram Sang int ret; 5690e587014SWolfram Sang u16 val; 5700e587014SWolfram Sang 571b4d86f37SWolfram Sang if (priv->rstc) { 572b4d86f37SWolfram Sang reset_control_reset(priv->rstc); 573b4d86f37SWolfram Sang /* Unknown why but without polling reset status, it will hang */ 574b4d86f37SWolfram Sang read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 575b4d86f37SWolfram Sang false, priv->rstc); 576b81bede4SWolfram Sang /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 577b81bede4SWolfram Sang sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 578b4d86f37SWolfram Sang priv->needs_adjust_hs400 = false; 579b4d86f37SWolfram Sang renesas_sdhi_set_clock(host, host->clk_cache); 580b4d86f37SWolfram Sang } else if (priv->scc_ctl) { 5810e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 582b4d86f37SWolfram Sang } 5830e587014SWolfram Sang 584b191deceSWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 585b191deceSWolfram Sang val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 586b191deceSWolfram Sang val |= CARD_OPT_EXTOP; 587b191deceSWolfram Sang sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 588b191deceSWolfram Sang } 589b191deceSWolfram Sang } 590b191deceSWolfram Sang 591b191deceSWolfram Sang static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 592b191deceSWolfram Sang { 593b191deceSWolfram Sang u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 594b191deceSWolfram Sang 595b191deceSWolfram Sang num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 596b191deceSWolfram Sang return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 597b191deceSWolfram Sang 5985b0739d7SWolfram Sang } 5995b0739d7SWolfram Sang 600ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 601b5b6a5f4SSimon Horman 602b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 603b5b6a5f4SSimon Horman { 604b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 60592fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 6065fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row; 6075fb6bf51SWolfram Sang unsigned long *bitmap; 608b5b6a5f4SSimon Horman 609b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 610b5b6a5f4SSimon Horman 611b5b6a5f4SSimon Horman /* 6125c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 6135c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 6145c99826bSNiklas Söderlund * considering it for tuning selection. 6155c99826bSNiklas Söderlund */ 61692fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) { 617b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 6185c99826bSNiklas Söderlund 619b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps)) 620b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps); 6215fb6bf51SWolfram Sang 6225fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp)) 6235fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp); 6245fb6bf51SWolfram Sang } 6255fb6bf51SWolfram Sang 6265fb6bf51SWolfram Sang /* 6275fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by 6285fb6bf51SWolfram Sang * identifying the change point of data. 6295fb6bf51SWolfram Sang */ 6305fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) { 6315fb6bf51SWolfram Sang bitmap = priv->smpcmp; 6325fb6bf51SWolfram Sang min_tap_row = 1; 6335fb6bf51SWolfram Sang } else { 6345fb6bf51SWolfram Sang bitmap = priv->taps; 6355fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 6365c99826bSNiklas Söderlund } 6375c99826bSNiklas Söderlund 6385c99826bSNiklas Söderlund /* 639b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 640ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 641ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out. 642b5b6a5f4SSimon Horman */ 643ec288a2cSYury Norov for_each_set_bitrange(rs, re, bitmap, taps_size) { 64492fa2a56SWolfram Sang if (re - rs > tap_cnt) { 64592fa2a56SWolfram Sang tap_end = re; 64692fa2a56SWolfram Sang tap_start = rs; 64792fa2a56SWolfram Sang tap_cnt = tap_end - tap_start; 648b5b6a5f4SSimon Horman } 649b5b6a5f4SSimon Horman } 650b5b6a5f4SSimon Horman 6515fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row) 652b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 653b5b6a5f4SSimon Horman else 654b5b6a5f4SSimon Horman return -EIO; 655b5b6a5f4SSimon Horman 656b5b6a5f4SSimon Horman /* Set SCC */ 657b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 658b5b6a5f4SSimon Horman 659b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 660b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 661b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 662b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 663b5b6a5f4SSimon Horman 664b5b6a5f4SSimon Horman return 0; 665b5b6a5f4SSimon Horman } 666b5b6a5f4SSimon Horman 667510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 6680c482d82SWolfram Sang { 669510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 6700c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 6715b0739d7SWolfram Sang int i, ret; 6720c482d82SWolfram Sang 673b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host); 674b2dd9a13SWolfram Sang if (!priv->tap_num) 6750c482d82SWolfram Sang return 0; /* Tuning is not supported */ 6760c482d82SWolfram Sang 677b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 6783a821a82SWolfram Sang dev_err(&host->pdev->dev, 6793a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 6803a821a82SWolfram Sang return -EINVAL; 6810c482d82SWolfram Sang } 6820c482d82SWolfram Sang 683b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2); 6845fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2); 6850c482d82SWolfram Sang 6860c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 687b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) { 6887dba4028SWolfram Sang int cmd_error = 0; 6892c9017d0SWolfram Sang 6900c482d82SWolfram Sang /* Set sampling clock position */ 691b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 6920c482d82SWolfram Sang 6932c9017d0SWolfram Sang if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 694b2dd9a13SWolfram Sang set_bit(i, priv->taps); 6955fb6bf51SWolfram Sang 6965fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 6975fb6bf51SWolfram Sang set_bit(i, priv->smpcmp); 6982c9017d0SWolfram Sang 6992c9017d0SWolfram Sang if (cmd_error) 70021adc2e4SWolfram Sang mmc_send_abort_tuning(mmc, opcode); 7010c482d82SWolfram Sang } 7020c482d82SWolfram Sang 7035b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host); 7045b0739d7SWolfram Sang if (ret < 0) 7050e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 7065b0739d7SWolfram Sang return ret; 7070c482d82SWolfram Sang } 7080c482d82SWolfram Sang 70911a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 71011a21960STakeshi Saito { 71111a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 712a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 71311a21960STakeshi Saito u32 val; 71411a21960STakeshi Saito 71511a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 71611a21960STakeshi Saito if (!val) 71711a21960STakeshi Saito return false; 71811a21960STakeshi Saito 71911a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 72011a21960STakeshi Saito 72111a21960STakeshi Saito /* Change TAP position according to correction status */ 72271cfc927STakeshi Saito if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 72371cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 724a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 72571cfc927STakeshi Saito /* 72671cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 72771cfc927STakeshi Saito * Therefore, use only CMD status. 72871cfc927STakeshi Saito */ 72971cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 73071cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 731a38c078fSTakeshi Saito if (!smpcmp) { 73271cfc927STakeshi Saito return false; /* no error in CMD signal */ 733a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 73471cfc927STakeshi Saito new_tap++; 735a38c078fSTakeshi Saito error_tap--; 736a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 73771cfc927STakeshi Saito new_tap--; 738a38c078fSTakeshi Saito error_tap++; 739a38c078fSTakeshi Saito } else { 74071cfc927STakeshi Saito return true; /* need retune */ 741a38c078fSTakeshi Saito } 742a38c078fSTakeshi Saito 743a38c078fSTakeshi Saito /* 744a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare 745a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK, 746a38c078fSTakeshi Saito * we can at least retune. 747a38c078fSTakeshi Saito */ 748a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num)) 749a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp); 75071cfc927STakeshi Saito } else { 75111a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 75271cfc927STakeshi Saito return true; /* need retune */ 75311a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 75471cfc927STakeshi Saito new_tap++; 75511a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 75671cfc927STakeshi Saito new_tap--; 75711a21960STakeshi Saito else 75811a21960STakeshi Saito return false; 75971cfc927STakeshi Saito } 76011a21960STakeshi Saito 761b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num); 76211a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 763b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1)); 76411a21960STakeshi Saito 76511a21960STakeshi Saito return false; 76611a21960STakeshi Saito } 76711a21960STakeshi Saito 76811a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 76911a21960STakeshi Saito { 77011a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 77111a21960STakeshi Saito 77211a21960STakeshi Saito /* Check SCC error */ 77311a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 77411a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 77511a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 77611a21960STakeshi Saito return true; 77711a21960STakeshi Saito } 77811a21960STakeshi Saito 77911a21960STakeshi Saito return false; 78011a21960STakeshi Saito } 78111a21960STakeshi Saito 782ed2fab9aSYoshihiro Shimoda static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 783ed2fab9aSYoshihiro Shimoda struct mmc_request *mrq) 784b5b6a5f4SSimon Horman { 785b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 78612e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 787ed2fab9aSYoshihiro Shimoda bool ret = false; 78875f349a1SMasaharu Hayakawa 78975f349a1SMasaharu Hayakawa /* 79075f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 79175f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 79275f349a1SMasaharu Hayakawa */ 79375f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 79475f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 79575f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 79675f349a1SMasaharu Hayakawa return false; 79775f349a1SMasaharu Hayakawa 798fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc)) 79975f349a1SMasaharu Hayakawa return false; 800b5b6a5f4SSimon Horman 801ed2fab9aSYoshihiro Shimoda if (((mrq->cmd->error == -ETIMEDOUT) || 802ed2fab9aSYoshihiro Shimoda (mrq->data && mrq->data->error == -ETIMEDOUT)) && 803ed2fab9aSYoshihiro Shimoda ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 804ed2fab9aSYoshihiro Shimoda (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 805ed2fab9aSYoshihiro Shimoda ret |= true; 806ed2fab9aSYoshihiro Shimoda 807b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 80811a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 809ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_auto_correction(host); 810ed2fab9aSYoshihiro Shimoda else 811ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_manual_correction(host, use_4tap); 812b5b6a5f4SSimon Horman 813ed2fab9aSYoshihiro Shimoda return ret; 814b5b6a5f4SSimon Horman } 815b5b6a5f4SSimon Horman 8164dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 817b5b6a5f4SSimon Horman { 818b5b6a5f4SSimon Horman int timeout = 1000; 8194dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 8204dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 821b5b6a5f4SSimon Horman 8224dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 8234dc48a95SWolfram Sang & bit) == wait_state) 824b5b6a5f4SSimon Horman udelay(1); 825b5b6a5f4SSimon Horman 826b5b6a5f4SSimon Horman if (!timeout) { 827b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 828b5b6a5f4SSimon Horman return -EBUSY; 829b5b6a5f4SSimon Horman } 830b5b6a5f4SSimon Horman 831b5b6a5f4SSimon Horman return 0; 832b5b6a5f4SSimon Horman } 833b5b6a5f4SSimon Horman 834b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 835b5b6a5f4SSimon Horman { 8364dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 8374dc48a95SWolfram Sang 8382fe35968SSimon Horman switch (addr) { 839b5b6a5f4SSimon Horman case CTL_SD_CMD: 840b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 841b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 842b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 843b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 844b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 845b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 8464533c3ebSWolfram Sang case CTL_HOST_MODE: 8475124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 8484dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 849df561f66SGustavo A. R. Silva fallthrough; 8504dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 8514dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 852b5b6a5f4SSimon Horman } 853b5b6a5f4SSimon Horman 854b5b6a5f4SSimon Horman return 0; 855b5b6a5f4SSimon Horman } 856b5b6a5f4SSimon Horman 857b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 858b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 859b5b6a5f4SSimon Horman { 860b5b6a5f4SSimon Horman /* 861b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 862b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 863b5b6a5f4SSimon Horman * depending on the timing with which the 864b5b6a5f4SSimon Horman * response register is read, the response 865b5b6a5f4SSimon Horman * value may not be read properly. 866b5b6a5f4SSimon Horman * Use single block read for this HW bug 867b5b6a5f4SSimon Horman */ 868b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 869b5b6a5f4SSimon Horman blk_size == 2) 870b5b6a5f4SSimon Horman return 1; 871b5b6a5f4SSimon Horman 872b5b6a5f4SSimon Horman return blk_size; 873b5b6a5f4SSimon Horman } 874b5b6a5f4SSimon Horman 875ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 876ce6f92c2SWolfram Sang { 877ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 878ce6f92c2SWolfram Sang 879ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 880ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host); 881ce6f92c2SWolfram Sang } 882b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 883b5b6a5f4SSimon Horman { 88441279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 88541279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 886b5b6a5f4SSimon Horman 88741279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 88841279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 889b5b6a5f4SSimon Horman } 890b5b6a5f4SSimon Horman 8919d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 89271b7597cSYoshihiro Shimoda const struct tmio_mmc_dma_ops *dma_ops, 89371b7597cSYoshihiro Shimoda const struct renesas_sdhi_of_data *of_data, 89471b7597cSYoshihiro Shimoda const struct renesas_sdhi_quirks *quirks) 895b5b6a5f4SSimon Horman { 896b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 8972fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 8982fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 899b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 9002fe35968SSimon Horman struct renesas_sdhi *priv; 901e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 902b5b6a5f4SSimon Horman struct resource *res; 903c9a9497cSWolfram Sang u16 ver; 9042fe35968SSimon Horman 905b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 906b5b6a5f4SSimon Horman if (!res) 907b5b6a5f4SSimon Horman return -EINVAL; 908b5b6a5f4SSimon Horman 9092fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 9102fe35968SSimon Horman GFP_KERNEL); 911b5b6a5f4SSimon Horman if (!priv) 912b5b6a5f4SSimon Horman return -ENOMEM; 913b5b6a5f4SSimon Horman 9147af08206SWolfram Sang priv->quirks = quirks; 915b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 916b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 917b5b6a5f4SSimon Horman 918b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 919079e83b9SWolfram Sang if (IS_ERR(priv->clk)) 920079e83b9SWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 921b5b6a5f4SSimon Horman 922e5f7e81eSWolfram Sang priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 923e5f7e81eSWolfram Sang if (IS_ERR(priv->clkh)) 924e5f7e81eSWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 925b5b6a5f4SSimon Horman 926b5b6a5f4SSimon Horman /* 927b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 928b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 929b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 930b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 931b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 932b5b6a5f4SSimon Horman * disable it. 933b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 934b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 935b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 936b5b6a5f4SSimon Horman */ 937366df82fSGeert Uytterhoeven priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 938b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 939366df82fSGeert Uytterhoeven return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 940b5b6a5f4SSimon Horman 941*0dac1e49SLad Prabhakar priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 942*0dac1e49SLad Prabhakar if (IS_ERR(priv->rstc)) 943*0dac1e49SLad Prabhakar return PTR_ERR(priv->rstc); 944*0dac1e49SLad Prabhakar 945b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 946b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 947b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 948b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 949b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 950b5b6a5f4SSimon Horman "state_uhs"); 951b5b6a5f4SSimon Horman } 952b5b6a5f4SSimon Horman 953b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 9548d09a133SMasahiro Yamada if (IS_ERR(host)) 9558d09a133SMasahiro Yamada return PTR_ERR(host); 956b5b6a5f4SSimon Horman 957b5b6a5f4SSimon Horman if (of_data) { 958b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 959b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 960b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 961b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 962b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 963603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 964603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 965b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 966b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 967bb6d3fa9SWolfram Sang /* Fallback for old DTs */ 968e5f7e81eSWolfram Sang if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 969bb6d3fa9SWolfram Sang priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 970bb6d3fa9SWolfram Sang 971b5b6a5f4SSimon Horman } 972b5b6a5f4SSimon Horman 973b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 974b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 975b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 9760196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 977b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 978bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 979b5b6a5f4SSimon Horman 9800f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 9810f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 9820f4e2054SNiklas Söderlund 983ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 984ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 985ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 986ef5332c1SWolfram Sang 987b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 988b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 989b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 9902aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 9912aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 992b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 9931970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 9949f12cac1SWolfram Sang host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 9956e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset; 996d30ae056STakeshi Saito } 997b5b6a5f4SSimon Horman 998b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 999b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1000b5b6a5f4SSimon Horman host->bus_shift = 1; 1001b5b6a5f4SSimon Horman 1002b5b6a5f4SSimon Horman if (mmd) 1003b5b6a5f4SSimon Horman *mmc_data = *mmd; 1004b5b6a5f4SSimon Horman 1005b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 1006b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 1007b5b6a5f4SSimon Horman 1008b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1009b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1010b5b6a5f4SSimon Horman 1011b5b6a5f4SSimon Horman /* 1012b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1013b5b6a5f4SSimon Horman * bus width mode. 1014b5b6a5f4SSimon Horman */ 1015b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1016b5b6a5f4SSimon Horman 1017b5b6a5f4SSimon Horman /* 1018b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 1019b5b6a5f4SSimon Horman */ 1020b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1021b5b6a5f4SSimon Horman 10222fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 1023b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1024b5b6a5f4SSimon Horman 1025b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 1026b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1027b5b6a5f4SSimon Horman 102830ae3e13SWolfram Sang /* All SDHI support HW busy detection */ 102930ae3e13SWolfram Sang mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 103030ae3e13SWolfram Sang 103163fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev); 103263fd8ef3SUlf Hansson 1033b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 1034b21fc294SMasahiro Yamada if (ret) 1035b5b6a5f4SSimon Horman goto efree; 1036b5b6a5f4SSimon Horman 1037c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 1038c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1039c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1040c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 1041c9a9497cSWolfram Sang 10425124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1043c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 10445124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 10455124b592SWolfram Sang 1046ce6f92c2SWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1047ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request; 1048ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *( 1049ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ? 1050ce6f92c2SWolfram Sang quirks->hs400_calib_table : 1051ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1); 1052ce6f92c2SWolfram Sang } 1053ce6f92c2SWolfram Sang 1054b191deceSWolfram Sang /* these have an EXTOP bit */ 1055b191deceSWolfram Sang if (ver >= SDHI_VER_GEN3_SD) 1056b191deceSWolfram Sang host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1057b191deceSWolfram Sang 1058b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 1059b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 1060b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 106126eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 106226eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 1063b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 106445177fc6SWolfram Sang bool use_4tap = quirks && quirks->hs400_4taps; 1065b5b6a5f4SSimon Horman bool hit = false; 1066b5b6a5f4SSimon Horman 1067b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 1068b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 1069b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 1070852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 1071c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 1072c1a49782SWolfram Sang taps->tap_hs400_4tap : 1073c1a49782SWolfram Sang taps->tap; 1074b5b6a5f4SSimon Horman hit = true; 1075b5b6a5f4SSimon Horman break; 1076b5b6a5f4SSimon Horman } 1077b5b6a5f4SSimon Horman } 1078b5b6a5f4SSimon Horman 1079b5b6a5f4SSimon Horman if (!hit) 1080e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1081b5b6a5f4SSimon Horman 1082d14ac691SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset; 108364982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error; 1084510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1085f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1086f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1087f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1088b5b6a5f4SSimon Horman } 1089b5b6a5f4SSimon Horman 1090b161d87dSWolfram Sang ret = tmio_mmc_host_probe(host); 1091b161d87dSWolfram Sang if (ret < 0) 1092b161d87dSWolfram Sang goto edisclk; 1093b161d87dSWolfram Sang 1094e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 1095e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 1096e8307ec5SGeert Uytterhoeven ret = num_irqs; 1097b5b6a5f4SSimon Horman goto eirq; 1098b5b6a5f4SSimon Horman } 1099b5b6a5f4SSimon Horman 1100b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 1101e8307ec5SGeert Uytterhoeven if (!num_irqs) { 1102e8307ec5SGeert Uytterhoeven ret = -ENXIO; 1103e8307ec5SGeert Uytterhoeven goto eirq; 1104e8307ec5SGeert Uytterhoeven } 1105e8307ec5SGeert Uytterhoeven 1106e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 1107e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 1108e8307ec5SGeert Uytterhoeven if (irq < 0) { 1109b5b6a5f4SSimon Horman ret = irq; 1110b5b6a5f4SSimon Horman goto eirq; 1111b5b6a5f4SSimon Horman } 1112b5b6a5f4SSimon Horman 1113e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1114e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 1115e8307ec5SGeert Uytterhoeven if (ret) 1116e8307ec5SGeert Uytterhoeven goto eirq; 1117e8307ec5SGeert Uytterhoeven } 1118e8307ec5SGeert Uytterhoeven 1119bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1120bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1121b5b6a5f4SSimon Horman 1122b5b6a5f4SSimon Horman return ret; 1123b5b6a5f4SSimon Horman 1124b5b6a5f4SSimon Horman eirq: 1125b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1126b21fc294SMasahiro Yamada edisclk: 1127b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1128b5b6a5f4SSimon Horman efree: 1129b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 11304ce62817SMasahiro Yamada 1131b5b6a5f4SSimon Horman return ret; 1132b5b6a5f4SSimon Horman } 11339d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1134b5b6a5f4SSimon Horman 11359d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 1136b5b6a5f4SSimon Horman { 1137a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1138b5b6a5f4SSimon Horman 1139b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1140b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1141e8973201SYoshihiro Shimoda tmio_mmc_host_free(host); 1142b5b6a5f4SSimon Horman 1143b5b6a5f4SSimon Horman return 0; 1144b5b6a5f4SSimon Horman } 11459d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1146967a6a07SMasaharu Hayakawa 1147967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 1148