1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2b5b6a5f4SSimon Horman /* 39d08428aSSimon Horman * Renesas SDHI 4b5b6a5f4SSimon Horman * 5f49bdcdeSWolfram Sang * Copyright (C) 2015-19 Renesas Electronics Corporation 6f49bdcdeSWolfram Sang * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 787317c4dSSimon Horman * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8b5b6a5f4SSimon Horman * Copyright (C) 2009 Magnus Damm 9b5b6a5f4SSimon Horman * 10b5b6a5f4SSimon Horman * Based on "Compaq ASIC3 support": 11b5b6a5f4SSimon Horman * 12b5b6a5f4SSimon Horman * Copyright 2001 Compaq Computer Corporation. 13b5b6a5f4SSimon Horman * Copyright 2004-2005 Phil Blundell 14b5b6a5f4SSimon Horman * Copyright 2007-2008 OpenedHand Ltd. 15b5b6a5f4SSimon Horman * 16b5b6a5f4SSimon Horman * Authors: Phil Blundell <pb@handhelds.org>, 17b5b6a5f4SSimon Horman * Samuel Ortiz <sameo@openedhand.com> 18b5b6a5f4SSimon Horman * 19b5b6a5f4SSimon Horman */ 20b5b6a5f4SSimon Horman 21b5b6a5f4SSimon Horman #include <linux/clk.h> 22ab07a135SWolfram Sang #include <linux/delay.h> 23b4d86f37SWolfram Sang #include <linux/iopoll.h> 24ab07a135SWolfram Sang #include <linux/kernel.h> 25ab07a135SWolfram Sang #include <linux/mfd/tmio.h> 26b5b6a5f4SSimon Horman #include <linux/mmc/host.h> 27ce6f92c2SWolfram Sang #include <linux/mmc/mmc.h> 28ef5332c1SWolfram Sang #include <linux/mmc/slot-gpio.h> 29ab07a135SWolfram Sang #include <linux/module.h> 30b5b6a5f4SSimon Horman #include <linux/pinctrl/consumer.h> 31b5b6a5f4SSimon Horman #include <linux/pinctrl/pinctrl-state.h> 32ab07a135SWolfram Sang #include <linux/platform_device.h> 33ab07a135SWolfram Sang #include <linux/pm_domain.h> 34b5b6a5f4SSimon Horman #include <linux/regulator/consumer.h> 35b4d86f37SWolfram Sang #include <linux/reset.h> 36ab07a135SWolfram Sang #include <linux/sh_dma.h> 37ab07a135SWolfram Sang #include <linux/slab.h> 38b5b6a5f4SSimon Horman 39b5b6a5f4SSimon Horman #include "renesas_sdhi.h" 40b5b6a5f4SSimon Horman #include "tmio_mmc.h" 41b5b6a5f4SSimon Horman 424533c3ebSWolfram Sang #define CTL_HOST_MODE 0xe4 434533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 444533c3ebSWolfram Sang #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 454533c3ebSWolfram Sang #define HOST_MODE_GEN3_WMODE BIT(0) 464533c3ebSWolfram Sang #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 474533c3ebSWolfram Sang 484533c3ebSWolfram Sang #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 494533c3ebSWolfram Sang #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 504533c3ebSWolfram Sang #define HOST_MODE_GEN3_64BIT 0 51b5b6a5f4SSimon Horman 52b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR50 0x490c 53c7825151SWolfram Sang #define SDHI_VER_RZ_A1 0x820b 54b5b6a5f4SSimon Horman /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 55b5b6a5f4SSimon Horman #define SDHI_VER_GEN2_SDR104 0xcb0d 56b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SD 0xcc10 57b5b6a5f4SSimon Horman #define SDHI_VER_GEN3_SDMMC 0xcd10 58b5b6a5f4SSimon Horman 59ce6f92c2SWolfram Sang #define SDHI_GEN3_MMC0_ADDR 0xee140000 60ce6f92c2SWolfram Sang 61b5b6a5f4SSimon Horman static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 62b5b6a5f4SSimon Horman { 63b5b6a5f4SSimon Horman u32 val; 64b5b6a5f4SSimon Horman 65b5b6a5f4SSimon Horman /* 66b5b6a5f4SSimon Horman * see also 67b5b6a5f4SSimon Horman * renesas_sdhi_of_data :: dma_buswidth 68b5b6a5f4SSimon Horman */ 69b5b6a5f4SSimon Horman switch (sd_ctrl_read16(host, CTL_VERSION)) { 70b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR50: 714533c3ebSWolfram Sang val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 72b5b6a5f4SSimon Horman break; 73b5b6a5f4SSimon Horman case SDHI_VER_GEN2_SDR104: 744533c3ebSWolfram Sang val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 75b5b6a5f4SSimon Horman break; 76b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SD: 77b5b6a5f4SSimon Horman case SDHI_VER_GEN3_SDMMC: 78b5b6a5f4SSimon Horman if (width == 64) 794533c3ebSWolfram Sang val = HOST_MODE_GEN3_64BIT; 80b5b6a5f4SSimon Horman else if (width == 32) 814533c3ebSWolfram Sang val = HOST_MODE_GEN3_32BIT; 82b5b6a5f4SSimon Horman else 834533c3ebSWolfram Sang val = HOST_MODE_GEN3_16BIT; 84b5b6a5f4SSimon Horman break; 85b5b6a5f4SSimon Horman default: 86b5b6a5f4SSimon Horman /* nothing to do */ 87b5b6a5f4SSimon Horman return; 88b5b6a5f4SSimon Horman } 89b5b6a5f4SSimon Horman 904533c3ebSWolfram Sang sd_ctrl_write16(host, CTL_HOST_MODE, val); 91b5b6a5f4SSimon Horman } 92b5b6a5f4SSimon Horman 93b5b6a5f4SSimon Horman static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 94b5b6a5f4SSimon Horman { 95b5b6a5f4SSimon Horman struct mmc_host *mmc = host->mmc; 96b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 97d42c9fffSWolfram Sang int ret; 98b5b6a5f4SSimon Horman 99b5b6a5f4SSimon Horman ret = clk_prepare_enable(priv->clk_cd); 100d42c9fffSWolfram Sang if (ret < 0) 101b5b6a5f4SSimon Horman return ret; 102b5b6a5f4SSimon Horman 103b5b6a5f4SSimon Horman /* 104b5b6a5f4SSimon Horman * The clock driver may not know what maximum frequency 105b5b6a5f4SSimon Horman * actually works, so it should be set with the max-frequency 106b5b6a5f4SSimon Horman * property which will already have been read to f_max. If it 107b5b6a5f4SSimon Horman * was missing, assume the current frequency is the maximum. 108b5b6a5f4SSimon Horman */ 109b5b6a5f4SSimon Horman if (!mmc->f_max) 110b5b6a5f4SSimon Horman mmc->f_max = clk_get_rate(priv->clk); 111b5b6a5f4SSimon Horman 112b5b6a5f4SSimon Horman /* 113b5b6a5f4SSimon Horman * Minimum frequency is the minimum input clock frequency 114b5b6a5f4SSimon Horman * divided by our maximum divider. 115b5b6a5f4SSimon Horman */ 116b5b6a5f4SSimon Horman mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 117b5b6a5f4SSimon Horman 118b5b6a5f4SSimon Horman /* enable 16bit data access on SDBUF as default */ 119b5b6a5f4SSimon Horman renesas_sdhi_sdbuf_width(host, 16); 120b5b6a5f4SSimon Horman 121b5b6a5f4SSimon Horman return 0; 122b5b6a5f4SSimon Horman } 123b5b6a5f4SSimon Horman 124b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 125bb6d3fa9SWolfram Sang unsigned int wanted_clock) 126b5b6a5f4SSimon Horman { 127b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 128bb6d3fa9SWolfram Sang struct clk *ref_clk = priv->clk; 129b5b6a5f4SSimon Horman unsigned int freq, diff, best_freq = 0, diff_min = ~0; 130bb6d3fa9SWolfram Sang unsigned int new_clock, clkh_shift = 0; 13175eaf49fSTamás Szűcs int i; 132b5b6a5f4SSimon Horman 1330f93db65SWolfram Sang /* 1340f93db65SWolfram Sang * We simply return the current rate if a) we are not on a R-Car Gen2+ 1350f93db65SWolfram Sang * SoC (may work for others, but untested) or b) if the SCC needs its 1360f93db65SWolfram Sang * clock during tuning, so we don't change the external clock setup. 1370f93db65SWolfram Sang */ 1380f93db65SWolfram Sang if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 139b5b6a5f4SSimon Horman return clk_get_rate(priv->clk); 140b5b6a5f4SSimon Horman 141bb6d3fa9SWolfram Sang if (priv->clkh) { 14246d4820fSWolfram Sang /* HS400 with 4TAP needs different clock settings */ 143bb6d3fa9SWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 14446d4820fSWolfram Sang bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 145bb6d3fa9SWolfram Sang clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 146bb6d3fa9SWolfram Sang ref_clk = priv->clkh; 147bb6d3fa9SWolfram Sang } 148bb6d3fa9SWolfram Sang 149bb6d3fa9SWolfram Sang new_clock = wanted_clock << clkh_shift; 150bb6d3fa9SWolfram Sang 151b5b6a5f4SSimon Horman /* 152b5b6a5f4SSimon Horman * We want the bus clock to be as close as possible to, but no 153b5b6a5f4SSimon Horman * greater than, new_clock. As we can divide by 1 << i for 154b5b6a5f4SSimon Horman * any i in [0, 9] we want the input clock to be as close as 155b5b6a5f4SSimon Horman * possible, but no greater than, new_clock << i. 156b5b6a5f4SSimon Horman */ 157b5b6a5f4SSimon Horman for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 158bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, new_clock << i); 159b5b6a5f4SSimon Horman if (freq > (new_clock << i)) { 160b5b6a5f4SSimon Horman /* Too fast; look for a slightly slower option */ 161bb6d3fa9SWolfram Sang freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 162b5b6a5f4SSimon Horman if (freq > (new_clock << i)) 163b5b6a5f4SSimon Horman continue; 164b5b6a5f4SSimon Horman } 165b5b6a5f4SSimon Horman 166b5b6a5f4SSimon Horman diff = new_clock - (freq >> i); 167b5b6a5f4SSimon Horman if (diff <= diff_min) { 168b5b6a5f4SSimon Horman best_freq = freq; 169b5b6a5f4SSimon Horman diff_min = diff; 170b5b6a5f4SSimon Horman } 171b5b6a5f4SSimon Horman } 172b5b6a5f4SSimon Horman 173bb6d3fa9SWolfram Sang clk_set_rate(ref_clk, best_freq); 174bb6d3fa9SWolfram Sang 175bb6d3fa9SWolfram Sang if (priv->clkh) 176bb6d3fa9SWolfram Sang clk_set_rate(priv->clk, best_freq >> clkh_shift); 177b5b6a5f4SSimon Horman 17875eaf49fSTamás Szűcs return clk_get_rate(priv->clk); 179b5b6a5f4SSimon Horman } 180b5b6a5f4SSimon Horman 1810196c8dbSMasahiro Yamada static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 1820196c8dbSMasahiro Yamada unsigned int new_clock) 1830196c8dbSMasahiro Yamada { 1840196c8dbSMasahiro Yamada u32 clk = 0, clock; 1850196c8dbSMasahiro Yamada 18668f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 18768f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 18868f83127SMasahiro Yamada 18975eaf49fSTamás Szűcs if (new_clock == 0) { 19075eaf49fSTamás Szűcs host->mmc->actual_clock = 0; 19168f83127SMasahiro Yamada goto out; 19275eaf49fSTamás Szűcs } 19368f83127SMasahiro Yamada 19475eaf49fSTamás Szűcs host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 19575eaf49fSTamás Szűcs clock = host->mmc->actual_clock / 512; 1960196c8dbSMasahiro Yamada 1970196c8dbSMasahiro Yamada for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 1980196c8dbSMasahiro Yamada clock <<= 1; 1990196c8dbSMasahiro Yamada 2000196c8dbSMasahiro Yamada /* 1/1 clock is option */ 2010196c8dbSMasahiro Yamada if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 2020196c8dbSMasahiro Yamada if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 2030196c8dbSMasahiro Yamada clk |= 0xff; 2040196c8dbSMasahiro Yamada else 2050196c8dbSMasahiro Yamada clk &= ~0xff; 2060196c8dbSMasahiro Yamada } 2070196c8dbSMasahiro Yamada 2080196c8dbSMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 2090196c8dbSMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 2100196c8dbSMasahiro Yamada usleep_range(10000, 11000); 2110196c8dbSMasahiro Yamada 21268f83127SMasahiro Yamada sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 21368f83127SMasahiro Yamada sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 21468f83127SMasahiro Yamada 21568f83127SMasahiro Yamada out: 21668f83127SMasahiro Yamada /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 21768f83127SMasahiro Yamada if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 21868f83127SMasahiro Yamada usleep_range(10000, 11000); 2190196c8dbSMasahiro Yamada } 2200196c8dbSMasahiro Yamada 221b5b6a5f4SSimon Horman static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 222b5b6a5f4SSimon Horman { 223b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 224b5b6a5f4SSimon Horman 225b5b6a5f4SSimon Horman clk_disable_unprepare(priv->clk_cd); 226b5b6a5f4SSimon Horman } 227b5b6a5f4SSimon Horman 228b5b6a5f4SSimon Horman static int renesas_sdhi_card_busy(struct mmc_host *mmc) 229b5b6a5f4SSimon Horman { 230b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 231b5b6a5f4SSimon Horman 2322fe35968SSimon Horman return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 2332fe35968SSimon Horman TMIO_STAT_DAT0); 234b5b6a5f4SSimon Horman } 235b5b6a5f4SSimon Horman 236b5b6a5f4SSimon Horman static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 237b5b6a5f4SSimon Horman struct mmc_ios *ios) 238b5b6a5f4SSimon Horman { 239b5b6a5f4SSimon Horman struct tmio_mmc_host *host = mmc_priv(mmc); 240b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 241b5b6a5f4SSimon Horman struct pinctrl_state *pin_state; 242b5b6a5f4SSimon Horman int ret; 243b5b6a5f4SSimon Horman 244b5b6a5f4SSimon Horman switch (ios->signal_voltage) { 245b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_330: 246b5b6a5f4SSimon Horman pin_state = priv->pins_default; 247b5b6a5f4SSimon Horman break; 248b5b6a5f4SSimon Horman case MMC_SIGNAL_VOLTAGE_180: 249b5b6a5f4SSimon Horman pin_state = priv->pins_uhs; 250b5b6a5f4SSimon Horman break; 251b5b6a5f4SSimon Horman default: 252b5b6a5f4SSimon Horman return -EINVAL; 253b5b6a5f4SSimon Horman } 254b5b6a5f4SSimon Horman 255b5b6a5f4SSimon Horman /* 256b5b6a5f4SSimon Horman * If anything is missing, assume signal voltage is fixed at 257b5b6a5f4SSimon Horman * 3.3V and succeed/fail accordingly. 258b5b6a5f4SSimon Horman */ 259b5b6a5f4SSimon Horman if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 260b5b6a5f4SSimon Horman return ios->signal_voltage == 261b5b6a5f4SSimon Horman MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 262b5b6a5f4SSimon Horman 263b5b6a5f4SSimon Horman ret = mmc_regulator_set_vqmmc(host->mmc, ios); 2649cbe0fc8SMarek Vasut if (ret < 0) 265b5b6a5f4SSimon Horman return ret; 266b5b6a5f4SSimon Horman 267b5b6a5f4SSimon Horman return pinctrl_select_state(priv->pinctrl, pin_state); 268b5b6a5f4SSimon Horman } 269b5b6a5f4SSimon Horman 270b5b6a5f4SSimon Horman /* SCC registers */ 271b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 272b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 273b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 274b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 275b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 276b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 27771cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 27826eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 279ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 280ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 281ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 282ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 283ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 284b5b6a5f4SSimon Horman 285b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 286b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 287b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 288b5b6a5f4SSimon Horman 289b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 2906199a10eSWolfram Sang 291b5b6a5f4SSimon Horman #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 2926199a10eSWolfram Sang 29311a21960STakeshi Saito #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 2946199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 2956199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 2966199a10eSWolfram Sang 29771cfc927STakeshi Saito #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 2986199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 2996199a10eSWolfram Sang #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 3006199a10eSWolfram Sang 30126eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 30226eb2607SMasaharu Hayakawa #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 303b5b6a5f4SSimon Horman 304ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 305ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 306ce6f92c2SWolfram Sang 307ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 308ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 309ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 310ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 311ce6f92c2SWolfram Sang 312ce6f92c2SWolfram Sang /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 313ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 314ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 315ce6f92c2SWolfram Sang #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 316ce6f92c2SWolfram Sang 317b5b6a5f4SSimon Horman static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 318b5b6a5f4SSimon Horman struct renesas_sdhi *priv, int addr) 319b5b6a5f4SSimon Horman { 320b5b6a5f4SSimon Horman return readl(priv->scc_ctl + (addr << host->bus_shift)); 321b5b6a5f4SSimon Horman } 322b5b6a5f4SSimon Horman 323b5b6a5f4SSimon Horman static inline void sd_scc_write32(struct tmio_mmc_host *host, 324b5b6a5f4SSimon Horman struct renesas_sdhi *priv, 325b5b6a5f4SSimon Horman int addr, u32 val) 326b5b6a5f4SSimon Horman { 327b5b6a5f4SSimon Horman writel(val, priv->scc_ctl + (addr << host->bus_shift)); 328b5b6a5f4SSimon Horman } 329b5b6a5f4SSimon Horman 330b5b6a5f4SSimon Horman static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 331b5b6a5f4SSimon Horman { 332b5b6a5f4SSimon Horman struct renesas_sdhi *priv; 333b5b6a5f4SSimon Horman 334b5b6a5f4SSimon Horman priv = host_to_priv(host); 335b5b6a5f4SSimon Horman 336b5b6a5f4SSimon Horman /* Initialize SCC */ 337b5b6a5f4SSimon Horman sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 338b5b6a5f4SSimon Horman 339b5b6a5f4SSimon Horman sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 340b5b6a5f4SSimon Horman sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 341b5b6a5f4SSimon Horman 34226eb2607SMasaharu Hayakawa /* set sampling clock selection range */ 34326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 34426eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 34526eb2607SMasaharu Hayakawa 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 34626eb2607SMasaharu Hayakawa 347b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 348b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 349b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 350b5b6a5f4SSimon Horman 351b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 352b5b6a5f4SSimon Horman ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 353b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 354b5b6a5f4SSimon Horman 355852d258fSMasahiro Yamada sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 356b5b6a5f4SSimon Horman 35726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 35826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 35926eb2607SMasaharu Hayakawa 360b5b6a5f4SSimon Horman /* Read TAPNUM */ 361b5b6a5f4SSimon Horman return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 362b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 363b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 364b5b6a5f4SSimon Horman } 365b5b6a5f4SSimon Horman 366f22084b6SWolfram Sang static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 36726eb2607SMasaharu Hayakawa { 368f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 36926eb2607SMasaharu Hayakawa struct renesas_sdhi *priv = host_to_priv(host); 370a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 371a38c078fSTakeshi Saito bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 37226eb2607SMasaharu Hayakawa 37326eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 37426eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 37526eb2607SMasaharu Hayakawa 37626eb2607SMasaharu Hayakawa /* Set HS400 mode */ 3770e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 37826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 379f0c8234cSTakeshi Saito 380f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 381f0c8234cSTakeshi Saito priv->scc_tappos_hs400); 382f0c8234cSTakeshi Saito 383*00e8c11cSTakeshi Saito if (priv->quirks && priv->quirks->manual_tap_correction) 3849b0d6855SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 3859b0d6855SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 3869b0d6855SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 3879b0d6855SWolfram Sang 38826eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 38926eb2607SMasaharu Hayakawa (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 39026eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 39126eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 39226eb2607SMasaharu Hayakawa 39326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 39426eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 39503e59b1eSWolfram Sang sd_scc_read32(host, priv, 39603e59b1eSWolfram Sang SH_MOBILE_SDHI_SCC_DTCNTL)); 39726eb2607SMasaharu Hayakawa 398a38c078fSTakeshi Saito /* Avoid bad TAP */ 399a38c078fSTakeshi Saito if (bad_taps & BIT(priv->tap_set)) { 400a38c078fSTakeshi Saito u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 40126eb2607SMasaharu Hayakawa 402a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) 403a38c078fSTakeshi Saito new_tap = (priv->tap_set - 1) % priv->tap_num; 404a38c078fSTakeshi Saito 405a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap)) { 406a38c078fSTakeshi Saito new_tap = priv->tap_set; 407a38c078fSTakeshi Saito dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 408a38c078fSTakeshi Saito } 409a38c078fSTakeshi Saito 410a38c078fSTakeshi Saito priv->tap_set = new_tap; 411a38c078fSTakeshi Saito } 412a38c078fSTakeshi Saito 41326eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 414a38c078fSTakeshi Saito priv->tap_set / (use_4tap ? 2 : 1)); 41526eb2607SMasaharu Hayakawa 41626eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 41726eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 41826eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 41926eb2607SMasaharu Hayakawa 42026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 42126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 422ce6f92c2SWolfram Sang 423ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 424ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = true; 42526eb2607SMasaharu Hayakawa } 42626eb2607SMasaharu Hayakawa 42780d0be81SWolfram Sang static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 42826eb2607SMasaharu Hayakawa { 42980d0be81SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 43080d0be81SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 43180d0be81SWolfram Sang 43226eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 43326eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 43426eb2607SMasaharu Hayakawa 43526eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 43626eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 43726eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 43826eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_CKSEL)); 43926eb2607SMasaharu Hayakawa 44026eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 44126eb2607SMasaharu Hayakawa ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 44226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, 44326eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_DTCNTL)); 44426eb2607SMasaharu Hayakawa 44526eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 44626eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 44726eb2607SMasaharu Hayakawa } 44826eb2607SMasaharu Hayakawa 449ce6f92c2SWolfram Sang static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 450ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr) 451ce6f92c2SWolfram Sang { 452ce6f92c2SWolfram Sang /* read mode */ 453ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 454ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 455ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 456ce6f92c2SWolfram Sang 457ce6f92c2SWolfram Sang /* access start and stop */ 458ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 459ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 460ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 461ce6f92c2SWolfram Sang 462ce6f92c2SWolfram Sang return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 463ce6f92c2SWolfram Sang } 464ce6f92c2SWolfram Sang 465ce6f92c2SWolfram Sang static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 466ce6f92c2SWolfram Sang struct renesas_sdhi *priv, u32 addr, u32 val) 467ce6f92c2SWolfram Sang { 468ce6f92c2SWolfram Sang /* write mode */ 469ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 470ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 471ce6f92c2SWolfram Sang (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 472ce6f92c2SWolfram Sang 473ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 474ce6f92c2SWolfram Sang 475ce6f92c2SWolfram Sang /* access start and stop */ 476ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 477ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 478ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 479ce6f92c2SWolfram Sang } 480ce6f92c2SWolfram Sang 481ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 482ce6f92c2SWolfram Sang { 483ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 484ce6f92c2SWolfram Sang u32 calib_code; 485ce6f92c2SWolfram Sang 486ce6f92c2SWolfram Sang /* disable write protect */ 487ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 488ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 489ce6f92c2SWolfram Sang /* read calibration code and adjust */ 490ce6f92c2SWolfram Sang calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 491ce6f92c2SWolfram Sang calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 492ce6f92c2SWolfram Sang 493ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 494ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 495ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table[calib_code]); 496ce6f92c2SWolfram Sang 497ce6f92c2SWolfram Sang /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 498ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 499ce6f92c2SWolfram Sang 500ce6f92c2SWolfram Sang /* adjustment done, clear flag */ 501ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 502ce6f92c2SWolfram Sang } 503ce6f92c2SWolfram Sang 504ce6f92c2SWolfram Sang static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 505ce6f92c2SWolfram Sang { 506ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 507ce6f92c2SWolfram Sang 508ce6f92c2SWolfram Sang /* disable write protect */ 509ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x00, 510ce6f92c2SWolfram Sang SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 511ce6f92c2SWolfram Sang /* disable manual calibration */ 512ce6f92c2SWolfram Sang sd_scc_tmpport_write32(host, priv, 0x22, 0); 513ce6f92c2SWolfram Sang /* clear offset value of TMPPORT3 */ 514ce6f92c2SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 515ce6f92c2SWolfram Sang } 516ce6f92c2SWolfram Sang 51726eb2607SMasaharu Hayakawa static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 51826eb2607SMasaharu Hayakawa struct renesas_sdhi *priv) 51926eb2607SMasaharu Hayakawa { 52026eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 52126eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 52226eb2607SMasaharu Hayakawa 52326eb2607SMasaharu Hayakawa /* Reset HS400 mode */ 5240e08a411SWolfram Sang sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 52526eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SDIF_MODE)); 526f0c8234cSTakeshi Saito 527f0c8234cSTakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 528f0c8234cSTakeshi Saito 52926eb2607SMasaharu Hayakawa sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 53026eb2607SMasaharu Hayakawa ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 53126eb2607SMasaharu Hayakawa SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 53226eb2607SMasaharu Hayakawa sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 53326eb2607SMasaharu Hayakawa 534ce6f92c2SWolfram Sang if (priv->adjust_hs400_calib_table) 535ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_disable(host); 536ce6f92c2SWolfram Sang 53726eb2607SMasaharu Hayakawa sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 53826eb2607SMasaharu Hayakawa sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 53926eb2607SMasaharu Hayakawa } 54026eb2607SMasaharu Hayakawa 541f22084b6SWolfram Sang static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 54226eb2607SMasaharu Hayakawa { 543f22084b6SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 544f22084b6SWolfram Sang 54526eb2607SMasaharu Hayakawa renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 546f22084b6SWolfram Sang return 0; 54726eb2607SMasaharu Hayakawa } 54826eb2607SMasaharu Hayakawa 5490e587014SWolfram Sang static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 5505b0739d7SWolfram Sang { 551183edc06SWolfram Sang renesas_sdhi_disable_scc(host->mmc); 5525b0739d7SWolfram Sang renesas_sdhi_reset_hs400_mode(host, priv); 553ce6f92c2SWolfram Sang priv->needs_adjust_hs400 = false; 5545b0739d7SWolfram Sang 5555b0739d7SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 5565b0739d7SWolfram Sang ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 5575b0739d7SWolfram Sang sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 55845bffc37SWolfram Sang } 5595b0739d7SWolfram Sang 5600e587014SWolfram Sang /* only populated for TMIO_MMC_MIN_RCAR2 */ 5612e586f8aSWolfram Sang static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 5620e587014SWolfram Sang { 5630e587014SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 564b4d86f37SWolfram Sang int ret; 5650e587014SWolfram Sang u16 val; 5660e587014SWolfram Sang 5672e586f8aSWolfram Sang if (!preserve) { 568b4d86f37SWolfram Sang if (priv->rstc) { 569b4d86f37SWolfram Sang reset_control_reset(priv->rstc); 570b4d86f37SWolfram Sang /* Unknown why but without polling reset status, it will hang */ 571b4d86f37SWolfram Sang read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 572b4d86f37SWolfram Sang false, priv->rstc); 573b81bede4SWolfram Sang /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 574b81bede4SWolfram Sang sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 575b4d86f37SWolfram Sang priv->needs_adjust_hs400 = false; 576b4d86f37SWolfram Sang renesas_sdhi_set_clock(host, host->clk_cache); 577b4d86f37SWolfram Sang } else if (priv->scc_ctl) { 5780e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 579b4d86f37SWolfram Sang } 5802e586f8aSWolfram Sang } 5810e587014SWolfram Sang 582b191deceSWolfram Sang if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 583b191deceSWolfram Sang val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 584b191deceSWolfram Sang val |= CARD_OPT_EXTOP; 585b191deceSWolfram Sang sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 586b191deceSWolfram Sang } 587b191deceSWolfram Sang } 588b191deceSWolfram Sang 589b191deceSWolfram Sang static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 590b191deceSWolfram Sang { 591b191deceSWolfram Sang u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 592b191deceSWolfram Sang 593b191deceSWolfram Sang num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 594b191deceSWolfram Sang return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 595b191deceSWolfram Sang 5965b0739d7SWolfram Sang } 5975b0739d7SWolfram Sang 598ec4fc1acSWolfram Sang #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 599b5b6a5f4SSimon Horman 600b5b6a5f4SSimon Horman static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 601b5b6a5f4SSimon Horman { 602b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 60392fa2a56SWolfram Sang unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 6045fb6bf51SWolfram Sang unsigned int taps_size = priv->tap_num * 2, min_tap_row; 6055fb6bf51SWolfram Sang unsigned long *bitmap; 606b5b6a5f4SSimon Horman 607b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 608b5b6a5f4SSimon Horman 609b5b6a5f4SSimon Horman /* 6105c99826bSNiklas Söderlund * When tuning CMD19 is issued twice for each tap, merge the 6115c99826bSNiklas Söderlund * result requiring the tap to be good in both runs before 6125c99826bSNiklas Söderlund * considering it for tuning selection. 6135c99826bSNiklas Söderlund */ 61492fa2a56SWolfram Sang for (i = 0; i < taps_size; i++) { 615b2dd9a13SWolfram Sang int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 6165c99826bSNiklas Söderlund 617b2dd9a13SWolfram Sang if (!test_bit(i, priv->taps)) 618b2dd9a13SWolfram Sang clear_bit(i + offset, priv->taps); 6195fb6bf51SWolfram Sang 6205fb6bf51SWolfram Sang if (!test_bit(i, priv->smpcmp)) 6215fb6bf51SWolfram Sang clear_bit(i + offset, priv->smpcmp); 6225fb6bf51SWolfram Sang } 6235fb6bf51SWolfram Sang 6245fb6bf51SWolfram Sang /* 6255fb6bf51SWolfram Sang * If all TAP are OK, the sampling clock position is selected by 6265fb6bf51SWolfram Sang * identifying the change point of data. 6275fb6bf51SWolfram Sang */ 6285fb6bf51SWolfram Sang if (bitmap_full(priv->taps, taps_size)) { 6295fb6bf51SWolfram Sang bitmap = priv->smpcmp; 6305fb6bf51SWolfram Sang min_tap_row = 1; 6315fb6bf51SWolfram Sang } else { 6325fb6bf51SWolfram Sang bitmap = priv->taps; 6335fb6bf51SWolfram Sang min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 6345c99826bSNiklas Söderlund } 6355c99826bSNiklas Söderlund 6365c99826bSNiklas Söderlund /* 637b5b6a5f4SSimon Horman * Find the longest consecutive run of successful probes. If that 638ec4fc1acSWolfram Sang * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 639ec4fc1acSWolfram Sang * center index as the tap, otherwise bail out. 640b5b6a5f4SSimon Horman */ 641ec288a2cSYury Norov for_each_set_bitrange(rs, re, bitmap, taps_size) { 64292fa2a56SWolfram Sang if (re - rs > tap_cnt) { 64392fa2a56SWolfram Sang tap_end = re; 64492fa2a56SWolfram Sang tap_start = rs; 64592fa2a56SWolfram Sang tap_cnt = tap_end - tap_start; 646b5b6a5f4SSimon Horman } 647b5b6a5f4SSimon Horman } 648b5b6a5f4SSimon Horman 6495fb6bf51SWolfram Sang if (tap_cnt >= min_tap_row) 650b2dd9a13SWolfram Sang priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 651b5b6a5f4SSimon Horman else 652b5b6a5f4SSimon Horman return -EIO; 653b5b6a5f4SSimon Horman 654b5b6a5f4SSimon Horman /* Set SCC */ 655b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 656b5b6a5f4SSimon Horman 657b5b6a5f4SSimon Horman /* Enable auto re-tuning */ 658b5b6a5f4SSimon Horman sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 659b5b6a5f4SSimon Horman SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 660b5b6a5f4SSimon Horman sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 661b5b6a5f4SSimon Horman 662b5b6a5f4SSimon Horman return 0; 663b5b6a5f4SSimon Horman } 664b5b6a5f4SSimon Horman 665510bfe58SWolfram Sang static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 6660c482d82SWolfram Sang { 667510bfe58SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc); 6680c482d82SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 6695b0739d7SWolfram Sang int i, ret; 6700c482d82SWolfram Sang 671b2dd9a13SWolfram Sang priv->tap_num = renesas_sdhi_init_tuning(host); 672b2dd9a13SWolfram Sang if (!priv->tap_num) 6730c482d82SWolfram Sang return 0; /* Tuning is not supported */ 6740c482d82SWolfram Sang 675b2dd9a13SWolfram Sang if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 6763a821a82SWolfram Sang dev_err(&host->pdev->dev, 6773a821a82SWolfram Sang "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 6783a821a82SWolfram Sang return -EINVAL; 6790c482d82SWolfram Sang } 6800c482d82SWolfram Sang 681b2dd9a13SWolfram Sang bitmap_zero(priv->taps, priv->tap_num * 2); 6825fb6bf51SWolfram Sang bitmap_zero(priv->smpcmp, priv->tap_num * 2); 6830c482d82SWolfram Sang 6840c482d82SWolfram Sang /* Issue CMD19 twice for each tap */ 685b2dd9a13SWolfram Sang for (i = 0; i < 2 * priv->tap_num; i++) { 6867dba4028SWolfram Sang int cmd_error = 0; 6872c9017d0SWolfram Sang 6880c482d82SWolfram Sang /* Set sampling clock position */ 689b2dd9a13SWolfram Sang sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 6900c482d82SWolfram Sang 6912c9017d0SWolfram Sang if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 692b2dd9a13SWolfram Sang set_bit(i, priv->taps); 6935fb6bf51SWolfram Sang 6945fb6bf51SWolfram Sang if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 6955fb6bf51SWolfram Sang set_bit(i, priv->smpcmp); 6962c9017d0SWolfram Sang 6972c9017d0SWolfram Sang if (cmd_error) 69821adc2e4SWolfram Sang mmc_send_abort_tuning(mmc, opcode); 6990c482d82SWolfram Sang } 7000c482d82SWolfram Sang 7015b0739d7SWolfram Sang ret = renesas_sdhi_select_tuning(host); 7025b0739d7SWolfram Sang if (ret < 0) 7030e587014SWolfram Sang renesas_sdhi_scc_reset(host, priv); 7045b0739d7SWolfram Sang return ret; 7050c482d82SWolfram Sang } 7060c482d82SWolfram Sang 70711a21960STakeshi Saito static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 70811a21960STakeshi Saito { 70911a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 710a38c078fSTakeshi Saito unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 71111a21960STakeshi Saito u32 val; 71211a21960STakeshi Saito 71311a21960STakeshi Saito val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 71411a21960STakeshi Saito if (!val) 71511a21960STakeshi Saito return false; 71611a21960STakeshi Saito 71711a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 71811a21960STakeshi Saito 71911a21960STakeshi Saito /* Change TAP position according to correction status */ 720*00e8c11cSTakeshi Saito if (priv->quirks && priv->quirks->manual_tap_correction && 72171cfc927STakeshi Saito host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 722a38c078fSTakeshi Saito u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 72371cfc927STakeshi Saito /* 72471cfc927STakeshi Saito * With HS400, the DAT signal is based on DS, not CLK. 72571cfc927STakeshi Saito * Therefore, use only CMD status. 72671cfc927STakeshi Saito */ 72771cfc927STakeshi Saito u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 72871cfc927STakeshi Saito SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 729a38c078fSTakeshi Saito if (!smpcmp) { 73071cfc927STakeshi Saito return false; /* no error in CMD signal */ 731a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 73271cfc927STakeshi Saito new_tap++; 733a38c078fSTakeshi Saito error_tap--; 734a38c078fSTakeshi Saito } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 73571cfc927STakeshi Saito new_tap--; 736a38c078fSTakeshi Saito error_tap++; 737a38c078fSTakeshi Saito } else { 73871cfc927STakeshi Saito return true; /* need retune */ 739a38c078fSTakeshi Saito } 740a38c078fSTakeshi Saito 741a38c078fSTakeshi Saito /* 742a38c078fSTakeshi Saito * When new_tap is a bad tap, we cannot change. Then, we compare 743a38c078fSTakeshi Saito * with the HS200 tuning result. When smpcmp[error_tap] is OK, 744a38c078fSTakeshi Saito * we can at least retune. 745a38c078fSTakeshi Saito */ 746a38c078fSTakeshi Saito if (bad_taps & BIT(new_tap % priv->tap_num)) 747a38c078fSTakeshi Saito return test_bit(error_tap % priv->tap_num, priv->smpcmp); 74871cfc927STakeshi Saito } else { 74911a21960STakeshi Saito if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 75071cfc927STakeshi Saito return true; /* need retune */ 75111a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 75271cfc927STakeshi Saito new_tap++; 75311a21960STakeshi Saito else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 75471cfc927STakeshi Saito new_tap--; 75511a21960STakeshi Saito else 75611a21960STakeshi Saito return false; 75771cfc927STakeshi Saito } 75811a21960STakeshi Saito 759b2dd9a13SWolfram Sang priv->tap_set = (new_tap % priv->tap_num); 76011a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 761b2dd9a13SWolfram Sang priv->tap_set / (use_4tap ? 2 : 1)); 76211a21960STakeshi Saito 76311a21960STakeshi Saito return false; 76411a21960STakeshi Saito } 76511a21960STakeshi Saito 76611a21960STakeshi Saito static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 76711a21960STakeshi Saito { 76811a21960STakeshi Saito struct renesas_sdhi *priv = host_to_priv(host); 76911a21960STakeshi Saito 77011a21960STakeshi Saito /* Check SCC error */ 77111a21960STakeshi Saito if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 77211a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 77311a21960STakeshi Saito sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 77411a21960STakeshi Saito return true; 77511a21960STakeshi Saito } 77611a21960STakeshi Saito 77711a21960STakeshi Saito return false; 77811a21960STakeshi Saito } 77911a21960STakeshi Saito 780ed2fab9aSYoshihiro Shimoda static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 781ed2fab9aSYoshihiro Shimoda struct mmc_request *mrq) 782b5b6a5f4SSimon Horman { 783b5b6a5f4SSimon Horman struct renesas_sdhi *priv = host_to_priv(host); 78412e3c55dSWolfram Sang bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 785ed2fab9aSYoshihiro Shimoda bool ret = false; 78675f349a1SMasaharu Hayakawa 78775f349a1SMasaharu Hayakawa /* 78875f349a1SMasaharu Hayakawa * Skip checking SCC errors when running on 4 taps in HS400 mode as 78975f349a1SMasaharu Hayakawa * any retuning would still result in the same 4 taps being used. 79075f349a1SMasaharu Hayakawa */ 79175f349a1SMasaharu Hayakawa if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 79275f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 79375f349a1SMasaharu Hayakawa !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 79475f349a1SMasaharu Hayakawa return false; 79575f349a1SMasaharu Hayakawa 796fbb31330SWolfram Sang if (mmc_doing_tune(host->mmc)) 79775f349a1SMasaharu Hayakawa return false; 798b5b6a5f4SSimon Horman 799ed2fab9aSYoshihiro Shimoda if (((mrq->cmd->error == -ETIMEDOUT) || 800ed2fab9aSYoshihiro Shimoda (mrq->data && mrq->data->error == -ETIMEDOUT)) && 801ed2fab9aSYoshihiro Shimoda ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 802ed2fab9aSYoshihiro Shimoda (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 803ed2fab9aSYoshihiro Shimoda ret |= true; 804ed2fab9aSYoshihiro Shimoda 805b5b6a5f4SSimon Horman if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 80611a21960STakeshi Saito SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 807ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_auto_correction(host); 808ed2fab9aSYoshihiro Shimoda else 809ed2fab9aSYoshihiro Shimoda ret |= renesas_sdhi_manual_correction(host, use_4tap); 810b5b6a5f4SSimon Horman 811ed2fab9aSYoshihiro Shimoda return ret; 812b5b6a5f4SSimon Horman } 813b5b6a5f4SSimon Horman 8144dc48a95SWolfram Sang static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 815b5b6a5f4SSimon Horman { 816b5b6a5f4SSimon Horman int timeout = 1000; 8174dc48a95SWolfram Sang /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 8184dc48a95SWolfram Sang u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 819b5b6a5f4SSimon Horman 8204dc48a95SWolfram Sang while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 8214dc48a95SWolfram Sang & bit) == wait_state) 822b5b6a5f4SSimon Horman udelay(1); 823b5b6a5f4SSimon Horman 824b5b6a5f4SSimon Horman if (!timeout) { 825b5b6a5f4SSimon Horman dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 826b5b6a5f4SSimon Horman return -EBUSY; 827b5b6a5f4SSimon Horman } 828b5b6a5f4SSimon Horman 829b5b6a5f4SSimon Horman return 0; 830b5b6a5f4SSimon Horman } 831b5b6a5f4SSimon Horman 832b5b6a5f4SSimon Horman static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 833b5b6a5f4SSimon Horman { 8344dc48a95SWolfram Sang u32 bit = TMIO_STAT_SCLKDIVEN; 8354dc48a95SWolfram Sang 8362fe35968SSimon Horman switch (addr) { 837b5b6a5f4SSimon Horman case CTL_SD_CMD: 838b5b6a5f4SSimon Horman case CTL_STOP_INTERNAL_ACTION: 839b5b6a5f4SSimon Horman case CTL_XFER_BLK_COUNT: 840b5b6a5f4SSimon Horman case CTL_SD_XFER_LEN: 841b5b6a5f4SSimon Horman case CTL_SD_MEM_CARD_OPT: 842b5b6a5f4SSimon Horman case CTL_TRANSACTION_CTL: 843b5b6a5f4SSimon Horman case CTL_DMA_ENABLE: 8444533c3ebSWolfram Sang case CTL_HOST_MODE: 8455124b592SWolfram Sang if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 8464dc48a95SWolfram Sang bit = TMIO_STAT_CMD_BUSY; 847df561f66SGustavo A. R. Silva fallthrough; 8484dc48a95SWolfram Sang case CTL_SD_CARD_CLK_CTL: 8494dc48a95SWolfram Sang return renesas_sdhi_wait_idle(host, bit); 850b5b6a5f4SSimon Horman } 851b5b6a5f4SSimon Horman 852b5b6a5f4SSimon Horman return 0; 853b5b6a5f4SSimon Horman } 854b5b6a5f4SSimon Horman 855b5b6a5f4SSimon Horman static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 856b5b6a5f4SSimon Horman unsigned int direction, int blk_size) 857b5b6a5f4SSimon Horman { 858b5b6a5f4SSimon Horman /* 859b5b6a5f4SSimon Horman * In Renesas controllers, when performing a 860b5b6a5f4SSimon Horman * multiple block read of one or two blocks, 861b5b6a5f4SSimon Horman * depending on the timing with which the 862b5b6a5f4SSimon Horman * response register is read, the response 863b5b6a5f4SSimon Horman * value may not be read properly. 864b5b6a5f4SSimon Horman * Use single block read for this HW bug 865b5b6a5f4SSimon Horman */ 866b5b6a5f4SSimon Horman if ((direction == MMC_DATA_READ) && 867b5b6a5f4SSimon Horman blk_size == 2) 868b5b6a5f4SSimon Horman return 1; 869b5b6a5f4SSimon Horman 870b5b6a5f4SSimon Horman return blk_size; 871b5b6a5f4SSimon Horman } 872b5b6a5f4SSimon Horman 873ce6f92c2SWolfram Sang static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 874ce6f92c2SWolfram Sang { 875ce6f92c2SWolfram Sang struct renesas_sdhi *priv = host_to_priv(host); 876ce6f92c2SWolfram Sang 877ce6f92c2SWolfram Sang if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 878ce6f92c2SWolfram Sang renesas_sdhi_adjust_hs400_mode_enable(host); 879ce6f92c2SWolfram Sang } 880b5b6a5f4SSimon Horman static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 881b5b6a5f4SSimon Horman { 88241279f01SWolfram Sang /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 88341279f01SWolfram Sang int width = (host->bus_shift == 2) ? 64 : 32; 884b5b6a5f4SSimon Horman 88541279f01SWolfram Sang sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 88641279f01SWolfram Sang renesas_sdhi_sdbuf_width(host, enable ? width : 16); 887b5b6a5f4SSimon Horman } 888b5b6a5f4SSimon Horman 8899d08428aSSimon Horman int renesas_sdhi_probe(struct platform_device *pdev, 89071b7597cSYoshihiro Shimoda const struct tmio_mmc_dma_ops *dma_ops, 89171b7597cSYoshihiro Shimoda const struct renesas_sdhi_of_data *of_data, 89271b7597cSYoshihiro Shimoda const struct renesas_sdhi_quirks *quirks) 893b5b6a5f4SSimon Horman { 894b5b6a5f4SSimon Horman struct tmio_mmc_data *mmd = pdev->dev.platform_data; 8952fe35968SSimon Horman struct tmio_mmc_data *mmc_data; 8962fe35968SSimon Horman struct tmio_mmc_dma *dma_priv; 897b5b6a5f4SSimon Horman struct tmio_mmc_host *host; 8982fe35968SSimon Horman struct renesas_sdhi *priv; 899e8307ec5SGeert Uytterhoeven int num_irqs, irq, ret, i; 900b5b6a5f4SSimon Horman struct resource *res; 901c9a9497cSWolfram Sang u16 ver; 9022fe35968SSimon Horman 903b5b6a5f4SSimon Horman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904b5b6a5f4SSimon Horman if (!res) 905b5b6a5f4SSimon Horman return -EINVAL; 906b5b6a5f4SSimon Horman 9072fe35968SSimon Horman priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 9082fe35968SSimon Horman GFP_KERNEL); 909b5b6a5f4SSimon Horman if (!priv) 910b5b6a5f4SSimon Horman return -ENOMEM; 911b5b6a5f4SSimon Horman 9127af08206SWolfram Sang priv->quirks = quirks; 913b5b6a5f4SSimon Horman mmc_data = &priv->mmc_data; 914b5b6a5f4SSimon Horman dma_priv = &priv->dma_priv; 915b5b6a5f4SSimon Horman 916b5b6a5f4SSimon Horman priv->clk = devm_clk_get(&pdev->dev, NULL); 917079e83b9SWolfram Sang if (IS_ERR(priv->clk)) 918079e83b9SWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 919b5b6a5f4SSimon Horman 920e5f7e81eSWolfram Sang priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 921e5f7e81eSWolfram Sang if (IS_ERR(priv->clkh)) 922e5f7e81eSWolfram Sang return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 923b5b6a5f4SSimon Horman 924b5b6a5f4SSimon Horman /* 925b5b6a5f4SSimon Horman * Some controllers provide a 2nd clock just to run the internal card 926b5b6a5f4SSimon Horman * detection logic. Unfortunately, the existing driver architecture does 927b5b6a5f4SSimon Horman * not support a separation of clocks for runtime PM usage. When 928b5b6a5f4SSimon Horman * native hotplug is used, the tmio driver assumes that the core 929b5b6a5f4SSimon Horman * must continue to run for card detect to stay active, so we cannot 930b5b6a5f4SSimon Horman * disable it. 931b5b6a5f4SSimon Horman * Additionally, it is prohibited to supply a clock to the core but not 932b5b6a5f4SSimon Horman * to the card detect circuit. That leaves us with if separate clocks 933b5b6a5f4SSimon Horman * are presented, we must treat them both as virtually 1 clock. 934b5b6a5f4SSimon Horman */ 935366df82fSGeert Uytterhoeven priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 936b5b6a5f4SSimon Horman if (IS_ERR(priv->clk_cd)) 937366df82fSGeert Uytterhoeven return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 938b5b6a5f4SSimon Horman 9390dac1e49SLad Prabhakar priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 9400dac1e49SLad Prabhakar if (IS_ERR(priv->rstc)) 9410dac1e49SLad Prabhakar return PTR_ERR(priv->rstc); 9420dac1e49SLad Prabhakar 943b5b6a5f4SSimon Horman priv->pinctrl = devm_pinctrl_get(&pdev->dev); 944b5b6a5f4SSimon Horman if (!IS_ERR(priv->pinctrl)) { 945b5b6a5f4SSimon Horman priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 946b5b6a5f4SSimon Horman PINCTRL_STATE_DEFAULT); 947b5b6a5f4SSimon Horman priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 948b5b6a5f4SSimon Horman "state_uhs"); 949b5b6a5f4SSimon Horman } 950b5b6a5f4SSimon Horman 951b21fc294SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, mmc_data); 9528d09a133SMasahiro Yamada if (IS_ERR(host)) 9538d09a133SMasahiro Yamada return PTR_ERR(host); 954b5b6a5f4SSimon Horman 955b5b6a5f4SSimon Horman if (of_data) { 956b5b6a5f4SSimon Horman mmc_data->flags |= of_data->tmio_flags; 957b5b6a5f4SSimon Horman mmc_data->ocr_mask = of_data->tmio_ocr_mask; 958b5b6a5f4SSimon Horman mmc_data->capabilities |= of_data->capabilities; 959b5b6a5f4SSimon Horman mmc_data->capabilities2 |= of_data->capabilities2; 960b5b6a5f4SSimon Horman mmc_data->dma_rx_offset = of_data->dma_rx_offset; 961603aa14dSYoshihiro Shimoda mmc_data->max_blk_count = of_data->max_blk_count; 962603aa14dSYoshihiro Shimoda mmc_data->max_segs = of_data->max_segs; 963b5b6a5f4SSimon Horman dma_priv->dma_buswidth = of_data->dma_buswidth; 964b5b6a5f4SSimon Horman host->bus_shift = of_data->bus_shift; 965bb6d3fa9SWolfram Sang /* Fallback for old DTs */ 966e5f7e81eSWolfram Sang if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 967bb6d3fa9SWolfram Sang priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 968bb6d3fa9SWolfram Sang 969b5b6a5f4SSimon Horman } 970b5b6a5f4SSimon Horman 971b5b6a5f4SSimon Horman host->write16_hook = renesas_sdhi_write16_hook; 972b5b6a5f4SSimon Horman host->clk_enable = renesas_sdhi_clk_enable; 973b5b6a5f4SSimon Horman host->clk_disable = renesas_sdhi_clk_disable; 9740196c8dbSMasahiro Yamada host->set_clock = renesas_sdhi_set_clock; 975b5b6a5f4SSimon Horman host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 976bc45719cSMasahiro Yamada host->dma_ops = dma_ops; 977b5b6a5f4SSimon Horman 9780f4e2054SNiklas Söderlund if (quirks && quirks->hs400_disabled) 9790f4e2054SNiklas Söderlund host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 9800f4e2054SNiklas Söderlund 981ef5332c1SWolfram Sang /* For some SoC, we disable internal WP. GPIO may override this */ 982ef5332c1SWolfram Sang if (mmc_can_gpio_ro(host->mmc)) 983ef5332c1SWolfram Sang mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 984ef5332c1SWolfram Sang 985b5b6a5f4SSimon Horman /* SDR speeds are only available on Gen2+ */ 986b5b6a5f4SSimon Horman if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 987b5b6a5f4SSimon Horman /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 9882aaa3c51SMasahiro Yamada host->ops.card_busy = renesas_sdhi_card_busy; 9892aaa3c51SMasahiro Yamada host->ops.start_signal_voltage_switch = 990b5b6a5f4SSimon Horman renesas_sdhi_start_signal_voltage_switch; 9911970701fSWolfram Sang host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 9929f12cac1SWolfram Sang host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 9936e7d4de1SWolfram Sang host->reset = renesas_sdhi_reset; 994d30ae056STakeshi Saito } 995b5b6a5f4SSimon Horman 996b5b6a5f4SSimon Horman /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 997b5b6a5f4SSimon Horman if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 998b5b6a5f4SSimon Horman host->bus_shift = 1; 999b5b6a5f4SSimon Horman 1000b5b6a5f4SSimon Horman if (mmd) 1001b5b6a5f4SSimon Horman *mmc_data = *mmd; 1002b5b6a5f4SSimon Horman 1003b5b6a5f4SSimon Horman dma_priv->filter = shdma_chan_filter; 1004b5b6a5f4SSimon Horman dma_priv->enable = renesas_sdhi_enable_dma; 1005b5b6a5f4SSimon Horman 1006b5b6a5f4SSimon Horman mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1007b5b6a5f4SSimon Horman mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1008b5b6a5f4SSimon Horman 1009b5b6a5f4SSimon Horman /* 1010b5b6a5f4SSimon Horman * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1011b5b6a5f4SSimon Horman * bus width mode. 1012b5b6a5f4SSimon Horman */ 1013b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1014b5b6a5f4SSimon Horman 1015b5b6a5f4SSimon Horman /* 1016b5b6a5f4SSimon Horman * All SDHI blocks support SDIO IRQ signalling. 1017b5b6a5f4SSimon Horman */ 1018b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1019b5b6a5f4SSimon Horman 10202fe35968SSimon Horman /* All SDHI have CMD12 control bit */ 1021b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1022b5b6a5f4SSimon Horman 1023b5b6a5f4SSimon Horman /* All SDHI have SDIO status bits which must be 1 */ 1024b5b6a5f4SSimon Horman mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1025b5b6a5f4SSimon Horman 102630ae3e13SWolfram Sang /* All SDHI support HW busy detection */ 102730ae3e13SWolfram Sang mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 102830ae3e13SWolfram Sang 102963fd8ef3SUlf Hansson dev_pm_domain_start(&pdev->dev); 103063fd8ef3SUlf Hansson 1031b21fc294SMasahiro Yamada ret = renesas_sdhi_clk_enable(host); 1032b21fc294SMasahiro Yamada if (ret) 1033b5b6a5f4SSimon Horman goto efree; 1034b5b6a5f4SSimon Horman 1035c9a9497cSWolfram Sang ver = sd_ctrl_read16(host, CTL_VERSION); 1036c9a9497cSWolfram Sang /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1037c9a9497cSWolfram Sang if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1038c9a9497cSWolfram Sang mmc_data->max_blk_count = U16_MAX; 1039c9a9497cSWolfram Sang 10405124b592SWolfram Sang /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1041c9a9497cSWolfram Sang if (ver == SDHI_VER_GEN2_SDR50) 10425124b592SWolfram Sang mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 10435124b592SWolfram Sang 1044ce6f92c2SWolfram Sang if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1045ce6f92c2SWolfram Sang host->fixup_request = renesas_sdhi_fixup_request; 1046ce6f92c2SWolfram Sang priv->adjust_hs400_calib_table = *( 1047ce6f92c2SWolfram Sang res->start == SDHI_GEN3_MMC0_ADDR ? 1048ce6f92c2SWolfram Sang quirks->hs400_calib_table : 1049ce6f92c2SWolfram Sang quirks->hs400_calib_table + 1); 1050ce6f92c2SWolfram Sang } 1051ce6f92c2SWolfram Sang 1052b191deceSWolfram Sang /* these have an EXTOP bit */ 1053b191deceSWolfram Sang if (ver >= SDHI_VER_GEN3_SD) 1054b191deceSWolfram Sang host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1055b191deceSWolfram Sang 1056b5b6a5f4SSimon Horman /* Enable tuning iff we have an SCC and a supported mode */ 1057b5b6a5f4SSimon Horman if (of_data && of_data->scc_offset && 1058b5b6a5f4SSimon Horman (host->mmc->caps & MMC_CAP_UHS_SDR104 || 105926eb2607SMasaharu Hayakawa host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 106026eb2607SMasaharu Hayakawa MMC_CAP2_HS400_1_8V))) { 1061b5b6a5f4SSimon Horman const struct renesas_sdhi_scc *taps = of_data->taps; 106245177fc6SWolfram Sang bool use_4tap = quirks && quirks->hs400_4taps; 1063b5b6a5f4SSimon Horman bool hit = false; 1064b5b6a5f4SSimon Horman 1065b5b6a5f4SSimon Horman for (i = 0; i < of_data->taps_num; i++) { 1066b5b6a5f4SSimon Horman if (taps[i].clk_rate == 0 || 1067b5b6a5f4SSimon Horman taps[i].clk_rate == host->mmc->f_max) { 1068852d258fSMasahiro Yamada priv->scc_tappos = taps->tap; 1069c1a49782SWolfram Sang priv->scc_tappos_hs400 = use_4tap ? 1070c1a49782SWolfram Sang taps->tap_hs400_4tap : 1071c1a49782SWolfram Sang taps->tap; 1072b5b6a5f4SSimon Horman hit = true; 1073b5b6a5f4SSimon Horman break; 1074b5b6a5f4SSimon Horman } 1075b5b6a5f4SSimon Horman } 1076b5b6a5f4SSimon Horman 1077b5b6a5f4SSimon Horman if (!hit) 1078e5088f20SWolfram Sang dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1079b5b6a5f4SSimon Horman 1080d14ac691SWolfram Sang priv->scc_ctl = host->ctl + of_data->scc_offset; 108164982b9fSWolfram Sang host->check_retune = renesas_sdhi_check_scc_error; 1082510bfe58SWolfram Sang host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1083f22084b6SWolfram Sang host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1084f22084b6SWolfram Sang host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1085f22084b6SWolfram Sang host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1086b5b6a5f4SSimon Horman } 1087b5b6a5f4SSimon Horman 1088b161d87dSWolfram Sang ret = tmio_mmc_host_probe(host); 1089b161d87dSWolfram Sang if (ret < 0) 1090b161d87dSWolfram Sang goto edisclk; 1091b161d87dSWolfram Sang 1092e8307ec5SGeert Uytterhoeven num_irqs = platform_irq_count(pdev); 1093e8307ec5SGeert Uytterhoeven if (num_irqs < 0) { 1094e8307ec5SGeert Uytterhoeven ret = num_irqs; 1095b5b6a5f4SSimon Horman goto eirq; 1096b5b6a5f4SSimon Horman } 1097b5b6a5f4SSimon Horman 1098b5b6a5f4SSimon Horman /* There must be at least one IRQ source */ 1099e8307ec5SGeert Uytterhoeven if (!num_irqs) { 1100e8307ec5SGeert Uytterhoeven ret = -ENXIO; 1101e8307ec5SGeert Uytterhoeven goto eirq; 1102e8307ec5SGeert Uytterhoeven } 1103e8307ec5SGeert Uytterhoeven 1104e8307ec5SGeert Uytterhoeven for (i = 0; i < num_irqs; i++) { 1105e8307ec5SGeert Uytterhoeven irq = platform_get_irq(pdev, i); 1106e8307ec5SGeert Uytterhoeven if (irq < 0) { 1107b5b6a5f4SSimon Horman ret = irq; 1108b5b6a5f4SSimon Horman goto eirq; 1109b5b6a5f4SSimon Horman } 1110b5b6a5f4SSimon Horman 1111e8307ec5SGeert Uytterhoeven ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1112e8307ec5SGeert Uytterhoeven dev_name(&pdev->dev), host); 1113e8307ec5SGeert Uytterhoeven if (ret) 1114e8307ec5SGeert Uytterhoeven goto eirq; 1115e8307ec5SGeert Uytterhoeven } 1116e8307ec5SGeert Uytterhoeven 1117bcf89cb8SWolfram Sang dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1118bcf89cb8SWolfram Sang mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1119b5b6a5f4SSimon Horman 1120b5b6a5f4SSimon Horman return ret; 1121b5b6a5f4SSimon Horman 1122b5b6a5f4SSimon Horman eirq: 1123b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1124b21fc294SMasahiro Yamada edisclk: 1125b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1126b5b6a5f4SSimon Horman efree: 1127b5b6a5f4SSimon Horman tmio_mmc_host_free(host); 11284ce62817SMasahiro Yamada 1129b5b6a5f4SSimon Horman return ret; 1130b5b6a5f4SSimon Horman } 11319d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1132b5b6a5f4SSimon Horman 11339d08428aSSimon Horman int renesas_sdhi_remove(struct platform_device *pdev) 1134b5b6a5f4SSimon Horman { 1135a3b05373SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1136b5b6a5f4SSimon Horman 1137b5b6a5f4SSimon Horman tmio_mmc_host_remove(host); 1138b21fc294SMasahiro Yamada renesas_sdhi_clk_disable(host); 1139e8973201SYoshihiro Shimoda tmio_mmc_host_free(host); 1140b5b6a5f4SSimon Horman 1141b5b6a5f4SSimon Horman return 0; 1142b5b6a5f4SSimon Horman } 11439d08428aSSimon Horman EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1144967a6a07SMasaharu Hayakawa 1145967a6a07SMasaharu Hayakawa MODULE_LICENSE("GPL v2"); 1146