1 /* 2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver 3 * 4 * Copyright (C) 2003 Russell King, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This hardware is really sick: 11 * - No way to clear interrupts. 12 * - Have to turn off the clock whenever we touch the device. 13 * - Doesn't tell you how many data blocks were transferred. 14 * Yuck! 15 * 16 * 1 and 3 byte data transfers not supported 17 * max block length up to 1023 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/mmc/host.h> 29 #include <linux/io.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/gpio.h> 32 #include <linux/gfp.h> 33 34 #include <asm/sizes.h> 35 36 #include <mach/hardware.h> 37 #include <mach/dma.h> 38 #include <mach/mmc.h> 39 40 #include "pxamci.h" 41 42 #define DRIVER_NAME "pxa2xx-mci" 43 44 #define NR_SG 1 45 #define CLKRT_OFF (~0) 46 47 #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ 48 || cpu_is_pxa935()) 49 50 struct pxamci_host { 51 struct mmc_host *mmc; 52 spinlock_t lock; 53 struct resource *res; 54 void __iomem *base; 55 struct clk *clk; 56 unsigned long clkrate; 57 int irq; 58 int dma; 59 unsigned int clkrt; 60 unsigned int cmdat; 61 unsigned int imask; 62 unsigned int power_mode; 63 struct pxamci_platform_data *pdata; 64 65 struct mmc_request *mrq; 66 struct mmc_command *cmd; 67 struct mmc_data *data; 68 69 dma_addr_t sg_dma; 70 struct pxa_dma_desc *sg_cpu; 71 unsigned int dma_len; 72 73 unsigned int dma_dir; 74 unsigned int dma_drcmrrx; 75 unsigned int dma_drcmrtx; 76 77 struct regulator *vcc; 78 }; 79 80 static inline void pxamci_init_ocr(struct pxamci_host *host) 81 { 82 #ifdef CONFIG_REGULATOR 83 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 84 85 if (IS_ERR(host->vcc)) 86 host->vcc = NULL; 87 else { 88 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 89 if (host->pdata && host->pdata->ocr_mask) 90 dev_warn(mmc_dev(host->mmc), 91 "ocr_mask/setpower will not be used\n"); 92 } 93 #endif 94 if (host->vcc == NULL) { 95 /* fall-back to platform data */ 96 host->mmc->ocr_avail = host->pdata ? 97 host->pdata->ocr_mask : 98 MMC_VDD_32_33 | MMC_VDD_33_34; 99 } 100 } 101 102 static inline int pxamci_set_power(struct pxamci_host *host, 103 unsigned char power_mode, 104 unsigned int vdd) 105 { 106 int on; 107 108 if (host->vcc) { 109 int ret; 110 111 if (power_mode == MMC_POWER_UP) { 112 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 113 if (ret) 114 return ret; 115 } else if (power_mode == MMC_POWER_OFF) { 116 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 117 if (ret) 118 return ret; 119 } 120 } 121 if (!host->vcc && host->pdata && 122 gpio_is_valid(host->pdata->gpio_power)) { 123 on = ((1 << vdd) & host->pdata->ocr_mask); 124 gpio_set_value(host->pdata->gpio_power, 125 !!on ^ host->pdata->gpio_power_invert); 126 } 127 if (!host->vcc && host->pdata && host->pdata->setpower) 128 host->pdata->setpower(mmc_dev(host->mmc), vdd); 129 130 return 0; 131 } 132 133 static void pxamci_stop_clock(struct pxamci_host *host) 134 { 135 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { 136 unsigned long timeout = 10000; 137 unsigned int v; 138 139 writel(STOP_CLOCK, host->base + MMC_STRPCL); 140 141 do { 142 v = readl(host->base + MMC_STAT); 143 if (!(v & STAT_CLK_EN)) 144 break; 145 udelay(1); 146 } while (timeout--); 147 148 if (v & STAT_CLK_EN) 149 dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); 150 } 151 } 152 153 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) 154 { 155 unsigned long flags; 156 157 spin_lock_irqsave(&host->lock, flags); 158 host->imask &= ~mask; 159 writel(host->imask, host->base + MMC_I_MASK); 160 spin_unlock_irqrestore(&host->lock, flags); 161 } 162 163 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) 164 { 165 unsigned long flags; 166 167 spin_lock_irqsave(&host->lock, flags); 168 host->imask |= mask; 169 writel(host->imask, host->base + MMC_I_MASK); 170 spin_unlock_irqrestore(&host->lock, flags); 171 } 172 173 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) 174 { 175 unsigned int nob = data->blocks; 176 unsigned long long clks; 177 unsigned int timeout; 178 bool dalgn = 0; 179 u32 dcmd; 180 int i; 181 182 host->data = data; 183 184 if (data->flags & MMC_DATA_STREAM) 185 nob = 0xffff; 186 187 writel(nob, host->base + MMC_NOB); 188 writel(data->blksz, host->base + MMC_BLKLEN); 189 190 clks = (unsigned long long)data->timeout_ns * host->clkrate; 191 do_div(clks, 1000000000UL); 192 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); 193 writel((timeout + 255) / 256, host->base + MMC_RDTO); 194 195 if (data->flags & MMC_DATA_READ) { 196 host->dma_dir = DMA_FROM_DEVICE; 197 dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; 198 DRCMR(host->dma_drcmrtx) = 0; 199 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; 200 } else { 201 host->dma_dir = DMA_TO_DEVICE; 202 dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; 203 DRCMR(host->dma_drcmrrx) = 0; 204 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; 205 } 206 207 dcmd |= DCMD_BURST32 | DCMD_WIDTH1; 208 209 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 210 host->dma_dir); 211 212 for (i = 0; i < host->dma_len; i++) { 213 unsigned int length = sg_dma_len(&data->sg[i]); 214 host->sg_cpu[i].dcmd = dcmd | length; 215 if (length & 31 && !(data->flags & MMC_DATA_READ)) 216 host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; 217 /* Not aligned to 8-byte boundary? */ 218 if (sg_dma_address(&data->sg[i]) & 0x7) 219 dalgn = 1; 220 if (data->flags & MMC_DATA_READ) { 221 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; 222 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); 223 } else { 224 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); 225 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; 226 } 227 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * 228 sizeof(struct pxa_dma_desc); 229 } 230 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; 231 wmb(); 232 233 /* 234 * The PXA27x DMA controller encounters overhead when working with 235 * unaligned (to 8-byte boundaries) data, so switch on byte alignment 236 * mode only if we have unaligned data. 237 */ 238 if (dalgn) 239 DALGN |= (1 << host->dma); 240 else 241 DALGN &= ~(1 << host->dma); 242 DDADR(host->dma) = host->sg_dma; 243 244 /* 245 * workaround for erratum #91: 246 * only start DMA now if we are doing a read, 247 * otherwise we wait until CMD/RESP has finished 248 * before starting DMA. 249 */ 250 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) 251 DCSR(host->dma) = DCSR_RUN; 252 } 253 254 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) 255 { 256 WARN_ON(host->cmd != NULL); 257 host->cmd = cmd; 258 259 if (cmd->flags & MMC_RSP_BUSY) 260 cmdat |= CMDAT_BUSY; 261 262 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) 263 switch (RSP_TYPE(mmc_resp_type(cmd))) { 264 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ 265 cmdat |= CMDAT_RESP_SHORT; 266 break; 267 case RSP_TYPE(MMC_RSP_R3): 268 cmdat |= CMDAT_RESP_R3; 269 break; 270 case RSP_TYPE(MMC_RSP_R2): 271 cmdat |= CMDAT_RESP_R2; 272 break; 273 default: 274 break; 275 } 276 277 writel(cmd->opcode, host->base + MMC_CMD); 278 writel(cmd->arg >> 16, host->base + MMC_ARGH); 279 writel(cmd->arg & 0xffff, host->base + MMC_ARGL); 280 writel(cmdat, host->base + MMC_CMDAT); 281 writel(host->clkrt, host->base + MMC_CLKRT); 282 283 writel(START_CLOCK, host->base + MMC_STRPCL); 284 285 pxamci_enable_irq(host, END_CMD_RES); 286 } 287 288 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) 289 { 290 host->mrq = NULL; 291 host->cmd = NULL; 292 host->data = NULL; 293 mmc_request_done(host->mmc, mrq); 294 } 295 296 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) 297 { 298 struct mmc_command *cmd = host->cmd; 299 int i; 300 u32 v; 301 302 if (!cmd) 303 return 0; 304 305 host->cmd = NULL; 306 307 /* 308 * Did I mention this is Sick. We always need to 309 * discard the upper 8 bits of the first 16-bit word. 310 */ 311 v = readl(host->base + MMC_RES) & 0xffff; 312 for (i = 0; i < 4; i++) { 313 u32 w1 = readl(host->base + MMC_RES) & 0xffff; 314 u32 w2 = readl(host->base + MMC_RES) & 0xffff; 315 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; 316 v = w2; 317 } 318 319 if (stat & STAT_TIME_OUT_RESPONSE) { 320 cmd->error = -ETIMEDOUT; 321 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 322 /* 323 * workaround for erratum #42: 324 * Intel PXA27x Family Processor Specification Update Rev 001 325 * A bogus CRC error can appear if the msb of a 136 bit 326 * response is a one. 327 */ 328 if (cpu_is_pxa27x() && 329 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) 330 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); 331 else 332 cmd->error = -EILSEQ; 333 } 334 335 pxamci_disable_irq(host, END_CMD_RES); 336 if (host->data && !cmd->error) { 337 pxamci_enable_irq(host, DATA_TRAN_DONE); 338 /* 339 * workaround for erratum #91, if doing write 340 * enable DMA late 341 */ 342 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) 343 DCSR(host->dma) = DCSR_RUN; 344 } else { 345 pxamci_finish_request(host, host->mrq); 346 } 347 348 return 1; 349 } 350 351 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) 352 { 353 struct mmc_data *data = host->data; 354 355 if (!data) 356 return 0; 357 358 DCSR(host->dma) = 0; 359 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 360 host->dma_dir); 361 362 if (stat & STAT_READ_TIME_OUT) 363 data->error = -ETIMEDOUT; 364 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) 365 data->error = -EILSEQ; 366 367 /* 368 * There appears to be a hardware design bug here. There seems to 369 * be no way to find out how much data was transferred to the card. 370 * This means that if there was an error on any block, we mark all 371 * data blocks as being in error. 372 */ 373 if (!data->error) 374 data->bytes_xfered = data->blocks * data->blksz; 375 else 376 data->bytes_xfered = 0; 377 378 pxamci_disable_irq(host, DATA_TRAN_DONE); 379 380 host->data = NULL; 381 if (host->mrq->stop) { 382 pxamci_stop_clock(host); 383 pxamci_start_cmd(host, host->mrq->stop, host->cmdat); 384 } else { 385 pxamci_finish_request(host, host->mrq); 386 } 387 388 return 1; 389 } 390 391 static irqreturn_t pxamci_irq(int irq, void *devid) 392 { 393 struct pxamci_host *host = devid; 394 unsigned int ireg; 395 int handled = 0; 396 397 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); 398 399 if (ireg) { 400 unsigned stat = readl(host->base + MMC_STAT); 401 402 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); 403 404 if (ireg & END_CMD_RES) 405 handled |= pxamci_cmd_done(host, stat); 406 if (ireg & DATA_TRAN_DONE) 407 handled |= pxamci_data_done(host, stat); 408 if (ireg & SDIO_INT) { 409 mmc_signal_sdio_irq(host->mmc); 410 handled = 1; 411 } 412 } 413 414 return IRQ_RETVAL(handled); 415 } 416 417 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) 418 { 419 struct pxamci_host *host = mmc_priv(mmc); 420 unsigned int cmdat; 421 422 WARN_ON(host->mrq != NULL); 423 424 host->mrq = mrq; 425 426 pxamci_stop_clock(host); 427 428 cmdat = host->cmdat; 429 host->cmdat &= ~CMDAT_INIT; 430 431 if (mrq->data) { 432 pxamci_setup_data(host, mrq->data); 433 434 cmdat &= ~CMDAT_BUSY; 435 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; 436 if (mrq->data->flags & MMC_DATA_WRITE) 437 cmdat |= CMDAT_WRITE; 438 439 if (mrq->data->flags & MMC_DATA_STREAM) 440 cmdat |= CMDAT_STREAM; 441 } 442 443 pxamci_start_cmd(host, mrq->cmd, cmdat); 444 } 445 446 static int pxamci_get_ro(struct mmc_host *mmc) 447 { 448 struct pxamci_host *host = mmc_priv(mmc); 449 450 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) { 451 if (host->pdata->gpio_card_ro_invert) 452 return !gpio_get_value(host->pdata->gpio_card_ro); 453 else 454 return gpio_get_value(host->pdata->gpio_card_ro); 455 } 456 if (host->pdata && host->pdata->get_ro) 457 return !!host->pdata->get_ro(mmc_dev(mmc)); 458 /* 459 * Board doesn't support read only detection; let the mmc core 460 * decide what to do. 461 */ 462 return -ENOSYS; 463 } 464 465 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 466 { 467 struct pxamci_host *host = mmc_priv(mmc); 468 469 if (ios->clock) { 470 unsigned long rate = host->clkrate; 471 unsigned int clk = rate / ios->clock; 472 473 if (host->clkrt == CLKRT_OFF) 474 clk_enable(host->clk); 475 476 if (ios->clock == 26000000) { 477 /* to support 26MHz */ 478 host->clkrt = 7; 479 } else { 480 /* to handle (19.5MHz, 26MHz) */ 481 if (!clk) 482 clk = 1; 483 484 /* 485 * clk might result in a lower divisor than we 486 * desire. check for that condition and adjust 487 * as appropriate. 488 */ 489 if (rate / clk > ios->clock) 490 clk <<= 1; 491 host->clkrt = fls(clk) - 1; 492 } 493 494 /* 495 * we write clkrt on the next command 496 */ 497 } else { 498 pxamci_stop_clock(host); 499 if (host->clkrt != CLKRT_OFF) { 500 host->clkrt = CLKRT_OFF; 501 clk_disable(host->clk); 502 } 503 } 504 505 if (host->power_mode != ios->power_mode) { 506 int ret; 507 508 host->power_mode = ios->power_mode; 509 510 ret = pxamci_set_power(host, ios->power_mode, ios->vdd); 511 if (ret) { 512 dev_err(mmc_dev(mmc), "unable to set power\n"); 513 /* 514 * The .set_ios() function in the mmc_host_ops 515 * struct return void, and failing to set the 516 * power should be rare so we print an error and 517 * return here. 518 */ 519 return; 520 } 521 522 if (ios->power_mode == MMC_POWER_ON) 523 host->cmdat |= CMDAT_INIT; 524 } 525 526 if (ios->bus_width == MMC_BUS_WIDTH_4) 527 host->cmdat |= CMDAT_SD_4DAT; 528 else 529 host->cmdat &= ~CMDAT_SD_4DAT; 530 531 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n", 532 host->clkrt, host->cmdat); 533 } 534 535 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) 536 { 537 struct pxamci_host *pxa_host = mmc_priv(host); 538 539 if (enable) 540 pxamci_enable_irq(pxa_host, SDIO_INT); 541 else 542 pxamci_disable_irq(pxa_host, SDIO_INT); 543 } 544 545 static const struct mmc_host_ops pxamci_ops = { 546 .request = pxamci_request, 547 .get_ro = pxamci_get_ro, 548 .set_ios = pxamci_set_ios, 549 .enable_sdio_irq = pxamci_enable_sdio_irq, 550 }; 551 552 static void pxamci_dma_irq(int dma, void *devid) 553 { 554 struct pxamci_host *host = devid; 555 int dcsr = DCSR(dma); 556 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; 557 558 if (dcsr & DCSR_ENDINTR) { 559 writel(BUF_PART_FULL, host->base + MMC_PRTBUF); 560 } else { 561 pr_err("%s: DMA error on channel %d (DCSR=%#x)\n", 562 mmc_hostname(host->mmc), dma, dcsr); 563 host->data->error = -EIO; 564 pxamci_data_done(host, 0); 565 } 566 } 567 568 static irqreturn_t pxamci_detect_irq(int irq, void *devid) 569 { 570 struct pxamci_host *host = mmc_priv(devid); 571 572 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms)); 573 return IRQ_HANDLED; 574 } 575 576 static int pxamci_probe(struct platform_device *pdev) 577 { 578 struct mmc_host *mmc; 579 struct pxamci_host *host = NULL; 580 struct resource *r, *dmarx, *dmatx; 581 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 582 583 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 584 irq = platform_get_irq(pdev, 0); 585 if (!r || irq < 0) 586 return -ENXIO; 587 588 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); 589 if (!r) 590 return -EBUSY; 591 592 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); 593 if (!mmc) { 594 ret = -ENOMEM; 595 goto out; 596 } 597 598 mmc->ops = &pxamci_ops; 599 600 /* 601 * We can do SG-DMA, but we don't because we never know how much 602 * data we successfully wrote to the card. 603 */ 604 mmc->max_segs = NR_SG; 605 606 /* 607 * Our hardware DMA can handle a maximum of one page per SG entry. 608 */ 609 mmc->max_seg_size = PAGE_SIZE; 610 611 /* 612 * Block length register is only 10 bits before PXA27x. 613 */ 614 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; 615 616 /* 617 * Block count register is 16 bits. 618 */ 619 mmc->max_blk_count = 65535; 620 621 host = mmc_priv(mmc); 622 host->mmc = mmc; 623 host->dma = -1; 624 host->pdata = pdev->dev.platform_data; 625 host->clkrt = CLKRT_OFF; 626 627 host->clk = clk_get(&pdev->dev, NULL); 628 if (IS_ERR(host->clk)) { 629 ret = PTR_ERR(host->clk); 630 host->clk = NULL; 631 goto out; 632 } 633 634 host->clkrate = clk_get_rate(host->clk); 635 636 /* 637 * Calculate minimum clock rate, rounding up. 638 */ 639 mmc->f_min = (host->clkrate + 63) / 64; 640 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; 641 642 pxamci_init_ocr(host); 643 644 mmc->caps = 0; 645 host->cmdat = 0; 646 if (!cpu_is_pxa25x()) { 647 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 648 host->cmdat |= CMDAT_SDIO_INT_EN; 649 if (mmc_has_26MHz()) 650 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | 651 MMC_CAP_SD_HIGHSPEED; 652 } 653 654 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); 655 if (!host->sg_cpu) { 656 ret = -ENOMEM; 657 goto out; 658 } 659 660 spin_lock_init(&host->lock); 661 host->res = r; 662 host->irq = irq; 663 host->imask = MMC_I_MASK_ALL; 664 665 host->base = ioremap(r->start, SZ_4K); 666 if (!host->base) { 667 ret = -ENOMEM; 668 goto out; 669 } 670 671 /* 672 * Ensure that the host controller is shut down, and setup 673 * with our defaults. 674 */ 675 pxamci_stop_clock(host); 676 writel(0, host->base + MMC_SPI); 677 writel(64, host->base + MMC_RESTO); 678 writel(host->imask, host->base + MMC_I_MASK); 679 680 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, 681 pxamci_dma_irq, host); 682 if (host->dma < 0) { 683 ret = -EBUSY; 684 goto out; 685 } 686 687 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); 688 if (ret) 689 goto out; 690 691 platform_set_drvdata(pdev, mmc); 692 693 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); 694 if (!dmarx) { 695 ret = -ENXIO; 696 goto out; 697 } 698 host->dma_drcmrrx = dmarx->start; 699 700 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); 701 if (!dmatx) { 702 ret = -ENXIO; 703 goto out; 704 } 705 host->dma_drcmrtx = dmatx->start; 706 707 if (host->pdata) { 708 gpio_cd = host->pdata->gpio_card_detect; 709 gpio_ro = host->pdata->gpio_card_ro; 710 gpio_power = host->pdata->gpio_power; 711 } 712 if (gpio_is_valid(gpio_power)) { 713 ret = gpio_request(gpio_power, "mmc card power"); 714 if (ret) { 715 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power); 716 goto out; 717 } 718 gpio_direction_output(gpio_power, 719 host->pdata->gpio_power_invert); 720 } 721 if (gpio_is_valid(gpio_ro)) { 722 ret = gpio_request(gpio_ro, "mmc card read only"); 723 if (ret) { 724 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro); 725 goto err_gpio_ro; 726 } 727 gpio_direction_input(gpio_ro); 728 } 729 if (gpio_is_valid(gpio_cd)) { 730 ret = gpio_request(gpio_cd, "mmc card detect"); 731 if (ret) { 732 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd); 733 goto err_gpio_cd; 734 } 735 gpio_direction_input(gpio_cd); 736 737 ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq, 738 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 739 "mmc card detect", mmc); 740 if (ret) { 741 dev_err(&pdev->dev, "failed to request card detect IRQ\n"); 742 goto err_request_irq; 743 } 744 } 745 746 if (host->pdata && host->pdata->init) 747 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); 748 749 if (gpio_is_valid(gpio_power) && host->pdata->setpower) 750 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n"); 751 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro) 752 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n"); 753 754 mmc_add_host(mmc); 755 756 return 0; 757 758 err_request_irq: 759 gpio_free(gpio_cd); 760 err_gpio_cd: 761 gpio_free(gpio_ro); 762 err_gpio_ro: 763 gpio_free(gpio_power); 764 out: 765 if (host) { 766 if (host->dma >= 0) 767 pxa_free_dma(host->dma); 768 if (host->base) 769 iounmap(host->base); 770 if (host->sg_cpu) 771 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 772 if (host->clk) 773 clk_put(host->clk); 774 } 775 if (mmc) 776 mmc_free_host(mmc); 777 release_resource(r); 778 return ret; 779 } 780 781 static int pxamci_remove(struct platform_device *pdev) 782 { 783 struct mmc_host *mmc = platform_get_drvdata(pdev); 784 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 785 786 platform_set_drvdata(pdev, NULL); 787 788 if (mmc) { 789 struct pxamci_host *host = mmc_priv(mmc); 790 791 mmc_remove_host(mmc); 792 793 if (host->pdata) { 794 gpio_cd = host->pdata->gpio_card_detect; 795 gpio_ro = host->pdata->gpio_card_ro; 796 gpio_power = host->pdata->gpio_power; 797 } 798 if (gpio_is_valid(gpio_cd)) { 799 free_irq(gpio_to_irq(gpio_cd), mmc); 800 gpio_free(gpio_cd); 801 } 802 if (gpio_is_valid(gpio_ro)) 803 gpio_free(gpio_ro); 804 if (gpio_is_valid(gpio_power)) 805 gpio_free(gpio_power); 806 if (host->vcc) 807 regulator_put(host->vcc); 808 809 if (host->pdata && host->pdata->exit) 810 host->pdata->exit(&pdev->dev, mmc); 811 812 pxamci_stop_clock(host); 813 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| 814 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, 815 host->base + MMC_I_MASK); 816 817 DRCMR(host->dma_drcmrrx) = 0; 818 DRCMR(host->dma_drcmrtx) = 0; 819 820 free_irq(host->irq, host); 821 pxa_free_dma(host->dma); 822 iounmap(host->base); 823 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 824 825 clk_put(host->clk); 826 827 release_resource(host->res); 828 829 mmc_free_host(mmc); 830 } 831 return 0; 832 } 833 834 #ifdef CONFIG_PM 835 static int pxamci_suspend(struct device *dev) 836 { 837 struct mmc_host *mmc = dev_get_drvdata(dev); 838 int ret = 0; 839 840 if (mmc) 841 ret = mmc_suspend_host(mmc); 842 843 return ret; 844 } 845 846 static int pxamci_resume(struct device *dev) 847 { 848 struct mmc_host *mmc = dev_get_drvdata(dev); 849 int ret = 0; 850 851 if (mmc) 852 ret = mmc_resume_host(mmc); 853 854 return ret; 855 } 856 857 static const struct dev_pm_ops pxamci_pm_ops = { 858 .suspend = pxamci_suspend, 859 .resume = pxamci_resume, 860 }; 861 #endif 862 863 static struct platform_driver pxamci_driver = { 864 .probe = pxamci_probe, 865 .remove = pxamci_remove, 866 .driver = { 867 .name = DRIVER_NAME, 868 .owner = THIS_MODULE, 869 #ifdef CONFIG_PM 870 .pm = &pxamci_pm_ops, 871 #endif 872 }, 873 }; 874 875 static int __init pxamci_init(void) 876 { 877 return platform_driver_register(&pxamci_driver); 878 } 879 880 static void __exit pxamci_exit(void) 881 { 882 platform_driver_unregister(&pxamci_driver); 883 } 884 885 module_init(pxamci_init); 886 module_exit(pxamci_exit); 887 888 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); 889 MODULE_LICENSE("GPL"); 890 MODULE_ALIAS("platform:pxa2xx-mci"); 891