1 /* 2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver 3 * 4 * Copyright (C) 2003 Russell King, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This hardware is really sick: 11 * - No way to clear interrupts. 12 * - Have to turn off the clock whenever we touch the device. 13 * - Doesn't tell you how many data blocks were transferred. 14 * Yuck! 15 * 16 * 1 and 3 byte data transfers not supported 17 * max block length up to 1023 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dma/pxa-dma.h> 28 #include <linux/clk.h> 29 #include <linux/err.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/io.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/gpio.h> 35 #include <linux/gfp.h> 36 #include <linux/of.h> 37 #include <linux/of_gpio.h> 38 #include <linux/of_device.h> 39 40 #include <asm/sizes.h> 41 42 #include <mach/hardware.h> 43 #include <linux/platform_data/mmc-pxamci.h> 44 45 #include "pxamci.h" 46 47 #define DRIVER_NAME "pxa2xx-mci" 48 49 #define NR_SG 1 50 #define CLKRT_OFF (~0) 51 52 #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ 53 || cpu_is_pxa935()) 54 55 struct pxamci_host { 56 struct mmc_host *mmc; 57 spinlock_t lock; 58 struct resource *res; 59 void __iomem *base; 60 struct clk *clk; 61 unsigned long clkrate; 62 int irq; 63 unsigned int clkrt; 64 unsigned int cmdat; 65 unsigned int imask; 66 unsigned int power_mode; 67 struct pxamci_platform_data *pdata; 68 69 struct mmc_request *mrq; 70 struct mmc_command *cmd; 71 struct mmc_data *data; 72 73 struct dma_chan *dma_chan_rx; 74 struct dma_chan *dma_chan_tx; 75 dma_cookie_t dma_cookie; 76 dma_addr_t sg_dma; 77 unsigned int dma_len; 78 79 unsigned int dma_dir; 80 unsigned int dma_drcmrrx; 81 unsigned int dma_drcmrtx; 82 83 struct regulator *vcc; 84 }; 85 86 static inline void pxamci_init_ocr(struct pxamci_host *host) 87 { 88 #ifdef CONFIG_REGULATOR 89 host->vcc = regulator_get_optional(mmc_dev(host->mmc), "vmmc"); 90 91 if (IS_ERR(host->vcc)) 92 host->vcc = NULL; 93 else { 94 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 95 if (host->pdata && host->pdata->ocr_mask) 96 dev_warn(mmc_dev(host->mmc), 97 "ocr_mask/setpower will not be used\n"); 98 } 99 #endif 100 if (host->vcc == NULL) { 101 /* fall-back to platform data */ 102 host->mmc->ocr_avail = host->pdata ? 103 host->pdata->ocr_mask : 104 MMC_VDD_32_33 | MMC_VDD_33_34; 105 } 106 } 107 108 static inline int pxamci_set_power(struct pxamci_host *host, 109 unsigned char power_mode, 110 unsigned int vdd) 111 { 112 int on; 113 114 if (host->vcc) { 115 int ret; 116 117 if (power_mode == MMC_POWER_UP) { 118 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 119 if (ret) 120 return ret; 121 } else if (power_mode == MMC_POWER_OFF) { 122 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 123 if (ret) 124 return ret; 125 } 126 } 127 if (!host->vcc && host->pdata && 128 gpio_is_valid(host->pdata->gpio_power)) { 129 on = ((1 << vdd) & host->pdata->ocr_mask); 130 gpio_set_value(host->pdata->gpio_power, 131 !!on ^ host->pdata->gpio_power_invert); 132 } 133 if (!host->vcc && host->pdata && host->pdata->setpower) 134 return host->pdata->setpower(mmc_dev(host->mmc), vdd); 135 136 return 0; 137 } 138 139 static void pxamci_stop_clock(struct pxamci_host *host) 140 { 141 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { 142 unsigned long timeout = 10000; 143 unsigned int v; 144 145 writel(STOP_CLOCK, host->base + MMC_STRPCL); 146 147 do { 148 v = readl(host->base + MMC_STAT); 149 if (!(v & STAT_CLK_EN)) 150 break; 151 udelay(1); 152 } while (timeout--); 153 154 if (v & STAT_CLK_EN) 155 dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); 156 } 157 } 158 159 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) 160 { 161 unsigned long flags; 162 163 spin_lock_irqsave(&host->lock, flags); 164 host->imask &= ~mask; 165 writel(host->imask, host->base + MMC_I_MASK); 166 spin_unlock_irqrestore(&host->lock, flags); 167 } 168 169 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) 170 { 171 unsigned long flags; 172 173 spin_lock_irqsave(&host->lock, flags); 174 host->imask |= mask; 175 writel(host->imask, host->base + MMC_I_MASK); 176 spin_unlock_irqrestore(&host->lock, flags); 177 } 178 179 static void pxamci_dma_irq(void *param); 180 181 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) 182 { 183 struct dma_async_tx_descriptor *tx; 184 enum dma_data_direction direction; 185 struct dma_slave_config config; 186 struct dma_chan *chan; 187 unsigned int nob = data->blocks; 188 unsigned long long clks; 189 unsigned int timeout; 190 int ret; 191 192 host->data = data; 193 194 if (data->flags & MMC_DATA_STREAM) 195 nob = 0xffff; 196 197 writel(nob, host->base + MMC_NOB); 198 writel(data->blksz, host->base + MMC_BLKLEN); 199 200 clks = (unsigned long long)data->timeout_ns * host->clkrate; 201 do_div(clks, 1000000000UL); 202 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); 203 writel((timeout + 255) / 256, host->base + MMC_RDTO); 204 205 memset(&config, 0, sizeof(config)); 206 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 207 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 208 config.src_addr = host->res->start + MMC_RXFIFO; 209 config.dst_addr = host->res->start + MMC_TXFIFO; 210 config.src_maxburst = 32; 211 config.dst_maxburst = 32; 212 213 if (data->flags & MMC_DATA_READ) { 214 host->dma_dir = DMA_FROM_DEVICE; 215 direction = DMA_DEV_TO_MEM; 216 chan = host->dma_chan_rx; 217 } else { 218 host->dma_dir = DMA_TO_DEVICE; 219 direction = DMA_MEM_TO_DEV; 220 chan = host->dma_chan_tx; 221 } 222 223 config.direction = direction; 224 225 ret = dmaengine_slave_config(chan, &config); 226 if (ret < 0) { 227 dev_err(mmc_dev(host->mmc), "dma slave config failed\n"); 228 return; 229 } 230 231 host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 232 host->dma_dir); 233 234 tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction, 235 DMA_PREP_INTERRUPT); 236 if (!tx) { 237 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 238 return; 239 } 240 241 if (!(data->flags & MMC_DATA_READ)) { 242 tx->callback = pxamci_dma_irq; 243 tx->callback_param = host; 244 } 245 246 host->dma_cookie = dmaengine_submit(tx); 247 248 /* 249 * workaround for erratum #91: 250 * only start DMA now if we are doing a read, 251 * otherwise we wait until CMD/RESP has finished 252 * before starting DMA. 253 */ 254 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) 255 dma_async_issue_pending(chan); 256 } 257 258 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) 259 { 260 WARN_ON(host->cmd != NULL); 261 host->cmd = cmd; 262 263 if (cmd->flags & MMC_RSP_BUSY) 264 cmdat |= CMDAT_BUSY; 265 266 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) 267 switch (RSP_TYPE(mmc_resp_type(cmd))) { 268 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ 269 cmdat |= CMDAT_RESP_SHORT; 270 break; 271 case RSP_TYPE(MMC_RSP_R3): 272 cmdat |= CMDAT_RESP_R3; 273 break; 274 case RSP_TYPE(MMC_RSP_R2): 275 cmdat |= CMDAT_RESP_R2; 276 break; 277 default: 278 break; 279 } 280 281 writel(cmd->opcode, host->base + MMC_CMD); 282 writel(cmd->arg >> 16, host->base + MMC_ARGH); 283 writel(cmd->arg & 0xffff, host->base + MMC_ARGL); 284 writel(cmdat, host->base + MMC_CMDAT); 285 writel(host->clkrt, host->base + MMC_CLKRT); 286 287 writel(START_CLOCK, host->base + MMC_STRPCL); 288 289 pxamci_enable_irq(host, END_CMD_RES); 290 } 291 292 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) 293 { 294 host->mrq = NULL; 295 host->cmd = NULL; 296 host->data = NULL; 297 mmc_request_done(host->mmc, mrq); 298 } 299 300 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) 301 { 302 struct mmc_command *cmd = host->cmd; 303 int i; 304 u32 v; 305 306 if (!cmd) 307 return 0; 308 309 host->cmd = NULL; 310 311 /* 312 * Did I mention this is Sick. We always need to 313 * discard the upper 8 bits of the first 16-bit word. 314 */ 315 v = readl(host->base + MMC_RES) & 0xffff; 316 for (i = 0; i < 4; i++) { 317 u32 w1 = readl(host->base + MMC_RES) & 0xffff; 318 u32 w2 = readl(host->base + MMC_RES) & 0xffff; 319 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; 320 v = w2; 321 } 322 323 if (stat & STAT_TIME_OUT_RESPONSE) { 324 cmd->error = -ETIMEDOUT; 325 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 326 /* 327 * workaround for erratum #42: 328 * Intel PXA27x Family Processor Specification Update Rev 001 329 * A bogus CRC error can appear if the msb of a 136 bit 330 * response is a one. 331 */ 332 if (cpu_is_pxa27x() && 333 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) 334 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); 335 else 336 cmd->error = -EILSEQ; 337 } 338 339 pxamci_disable_irq(host, END_CMD_RES); 340 if (host->data && !cmd->error) { 341 pxamci_enable_irq(host, DATA_TRAN_DONE); 342 /* 343 * workaround for erratum #91, if doing write 344 * enable DMA late 345 */ 346 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) 347 dma_async_issue_pending(host->dma_chan_tx); 348 } else { 349 pxamci_finish_request(host, host->mrq); 350 } 351 352 return 1; 353 } 354 355 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) 356 { 357 struct mmc_data *data = host->data; 358 struct dma_chan *chan; 359 360 if (!data) 361 return 0; 362 363 if (data->flags & MMC_DATA_READ) 364 chan = host->dma_chan_rx; 365 else 366 chan = host->dma_chan_tx; 367 dma_unmap_sg(chan->device->dev, 368 data->sg, data->sg_len, host->dma_dir); 369 370 if (stat & STAT_READ_TIME_OUT) 371 data->error = -ETIMEDOUT; 372 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) 373 data->error = -EILSEQ; 374 375 /* 376 * There appears to be a hardware design bug here. There seems to 377 * be no way to find out how much data was transferred to the card. 378 * This means that if there was an error on any block, we mark all 379 * data blocks as being in error. 380 */ 381 if (!data->error) 382 data->bytes_xfered = data->blocks * data->blksz; 383 else 384 data->bytes_xfered = 0; 385 386 pxamci_disable_irq(host, DATA_TRAN_DONE); 387 388 host->data = NULL; 389 if (host->mrq->stop) { 390 pxamci_stop_clock(host); 391 pxamci_start_cmd(host, host->mrq->stop, host->cmdat); 392 } else { 393 pxamci_finish_request(host, host->mrq); 394 } 395 396 return 1; 397 } 398 399 static irqreturn_t pxamci_irq(int irq, void *devid) 400 { 401 struct pxamci_host *host = devid; 402 unsigned int ireg; 403 int handled = 0; 404 405 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); 406 407 if (ireg) { 408 unsigned stat = readl(host->base + MMC_STAT); 409 410 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); 411 412 if (ireg & END_CMD_RES) 413 handled |= pxamci_cmd_done(host, stat); 414 if (ireg & DATA_TRAN_DONE) 415 handled |= pxamci_data_done(host, stat); 416 if (ireg & SDIO_INT) { 417 mmc_signal_sdio_irq(host->mmc); 418 handled = 1; 419 } 420 } 421 422 return IRQ_RETVAL(handled); 423 } 424 425 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) 426 { 427 struct pxamci_host *host = mmc_priv(mmc); 428 unsigned int cmdat; 429 430 WARN_ON(host->mrq != NULL); 431 432 host->mrq = mrq; 433 434 pxamci_stop_clock(host); 435 436 cmdat = host->cmdat; 437 host->cmdat &= ~CMDAT_INIT; 438 439 if (mrq->data) { 440 pxamci_setup_data(host, mrq->data); 441 442 cmdat &= ~CMDAT_BUSY; 443 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; 444 if (mrq->data->flags & MMC_DATA_WRITE) 445 cmdat |= CMDAT_WRITE; 446 447 if (mrq->data->flags & MMC_DATA_STREAM) 448 cmdat |= CMDAT_STREAM; 449 } 450 451 pxamci_start_cmd(host, mrq->cmd, cmdat); 452 } 453 454 static int pxamci_get_ro(struct mmc_host *mmc) 455 { 456 struct pxamci_host *host = mmc_priv(mmc); 457 458 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) 459 return mmc_gpio_get_ro(mmc); 460 if (host->pdata && host->pdata->get_ro) 461 return !!host->pdata->get_ro(mmc_dev(mmc)); 462 /* 463 * Board doesn't support read only detection; let the mmc core 464 * decide what to do. 465 */ 466 return -ENOSYS; 467 } 468 469 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 470 { 471 struct pxamci_host *host = mmc_priv(mmc); 472 473 if (ios->clock) { 474 unsigned long rate = host->clkrate; 475 unsigned int clk = rate / ios->clock; 476 477 if (host->clkrt == CLKRT_OFF) 478 clk_prepare_enable(host->clk); 479 480 if (ios->clock == 26000000) { 481 /* to support 26MHz */ 482 host->clkrt = 7; 483 } else { 484 /* to handle (19.5MHz, 26MHz) */ 485 if (!clk) 486 clk = 1; 487 488 /* 489 * clk might result in a lower divisor than we 490 * desire. check for that condition and adjust 491 * as appropriate. 492 */ 493 if (rate / clk > ios->clock) 494 clk <<= 1; 495 host->clkrt = fls(clk) - 1; 496 } 497 498 /* 499 * we write clkrt on the next command 500 */ 501 } else { 502 pxamci_stop_clock(host); 503 if (host->clkrt != CLKRT_OFF) { 504 host->clkrt = CLKRT_OFF; 505 clk_disable_unprepare(host->clk); 506 } 507 } 508 509 if (host->power_mode != ios->power_mode) { 510 int ret; 511 512 host->power_mode = ios->power_mode; 513 514 ret = pxamci_set_power(host, ios->power_mode, ios->vdd); 515 if (ret) { 516 dev_err(mmc_dev(mmc), "unable to set power\n"); 517 /* 518 * The .set_ios() function in the mmc_host_ops 519 * struct return void, and failing to set the 520 * power should be rare so we print an error and 521 * return here. 522 */ 523 return; 524 } 525 526 if (ios->power_mode == MMC_POWER_ON) 527 host->cmdat |= CMDAT_INIT; 528 } 529 530 if (ios->bus_width == MMC_BUS_WIDTH_4) 531 host->cmdat |= CMDAT_SD_4DAT; 532 else 533 host->cmdat &= ~CMDAT_SD_4DAT; 534 535 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n", 536 host->clkrt, host->cmdat); 537 } 538 539 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) 540 { 541 struct pxamci_host *pxa_host = mmc_priv(host); 542 543 if (enable) 544 pxamci_enable_irq(pxa_host, SDIO_INT); 545 else 546 pxamci_disable_irq(pxa_host, SDIO_INT); 547 } 548 549 static const struct mmc_host_ops pxamci_ops = { 550 .request = pxamci_request, 551 .get_cd = mmc_gpio_get_cd, 552 .get_ro = pxamci_get_ro, 553 .set_ios = pxamci_set_ios, 554 .enable_sdio_irq = pxamci_enable_sdio_irq, 555 }; 556 557 static void pxamci_dma_irq(void *param) 558 { 559 struct pxamci_host *host = param; 560 struct dma_tx_state state; 561 enum dma_status status; 562 struct dma_chan *chan; 563 unsigned long flags; 564 565 spin_lock_irqsave(&host->lock, flags); 566 567 if (!host->data) 568 goto out_unlock; 569 570 if (host->data->flags & MMC_DATA_READ) 571 chan = host->dma_chan_rx; 572 else 573 chan = host->dma_chan_tx; 574 575 status = dmaengine_tx_status(chan, host->dma_cookie, &state); 576 577 if (likely(status == DMA_COMPLETE)) { 578 writel(BUF_PART_FULL, host->base + MMC_PRTBUF); 579 } else { 580 pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc), 581 host->data->flags & MMC_DATA_READ ? "rx" : "tx"); 582 host->data->error = -EIO; 583 pxamci_data_done(host, 0); 584 } 585 586 out_unlock: 587 spin_unlock_irqrestore(&host->lock, flags); 588 } 589 590 static irqreturn_t pxamci_detect_irq(int irq, void *devid) 591 { 592 struct pxamci_host *host = mmc_priv(devid); 593 594 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms)); 595 return IRQ_HANDLED; 596 } 597 598 #ifdef CONFIG_OF 599 static const struct of_device_id pxa_mmc_dt_ids[] = { 600 { .compatible = "marvell,pxa-mmc" }, 601 { } 602 }; 603 604 MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids); 605 606 static int pxamci_of_init(struct platform_device *pdev) 607 { 608 struct device_node *np = pdev->dev.of_node; 609 struct pxamci_platform_data *pdata; 610 u32 tmp; 611 612 if (!np) 613 return 0; 614 615 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 616 if (!pdata) 617 return -ENOMEM; 618 619 pdata->gpio_card_detect = 620 of_get_named_gpio(np, "cd-gpios", 0); 621 pdata->gpio_card_ro = 622 of_get_named_gpio(np, "wp-gpios", 0); 623 624 /* pxa-mmc specific */ 625 pdata->gpio_power = 626 of_get_named_gpio(np, "pxa-mmc,gpio-power", 0); 627 628 if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0) 629 pdata->detect_delay_ms = tmp; 630 631 pdev->dev.platform_data = pdata; 632 633 return 0; 634 } 635 #else 636 static int pxamci_of_init(struct platform_device *pdev) 637 { 638 return 0; 639 } 640 #endif 641 642 static int pxamci_probe(struct platform_device *pdev) 643 { 644 struct mmc_host *mmc; 645 struct pxamci_host *host = NULL; 646 struct resource *r, *dmarx, *dmatx; 647 struct pxad_param param_rx, param_tx; 648 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 649 dma_cap_mask_t mask; 650 651 ret = pxamci_of_init(pdev); 652 if (ret) 653 return ret; 654 655 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 656 irq = platform_get_irq(pdev, 0); 657 if (!r || irq < 0) 658 return -ENXIO; 659 660 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); 661 if (!r) 662 return -EBUSY; 663 664 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); 665 if (!mmc) { 666 ret = -ENOMEM; 667 goto out; 668 } 669 670 mmc->ops = &pxamci_ops; 671 672 /* 673 * We can do SG-DMA, but we don't because we never know how much 674 * data we successfully wrote to the card. 675 */ 676 mmc->max_segs = NR_SG; 677 678 /* 679 * Our hardware DMA can handle a maximum of one page per SG entry. 680 */ 681 mmc->max_seg_size = PAGE_SIZE; 682 683 /* 684 * Block length register is only 10 bits before PXA27x. 685 */ 686 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; 687 688 /* 689 * Block count register is 16 bits. 690 */ 691 mmc->max_blk_count = 65535; 692 693 host = mmc_priv(mmc); 694 host->mmc = mmc; 695 host->pdata = pdev->dev.platform_data; 696 host->clkrt = CLKRT_OFF; 697 698 host->clk = clk_get(&pdev->dev, NULL); 699 if (IS_ERR(host->clk)) { 700 ret = PTR_ERR(host->clk); 701 host->clk = NULL; 702 goto out; 703 } 704 705 host->clkrate = clk_get_rate(host->clk); 706 707 /* 708 * Calculate minimum clock rate, rounding up. 709 */ 710 mmc->f_min = (host->clkrate + 63) / 64; 711 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; 712 713 pxamci_init_ocr(host); 714 715 mmc->caps = 0; 716 host->cmdat = 0; 717 if (!cpu_is_pxa25x()) { 718 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 719 host->cmdat |= CMDAT_SDIO_INT_EN; 720 if (mmc_has_26MHz()) 721 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | 722 MMC_CAP_SD_HIGHSPEED; 723 } 724 725 spin_lock_init(&host->lock); 726 host->res = r; 727 host->irq = irq; 728 host->imask = MMC_I_MASK_ALL; 729 730 host->base = ioremap(r->start, SZ_4K); 731 if (!host->base) { 732 ret = -ENOMEM; 733 goto out; 734 } 735 736 /* 737 * Ensure that the host controller is shut down, and setup 738 * with our defaults. 739 */ 740 pxamci_stop_clock(host); 741 writel(0, host->base + MMC_SPI); 742 writel(64, host->base + MMC_RESTO); 743 writel(host->imask, host->base + MMC_I_MASK); 744 745 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); 746 if (ret) 747 goto out; 748 749 platform_set_drvdata(pdev, mmc); 750 751 if (!pdev->dev.of_node) { 752 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); 753 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); 754 if (!dmarx || !dmatx) { 755 ret = -ENXIO; 756 goto out; 757 } 758 param_rx.prio = PXAD_PRIO_LOWEST; 759 param_rx.drcmr = dmarx->start; 760 param_tx.prio = PXAD_PRIO_LOWEST; 761 param_tx.drcmr = dmatx->start; 762 } 763 764 dma_cap_zero(mask); 765 dma_cap_set(DMA_SLAVE, mask); 766 767 host->dma_chan_rx = 768 dma_request_slave_channel_compat(mask, pxad_filter_fn, 769 ¶m_rx, &pdev->dev, "rx"); 770 if (host->dma_chan_rx == NULL) { 771 dev_err(&pdev->dev, "unable to request rx dma channel\n"); 772 ret = -ENODEV; 773 goto out; 774 } 775 776 host->dma_chan_tx = 777 dma_request_slave_channel_compat(mask, pxad_filter_fn, 778 ¶m_tx, &pdev->dev, "tx"); 779 if (host->dma_chan_tx == NULL) { 780 dev_err(&pdev->dev, "unable to request tx dma channel\n"); 781 ret = -ENODEV; 782 goto out; 783 } 784 785 if (host->pdata) { 786 gpio_cd = host->pdata->gpio_card_detect; 787 gpio_ro = host->pdata->gpio_card_ro; 788 gpio_power = host->pdata->gpio_power; 789 } 790 if (gpio_is_valid(gpio_power)) { 791 ret = devm_gpio_request(&pdev->dev, gpio_power, 792 "mmc card power"); 793 if (ret) { 794 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", 795 gpio_power); 796 goto out; 797 } 798 gpio_direction_output(gpio_power, 799 host->pdata->gpio_power_invert); 800 } 801 if (gpio_is_valid(gpio_ro)) 802 ret = mmc_gpio_request_ro(mmc, gpio_ro); 803 if (ret) { 804 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro); 805 goto out; 806 } else { 807 mmc->caps |= host->pdata->gpio_card_ro_invert ? 808 0 : MMC_CAP2_RO_ACTIVE_HIGH; 809 } 810 811 if (gpio_is_valid(gpio_cd)) 812 ret = mmc_gpio_request_cd(mmc, gpio_cd, 0); 813 if (ret) { 814 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd); 815 goto out; 816 } 817 818 if (host->pdata && host->pdata->init) 819 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); 820 821 if (gpio_is_valid(gpio_power) && host->pdata->setpower) 822 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n"); 823 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro) 824 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n"); 825 826 mmc_add_host(mmc); 827 828 return 0; 829 830 out: 831 if (host) { 832 if (host->dma_chan_rx) 833 dma_release_channel(host->dma_chan_rx); 834 if (host->dma_chan_tx) 835 dma_release_channel(host->dma_chan_tx); 836 if (host->base) 837 iounmap(host->base); 838 if (host->clk) 839 clk_put(host->clk); 840 } 841 if (mmc) 842 mmc_free_host(mmc); 843 release_resource(r); 844 return ret; 845 } 846 847 static int pxamci_remove(struct platform_device *pdev) 848 { 849 struct mmc_host *mmc = platform_get_drvdata(pdev); 850 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 851 852 if (mmc) { 853 struct pxamci_host *host = mmc_priv(mmc); 854 855 mmc_remove_host(mmc); 856 857 if (host->pdata) { 858 gpio_cd = host->pdata->gpio_card_detect; 859 gpio_ro = host->pdata->gpio_card_ro; 860 gpio_power = host->pdata->gpio_power; 861 } 862 if (host->vcc) 863 regulator_put(host->vcc); 864 865 if (host->pdata && host->pdata->exit) 866 host->pdata->exit(&pdev->dev, mmc); 867 868 pxamci_stop_clock(host); 869 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| 870 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, 871 host->base + MMC_I_MASK); 872 873 free_irq(host->irq, host); 874 dmaengine_terminate_all(host->dma_chan_rx); 875 dmaengine_terminate_all(host->dma_chan_tx); 876 dma_release_channel(host->dma_chan_rx); 877 dma_release_channel(host->dma_chan_tx); 878 iounmap(host->base); 879 880 clk_put(host->clk); 881 882 release_resource(host->res); 883 884 mmc_free_host(mmc); 885 } 886 return 0; 887 } 888 889 static struct platform_driver pxamci_driver = { 890 .probe = pxamci_probe, 891 .remove = pxamci_remove, 892 .driver = { 893 .name = DRIVER_NAME, 894 .of_match_table = of_match_ptr(pxa_mmc_dt_ids), 895 }, 896 }; 897 898 module_platform_driver(pxamci_driver); 899 900 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); 901 MODULE_LICENSE("GPL"); 902 MODULE_ALIAS("platform:pxa2xx-mci"); 903