1 /* 2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver 3 * 4 * Copyright (C) 2003 Russell King, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This hardware is really sick: 11 * - No way to clear interrupts. 12 * - Have to turn off the clock whenever we touch the device. 13 * - Doesn't tell you how many data blocks were transferred. 14 * Yuck! 15 * 16 * 1 and 3 byte data transfers not supported 17 * max block length up to 1023 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dma/pxa-dma.h> 28 #include <linux/clk.h> 29 #include <linux/err.h> 30 #include <linux/mmc/host.h> 31 #include <linux/io.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/gpio.h> 34 #include <linux/gfp.h> 35 #include <linux/of.h> 36 #include <linux/of_gpio.h> 37 #include <linux/of_device.h> 38 39 #include <asm/sizes.h> 40 41 #include <mach/hardware.h> 42 #include <linux/platform_data/mmc-pxamci.h> 43 44 #include "pxamci.h" 45 46 #define DRIVER_NAME "pxa2xx-mci" 47 48 #define NR_SG 1 49 #define CLKRT_OFF (~0) 50 51 #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ 52 || cpu_is_pxa935()) 53 54 struct pxamci_host { 55 struct mmc_host *mmc; 56 spinlock_t lock; 57 struct resource *res; 58 void __iomem *base; 59 struct clk *clk; 60 unsigned long clkrate; 61 int irq; 62 unsigned int clkrt; 63 unsigned int cmdat; 64 unsigned int imask; 65 unsigned int power_mode; 66 struct pxamci_platform_data *pdata; 67 68 struct mmc_request *mrq; 69 struct mmc_command *cmd; 70 struct mmc_data *data; 71 72 struct dma_chan *dma_chan_rx; 73 struct dma_chan *dma_chan_tx; 74 dma_cookie_t dma_cookie; 75 dma_addr_t sg_dma; 76 unsigned int dma_len; 77 78 unsigned int dma_dir; 79 unsigned int dma_drcmrrx; 80 unsigned int dma_drcmrtx; 81 82 struct regulator *vcc; 83 }; 84 85 static inline void pxamci_init_ocr(struct pxamci_host *host) 86 { 87 #ifdef CONFIG_REGULATOR 88 host->vcc = regulator_get_optional(mmc_dev(host->mmc), "vmmc"); 89 90 if (IS_ERR(host->vcc)) 91 host->vcc = NULL; 92 else { 93 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 94 if (host->pdata && host->pdata->ocr_mask) 95 dev_warn(mmc_dev(host->mmc), 96 "ocr_mask/setpower will not be used\n"); 97 } 98 #endif 99 if (host->vcc == NULL) { 100 /* fall-back to platform data */ 101 host->mmc->ocr_avail = host->pdata ? 102 host->pdata->ocr_mask : 103 MMC_VDD_32_33 | MMC_VDD_33_34; 104 } 105 } 106 107 static inline int pxamci_set_power(struct pxamci_host *host, 108 unsigned char power_mode, 109 unsigned int vdd) 110 { 111 int on; 112 113 if (host->vcc) { 114 int ret; 115 116 if (power_mode == MMC_POWER_UP) { 117 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 118 if (ret) 119 return ret; 120 } else if (power_mode == MMC_POWER_OFF) { 121 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 122 if (ret) 123 return ret; 124 } 125 } 126 if (!host->vcc && host->pdata && 127 gpio_is_valid(host->pdata->gpio_power)) { 128 on = ((1 << vdd) & host->pdata->ocr_mask); 129 gpio_set_value(host->pdata->gpio_power, 130 !!on ^ host->pdata->gpio_power_invert); 131 } 132 if (!host->vcc && host->pdata && host->pdata->setpower) 133 return host->pdata->setpower(mmc_dev(host->mmc), vdd); 134 135 return 0; 136 } 137 138 static void pxamci_stop_clock(struct pxamci_host *host) 139 { 140 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { 141 unsigned long timeout = 10000; 142 unsigned int v; 143 144 writel(STOP_CLOCK, host->base + MMC_STRPCL); 145 146 do { 147 v = readl(host->base + MMC_STAT); 148 if (!(v & STAT_CLK_EN)) 149 break; 150 udelay(1); 151 } while (timeout--); 152 153 if (v & STAT_CLK_EN) 154 dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); 155 } 156 } 157 158 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) 159 { 160 unsigned long flags; 161 162 spin_lock_irqsave(&host->lock, flags); 163 host->imask &= ~mask; 164 writel(host->imask, host->base + MMC_I_MASK); 165 spin_unlock_irqrestore(&host->lock, flags); 166 } 167 168 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) 169 { 170 unsigned long flags; 171 172 spin_lock_irqsave(&host->lock, flags); 173 host->imask |= mask; 174 writel(host->imask, host->base + MMC_I_MASK); 175 spin_unlock_irqrestore(&host->lock, flags); 176 } 177 178 static void pxamci_dma_irq(void *param); 179 180 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) 181 { 182 struct dma_async_tx_descriptor *tx; 183 enum dma_data_direction direction; 184 struct dma_slave_config config; 185 struct dma_chan *chan; 186 unsigned int nob = data->blocks; 187 unsigned long long clks; 188 unsigned int timeout; 189 int ret; 190 191 host->data = data; 192 193 if (data->flags & MMC_DATA_STREAM) 194 nob = 0xffff; 195 196 writel(nob, host->base + MMC_NOB); 197 writel(data->blksz, host->base + MMC_BLKLEN); 198 199 clks = (unsigned long long)data->timeout_ns * host->clkrate; 200 do_div(clks, 1000000000UL); 201 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); 202 writel((timeout + 255) / 256, host->base + MMC_RDTO); 203 204 memset(&config, 0, sizeof(config)); 205 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 206 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 207 config.src_addr = host->res->start + MMC_RXFIFO; 208 config.dst_addr = host->res->start + MMC_TXFIFO; 209 config.src_maxburst = 32; 210 config.dst_maxburst = 32; 211 212 if (data->flags & MMC_DATA_READ) { 213 host->dma_dir = DMA_FROM_DEVICE; 214 direction = DMA_DEV_TO_MEM; 215 chan = host->dma_chan_rx; 216 } else { 217 host->dma_dir = DMA_TO_DEVICE; 218 direction = DMA_MEM_TO_DEV; 219 chan = host->dma_chan_tx; 220 } 221 222 config.direction = direction; 223 224 ret = dmaengine_slave_config(chan, &config); 225 if (ret < 0) { 226 dev_err(mmc_dev(host->mmc), "dma slave config failed\n"); 227 return; 228 } 229 230 host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 231 host->dma_dir); 232 233 tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction, 234 DMA_PREP_INTERRUPT); 235 if (!tx) { 236 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 237 return; 238 } 239 240 if (!(data->flags & MMC_DATA_READ)) { 241 tx->callback = pxamci_dma_irq; 242 tx->callback_param = host; 243 } 244 245 host->dma_cookie = dmaengine_submit(tx); 246 247 /* 248 * workaround for erratum #91: 249 * only start DMA now if we are doing a read, 250 * otherwise we wait until CMD/RESP has finished 251 * before starting DMA. 252 */ 253 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) 254 dma_async_issue_pending(chan); 255 } 256 257 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) 258 { 259 WARN_ON(host->cmd != NULL); 260 host->cmd = cmd; 261 262 if (cmd->flags & MMC_RSP_BUSY) 263 cmdat |= CMDAT_BUSY; 264 265 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) 266 switch (RSP_TYPE(mmc_resp_type(cmd))) { 267 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ 268 cmdat |= CMDAT_RESP_SHORT; 269 break; 270 case RSP_TYPE(MMC_RSP_R3): 271 cmdat |= CMDAT_RESP_R3; 272 break; 273 case RSP_TYPE(MMC_RSP_R2): 274 cmdat |= CMDAT_RESP_R2; 275 break; 276 default: 277 break; 278 } 279 280 writel(cmd->opcode, host->base + MMC_CMD); 281 writel(cmd->arg >> 16, host->base + MMC_ARGH); 282 writel(cmd->arg & 0xffff, host->base + MMC_ARGL); 283 writel(cmdat, host->base + MMC_CMDAT); 284 writel(host->clkrt, host->base + MMC_CLKRT); 285 286 writel(START_CLOCK, host->base + MMC_STRPCL); 287 288 pxamci_enable_irq(host, END_CMD_RES); 289 } 290 291 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) 292 { 293 host->mrq = NULL; 294 host->cmd = NULL; 295 host->data = NULL; 296 mmc_request_done(host->mmc, mrq); 297 } 298 299 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) 300 { 301 struct mmc_command *cmd = host->cmd; 302 int i; 303 u32 v; 304 305 if (!cmd) 306 return 0; 307 308 host->cmd = NULL; 309 310 /* 311 * Did I mention this is Sick. We always need to 312 * discard the upper 8 bits of the first 16-bit word. 313 */ 314 v = readl(host->base + MMC_RES) & 0xffff; 315 for (i = 0; i < 4; i++) { 316 u32 w1 = readl(host->base + MMC_RES) & 0xffff; 317 u32 w2 = readl(host->base + MMC_RES) & 0xffff; 318 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; 319 v = w2; 320 } 321 322 if (stat & STAT_TIME_OUT_RESPONSE) { 323 cmd->error = -ETIMEDOUT; 324 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 325 /* 326 * workaround for erratum #42: 327 * Intel PXA27x Family Processor Specification Update Rev 001 328 * A bogus CRC error can appear if the msb of a 136 bit 329 * response is a one. 330 */ 331 if (cpu_is_pxa27x() && 332 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) 333 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); 334 else 335 cmd->error = -EILSEQ; 336 } 337 338 pxamci_disable_irq(host, END_CMD_RES); 339 if (host->data && !cmd->error) { 340 pxamci_enable_irq(host, DATA_TRAN_DONE); 341 /* 342 * workaround for erratum #91, if doing write 343 * enable DMA late 344 */ 345 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) 346 dma_async_issue_pending(host->dma_chan_tx); 347 } else { 348 pxamci_finish_request(host, host->mrq); 349 } 350 351 return 1; 352 } 353 354 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) 355 { 356 struct mmc_data *data = host->data; 357 struct dma_chan *chan; 358 359 if (!data) 360 return 0; 361 362 if (data->flags & MMC_DATA_READ) 363 chan = host->dma_chan_rx; 364 else 365 chan = host->dma_chan_tx; 366 dma_unmap_sg(chan->device->dev, 367 data->sg, data->sg_len, host->dma_dir); 368 369 if (stat & STAT_READ_TIME_OUT) 370 data->error = -ETIMEDOUT; 371 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) 372 data->error = -EILSEQ; 373 374 /* 375 * There appears to be a hardware design bug here. There seems to 376 * be no way to find out how much data was transferred to the card. 377 * This means that if there was an error on any block, we mark all 378 * data blocks as being in error. 379 */ 380 if (!data->error) 381 data->bytes_xfered = data->blocks * data->blksz; 382 else 383 data->bytes_xfered = 0; 384 385 pxamci_disable_irq(host, DATA_TRAN_DONE); 386 387 host->data = NULL; 388 if (host->mrq->stop) { 389 pxamci_stop_clock(host); 390 pxamci_start_cmd(host, host->mrq->stop, host->cmdat); 391 } else { 392 pxamci_finish_request(host, host->mrq); 393 } 394 395 return 1; 396 } 397 398 static irqreturn_t pxamci_irq(int irq, void *devid) 399 { 400 struct pxamci_host *host = devid; 401 unsigned int ireg; 402 int handled = 0; 403 404 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); 405 406 if (ireg) { 407 unsigned stat = readl(host->base + MMC_STAT); 408 409 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); 410 411 if (ireg & END_CMD_RES) 412 handled |= pxamci_cmd_done(host, stat); 413 if (ireg & DATA_TRAN_DONE) 414 handled |= pxamci_data_done(host, stat); 415 if (ireg & SDIO_INT) { 416 mmc_signal_sdio_irq(host->mmc); 417 handled = 1; 418 } 419 } 420 421 return IRQ_RETVAL(handled); 422 } 423 424 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) 425 { 426 struct pxamci_host *host = mmc_priv(mmc); 427 unsigned int cmdat; 428 429 WARN_ON(host->mrq != NULL); 430 431 host->mrq = mrq; 432 433 pxamci_stop_clock(host); 434 435 cmdat = host->cmdat; 436 host->cmdat &= ~CMDAT_INIT; 437 438 if (mrq->data) { 439 pxamci_setup_data(host, mrq->data); 440 441 cmdat &= ~CMDAT_BUSY; 442 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; 443 if (mrq->data->flags & MMC_DATA_WRITE) 444 cmdat |= CMDAT_WRITE; 445 446 if (mrq->data->flags & MMC_DATA_STREAM) 447 cmdat |= CMDAT_STREAM; 448 } 449 450 pxamci_start_cmd(host, mrq->cmd, cmdat); 451 } 452 453 static int pxamci_get_ro(struct mmc_host *mmc) 454 { 455 struct pxamci_host *host = mmc_priv(mmc); 456 457 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) { 458 if (host->pdata->gpio_card_ro_invert) 459 return !gpio_get_value(host->pdata->gpio_card_ro); 460 else 461 return gpio_get_value(host->pdata->gpio_card_ro); 462 } 463 if (host->pdata && host->pdata->get_ro) 464 return !!host->pdata->get_ro(mmc_dev(mmc)); 465 /* 466 * Board doesn't support read only detection; let the mmc core 467 * decide what to do. 468 */ 469 return -ENOSYS; 470 } 471 472 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 473 { 474 struct pxamci_host *host = mmc_priv(mmc); 475 476 if (ios->clock) { 477 unsigned long rate = host->clkrate; 478 unsigned int clk = rate / ios->clock; 479 480 if (host->clkrt == CLKRT_OFF) 481 clk_prepare_enable(host->clk); 482 483 if (ios->clock == 26000000) { 484 /* to support 26MHz */ 485 host->clkrt = 7; 486 } else { 487 /* to handle (19.5MHz, 26MHz) */ 488 if (!clk) 489 clk = 1; 490 491 /* 492 * clk might result in a lower divisor than we 493 * desire. check for that condition and adjust 494 * as appropriate. 495 */ 496 if (rate / clk > ios->clock) 497 clk <<= 1; 498 host->clkrt = fls(clk) - 1; 499 } 500 501 /* 502 * we write clkrt on the next command 503 */ 504 } else { 505 pxamci_stop_clock(host); 506 if (host->clkrt != CLKRT_OFF) { 507 host->clkrt = CLKRT_OFF; 508 clk_disable_unprepare(host->clk); 509 } 510 } 511 512 if (host->power_mode != ios->power_mode) { 513 int ret; 514 515 host->power_mode = ios->power_mode; 516 517 ret = pxamci_set_power(host, ios->power_mode, ios->vdd); 518 if (ret) { 519 dev_err(mmc_dev(mmc), "unable to set power\n"); 520 /* 521 * The .set_ios() function in the mmc_host_ops 522 * struct return void, and failing to set the 523 * power should be rare so we print an error and 524 * return here. 525 */ 526 return; 527 } 528 529 if (ios->power_mode == MMC_POWER_ON) 530 host->cmdat |= CMDAT_INIT; 531 } 532 533 if (ios->bus_width == MMC_BUS_WIDTH_4) 534 host->cmdat |= CMDAT_SD_4DAT; 535 else 536 host->cmdat &= ~CMDAT_SD_4DAT; 537 538 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n", 539 host->clkrt, host->cmdat); 540 } 541 542 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) 543 { 544 struct pxamci_host *pxa_host = mmc_priv(host); 545 546 if (enable) 547 pxamci_enable_irq(pxa_host, SDIO_INT); 548 else 549 pxamci_disable_irq(pxa_host, SDIO_INT); 550 } 551 552 static const struct mmc_host_ops pxamci_ops = { 553 .request = pxamci_request, 554 .get_ro = pxamci_get_ro, 555 .set_ios = pxamci_set_ios, 556 .enable_sdio_irq = pxamci_enable_sdio_irq, 557 }; 558 559 static void pxamci_dma_irq(void *param) 560 { 561 struct pxamci_host *host = param; 562 struct dma_tx_state state; 563 enum dma_status status; 564 struct dma_chan *chan; 565 unsigned long flags; 566 567 spin_lock_irqsave(&host->lock, flags); 568 569 if (!host->data) 570 goto out_unlock; 571 572 if (host->data->flags & MMC_DATA_READ) 573 chan = host->dma_chan_rx; 574 else 575 chan = host->dma_chan_tx; 576 577 status = dmaengine_tx_status(chan, host->dma_cookie, &state); 578 579 if (likely(status == DMA_COMPLETE)) { 580 writel(BUF_PART_FULL, host->base + MMC_PRTBUF); 581 } else { 582 pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc), 583 host->data->flags & MMC_DATA_READ ? "rx" : "tx"); 584 host->data->error = -EIO; 585 pxamci_data_done(host, 0); 586 } 587 588 out_unlock: 589 spin_unlock_irqrestore(&host->lock, flags); 590 } 591 592 static irqreturn_t pxamci_detect_irq(int irq, void *devid) 593 { 594 struct pxamci_host *host = mmc_priv(devid); 595 596 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms)); 597 return IRQ_HANDLED; 598 } 599 600 #ifdef CONFIG_OF 601 static const struct of_device_id pxa_mmc_dt_ids[] = { 602 { .compatible = "marvell,pxa-mmc" }, 603 { } 604 }; 605 606 MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids); 607 608 static int pxamci_of_init(struct platform_device *pdev) 609 { 610 struct device_node *np = pdev->dev.of_node; 611 struct pxamci_platform_data *pdata; 612 u32 tmp; 613 614 if (!np) 615 return 0; 616 617 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 618 if (!pdata) 619 return -ENOMEM; 620 621 pdata->gpio_card_detect = 622 of_get_named_gpio(np, "cd-gpios", 0); 623 pdata->gpio_card_ro = 624 of_get_named_gpio(np, "wp-gpios", 0); 625 626 /* pxa-mmc specific */ 627 pdata->gpio_power = 628 of_get_named_gpio(np, "pxa-mmc,gpio-power", 0); 629 630 if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0) 631 pdata->detect_delay_ms = tmp; 632 633 pdev->dev.platform_data = pdata; 634 635 return 0; 636 } 637 #else 638 static int pxamci_of_init(struct platform_device *pdev) 639 { 640 return 0; 641 } 642 #endif 643 644 static int pxamci_probe(struct platform_device *pdev) 645 { 646 struct mmc_host *mmc; 647 struct pxamci_host *host = NULL; 648 struct resource *r, *dmarx, *dmatx; 649 struct pxad_param param_rx, param_tx; 650 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 651 dma_cap_mask_t mask; 652 653 ret = pxamci_of_init(pdev); 654 if (ret) 655 return ret; 656 657 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 658 irq = platform_get_irq(pdev, 0); 659 if (!r || irq < 0) 660 return -ENXIO; 661 662 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); 663 if (!r) 664 return -EBUSY; 665 666 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); 667 if (!mmc) { 668 ret = -ENOMEM; 669 goto out; 670 } 671 672 mmc->ops = &pxamci_ops; 673 674 /* 675 * We can do SG-DMA, but we don't because we never know how much 676 * data we successfully wrote to the card. 677 */ 678 mmc->max_segs = NR_SG; 679 680 /* 681 * Our hardware DMA can handle a maximum of one page per SG entry. 682 */ 683 mmc->max_seg_size = PAGE_SIZE; 684 685 /* 686 * Block length register is only 10 bits before PXA27x. 687 */ 688 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; 689 690 /* 691 * Block count register is 16 bits. 692 */ 693 mmc->max_blk_count = 65535; 694 695 host = mmc_priv(mmc); 696 host->mmc = mmc; 697 host->pdata = pdev->dev.platform_data; 698 host->clkrt = CLKRT_OFF; 699 700 host->clk = clk_get(&pdev->dev, NULL); 701 if (IS_ERR(host->clk)) { 702 ret = PTR_ERR(host->clk); 703 host->clk = NULL; 704 goto out; 705 } 706 707 host->clkrate = clk_get_rate(host->clk); 708 709 /* 710 * Calculate minimum clock rate, rounding up. 711 */ 712 mmc->f_min = (host->clkrate + 63) / 64; 713 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; 714 715 pxamci_init_ocr(host); 716 717 mmc->caps = 0; 718 host->cmdat = 0; 719 if (!cpu_is_pxa25x()) { 720 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 721 host->cmdat |= CMDAT_SDIO_INT_EN; 722 if (mmc_has_26MHz()) 723 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | 724 MMC_CAP_SD_HIGHSPEED; 725 } 726 727 spin_lock_init(&host->lock); 728 host->res = r; 729 host->irq = irq; 730 host->imask = MMC_I_MASK_ALL; 731 732 host->base = ioremap(r->start, SZ_4K); 733 if (!host->base) { 734 ret = -ENOMEM; 735 goto out; 736 } 737 738 /* 739 * Ensure that the host controller is shut down, and setup 740 * with our defaults. 741 */ 742 pxamci_stop_clock(host); 743 writel(0, host->base + MMC_SPI); 744 writel(64, host->base + MMC_RESTO); 745 writel(host->imask, host->base + MMC_I_MASK); 746 747 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); 748 if (ret) 749 goto out; 750 751 platform_set_drvdata(pdev, mmc); 752 753 if (!pdev->dev.of_node) { 754 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); 755 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); 756 if (!dmarx || !dmatx) { 757 ret = -ENXIO; 758 goto out; 759 } 760 param_rx.prio = PXAD_PRIO_LOWEST; 761 param_rx.drcmr = dmarx->start; 762 param_tx.prio = PXAD_PRIO_LOWEST; 763 param_tx.drcmr = dmatx->start; 764 } 765 766 dma_cap_zero(mask); 767 dma_cap_set(DMA_SLAVE, mask); 768 769 host->dma_chan_rx = 770 dma_request_slave_channel_compat(mask, pxad_filter_fn, 771 ¶m_rx, &pdev->dev, "rx"); 772 if (host->dma_chan_rx == NULL) { 773 dev_err(&pdev->dev, "unable to request rx dma channel\n"); 774 ret = -ENODEV; 775 goto out; 776 } 777 778 host->dma_chan_tx = 779 dma_request_slave_channel_compat(mask, pxad_filter_fn, 780 ¶m_tx, &pdev->dev, "tx"); 781 if (host->dma_chan_tx == NULL) { 782 dev_err(&pdev->dev, "unable to request tx dma channel\n"); 783 ret = -ENODEV; 784 goto out; 785 } 786 787 if (host->pdata) { 788 gpio_cd = host->pdata->gpio_card_detect; 789 gpio_ro = host->pdata->gpio_card_ro; 790 gpio_power = host->pdata->gpio_power; 791 } 792 if (gpio_is_valid(gpio_power)) { 793 ret = gpio_request(gpio_power, "mmc card power"); 794 if (ret) { 795 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power); 796 goto out; 797 } 798 gpio_direction_output(gpio_power, 799 host->pdata->gpio_power_invert); 800 } 801 if (gpio_is_valid(gpio_ro)) { 802 ret = gpio_request(gpio_ro, "mmc card read only"); 803 if (ret) { 804 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro); 805 goto err_gpio_ro; 806 } 807 gpio_direction_input(gpio_ro); 808 } 809 if (gpio_is_valid(gpio_cd)) { 810 ret = gpio_request(gpio_cd, "mmc card detect"); 811 if (ret) { 812 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd); 813 goto err_gpio_cd; 814 } 815 gpio_direction_input(gpio_cd); 816 817 ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq, 818 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 819 "mmc card detect", mmc); 820 if (ret) { 821 dev_err(&pdev->dev, "failed to request card detect IRQ\n"); 822 goto err_request_irq; 823 } 824 } 825 826 if (host->pdata && host->pdata->init) 827 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); 828 829 if (gpio_is_valid(gpio_power) && host->pdata->setpower) 830 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n"); 831 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro) 832 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n"); 833 834 mmc_add_host(mmc); 835 836 return 0; 837 838 err_request_irq: 839 gpio_free(gpio_cd); 840 err_gpio_cd: 841 gpio_free(gpio_ro); 842 err_gpio_ro: 843 gpio_free(gpio_power); 844 out: 845 if (host) { 846 if (host->dma_chan_rx) 847 dma_release_channel(host->dma_chan_rx); 848 if (host->dma_chan_tx) 849 dma_release_channel(host->dma_chan_tx); 850 if (host->base) 851 iounmap(host->base); 852 if (host->clk) 853 clk_put(host->clk); 854 } 855 if (mmc) 856 mmc_free_host(mmc); 857 release_resource(r); 858 return ret; 859 } 860 861 static int pxamci_remove(struct platform_device *pdev) 862 { 863 struct mmc_host *mmc = platform_get_drvdata(pdev); 864 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; 865 866 if (mmc) { 867 struct pxamci_host *host = mmc_priv(mmc); 868 869 mmc_remove_host(mmc); 870 871 if (host->pdata) { 872 gpio_cd = host->pdata->gpio_card_detect; 873 gpio_ro = host->pdata->gpio_card_ro; 874 gpio_power = host->pdata->gpio_power; 875 } 876 if (gpio_is_valid(gpio_cd)) { 877 free_irq(gpio_to_irq(gpio_cd), mmc); 878 gpio_free(gpio_cd); 879 } 880 if (gpio_is_valid(gpio_ro)) 881 gpio_free(gpio_ro); 882 if (gpio_is_valid(gpio_power)) 883 gpio_free(gpio_power); 884 if (host->vcc) 885 regulator_put(host->vcc); 886 887 if (host->pdata && host->pdata->exit) 888 host->pdata->exit(&pdev->dev, mmc); 889 890 pxamci_stop_clock(host); 891 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| 892 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, 893 host->base + MMC_I_MASK); 894 895 free_irq(host->irq, host); 896 dmaengine_terminate_all(host->dma_chan_rx); 897 dmaengine_terminate_all(host->dma_chan_tx); 898 dma_release_channel(host->dma_chan_rx); 899 dma_release_channel(host->dma_chan_tx); 900 iounmap(host->base); 901 902 clk_put(host->clk); 903 904 release_resource(host->res); 905 906 mmc_free_host(mmc); 907 } 908 return 0; 909 } 910 911 static struct platform_driver pxamci_driver = { 912 .probe = pxamci_probe, 913 .remove = pxamci_remove, 914 .driver = { 915 .name = DRIVER_NAME, 916 .of_match_table = of_match_ptr(pxa_mmc_dt_ids), 917 }, 918 }; 919 920 module_platform_driver(pxamci_driver); 921 922 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); 923 MODULE_LICENSE("GPL"); 924 MODULE_ALIAS("platform:pxa2xx-mci"); 925