1ff65ffe4SManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0-or-later 2ff65ffe4SManivannan Sadhasivam /* 3ff65ffe4SManivannan Sadhasivam * Actions Semi Owl SoCs SD/MMC driver 4ff65ffe4SManivannan Sadhasivam * 5ff65ffe4SManivannan Sadhasivam * Copyright (c) 2014 Actions Semi Inc. 6ff65ffe4SManivannan Sadhasivam * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7ff65ffe4SManivannan Sadhasivam * 8ff65ffe4SManivannan Sadhasivam * TODO: SDIO support 9ff65ffe4SManivannan Sadhasivam */ 10ff65ffe4SManivannan Sadhasivam 11ff65ffe4SManivannan Sadhasivam #include <linux/clk.h> 12ff65ffe4SManivannan Sadhasivam #include <linux/delay.h> 13ff65ffe4SManivannan Sadhasivam #include <linux/dmaengine.h> 14ff65ffe4SManivannan Sadhasivam #include <linux/dma-direction.h> 15ff65ffe4SManivannan Sadhasivam #include <linux/dma-mapping.h> 16ff65ffe4SManivannan Sadhasivam #include <linux/interrupt.h> 17ff65ffe4SManivannan Sadhasivam #include <linux/mmc/host.h> 18ff65ffe4SManivannan Sadhasivam #include <linux/mmc/slot-gpio.h> 19ff65ffe4SManivannan Sadhasivam #include <linux/module.h> 20ff65ffe4SManivannan Sadhasivam #include <linux/of_platform.h> 21ff65ffe4SManivannan Sadhasivam #include <linux/reset.h> 22ff65ffe4SManivannan Sadhasivam #include <linux/spinlock.h> 23ff65ffe4SManivannan Sadhasivam 24ff65ffe4SManivannan Sadhasivam /* 25ff65ffe4SManivannan Sadhasivam * SDC registers 26ff65ffe4SManivannan Sadhasivam */ 27ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_EN 0x0000 28ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_CTL 0x0004 29ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_STATE 0x0008 30ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_CMD 0x000c 31ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_ARG 0x0010 32ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF0 0x0014 33ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF1 0x0018 34ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF2 0x001c 35ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF3 0x0020 36ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF4 0x0024 37ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_DAT 0x0028 38ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BLK_SIZE 0x002c 39ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BLK_NUM 0x0030 40ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BUF_SIZE 0x0034 41ff65ffe4SManivannan Sadhasivam 42ff65ffe4SManivannan Sadhasivam /* SD_EN Bits */ 43ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RANE BIT(31) 44ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24) 45ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_S18EN BIT(12) 46ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RESE BIT(10) 47ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DAT1_S BIT(9) 48ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_CLK_S BIT(8) 49ff65ffe4SManivannan Sadhasivam #define OWL_SD_ENABLE BIT(7) 50ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_BSEL BIT(6) 51ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_SDIOEN BIT(3) 52ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DDREN BIT(2) 53ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0) 54ff65ffe4SManivannan Sadhasivam 55ff65ffe4SManivannan Sadhasivam /* SD_CTL Bits */ 56ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TOUTEN BIT(31) 57ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24) 58ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16) 59ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20) 60ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16) 61ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_CMDLEN BIT(13) 62ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_SCC BIT(12) 63ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8) 64ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TS BIT(7) 65ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_LBE BIT(6) 66ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_C7EN BIT(5) 67ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0) 68ff65ffe4SManivannan Sadhasivam 69ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_LOW_CLK 0x0f 70ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_MID_CLK 0x0a 71ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_HIGH_CLK 0x09 72ff65ffe4SManivannan Sadhasivam #define OWL_SD_RDELAY_DDR50 0x0a 73ff65ffe4SManivannan Sadhasivam #define OWL_SD_WDELAY_DDR50 0x08 74ff65ffe4SManivannan Sadhasivam 75ff65ffe4SManivannan Sadhasivam /* SD_STATE Bits */ 76ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT1BS BIT(18) 77ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOB_P BIT(17) 78ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOB_EN BIT(16) 79ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TOUTE BIT(15) 80ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_BAEP BIT(14) 81ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_MEMRDY BIT(12) 82ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CMDS BIT(11) 83ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT1AS BIT(10) 84ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOA_P BIT(9) 85ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOA_EN BIT(8) 86ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT0S BIT(7) 87ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TEIE BIT(6) 88ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TEI BIT(5) 89ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CLNR BIT(4) 90ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CLC BIT(3) 91ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_WC16ER BIT(2) 92ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_RC16ER BIT(1) 93ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CRC7ER BIT(0) 94ff65ffe4SManivannan Sadhasivam 95f37ac1aeSUlf Hansson #define OWL_CMD_TIMEOUT_MS 30000 96f37ac1aeSUlf Hansson 97ff65ffe4SManivannan Sadhasivam struct owl_mmc_host { 98ff65ffe4SManivannan Sadhasivam struct device *dev; 99ff65ffe4SManivannan Sadhasivam struct reset_control *reset; 100ff65ffe4SManivannan Sadhasivam void __iomem *base; 101ff65ffe4SManivannan Sadhasivam struct clk *clk; 102ff65ffe4SManivannan Sadhasivam struct completion sdc_complete; 103ff65ffe4SManivannan Sadhasivam spinlock_t lock; 104ff65ffe4SManivannan Sadhasivam int irq; 105ff65ffe4SManivannan Sadhasivam u32 clock; 106ff65ffe4SManivannan Sadhasivam bool ddr_50; 107ff65ffe4SManivannan Sadhasivam 108ff65ffe4SManivannan Sadhasivam enum dma_data_direction dma_dir; 109ff65ffe4SManivannan Sadhasivam struct dma_chan *dma; 110ff65ffe4SManivannan Sadhasivam struct dma_async_tx_descriptor *desc; 111ff65ffe4SManivannan Sadhasivam struct dma_slave_config dma_cfg; 112ff65ffe4SManivannan Sadhasivam struct completion dma_complete; 113ff65ffe4SManivannan Sadhasivam 114ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc; 115ff65ffe4SManivannan Sadhasivam struct mmc_request *mrq; 116ff65ffe4SManivannan Sadhasivam struct mmc_command *cmd; 117ff65ffe4SManivannan Sadhasivam struct mmc_data *data; 118ff65ffe4SManivannan Sadhasivam }; 119ff65ffe4SManivannan Sadhasivam 120ff65ffe4SManivannan Sadhasivam static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state) 121ff65ffe4SManivannan Sadhasivam { 122ff65ffe4SManivannan Sadhasivam unsigned int regval; 123ff65ffe4SManivannan Sadhasivam 124ff65ffe4SManivannan Sadhasivam regval = readl(reg); 125ff65ffe4SManivannan Sadhasivam 126ff65ffe4SManivannan Sadhasivam if (state) 127ff65ffe4SManivannan Sadhasivam regval |= val; 128ff65ffe4SManivannan Sadhasivam else 129ff65ffe4SManivannan Sadhasivam regval &= ~val; 130ff65ffe4SManivannan Sadhasivam 131ff65ffe4SManivannan Sadhasivam writel(regval, reg); 132ff65ffe4SManivannan Sadhasivam } 133ff65ffe4SManivannan Sadhasivam 134ff65ffe4SManivannan Sadhasivam static irqreturn_t owl_irq_handler(int irq, void *devid) 135ff65ffe4SManivannan Sadhasivam { 136ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = devid; 137ff65ffe4SManivannan Sadhasivam u32 state; 138ff65ffe4SManivannan Sadhasivam 139fa4c9a49STian Tao spin_lock(&owl_host->lock); 140ff65ffe4SManivannan Sadhasivam 141ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 142ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_TEI) { 143ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 144ff65ffe4SManivannan Sadhasivam state |= OWL_SD_STATE_TEI; 145ff65ffe4SManivannan Sadhasivam writel(state, owl_host->base + OWL_REG_SD_STATE); 146ff65ffe4SManivannan Sadhasivam complete(&owl_host->sdc_complete); 147ff65ffe4SManivannan Sadhasivam } 148ff65ffe4SManivannan Sadhasivam 149fa4c9a49STian Tao spin_unlock(&owl_host->lock); 150ff65ffe4SManivannan Sadhasivam 151ff65ffe4SManivannan Sadhasivam return IRQ_HANDLED; 152ff65ffe4SManivannan Sadhasivam } 153ff65ffe4SManivannan Sadhasivam 154ff65ffe4SManivannan Sadhasivam static void owl_mmc_finish_request(struct owl_mmc_host *owl_host) 155ff65ffe4SManivannan Sadhasivam { 156ff65ffe4SManivannan Sadhasivam struct mmc_request *mrq = owl_host->mrq; 157ff65ffe4SManivannan Sadhasivam struct mmc_data *data = mrq->data; 158ff65ffe4SManivannan Sadhasivam 159ff65ffe4SManivannan Sadhasivam /* Should never be NULL */ 160ff65ffe4SManivannan Sadhasivam WARN_ON(!mrq); 161ff65ffe4SManivannan Sadhasivam 162ff65ffe4SManivannan Sadhasivam owl_host->mrq = NULL; 163ff65ffe4SManivannan Sadhasivam 164ff65ffe4SManivannan Sadhasivam if (data) 165ff65ffe4SManivannan Sadhasivam dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len, 166ff65ffe4SManivannan Sadhasivam owl_host->dma_dir); 167ff65ffe4SManivannan Sadhasivam 168ff65ffe4SManivannan Sadhasivam /* Finally finish request */ 169ff65ffe4SManivannan Sadhasivam mmc_request_done(owl_host->mmc, mrq); 170ff65ffe4SManivannan Sadhasivam } 171ff65ffe4SManivannan Sadhasivam 172ff65ffe4SManivannan Sadhasivam static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host, 173ff65ffe4SManivannan Sadhasivam struct mmc_command *cmd, 174ff65ffe4SManivannan Sadhasivam struct mmc_data *data) 175ff65ffe4SManivannan Sadhasivam { 176f37ac1aeSUlf Hansson unsigned long timeout; 177ff65ffe4SManivannan Sadhasivam u32 mode, state, resp[2]; 178ff65ffe4SManivannan Sadhasivam u32 cmd_rsp_mask = 0; 179ff65ffe4SManivannan Sadhasivam 180ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->sdc_complete); 181ff65ffe4SManivannan Sadhasivam 182ff65ffe4SManivannan Sadhasivam switch (mmc_resp_type(cmd)) { 183ff65ffe4SManivannan Sadhasivam case MMC_RSP_NONE: 184ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(0); 185ff65ffe4SManivannan Sadhasivam break; 186ff65ffe4SManivannan Sadhasivam 187ff65ffe4SManivannan Sadhasivam case MMC_RSP_R1: 188ff65ffe4SManivannan Sadhasivam if (data) { 189ff65ffe4SManivannan Sadhasivam if (data->flags & MMC_DATA_READ) 190ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(4); 191ff65ffe4SManivannan Sadhasivam else 192ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(5); 193ff65ffe4SManivannan Sadhasivam } else { 194ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(1); 195ff65ffe4SManivannan Sadhasivam } 196ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 197ff65ffe4SManivannan Sadhasivam 198ff65ffe4SManivannan Sadhasivam break; 199ff65ffe4SManivannan Sadhasivam 200ff65ffe4SManivannan Sadhasivam case MMC_RSP_R1B: 201ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(3); 202ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 203ff65ffe4SManivannan Sadhasivam break; 204ff65ffe4SManivannan Sadhasivam 205ff65ffe4SManivannan Sadhasivam case MMC_RSP_R2: 206ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(2); 207ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 208ff65ffe4SManivannan Sadhasivam break; 209ff65ffe4SManivannan Sadhasivam 210ff65ffe4SManivannan Sadhasivam case MMC_RSP_R3: 211ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(1); 212ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR; 213ff65ffe4SManivannan Sadhasivam break; 214ff65ffe4SManivannan Sadhasivam 215ff65ffe4SManivannan Sadhasivam default: 216ff65ffe4SManivannan Sadhasivam dev_warn(owl_host->dev, "Unknown MMC command\n"); 217ff65ffe4SManivannan Sadhasivam cmd->error = -EINVAL; 218ff65ffe4SManivannan Sadhasivam return; 219ff65ffe4SManivannan Sadhasivam } 220ff65ffe4SManivannan Sadhasivam 221ff65ffe4SManivannan Sadhasivam /* Keep current WDELAY and RDELAY */ 222ff65ffe4SManivannan Sadhasivam mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); 223ff65ffe4SManivannan Sadhasivam 224ff65ffe4SManivannan Sadhasivam /* Start to send corresponding command type */ 225ff65ffe4SManivannan Sadhasivam writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG); 226ff65ffe4SManivannan Sadhasivam writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD); 227ff65ffe4SManivannan Sadhasivam 228ff65ffe4SManivannan Sadhasivam /* Set LBE to send clk at the end of last read block */ 229ff65ffe4SManivannan Sadhasivam if (data) { 230ff65ffe4SManivannan Sadhasivam mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000); 231ff65ffe4SManivannan Sadhasivam } else { 232ff65ffe4SManivannan Sadhasivam mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE); 233ff65ffe4SManivannan Sadhasivam mode |= OWL_SD_CTL_TS; 234ff65ffe4SManivannan Sadhasivam } 235ff65ffe4SManivannan Sadhasivam 236ff65ffe4SManivannan Sadhasivam owl_host->cmd = cmd; 237ff65ffe4SManivannan Sadhasivam 238ff65ffe4SManivannan Sadhasivam /* Start transfer */ 239ff65ffe4SManivannan Sadhasivam writel(mode, owl_host->base + OWL_REG_SD_CTL); 240ff65ffe4SManivannan Sadhasivam 241ff65ffe4SManivannan Sadhasivam if (data) 242ff65ffe4SManivannan Sadhasivam return; 243ff65ffe4SManivannan Sadhasivam 244f37ac1aeSUlf Hansson timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout : 245f37ac1aeSUlf Hansson OWL_CMD_TIMEOUT_MS); 246f37ac1aeSUlf Hansson 247f37ac1aeSUlf Hansson if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) { 248ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 249ff65ffe4SManivannan Sadhasivam cmd->error = -ETIMEDOUT; 250ff65ffe4SManivannan Sadhasivam return; 251ff65ffe4SManivannan Sadhasivam } 252ff65ffe4SManivannan Sadhasivam 253ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 254ff65ffe4SManivannan Sadhasivam if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 255ff65ffe4SManivannan Sadhasivam if (cmd_rsp_mask & state) { 256ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_CLNR) { 257ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Error CMD_NO_RSP\n"); 258ff65ffe4SManivannan Sadhasivam cmd->error = -EILSEQ; 259ff65ffe4SManivannan Sadhasivam return; 260ff65ffe4SManivannan Sadhasivam } 261ff65ffe4SManivannan Sadhasivam 262ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_CRC7ER) { 263ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Error CMD_RSP_CRC\n"); 264ff65ffe4SManivannan Sadhasivam cmd->error = -EILSEQ; 265ff65ffe4SManivannan Sadhasivam return; 266ff65ffe4SManivannan Sadhasivam } 267ff65ffe4SManivannan Sadhasivam } 268ff65ffe4SManivannan Sadhasivam 269ff65ffe4SManivannan Sadhasivam if (mmc_resp_type(cmd) & MMC_RSP_136) { 270ff65ffe4SManivannan Sadhasivam cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); 271ff65ffe4SManivannan Sadhasivam cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); 272ff65ffe4SManivannan Sadhasivam cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2); 273ff65ffe4SManivannan Sadhasivam cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3); 274ff65ffe4SManivannan Sadhasivam } else { 275ff65ffe4SManivannan Sadhasivam resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); 276ff65ffe4SManivannan Sadhasivam resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); 277ff65ffe4SManivannan Sadhasivam cmd->resp[0] = resp[1] << 24 | resp[0] >> 8; 278ff65ffe4SManivannan Sadhasivam cmd->resp[1] = resp[1] >> 8; 279ff65ffe4SManivannan Sadhasivam } 280ff65ffe4SManivannan Sadhasivam } 281ff65ffe4SManivannan Sadhasivam } 282ff65ffe4SManivannan Sadhasivam 283ff65ffe4SManivannan Sadhasivam static void owl_mmc_dma_complete(void *param) 284ff65ffe4SManivannan Sadhasivam { 285ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = param; 286ff65ffe4SManivannan Sadhasivam struct mmc_data *data = owl_host->data; 287ff65ffe4SManivannan Sadhasivam 288ff65ffe4SManivannan Sadhasivam if (data) 289ff65ffe4SManivannan Sadhasivam complete(&owl_host->dma_complete); 290ff65ffe4SManivannan Sadhasivam } 291ff65ffe4SManivannan Sadhasivam 292ff65ffe4SManivannan Sadhasivam static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host, 293ff65ffe4SManivannan Sadhasivam struct mmc_data *data) 294ff65ffe4SManivannan Sadhasivam { 295ff65ffe4SManivannan Sadhasivam u32 total; 296ff65ffe4SManivannan Sadhasivam 297ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL, 298ff65ffe4SManivannan Sadhasivam true); 299ff65ffe4SManivannan Sadhasivam writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM); 300ff65ffe4SManivannan Sadhasivam writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE); 301ff65ffe4SManivannan Sadhasivam total = data->blksz * data->blocks; 302ff65ffe4SManivannan Sadhasivam 303ff65ffe4SManivannan Sadhasivam if (total < 512) 304ff65ffe4SManivannan Sadhasivam writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE); 305ff65ffe4SManivannan Sadhasivam else 306ff65ffe4SManivannan Sadhasivam writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE); 307ff65ffe4SManivannan Sadhasivam 308ff65ffe4SManivannan Sadhasivam if (data->flags & MMC_DATA_WRITE) { 309ff65ffe4SManivannan Sadhasivam owl_host->dma_dir = DMA_TO_DEVICE; 310ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction = DMA_MEM_TO_DEV; 311ff65ffe4SManivannan Sadhasivam } else { 312ff65ffe4SManivannan Sadhasivam owl_host->dma_dir = DMA_FROM_DEVICE; 313ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction = DMA_DEV_TO_MEM; 314ff65ffe4SManivannan Sadhasivam } 315ff65ffe4SManivannan Sadhasivam 316ff65ffe4SManivannan Sadhasivam dma_map_sg(owl_host->dma->device->dev, data->sg, 317ff65ffe4SManivannan Sadhasivam data->sg_len, owl_host->dma_dir); 318ff65ffe4SManivannan Sadhasivam 319ff65ffe4SManivannan Sadhasivam dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg); 320ff65ffe4SManivannan Sadhasivam owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg, 321ff65ffe4SManivannan Sadhasivam data->sg_len, 322ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction, 323ff65ffe4SManivannan Sadhasivam DMA_PREP_INTERRUPT | 324ff65ffe4SManivannan Sadhasivam DMA_CTRL_ACK); 325ff65ffe4SManivannan Sadhasivam if (!owl_host->desc) { 326ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Can't prepare slave sg\n"); 327ff65ffe4SManivannan Sadhasivam return -EBUSY; 328ff65ffe4SManivannan Sadhasivam } 329ff65ffe4SManivannan Sadhasivam 330ff65ffe4SManivannan Sadhasivam owl_host->data = data; 331ff65ffe4SManivannan Sadhasivam 332ff65ffe4SManivannan Sadhasivam owl_host->desc->callback = owl_mmc_dma_complete; 333ff65ffe4SManivannan Sadhasivam owl_host->desc->callback_param = (void *)owl_host; 334ff65ffe4SManivannan Sadhasivam data->error = 0; 335ff65ffe4SManivannan Sadhasivam 336ff65ffe4SManivannan Sadhasivam return 0; 337ff65ffe4SManivannan Sadhasivam } 338ff65ffe4SManivannan Sadhasivam 339ff65ffe4SManivannan Sadhasivam static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 340ff65ffe4SManivannan Sadhasivam { 341ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 342ff65ffe4SManivannan Sadhasivam struct mmc_data *data = mrq->data; 343ff65ffe4SManivannan Sadhasivam int ret; 344ff65ffe4SManivannan Sadhasivam 345ff65ffe4SManivannan Sadhasivam owl_host->mrq = mrq; 346ff65ffe4SManivannan Sadhasivam if (mrq->data) { 347ff65ffe4SManivannan Sadhasivam ret = owl_mmc_prepare_data(owl_host, data); 348ff65ffe4SManivannan Sadhasivam if (ret < 0) { 349ff65ffe4SManivannan Sadhasivam data->error = ret; 350ff65ffe4SManivannan Sadhasivam goto err_out; 351ff65ffe4SManivannan Sadhasivam } 352ff65ffe4SManivannan Sadhasivam 353ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->dma_complete); 354ff65ffe4SManivannan Sadhasivam dmaengine_submit(owl_host->desc); 355ff65ffe4SManivannan Sadhasivam dma_async_issue_pending(owl_host->dma); 356ff65ffe4SManivannan Sadhasivam } 357ff65ffe4SManivannan Sadhasivam 358ff65ffe4SManivannan Sadhasivam owl_mmc_send_cmd(owl_host, mrq->cmd, data); 359ff65ffe4SManivannan Sadhasivam 360ff65ffe4SManivannan Sadhasivam if (data) { 361ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->sdc_complete, 362ff65ffe4SManivannan Sadhasivam 10 * HZ)) { 363ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 364ff65ffe4SManivannan Sadhasivam mrq->cmd->error = -ETIMEDOUT; 365ff65ffe4SManivannan Sadhasivam dmaengine_terminate_all(owl_host->dma); 366ff65ffe4SManivannan Sadhasivam goto err_out; 367ff65ffe4SManivannan Sadhasivam } 368ff65ffe4SManivannan Sadhasivam 369ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->dma_complete, 370ff65ffe4SManivannan Sadhasivam 5 * HZ)) { 371ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "DMA interrupt timeout\n"); 372ff65ffe4SManivannan Sadhasivam mrq->cmd->error = -ETIMEDOUT; 373ff65ffe4SManivannan Sadhasivam dmaengine_terminate_all(owl_host->dma); 374ff65ffe4SManivannan Sadhasivam goto err_out; 375ff65ffe4SManivannan Sadhasivam } 376ff65ffe4SManivannan Sadhasivam 377ff65ffe4SManivannan Sadhasivam if (data->stop) 378ff65ffe4SManivannan Sadhasivam owl_mmc_send_cmd(owl_host, data->stop, NULL); 379ff65ffe4SManivannan Sadhasivam 380ff65ffe4SManivannan Sadhasivam data->bytes_xfered = data->blocks * data->blksz; 381ff65ffe4SManivannan Sadhasivam } 382ff65ffe4SManivannan Sadhasivam 383ff65ffe4SManivannan Sadhasivam err_out: 384ff65ffe4SManivannan Sadhasivam owl_mmc_finish_request(owl_host); 385ff65ffe4SManivannan Sadhasivam } 386ff65ffe4SManivannan Sadhasivam 387ff65ffe4SManivannan Sadhasivam static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host, 388ff65ffe4SManivannan Sadhasivam unsigned int rate) 389ff65ffe4SManivannan Sadhasivam { 390ff65ffe4SManivannan Sadhasivam unsigned long clk_rate; 391ff65ffe4SManivannan Sadhasivam int ret; 392ff65ffe4SManivannan Sadhasivam u32 reg; 393ff65ffe4SManivannan Sadhasivam 394ff65ffe4SManivannan Sadhasivam reg = readl(owl_host->base + OWL_REG_SD_CTL); 395ff65ffe4SManivannan Sadhasivam reg &= ~OWL_SD_CTL_DELAY_MSK; 396ff65ffe4SManivannan Sadhasivam 397ff65ffe4SManivannan Sadhasivam /* Set RDELAY and WDELAY based on the clock */ 398ff65ffe4SManivannan Sadhasivam if (rate <= 1000000) { 399ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) | 400ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK), 401ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 402ff65ffe4SManivannan Sadhasivam } else if ((rate > 1000000) && (rate <= 26000000)) { 403ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) | 404ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK), 405ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 406ff65ffe4SManivannan Sadhasivam } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) { 407ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) | 408ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK), 409ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 410ff65ffe4SManivannan Sadhasivam /* DDR50 mode has special delay chain */ 411ff65ffe4SManivannan Sadhasivam } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) { 412ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) | 413ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50), 414ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 415ff65ffe4SManivannan Sadhasivam } else { 416ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "SD clock rate not supported\n"); 417ff65ffe4SManivannan Sadhasivam return -EINVAL; 418ff65ffe4SManivannan Sadhasivam } 419ff65ffe4SManivannan Sadhasivam 420ff65ffe4SManivannan Sadhasivam clk_rate = clk_round_rate(owl_host->clk, rate << 1); 421ff65ffe4SManivannan Sadhasivam ret = clk_set_rate(owl_host->clk, clk_rate); 422ff65ffe4SManivannan Sadhasivam 423ff65ffe4SManivannan Sadhasivam return ret; 424ff65ffe4SManivannan Sadhasivam } 425ff65ffe4SManivannan Sadhasivam 426ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios) 427ff65ffe4SManivannan Sadhasivam { 428ff65ffe4SManivannan Sadhasivam if (!ios->clock) 429ff65ffe4SManivannan Sadhasivam return; 430ff65ffe4SManivannan Sadhasivam 431ff65ffe4SManivannan Sadhasivam owl_host->clock = ios->clock; 432ff65ffe4SManivannan Sadhasivam owl_mmc_set_clk_rate(owl_host, ios->clock); 433ff65ffe4SManivannan Sadhasivam } 434ff65ffe4SManivannan Sadhasivam 435ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host, 436ff65ffe4SManivannan Sadhasivam struct mmc_ios *ios) 437ff65ffe4SManivannan Sadhasivam { 438ff65ffe4SManivannan Sadhasivam u32 reg; 439ff65ffe4SManivannan Sadhasivam 440ff65ffe4SManivannan Sadhasivam reg = readl(owl_host->base + OWL_REG_SD_EN); 441ff65ffe4SManivannan Sadhasivam reg &= ~0x03; 442ff65ffe4SManivannan Sadhasivam switch (ios->bus_width) { 443ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_1: 444ff65ffe4SManivannan Sadhasivam break; 445ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_4: 446ff65ffe4SManivannan Sadhasivam reg |= OWL_SD_EN_DATAWID(1); 447ff65ffe4SManivannan Sadhasivam break; 448ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_8: 449ff65ffe4SManivannan Sadhasivam reg |= OWL_SD_EN_DATAWID(2); 450ff65ffe4SManivannan Sadhasivam break; 451ff65ffe4SManivannan Sadhasivam } 452ff65ffe4SManivannan Sadhasivam 453ff65ffe4SManivannan Sadhasivam writel(reg, owl_host->base + OWL_REG_SD_EN); 454ff65ffe4SManivannan Sadhasivam } 455ff65ffe4SManivannan Sadhasivam 456ff65ffe4SManivannan Sadhasivam static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host) 457ff65ffe4SManivannan Sadhasivam { 458ff65ffe4SManivannan Sadhasivam reset_control_assert(owl_host->reset); 459ff65ffe4SManivannan Sadhasivam udelay(20); 460ff65ffe4SManivannan Sadhasivam reset_control_deassert(owl_host->reset); 461ff65ffe4SManivannan Sadhasivam } 462ff65ffe4SManivannan Sadhasivam 463ff65ffe4SManivannan Sadhasivam static void owl_mmc_power_on(struct owl_mmc_host *owl_host) 464ff65ffe4SManivannan Sadhasivam { 465ff65ffe4SManivannan Sadhasivam u32 mode; 466ff65ffe4SManivannan Sadhasivam 467ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->sdc_complete); 468ff65ffe4SManivannan Sadhasivam 469ff65ffe4SManivannan Sadhasivam /* Enable transfer end IRQ */ 470ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE, 471ff65ffe4SManivannan Sadhasivam OWL_SD_STATE_TEIE, true); 472ff65ffe4SManivannan Sadhasivam 473ff65ffe4SManivannan Sadhasivam /* Send init clk */ 474ff65ffe4SManivannan Sadhasivam mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); 475ff65ffe4SManivannan Sadhasivam mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8); 476ff65ffe4SManivannan Sadhasivam writel(mode, owl_host->base + OWL_REG_SD_CTL); 477ff65ffe4SManivannan Sadhasivam 478ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) { 479ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 480ff65ffe4SManivannan Sadhasivam return; 481ff65ffe4SManivannan Sadhasivam } 482ff65ffe4SManivannan Sadhasivam } 483ff65ffe4SManivannan Sadhasivam 484ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 485ff65ffe4SManivannan Sadhasivam { 486ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 487ff65ffe4SManivannan Sadhasivam 488ff65ffe4SManivannan Sadhasivam switch (ios->power_mode) { 489ff65ffe4SManivannan Sadhasivam case MMC_POWER_UP: 490ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card up\n"); 491ff65ffe4SManivannan Sadhasivam 492ff65ffe4SManivannan Sadhasivam /* Reset the SDC controller to clear all previous states */ 493ff65ffe4SManivannan Sadhasivam owl_mmc_ctr_reset(owl_host); 494ff65ffe4SManivannan Sadhasivam clk_prepare_enable(owl_host->clk); 495ff65ffe4SManivannan Sadhasivam writel(OWL_SD_ENABLE | OWL_SD_EN_RESE, 496ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_EN); 497ff65ffe4SManivannan Sadhasivam 498ff65ffe4SManivannan Sadhasivam break; 499ff65ffe4SManivannan Sadhasivam 500ff65ffe4SManivannan Sadhasivam case MMC_POWER_ON: 501ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card on\n"); 502ff65ffe4SManivannan Sadhasivam owl_mmc_power_on(owl_host); 503ff65ffe4SManivannan Sadhasivam 504ff65ffe4SManivannan Sadhasivam break; 505ff65ffe4SManivannan Sadhasivam 506ff65ffe4SManivannan Sadhasivam case MMC_POWER_OFF: 507ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card off\n"); 508ff65ffe4SManivannan Sadhasivam clk_disable_unprepare(owl_host->clk); 509ff65ffe4SManivannan Sadhasivam 510ff65ffe4SManivannan Sadhasivam return; 511ff65ffe4SManivannan Sadhasivam 512ff65ffe4SManivannan Sadhasivam default: 513ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Ignoring unknown card power state\n"); 514ff65ffe4SManivannan Sadhasivam break; 515ff65ffe4SManivannan Sadhasivam } 516ff65ffe4SManivannan Sadhasivam 517ff65ffe4SManivannan Sadhasivam if (ios->clock != owl_host->clock) 518ff65ffe4SManivannan Sadhasivam owl_mmc_set_clk(owl_host, ios); 519ff65ffe4SManivannan Sadhasivam 520ff65ffe4SManivannan Sadhasivam owl_mmc_set_bus_width(owl_host, ios); 521ff65ffe4SManivannan Sadhasivam 522ff65ffe4SManivannan Sadhasivam /* Enable DDR mode if requested */ 523ff65ffe4SManivannan Sadhasivam if (ios->timing == MMC_TIMING_UHS_DDR50) { 5241f71b0bfSZou Wei owl_host->ddr_50 = true; 525ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 526ff65ffe4SManivannan Sadhasivam OWL_SD_EN_DDREN, true); 527ff65ffe4SManivannan Sadhasivam } else { 5281f71b0bfSZou Wei owl_host->ddr_50 = false; 529ff65ffe4SManivannan Sadhasivam } 530ff65ffe4SManivannan Sadhasivam } 531ff65ffe4SManivannan Sadhasivam 532ff65ffe4SManivannan Sadhasivam static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc, 533ff65ffe4SManivannan Sadhasivam struct mmc_ios *ios) 534ff65ffe4SManivannan Sadhasivam { 535ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 536ff65ffe4SManivannan Sadhasivam 537ff65ffe4SManivannan Sadhasivam /* It is enough to change the pad ctrl bit for voltage switch */ 538ff65ffe4SManivannan Sadhasivam switch (ios->signal_voltage) { 539ff65ffe4SManivannan Sadhasivam case MMC_SIGNAL_VOLTAGE_330: 540ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 541ff65ffe4SManivannan Sadhasivam OWL_SD_EN_S18EN, false); 542ff65ffe4SManivannan Sadhasivam break; 543ff65ffe4SManivannan Sadhasivam case MMC_SIGNAL_VOLTAGE_180: 544ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 545ff65ffe4SManivannan Sadhasivam OWL_SD_EN_S18EN, true); 546ff65ffe4SManivannan Sadhasivam break; 547ff65ffe4SManivannan Sadhasivam default: 548ff65ffe4SManivannan Sadhasivam return -ENOTSUPP; 549ff65ffe4SManivannan Sadhasivam } 550ff65ffe4SManivannan Sadhasivam 551ff65ffe4SManivannan Sadhasivam return 0; 552ff65ffe4SManivannan Sadhasivam } 553ff65ffe4SManivannan Sadhasivam 554ff65ffe4SManivannan Sadhasivam static const struct mmc_host_ops owl_mmc_ops = { 555ff65ffe4SManivannan Sadhasivam .request = owl_mmc_request, 556ff65ffe4SManivannan Sadhasivam .set_ios = owl_mmc_set_ios, 557ff65ffe4SManivannan Sadhasivam .get_ro = mmc_gpio_get_ro, 558ff65ffe4SManivannan Sadhasivam .get_cd = mmc_gpio_get_cd, 559ff65ffe4SManivannan Sadhasivam .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch, 560ff65ffe4SManivannan Sadhasivam }; 561ff65ffe4SManivannan Sadhasivam 562ff65ffe4SManivannan Sadhasivam static int owl_mmc_probe(struct platform_device *pdev) 563ff65ffe4SManivannan Sadhasivam { 564ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host; 565ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc; 566ff65ffe4SManivannan Sadhasivam struct resource *res; 567ff65ffe4SManivannan Sadhasivam int ret; 568ff65ffe4SManivannan Sadhasivam 569ff65ffe4SManivannan Sadhasivam mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev); 570ff65ffe4SManivannan Sadhasivam if (!mmc) { 571ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "mmc alloc host failed\n"); 572ff65ffe4SManivannan Sadhasivam return -ENOMEM; 573ff65ffe4SManivannan Sadhasivam } 574ff65ffe4SManivannan Sadhasivam platform_set_drvdata(pdev, mmc); 575ff65ffe4SManivannan Sadhasivam 576ff65ffe4SManivannan Sadhasivam owl_host = mmc_priv(mmc); 577ff65ffe4SManivannan Sadhasivam owl_host->dev = &pdev->dev; 578ff65ffe4SManivannan Sadhasivam owl_host->mmc = mmc; 579ff65ffe4SManivannan Sadhasivam spin_lock_init(&owl_host->lock); 580ff65ffe4SManivannan Sadhasivam 581*c66c55beSYang Li owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 582ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->base)) { 583ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->base); 584ff65ffe4SManivannan Sadhasivam goto err_free_host; 585ff65ffe4SManivannan Sadhasivam } 586ff65ffe4SManivannan Sadhasivam 587ff65ffe4SManivannan Sadhasivam owl_host->clk = devm_clk_get(&pdev->dev, NULL); 588ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->clk)) { 589ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "No clock defined\n"); 590ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->clk); 591ff65ffe4SManivannan Sadhasivam goto err_free_host; 592ff65ffe4SManivannan Sadhasivam } 593ff65ffe4SManivannan Sadhasivam 594ff65ffe4SManivannan Sadhasivam owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 595ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->reset)) { 596ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Could not get reset control\n"); 597ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->reset); 598ff65ffe4SManivannan Sadhasivam goto err_free_host; 599ff65ffe4SManivannan Sadhasivam } 600ff65ffe4SManivannan Sadhasivam 601ff65ffe4SManivannan Sadhasivam mmc->ops = &owl_mmc_ops; 602ff65ffe4SManivannan Sadhasivam mmc->max_blk_count = 512; 603ff65ffe4SManivannan Sadhasivam mmc->max_blk_size = 512; 604ff65ffe4SManivannan Sadhasivam mmc->max_segs = 256; 605ff65ffe4SManivannan Sadhasivam mmc->max_seg_size = 262144; 606ff65ffe4SManivannan Sadhasivam mmc->max_req_size = 262144; 607ff65ffe4SManivannan Sadhasivam /* 100kHz ~ 52MHz */ 608ff65ffe4SManivannan Sadhasivam mmc->f_min = 100000; 609ff65ffe4SManivannan Sadhasivam mmc->f_max = 52000000; 610ff65ffe4SManivannan Sadhasivam mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 611ff65ffe4SManivannan Sadhasivam MMC_CAP_4_BIT_DATA; 612ff65ffe4SManivannan Sadhasivam mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO); 613ff65ffe4SManivannan Sadhasivam mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | 614ff65ffe4SManivannan Sadhasivam MMC_VDD_165_195; 615ff65ffe4SManivannan Sadhasivam 616ff65ffe4SManivannan Sadhasivam ret = mmc_of_parse(mmc); 617ff65ffe4SManivannan Sadhasivam if (ret) 618ff65ffe4SManivannan Sadhasivam goto err_free_host; 619ff65ffe4SManivannan Sadhasivam 620ff65ffe4SManivannan Sadhasivam pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 621ff65ffe4SManivannan Sadhasivam pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 6222e2d12e1SPeter Ujfalusi owl_host->dma = dma_request_chan(&pdev->dev, "mmc"); 6232e2d12e1SPeter Ujfalusi if (IS_ERR(owl_host->dma)) { 624ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Failed to get external DMA channel.\n"); 6252e2d12e1SPeter Ujfalusi ret = PTR_ERR(owl_host->dma); 626ff65ffe4SManivannan Sadhasivam goto err_free_host; 627ff65ffe4SManivannan Sadhasivam } 628ff65ffe4SManivannan Sadhasivam 629ff65ffe4SManivannan Sadhasivam dev_info(&pdev->dev, "Using %s for DMA transfers\n", 630ff65ffe4SManivannan Sadhasivam dma_chan_name(owl_host->dma)); 631ff65ffe4SManivannan Sadhasivam 632ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT; 633ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT; 634ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 635ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 636ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.device_fc = false; 637ff65ffe4SManivannan Sadhasivam 638ff65ffe4SManivannan Sadhasivam owl_host->irq = platform_get_irq(pdev, 0); 639ff65ffe4SManivannan Sadhasivam if (owl_host->irq < 0) { 640ff65ffe4SManivannan Sadhasivam ret = -EINVAL; 6415d15cbf6SChristophe JAILLET goto err_release_channel; 642ff65ffe4SManivannan Sadhasivam } 643ff65ffe4SManivannan Sadhasivam 644ff65ffe4SManivannan Sadhasivam ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler, 645ff65ffe4SManivannan Sadhasivam 0, dev_name(&pdev->dev), owl_host); 646ff65ffe4SManivannan Sadhasivam if (ret) { 647ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Failed to request irq %d\n", 648ff65ffe4SManivannan Sadhasivam owl_host->irq); 6495d15cbf6SChristophe JAILLET goto err_release_channel; 650ff65ffe4SManivannan Sadhasivam } 651ff65ffe4SManivannan Sadhasivam 652ff65ffe4SManivannan Sadhasivam ret = mmc_add_host(mmc); 653ff65ffe4SManivannan Sadhasivam if (ret) { 654ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Failed to add host\n"); 6555d15cbf6SChristophe JAILLET goto err_release_channel; 656ff65ffe4SManivannan Sadhasivam } 657ff65ffe4SManivannan Sadhasivam 658ff65ffe4SManivannan Sadhasivam dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n"); 659ff65ffe4SManivannan Sadhasivam 660ff65ffe4SManivannan Sadhasivam return 0; 661ff65ffe4SManivannan Sadhasivam 6625d15cbf6SChristophe JAILLET err_release_channel: 6635d15cbf6SChristophe JAILLET dma_release_channel(owl_host->dma); 664ff65ffe4SManivannan Sadhasivam err_free_host: 665ff65ffe4SManivannan Sadhasivam mmc_free_host(mmc); 666ff65ffe4SManivannan Sadhasivam 667ff65ffe4SManivannan Sadhasivam return ret; 668ff65ffe4SManivannan Sadhasivam } 669ff65ffe4SManivannan Sadhasivam 670ff65ffe4SManivannan Sadhasivam static int owl_mmc_remove(struct platform_device *pdev) 671ff65ffe4SManivannan Sadhasivam { 672ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc = platform_get_drvdata(pdev); 673ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 674ff65ffe4SManivannan Sadhasivam 675ff65ffe4SManivannan Sadhasivam mmc_remove_host(mmc); 676ff65ffe4SManivannan Sadhasivam disable_irq(owl_host->irq); 6775d15cbf6SChristophe JAILLET dma_release_channel(owl_host->dma); 678ff65ffe4SManivannan Sadhasivam mmc_free_host(mmc); 679ff65ffe4SManivannan Sadhasivam 680ff65ffe4SManivannan Sadhasivam return 0; 681ff65ffe4SManivannan Sadhasivam } 682ff65ffe4SManivannan Sadhasivam 683ff65ffe4SManivannan Sadhasivam static const struct of_device_id owl_mmc_of_match[] = { 684ff65ffe4SManivannan Sadhasivam {.compatible = "actions,owl-mmc",}, 685ff65ffe4SManivannan Sadhasivam { /* sentinel */ } 686ff65ffe4SManivannan Sadhasivam }; 687ff65ffe4SManivannan Sadhasivam MODULE_DEVICE_TABLE(of, owl_mmc_of_match); 688ff65ffe4SManivannan Sadhasivam 689ff65ffe4SManivannan Sadhasivam static struct platform_driver owl_mmc_driver = { 690ff65ffe4SManivannan Sadhasivam .driver = { 691ff65ffe4SManivannan Sadhasivam .name = "owl_mmc", 69231ae4035SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 693f8884711SManivannan Sadhasivam .of_match_table = owl_mmc_of_match, 694ff65ffe4SManivannan Sadhasivam }, 695ff65ffe4SManivannan Sadhasivam .probe = owl_mmc_probe, 696ff65ffe4SManivannan Sadhasivam .remove = owl_mmc_remove, 697ff65ffe4SManivannan Sadhasivam }; 698ff65ffe4SManivannan Sadhasivam module_platform_driver(owl_mmc_driver); 699ff65ffe4SManivannan Sadhasivam 700ff65ffe4SManivannan Sadhasivam MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver"); 701ff65ffe4SManivannan Sadhasivam MODULE_AUTHOR("Actions Semi"); 702ff65ffe4SManivannan Sadhasivam MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 703ff65ffe4SManivannan Sadhasivam MODULE_LICENSE("GPL"); 704