1ff65ffe4SManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0-or-later 2ff65ffe4SManivannan Sadhasivam /* 3ff65ffe4SManivannan Sadhasivam * Actions Semi Owl SoCs SD/MMC driver 4ff65ffe4SManivannan Sadhasivam * 5ff65ffe4SManivannan Sadhasivam * Copyright (c) 2014 Actions Semi Inc. 6ff65ffe4SManivannan Sadhasivam * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7ff65ffe4SManivannan Sadhasivam * 8ff65ffe4SManivannan Sadhasivam * TODO: SDIO support 9ff65ffe4SManivannan Sadhasivam */ 10ff65ffe4SManivannan Sadhasivam 11ff65ffe4SManivannan Sadhasivam #include <linux/clk.h> 12ff65ffe4SManivannan Sadhasivam #include <linux/delay.h> 13ff65ffe4SManivannan Sadhasivam #include <linux/dmaengine.h> 14ff65ffe4SManivannan Sadhasivam #include <linux/dma-direction.h> 15ff65ffe4SManivannan Sadhasivam #include <linux/dma-mapping.h> 16ff65ffe4SManivannan Sadhasivam #include <linux/interrupt.h> 17ff65ffe4SManivannan Sadhasivam #include <linux/mmc/host.h> 18ff65ffe4SManivannan Sadhasivam #include <linux/mmc/slot-gpio.h> 19*c62da8a8SRob Herring #include <linux/mod_devicetable.h> 20ff65ffe4SManivannan Sadhasivam #include <linux/module.h> 21*c62da8a8SRob Herring #include <linux/platform_device.h> 22ff65ffe4SManivannan Sadhasivam #include <linux/reset.h> 23ff65ffe4SManivannan Sadhasivam #include <linux/spinlock.h> 24ff65ffe4SManivannan Sadhasivam 25ff65ffe4SManivannan Sadhasivam /* 26ff65ffe4SManivannan Sadhasivam * SDC registers 27ff65ffe4SManivannan Sadhasivam */ 28ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_EN 0x0000 29ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_CTL 0x0004 30ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_STATE 0x0008 31ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_CMD 0x000c 32ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_ARG 0x0010 33ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF0 0x0014 34ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF1 0x0018 35ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF2 0x001c 36ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF3 0x0020 37ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_RSPBUF4 0x0024 38ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_DAT 0x0028 39ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BLK_SIZE 0x002c 40ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BLK_NUM 0x0030 41ff65ffe4SManivannan Sadhasivam #define OWL_REG_SD_BUF_SIZE 0x0034 42ff65ffe4SManivannan Sadhasivam 43ff65ffe4SManivannan Sadhasivam /* SD_EN Bits */ 44ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RANE BIT(31) 45ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24) 46ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_S18EN BIT(12) 47ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_RESE BIT(10) 48ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DAT1_S BIT(9) 49ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_CLK_S BIT(8) 50ff65ffe4SManivannan Sadhasivam #define OWL_SD_ENABLE BIT(7) 51ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_BSEL BIT(6) 52ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_SDIOEN BIT(3) 53ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DDREN BIT(2) 54ff65ffe4SManivannan Sadhasivam #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0) 55ff65ffe4SManivannan Sadhasivam 56ff65ffe4SManivannan Sadhasivam /* SD_CTL Bits */ 57ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TOUTEN BIT(31) 58ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24) 59ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16) 60ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20) 61ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16) 62ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_CMDLEN BIT(13) 63ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_SCC BIT(12) 64ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8) 65ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TS BIT(7) 66ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_LBE BIT(6) 67ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_C7EN BIT(5) 68ff65ffe4SManivannan Sadhasivam #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0) 69ff65ffe4SManivannan Sadhasivam 70ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_LOW_CLK 0x0f 71ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_MID_CLK 0x0a 72ff65ffe4SManivannan Sadhasivam #define OWL_SD_DELAY_HIGH_CLK 0x09 73ff65ffe4SManivannan Sadhasivam #define OWL_SD_RDELAY_DDR50 0x0a 74ff65ffe4SManivannan Sadhasivam #define OWL_SD_WDELAY_DDR50 0x08 75ff65ffe4SManivannan Sadhasivam 76ff65ffe4SManivannan Sadhasivam /* SD_STATE Bits */ 77ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT1BS BIT(18) 78ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOB_P BIT(17) 79ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOB_EN BIT(16) 80ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TOUTE BIT(15) 81ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_BAEP BIT(14) 82ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_MEMRDY BIT(12) 83ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CMDS BIT(11) 84ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT1AS BIT(10) 85ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOA_P BIT(9) 86ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_SDIOA_EN BIT(8) 87ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_DAT0S BIT(7) 88ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TEIE BIT(6) 89ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_TEI BIT(5) 90ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CLNR BIT(4) 91ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CLC BIT(3) 92ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_WC16ER BIT(2) 93ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_RC16ER BIT(1) 94ff65ffe4SManivannan Sadhasivam #define OWL_SD_STATE_CRC7ER BIT(0) 95ff65ffe4SManivannan Sadhasivam 96f37ac1aeSUlf Hansson #define OWL_CMD_TIMEOUT_MS 30000 97f37ac1aeSUlf Hansson 98ff65ffe4SManivannan Sadhasivam struct owl_mmc_host { 99ff65ffe4SManivannan Sadhasivam struct device *dev; 100ff65ffe4SManivannan Sadhasivam struct reset_control *reset; 101ff65ffe4SManivannan Sadhasivam void __iomem *base; 102ff65ffe4SManivannan Sadhasivam struct clk *clk; 103ff65ffe4SManivannan Sadhasivam struct completion sdc_complete; 104ff65ffe4SManivannan Sadhasivam spinlock_t lock; 105ff65ffe4SManivannan Sadhasivam int irq; 106ff65ffe4SManivannan Sadhasivam u32 clock; 107ff65ffe4SManivannan Sadhasivam bool ddr_50; 108ff65ffe4SManivannan Sadhasivam 109ff65ffe4SManivannan Sadhasivam enum dma_data_direction dma_dir; 110ff65ffe4SManivannan Sadhasivam struct dma_chan *dma; 111ff65ffe4SManivannan Sadhasivam struct dma_async_tx_descriptor *desc; 112ff65ffe4SManivannan Sadhasivam struct dma_slave_config dma_cfg; 113ff65ffe4SManivannan Sadhasivam struct completion dma_complete; 114ff65ffe4SManivannan Sadhasivam 115ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc; 116ff65ffe4SManivannan Sadhasivam struct mmc_request *mrq; 117ff65ffe4SManivannan Sadhasivam struct mmc_command *cmd; 118ff65ffe4SManivannan Sadhasivam struct mmc_data *data; 119ff65ffe4SManivannan Sadhasivam }; 120ff65ffe4SManivannan Sadhasivam 121ff65ffe4SManivannan Sadhasivam static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state) 122ff65ffe4SManivannan Sadhasivam { 123ff65ffe4SManivannan Sadhasivam unsigned int regval; 124ff65ffe4SManivannan Sadhasivam 125ff65ffe4SManivannan Sadhasivam regval = readl(reg); 126ff65ffe4SManivannan Sadhasivam 127ff65ffe4SManivannan Sadhasivam if (state) 128ff65ffe4SManivannan Sadhasivam regval |= val; 129ff65ffe4SManivannan Sadhasivam else 130ff65ffe4SManivannan Sadhasivam regval &= ~val; 131ff65ffe4SManivannan Sadhasivam 132ff65ffe4SManivannan Sadhasivam writel(regval, reg); 133ff65ffe4SManivannan Sadhasivam } 134ff65ffe4SManivannan Sadhasivam 135ff65ffe4SManivannan Sadhasivam static irqreturn_t owl_irq_handler(int irq, void *devid) 136ff65ffe4SManivannan Sadhasivam { 137ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = devid; 138ff65ffe4SManivannan Sadhasivam u32 state; 139ff65ffe4SManivannan Sadhasivam 140fa4c9a49STian Tao spin_lock(&owl_host->lock); 141ff65ffe4SManivannan Sadhasivam 142ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 143ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_TEI) { 144ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 145ff65ffe4SManivannan Sadhasivam state |= OWL_SD_STATE_TEI; 146ff65ffe4SManivannan Sadhasivam writel(state, owl_host->base + OWL_REG_SD_STATE); 147ff65ffe4SManivannan Sadhasivam complete(&owl_host->sdc_complete); 148ff65ffe4SManivannan Sadhasivam } 149ff65ffe4SManivannan Sadhasivam 150fa4c9a49STian Tao spin_unlock(&owl_host->lock); 151ff65ffe4SManivannan Sadhasivam 152ff65ffe4SManivannan Sadhasivam return IRQ_HANDLED; 153ff65ffe4SManivannan Sadhasivam } 154ff65ffe4SManivannan Sadhasivam 155ff65ffe4SManivannan Sadhasivam static void owl_mmc_finish_request(struct owl_mmc_host *owl_host) 156ff65ffe4SManivannan Sadhasivam { 157ff65ffe4SManivannan Sadhasivam struct mmc_request *mrq = owl_host->mrq; 158ff65ffe4SManivannan Sadhasivam struct mmc_data *data = mrq->data; 159ff65ffe4SManivannan Sadhasivam 160ff65ffe4SManivannan Sadhasivam /* Should never be NULL */ 161ff65ffe4SManivannan Sadhasivam WARN_ON(!mrq); 162ff65ffe4SManivannan Sadhasivam 163ff65ffe4SManivannan Sadhasivam owl_host->mrq = NULL; 164ff65ffe4SManivannan Sadhasivam 165ff65ffe4SManivannan Sadhasivam if (data) 166ff65ffe4SManivannan Sadhasivam dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len, 167ff65ffe4SManivannan Sadhasivam owl_host->dma_dir); 168ff65ffe4SManivannan Sadhasivam 169ff65ffe4SManivannan Sadhasivam /* Finally finish request */ 170ff65ffe4SManivannan Sadhasivam mmc_request_done(owl_host->mmc, mrq); 171ff65ffe4SManivannan Sadhasivam } 172ff65ffe4SManivannan Sadhasivam 173ff65ffe4SManivannan Sadhasivam static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host, 174ff65ffe4SManivannan Sadhasivam struct mmc_command *cmd, 175ff65ffe4SManivannan Sadhasivam struct mmc_data *data) 176ff65ffe4SManivannan Sadhasivam { 177f37ac1aeSUlf Hansson unsigned long timeout; 178ff65ffe4SManivannan Sadhasivam u32 mode, state, resp[2]; 179ff65ffe4SManivannan Sadhasivam u32 cmd_rsp_mask = 0; 180ff65ffe4SManivannan Sadhasivam 181ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->sdc_complete); 182ff65ffe4SManivannan Sadhasivam 183ff65ffe4SManivannan Sadhasivam switch (mmc_resp_type(cmd)) { 184ff65ffe4SManivannan Sadhasivam case MMC_RSP_NONE: 185ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(0); 186ff65ffe4SManivannan Sadhasivam break; 187ff65ffe4SManivannan Sadhasivam 188ff65ffe4SManivannan Sadhasivam case MMC_RSP_R1: 189ff65ffe4SManivannan Sadhasivam if (data) { 190ff65ffe4SManivannan Sadhasivam if (data->flags & MMC_DATA_READ) 191ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(4); 192ff65ffe4SManivannan Sadhasivam else 193ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(5); 194ff65ffe4SManivannan Sadhasivam } else { 195ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(1); 196ff65ffe4SManivannan Sadhasivam } 197ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 198ff65ffe4SManivannan Sadhasivam 199ff65ffe4SManivannan Sadhasivam break; 200ff65ffe4SManivannan Sadhasivam 201ff65ffe4SManivannan Sadhasivam case MMC_RSP_R1B: 202ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(3); 203ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 204ff65ffe4SManivannan Sadhasivam break; 205ff65ffe4SManivannan Sadhasivam 206ff65ffe4SManivannan Sadhasivam case MMC_RSP_R2: 207ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(2); 208ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; 209ff65ffe4SManivannan Sadhasivam break; 210ff65ffe4SManivannan Sadhasivam 211ff65ffe4SManivannan Sadhasivam case MMC_RSP_R3: 212ff65ffe4SManivannan Sadhasivam mode = OWL_SD_CTL_TM(1); 213ff65ffe4SManivannan Sadhasivam cmd_rsp_mask = OWL_SD_STATE_CLNR; 214ff65ffe4SManivannan Sadhasivam break; 215ff65ffe4SManivannan Sadhasivam 216ff65ffe4SManivannan Sadhasivam default: 217ff65ffe4SManivannan Sadhasivam dev_warn(owl_host->dev, "Unknown MMC command\n"); 218ff65ffe4SManivannan Sadhasivam cmd->error = -EINVAL; 219ff65ffe4SManivannan Sadhasivam return; 220ff65ffe4SManivannan Sadhasivam } 221ff65ffe4SManivannan Sadhasivam 222ff65ffe4SManivannan Sadhasivam /* Keep current WDELAY and RDELAY */ 223ff65ffe4SManivannan Sadhasivam mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); 224ff65ffe4SManivannan Sadhasivam 225ff65ffe4SManivannan Sadhasivam /* Start to send corresponding command type */ 226ff65ffe4SManivannan Sadhasivam writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG); 227ff65ffe4SManivannan Sadhasivam writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD); 228ff65ffe4SManivannan Sadhasivam 229ff65ffe4SManivannan Sadhasivam /* Set LBE to send clk at the end of last read block */ 230ff65ffe4SManivannan Sadhasivam if (data) { 231ff65ffe4SManivannan Sadhasivam mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000); 232ff65ffe4SManivannan Sadhasivam } else { 233ff65ffe4SManivannan Sadhasivam mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE); 234ff65ffe4SManivannan Sadhasivam mode |= OWL_SD_CTL_TS; 235ff65ffe4SManivannan Sadhasivam } 236ff65ffe4SManivannan Sadhasivam 237ff65ffe4SManivannan Sadhasivam owl_host->cmd = cmd; 238ff65ffe4SManivannan Sadhasivam 239ff65ffe4SManivannan Sadhasivam /* Start transfer */ 240ff65ffe4SManivannan Sadhasivam writel(mode, owl_host->base + OWL_REG_SD_CTL); 241ff65ffe4SManivannan Sadhasivam 242ff65ffe4SManivannan Sadhasivam if (data) 243ff65ffe4SManivannan Sadhasivam return; 244ff65ffe4SManivannan Sadhasivam 245f37ac1aeSUlf Hansson timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout : 246f37ac1aeSUlf Hansson OWL_CMD_TIMEOUT_MS); 247f37ac1aeSUlf Hansson 248f37ac1aeSUlf Hansson if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) { 249ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 250ff65ffe4SManivannan Sadhasivam cmd->error = -ETIMEDOUT; 251ff65ffe4SManivannan Sadhasivam return; 252ff65ffe4SManivannan Sadhasivam } 253ff65ffe4SManivannan Sadhasivam 254ff65ffe4SManivannan Sadhasivam state = readl(owl_host->base + OWL_REG_SD_STATE); 255ff65ffe4SManivannan Sadhasivam if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 256ff65ffe4SManivannan Sadhasivam if (cmd_rsp_mask & state) { 257ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_CLNR) { 258ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Error CMD_NO_RSP\n"); 259ff65ffe4SManivannan Sadhasivam cmd->error = -EILSEQ; 260ff65ffe4SManivannan Sadhasivam return; 261ff65ffe4SManivannan Sadhasivam } 262ff65ffe4SManivannan Sadhasivam 263ff65ffe4SManivannan Sadhasivam if (state & OWL_SD_STATE_CRC7ER) { 264ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Error CMD_RSP_CRC\n"); 265ff65ffe4SManivannan Sadhasivam cmd->error = -EILSEQ; 266ff65ffe4SManivannan Sadhasivam return; 267ff65ffe4SManivannan Sadhasivam } 268ff65ffe4SManivannan Sadhasivam } 269ff65ffe4SManivannan Sadhasivam 270ff65ffe4SManivannan Sadhasivam if (mmc_resp_type(cmd) & MMC_RSP_136) { 271ff65ffe4SManivannan Sadhasivam cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); 272ff65ffe4SManivannan Sadhasivam cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); 273ff65ffe4SManivannan Sadhasivam cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2); 274ff65ffe4SManivannan Sadhasivam cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3); 275ff65ffe4SManivannan Sadhasivam } else { 276ff65ffe4SManivannan Sadhasivam resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); 277ff65ffe4SManivannan Sadhasivam resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); 278ff65ffe4SManivannan Sadhasivam cmd->resp[0] = resp[1] << 24 | resp[0] >> 8; 279ff65ffe4SManivannan Sadhasivam cmd->resp[1] = resp[1] >> 8; 280ff65ffe4SManivannan Sadhasivam } 281ff65ffe4SManivannan Sadhasivam } 282ff65ffe4SManivannan Sadhasivam } 283ff65ffe4SManivannan Sadhasivam 284ff65ffe4SManivannan Sadhasivam static void owl_mmc_dma_complete(void *param) 285ff65ffe4SManivannan Sadhasivam { 286ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = param; 287ff65ffe4SManivannan Sadhasivam struct mmc_data *data = owl_host->data; 288ff65ffe4SManivannan Sadhasivam 289ff65ffe4SManivannan Sadhasivam if (data) 290ff65ffe4SManivannan Sadhasivam complete(&owl_host->dma_complete); 291ff65ffe4SManivannan Sadhasivam } 292ff65ffe4SManivannan Sadhasivam 293ff65ffe4SManivannan Sadhasivam static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host, 294ff65ffe4SManivannan Sadhasivam struct mmc_data *data) 295ff65ffe4SManivannan Sadhasivam { 296ff65ffe4SManivannan Sadhasivam u32 total; 297ff65ffe4SManivannan Sadhasivam 298ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL, 299ff65ffe4SManivannan Sadhasivam true); 300ff65ffe4SManivannan Sadhasivam writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM); 301ff65ffe4SManivannan Sadhasivam writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE); 302ff65ffe4SManivannan Sadhasivam total = data->blksz * data->blocks; 303ff65ffe4SManivannan Sadhasivam 304ff65ffe4SManivannan Sadhasivam if (total < 512) 305ff65ffe4SManivannan Sadhasivam writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE); 306ff65ffe4SManivannan Sadhasivam else 307ff65ffe4SManivannan Sadhasivam writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE); 308ff65ffe4SManivannan Sadhasivam 309ff65ffe4SManivannan Sadhasivam if (data->flags & MMC_DATA_WRITE) { 310ff65ffe4SManivannan Sadhasivam owl_host->dma_dir = DMA_TO_DEVICE; 311ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction = DMA_MEM_TO_DEV; 312ff65ffe4SManivannan Sadhasivam } else { 313ff65ffe4SManivannan Sadhasivam owl_host->dma_dir = DMA_FROM_DEVICE; 314ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction = DMA_DEV_TO_MEM; 315ff65ffe4SManivannan Sadhasivam } 316ff65ffe4SManivannan Sadhasivam 317ff65ffe4SManivannan Sadhasivam dma_map_sg(owl_host->dma->device->dev, data->sg, 318ff65ffe4SManivannan Sadhasivam data->sg_len, owl_host->dma_dir); 319ff65ffe4SManivannan Sadhasivam 320ff65ffe4SManivannan Sadhasivam dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg); 321ff65ffe4SManivannan Sadhasivam owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg, 322ff65ffe4SManivannan Sadhasivam data->sg_len, 323ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.direction, 324ff65ffe4SManivannan Sadhasivam DMA_PREP_INTERRUPT | 325ff65ffe4SManivannan Sadhasivam DMA_CTRL_ACK); 326ff65ffe4SManivannan Sadhasivam if (!owl_host->desc) { 327ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Can't prepare slave sg\n"); 328ff65ffe4SManivannan Sadhasivam return -EBUSY; 329ff65ffe4SManivannan Sadhasivam } 330ff65ffe4SManivannan Sadhasivam 331ff65ffe4SManivannan Sadhasivam owl_host->data = data; 332ff65ffe4SManivannan Sadhasivam 333ff65ffe4SManivannan Sadhasivam owl_host->desc->callback = owl_mmc_dma_complete; 334ff65ffe4SManivannan Sadhasivam owl_host->desc->callback_param = (void *)owl_host; 335ff65ffe4SManivannan Sadhasivam data->error = 0; 336ff65ffe4SManivannan Sadhasivam 337ff65ffe4SManivannan Sadhasivam return 0; 338ff65ffe4SManivannan Sadhasivam } 339ff65ffe4SManivannan Sadhasivam 340ff65ffe4SManivannan Sadhasivam static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 341ff65ffe4SManivannan Sadhasivam { 342ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 343ff65ffe4SManivannan Sadhasivam struct mmc_data *data = mrq->data; 344ff65ffe4SManivannan Sadhasivam int ret; 345ff65ffe4SManivannan Sadhasivam 346ff65ffe4SManivannan Sadhasivam owl_host->mrq = mrq; 347ff65ffe4SManivannan Sadhasivam if (mrq->data) { 348ff65ffe4SManivannan Sadhasivam ret = owl_mmc_prepare_data(owl_host, data); 349ff65ffe4SManivannan Sadhasivam if (ret < 0) { 350ff65ffe4SManivannan Sadhasivam data->error = ret; 351ff65ffe4SManivannan Sadhasivam goto err_out; 352ff65ffe4SManivannan Sadhasivam } 353ff65ffe4SManivannan Sadhasivam 354ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->dma_complete); 355ff65ffe4SManivannan Sadhasivam dmaengine_submit(owl_host->desc); 356ff65ffe4SManivannan Sadhasivam dma_async_issue_pending(owl_host->dma); 357ff65ffe4SManivannan Sadhasivam } 358ff65ffe4SManivannan Sadhasivam 359ff65ffe4SManivannan Sadhasivam owl_mmc_send_cmd(owl_host, mrq->cmd, data); 360ff65ffe4SManivannan Sadhasivam 361ff65ffe4SManivannan Sadhasivam if (data) { 362ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->sdc_complete, 363ff65ffe4SManivannan Sadhasivam 10 * HZ)) { 364ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 365ff65ffe4SManivannan Sadhasivam mrq->cmd->error = -ETIMEDOUT; 366ff65ffe4SManivannan Sadhasivam dmaengine_terminate_all(owl_host->dma); 367ff65ffe4SManivannan Sadhasivam goto err_out; 368ff65ffe4SManivannan Sadhasivam } 369ff65ffe4SManivannan Sadhasivam 370ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->dma_complete, 371ff65ffe4SManivannan Sadhasivam 5 * HZ)) { 372ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "DMA interrupt timeout\n"); 373ff65ffe4SManivannan Sadhasivam mrq->cmd->error = -ETIMEDOUT; 374ff65ffe4SManivannan Sadhasivam dmaengine_terminate_all(owl_host->dma); 375ff65ffe4SManivannan Sadhasivam goto err_out; 376ff65ffe4SManivannan Sadhasivam } 377ff65ffe4SManivannan Sadhasivam 378ff65ffe4SManivannan Sadhasivam if (data->stop) 379ff65ffe4SManivannan Sadhasivam owl_mmc_send_cmd(owl_host, data->stop, NULL); 380ff65ffe4SManivannan Sadhasivam 381ff65ffe4SManivannan Sadhasivam data->bytes_xfered = data->blocks * data->blksz; 382ff65ffe4SManivannan Sadhasivam } 383ff65ffe4SManivannan Sadhasivam 384ff65ffe4SManivannan Sadhasivam err_out: 385ff65ffe4SManivannan Sadhasivam owl_mmc_finish_request(owl_host); 386ff65ffe4SManivannan Sadhasivam } 387ff65ffe4SManivannan Sadhasivam 388ff65ffe4SManivannan Sadhasivam static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host, 389ff65ffe4SManivannan Sadhasivam unsigned int rate) 390ff65ffe4SManivannan Sadhasivam { 391ff65ffe4SManivannan Sadhasivam unsigned long clk_rate; 392ff65ffe4SManivannan Sadhasivam int ret; 393ff65ffe4SManivannan Sadhasivam u32 reg; 394ff65ffe4SManivannan Sadhasivam 395ff65ffe4SManivannan Sadhasivam reg = readl(owl_host->base + OWL_REG_SD_CTL); 396ff65ffe4SManivannan Sadhasivam reg &= ~OWL_SD_CTL_DELAY_MSK; 397ff65ffe4SManivannan Sadhasivam 398ff65ffe4SManivannan Sadhasivam /* Set RDELAY and WDELAY based on the clock */ 399ff65ffe4SManivannan Sadhasivam if (rate <= 1000000) { 400ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) | 401ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK), 402ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 403ff65ffe4SManivannan Sadhasivam } else if ((rate > 1000000) && (rate <= 26000000)) { 404ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) | 405ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK), 406ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 407ff65ffe4SManivannan Sadhasivam } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) { 408ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) | 409ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK), 410ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 411ff65ffe4SManivannan Sadhasivam /* DDR50 mode has special delay chain */ 412ff65ffe4SManivannan Sadhasivam } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) { 413ff65ffe4SManivannan Sadhasivam writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) | 414ff65ffe4SManivannan Sadhasivam OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50), 415ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_CTL); 416ff65ffe4SManivannan Sadhasivam } else { 417ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "SD clock rate not supported\n"); 418ff65ffe4SManivannan Sadhasivam return -EINVAL; 419ff65ffe4SManivannan Sadhasivam } 420ff65ffe4SManivannan Sadhasivam 421ff65ffe4SManivannan Sadhasivam clk_rate = clk_round_rate(owl_host->clk, rate << 1); 422ff65ffe4SManivannan Sadhasivam ret = clk_set_rate(owl_host->clk, clk_rate); 423ff65ffe4SManivannan Sadhasivam 424ff65ffe4SManivannan Sadhasivam return ret; 425ff65ffe4SManivannan Sadhasivam } 426ff65ffe4SManivannan Sadhasivam 427ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios) 428ff65ffe4SManivannan Sadhasivam { 429ff65ffe4SManivannan Sadhasivam if (!ios->clock) 430ff65ffe4SManivannan Sadhasivam return; 431ff65ffe4SManivannan Sadhasivam 432ff65ffe4SManivannan Sadhasivam owl_host->clock = ios->clock; 433ff65ffe4SManivannan Sadhasivam owl_mmc_set_clk_rate(owl_host, ios->clock); 434ff65ffe4SManivannan Sadhasivam } 435ff65ffe4SManivannan Sadhasivam 436ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host, 437ff65ffe4SManivannan Sadhasivam struct mmc_ios *ios) 438ff65ffe4SManivannan Sadhasivam { 439ff65ffe4SManivannan Sadhasivam u32 reg; 440ff65ffe4SManivannan Sadhasivam 441ff65ffe4SManivannan Sadhasivam reg = readl(owl_host->base + OWL_REG_SD_EN); 442ff65ffe4SManivannan Sadhasivam reg &= ~0x03; 443ff65ffe4SManivannan Sadhasivam switch (ios->bus_width) { 444ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_1: 445ff65ffe4SManivannan Sadhasivam break; 446ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_4: 447ff65ffe4SManivannan Sadhasivam reg |= OWL_SD_EN_DATAWID(1); 448ff65ffe4SManivannan Sadhasivam break; 449ff65ffe4SManivannan Sadhasivam case MMC_BUS_WIDTH_8: 450ff65ffe4SManivannan Sadhasivam reg |= OWL_SD_EN_DATAWID(2); 451ff65ffe4SManivannan Sadhasivam break; 452ff65ffe4SManivannan Sadhasivam } 453ff65ffe4SManivannan Sadhasivam 454ff65ffe4SManivannan Sadhasivam writel(reg, owl_host->base + OWL_REG_SD_EN); 455ff65ffe4SManivannan Sadhasivam } 456ff65ffe4SManivannan Sadhasivam 457ff65ffe4SManivannan Sadhasivam static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host) 458ff65ffe4SManivannan Sadhasivam { 459ff65ffe4SManivannan Sadhasivam reset_control_assert(owl_host->reset); 460ff65ffe4SManivannan Sadhasivam udelay(20); 461ff65ffe4SManivannan Sadhasivam reset_control_deassert(owl_host->reset); 462ff65ffe4SManivannan Sadhasivam } 463ff65ffe4SManivannan Sadhasivam 464ff65ffe4SManivannan Sadhasivam static void owl_mmc_power_on(struct owl_mmc_host *owl_host) 465ff65ffe4SManivannan Sadhasivam { 466ff65ffe4SManivannan Sadhasivam u32 mode; 467ff65ffe4SManivannan Sadhasivam 468ff65ffe4SManivannan Sadhasivam init_completion(&owl_host->sdc_complete); 469ff65ffe4SManivannan Sadhasivam 470ff65ffe4SManivannan Sadhasivam /* Enable transfer end IRQ */ 471ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE, 472ff65ffe4SManivannan Sadhasivam OWL_SD_STATE_TEIE, true); 473ff65ffe4SManivannan Sadhasivam 474ff65ffe4SManivannan Sadhasivam /* Send init clk */ 475ff65ffe4SManivannan Sadhasivam mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); 476ff65ffe4SManivannan Sadhasivam mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8); 477ff65ffe4SManivannan Sadhasivam writel(mode, owl_host->base + OWL_REG_SD_CTL); 478ff65ffe4SManivannan Sadhasivam 479ff65ffe4SManivannan Sadhasivam if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) { 480ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "CMD interrupt timeout\n"); 481ff65ffe4SManivannan Sadhasivam return; 482ff65ffe4SManivannan Sadhasivam } 483ff65ffe4SManivannan Sadhasivam } 484ff65ffe4SManivannan Sadhasivam 485ff65ffe4SManivannan Sadhasivam static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 486ff65ffe4SManivannan Sadhasivam { 487ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 488ff65ffe4SManivannan Sadhasivam 489ff65ffe4SManivannan Sadhasivam switch (ios->power_mode) { 490ff65ffe4SManivannan Sadhasivam case MMC_POWER_UP: 491ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card up\n"); 492ff65ffe4SManivannan Sadhasivam 493ff65ffe4SManivannan Sadhasivam /* Reset the SDC controller to clear all previous states */ 494ff65ffe4SManivannan Sadhasivam owl_mmc_ctr_reset(owl_host); 495ff65ffe4SManivannan Sadhasivam clk_prepare_enable(owl_host->clk); 496ff65ffe4SManivannan Sadhasivam writel(OWL_SD_ENABLE | OWL_SD_EN_RESE, 497ff65ffe4SManivannan Sadhasivam owl_host->base + OWL_REG_SD_EN); 498ff65ffe4SManivannan Sadhasivam 499ff65ffe4SManivannan Sadhasivam break; 500ff65ffe4SManivannan Sadhasivam 501ff65ffe4SManivannan Sadhasivam case MMC_POWER_ON: 502ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card on\n"); 503ff65ffe4SManivannan Sadhasivam owl_mmc_power_on(owl_host); 504ff65ffe4SManivannan Sadhasivam 505ff65ffe4SManivannan Sadhasivam break; 506ff65ffe4SManivannan Sadhasivam 507ff65ffe4SManivannan Sadhasivam case MMC_POWER_OFF: 508ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Powering card off\n"); 509ff65ffe4SManivannan Sadhasivam clk_disable_unprepare(owl_host->clk); 510ff65ffe4SManivannan Sadhasivam 511ff65ffe4SManivannan Sadhasivam return; 512ff65ffe4SManivannan Sadhasivam 513ff65ffe4SManivannan Sadhasivam default: 514ff65ffe4SManivannan Sadhasivam dev_dbg(owl_host->dev, "Ignoring unknown card power state\n"); 515ff65ffe4SManivannan Sadhasivam break; 516ff65ffe4SManivannan Sadhasivam } 517ff65ffe4SManivannan Sadhasivam 518ff65ffe4SManivannan Sadhasivam if (ios->clock != owl_host->clock) 519ff65ffe4SManivannan Sadhasivam owl_mmc_set_clk(owl_host, ios); 520ff65ffe4SManivannan Sadhasivam 521ff65ffe4SManivannan Sadhasivam owl_mmc_set_bus_width(owl_host, ios); 522ff65ffe4SManivannan Sadhasivam 523ff65ffe4SManivannan Sadhasivam /* Enable DDR mode if requested */ 524ff65ffe4SManivannan Sadhasivam if (ios->timing == MMC_TIMING_UHS_DDR50) { 5251f71b0bfSZou Wei owl_host->ddr_50 = true; 526ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 527ff65ffe4SManivannan Sadhasivam OWL_SD_EN_DDREN, true); 528ff65ffe4SManivannan Sadhasivam } else { 5291f71b0bfSZou Wei owl_host->ddr_50 = false; 530ff65ffe4SManivannan Sadhasivam } 531ff65ffe4SManivannan Sadhasivam } 532ff65ffe4SManivannan Sadhasivam 533ff65ffe4SManivannan Sadhasivam static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc, 534ff65ffe4SManivannan Sadhasivam struct mmc_ios *ios) 535ff65ffe4SManivannan Sadhasivam { 536ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 537ff65ffe4SManivannan Sadhasivam 538ff65ffe4SManivannan Sadhasivam /* It is enough to change the pad ctrl bit for voltage switch */ 539ff65ffe4SManivannan Sadhasivam switch (ios->signal_voltage) { 540ff65ffe4SManivannan Sadhasivam case MMC_SIGNAL_VOLTAGE_330: 541ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 542ff65ffe4SManivannan Sadhasivam OWL_SD_EN_S18EN, false); 543ff65ffe4SManivannan Sadhasivam break; 544ff65ffe4SManivannan Sadhasivam case MMC_SIGNAL_VOLTAGE_180: 545ff65ffe4SManivannan Sadhasivam owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, 546ff65ffe4SManivannan Sadhasivam OWL_SD_EN_S18EN, true); 547ff65ffe4SManivannan Sadhasivam break; 548ff65ffe4SManivannan Sadhasivam default: 549ff65ffe4SManivannan Sadhasivam return -ENOTSUPP; 550ff65ffe4SManivannan Sadhasivam } 551ff65ffe4SManivannan Sadhasivam 552ff65ffe4SManivannan Sadhasivam return 0; 553ff65ffe4SManivannan Sadhasivam } 554ff65ffe4SManivannan Sadhasivam 555ff65ffe4SManivannan Sadhasivam static const struct mmc_host_ops owl_mmc_ops = { 556ff65ffe4SManivannan Sadhasivam .request = owl_mmc_request, 557ff65ffe4SManivannan Sadhasivam .set_ios = owl_mmc_set_ios, 558ff65ffe4SManivannan Sadhasivam .get_ro = mmc_gpio_get_ro, 559ff65ffe4SManivannan Sadhasivam .get_cd = mmc_gpio_get_cd, 560ff65ffe4SManivannan Sadhasivam .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch, 561ff65ffe4SManivannan Sadhasivam }; 562ff65ffe4SManivannan Sadhasivam 563ff65ffe4SManivannan Sadhasivam static int owl_mmc_probe(struct platform_device *pdev) 564ff65ffe4SManivannan Sadhasivam { 565ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host; 566ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc; 567ff65ffe4SManivannan Sadhasivam struct resource *res; 568ff65ffe4SManivannan Sadhasivam int ret; 569ff65ffe4SManivannan Sadhasivam 570ff65ffe4SManivannan Sadhasivam mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev); 571ff65ffe4SManivannan Sadhasivam if (!mmc) { 572ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "mmc alloc host failed\n"); 573ff65ffe4SManivannan Sadhasivam return -ENOMEM; 574ff65ffe4SManivannan Sadhasivam } 575ff65ffe4SManivannan Sadhasivam platform_set_drvdata(pdev, mmc); 576ff65ffe4SManivannan Sadhasivam 577ff65ffe4SManivannan Sadhasivam owl_host = mmc_priv(mmc); 578ff65ffe4SManivannan Sadhasivam owl_host->dev = &pdev->dev; 579ff65ffe4SManivannan Sadhasivam owl_host->mmc = mmc; 580ff65ffe4SManivannan Sadhasivam spin_lock_init(&owl_host->lock); 581ff65ffe4SManivannan Sadhasivam 582c66c55beSYang Li owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 583ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->base)) { 584ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->base); 585ff65ffe4SManivannan Sadhasivam goto err_free_host; 586ff65ffe4SManivannan Sadhasivam } 587ff65ffe4SManivannan Sadhasivam 588ff65ffe4SManivannan Sadhasivam owl_host->clk = devm_clk_get(&pdev->dev, NULL); 589ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->clk)) { 590ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "No clock defined\n"); 591ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->clk); 592ff65ffe4SManivannan Sadhasivam goto err_free_host; 593ff65ffe4SManivannan Sadhasivam } 594ff65ffe4SManivannan Sadhasivam 595ff65ffe4SManivannan Sadhasivam owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 596ff65ffe4SManivannan Sadhasivam if (IS_ERR(owl_host->reset)) { 597ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Could not get reset control\n"); 598ff65ffe4SManivannan Sadhasivam ret = PTR_ERR(owl_host->reset); 599ff65ffe4SManivannan Sadhasivam goto err_free_host; 600ff65ffe4SManivannan Sadhasivam } 601ff65ffe4SManivannan Sadhasivam 602ff65ffe4SManivannan Sadhasivam mmc->ops = &owl_mmc_ops; 603ff65ffe4SManivannan Sadhasivam mmc->max_blk_count = 512; 604ff65ffe4SManivannan Sadhasivam mmc->max_blk_size = 512; 605ff65ffe4SManivannan Sadhasivam mmc->max_segs = 256; 606ff65ffe4SManivannan Sadhasivam mmc->max_seg_size = 262144; 607ff65ffe4SManivannan Sadhasivam mmc->max_req_size = 262144; 608ff65ffe4SManivannan Sadhasivam /* 100kHz ~ 52MHz */ 609ff65ffe4SManivannan Sadhasivam mmc->f_min = 100000; 610ff65ffe4SManivannan Sadhasivam mmc->f_max = 52000000; 611ff65ffe4SManivannan Sadhasivam mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 612ff65ffe4SManivannan Sadhasivam MMC_CAP_4_BIT_DATA; 613ff65ffe4SManivannan Sadhasivam mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO); 614ff65ffe4SManivannan Sadhasivam mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | 615ff65ffe4SManivannan Sadhasivam MMC_VDD_165_195; 616ff65ffe4SManivannan Sadhasivam 617ff65ffe4SManivannan Sadhasivam ret = mmc_of_parse(mmc); 618ff65ffe4SManivannan Sadhasivam if (ret) 619ff65ffe4SManivannan Sadhasivam goto err_free_host; 620ff65ffe4SManivannan Sadhasivam 621ff65ffe4SManivannan Sadhasivam pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 622ff65ffe4SManivannan Sadhasivam pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 6232e2d12e1SPeter Ujfalusi owl_host->dma = dma_request_chan(&pdev->dev, "mmc"); 6242e2d12e1SPeter Ujfalusi if (IS_ERR(owl_host->dma)) { 625ff65ffe4SManivannan Sadhasivam dev_err(owl_host->dev, "Failed to get external DMA channel.\n"); 6262e2d12e1SPeter Ujfalusi ret = PTR_ERR(owl_host->dma); 627ff65ffe4SManivannan Sadhasivam goto err_free_host; 628ff65ffe4SManivannan Sadhasivam } 629ff65ffe4SManivannan Sadhasivam 630ff65ffe4SManivannan Sadhasivam dev_info(&pdev->dev, "Using %s for DMA transfers\n", 631ff65ffe4SManivannan Sadhasivam dma_chan_name(owl_host->dma)); 632ff65ffe4SManivannan Sadhasivam 633ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT; 634ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT; 635ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 636ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 637ff65ffe4SManivannan Sadhasivam owl_host->dma_cfg.device_fc = false; 638ff65ffe4SManivannan Sadhasivam 639ff65ffe4SManivannan Sadhasivam owl_host->irq = platform_get_irq(pdev, 0); 640ff65ffe4SManivannan Sadhasivam if (owl_host->irq < 0) { 6413c482e1eSSergey Shtylyov ret = owl_host->irq; 6425d15cbf6SChristophe JAILLET goto err_release_channel; 643ff65ffe4SManivannan Sadhasivam } 644ff65ffe4SManivannan Sadhasivam 645ff65ffe4SManivannan Sadhasivam ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler, 646ff65ffe4SManivannan Sadhasivam 0, dev_name(&pdev->dev), owl_host); 647ff65ffe4SManivannan Sadhasivam if (ret) { 648ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Failed to request irq %d\n", 649ff65ffe4SManivannan Sadhasivam owl_host->irq); 6505d15cbf6SChristophe JAILLET goto err_release_channel; 651ff65ffe4SManivannan Sadhasivam } 652ff65ffe4SManivannan Sadhasivam 653ff65ffe4SManivannan Sadhasivam ret = mmc_add_host(mmc); 654ff65ffe4SManivannan Sadhasivam if (ret) { 655ff65ffe4SManivannan Sadhasivam dev_err(&pdev->dev, "Failed to add host\n"); 6565d15cbf6SChristophe JAILLET goto err_release_channel; 657ff65ffe4SManivannan Sadhasivam } 658ff65ffe4SManivannan Sadhasivam 659ff65ffe4SManivannan Sadhasivam dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n"); 660ff65ffe4SManivannan Sadhasivam 661ff65ffe4SManivannan Sadhasivam return 0; 662ff65ffe4SManivannan Sadhasivam 6635d15cbf6SChristophe JAILLET err_release_channel: 6645d15cbf6SChristophe JAILLET dma_release_channel(owl_host->dma); 665ff65ffe4SManivannan Sadhasivam err_free_host: 666ff65ffe4SManivannan Sadhasivam mmc_free_host(mmc); 667ff65ffe4SManivannan Sadhasivam 668ff65ffe4SManivannan Sadhasivam return ret; 669ff65ffe4SManivannan Sadhasivam } 670ff65ffe4SManivannan Sadhasivam 671ff65ffe4SManivannan Sadhasivam static int owl_mmc_remove(struct platform_device *pdev) 672ff65ffe4SManivannan Sadhasivam { 673ff65ffe4SManivannan Sadhasivam struct mmc_host *mmc = platform_get_drvdata(pdev); 674ff65ffe4SManivannan Sadhasivam struct owl_mmc_host *owl_host = mmc_priv(mmc); 675ff65ffe4SManivannan Sadhasivam 676ff65ffe4SManivannan Sadhasivam mmc_remove_host(mmc); 677ff65ffe4SManivannan Sadhasivam disable_irq(owl_host->irq); 6785d15cbf6SChristophe JAILLET dma_release_channel(owl_host->dma); 679ff65ffe4SManivannan Sadhasivam mmc_free_host(mmc); 680ff65ffe4SManivannan Sadhasivam 681ff65ffe4SManivannan Sadhasivam return 0; 682ff65ffe4SManivannan Sadhasivam } 683ff65ffe4SManivannan Sadhasivam 684ff65ffe4SManivannan Sadhasivam static const struct of_device_id owl_mmc_of_match[] = { 685ff65ffe4SManivannan Sadhasivam {.compatible = "actions,owl-mmc",}, 686ff65ffe4SManivannan Sadhasivam { /* sentinel */ } 687ff65ffe4SManivannan Sadhasivam }; 688ff65ffe4SManivannan Sadhasivam MODULE_DEVICE_TABLE(of, owl_mmc_of_match); 689ff65ffe4SManivannan Sadhasivam 690ff65ffe4SManivannan Sadhasivam static struct platform_driver owl_mmc_driver = { 691ff65ffe4SManivannan Sadhasivam .driver = { 692ff65ffe4SManivannan Sadhasivam .name = "owl_mmc", 69331ae4035SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 694f8884711SManivannan Sadhasivam .of_match_table = owl_mmc_of_match, 695ff65ffe4SManivannan Sadhasivam }, 696ff65ffe4SManivannan Sadhasivam .probe = owl_mmc_probe, 697ff65ffe4SManivannan Sadhasivam .remove = owl_mmc_remove, 698ff65ffe4SManivannan Sadhasivam }; 699ff65ffe4SManivannan Sadhasivam module_platform_driver(owl_mmc_driver); 700ff65ffe4SManivannan Sadhasivam 701ff65ffe4SManivannan Sadhasivam MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver"); 702ff65ffe4SManivannan Sadhasivam MODULE_AUTHOR("Actions Semi"); 703ff65ffe4SManivannan Sadhasivam MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 704ff65ffe4SManivannan Sadhasivam MODULE_LICENSE("GPL"); 705