1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/debugfs.h> 21 #include <linux/seq_file.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/platform_device.h> 26 #include <linux/workqueue.h> 27 #include <linux/timer.h> 28 #include <linux/clk.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/io.h> 33 #include <linux/semaphore.h> 34 #include <linux/gpio.h> 35 #include <linux/regulator/consumer.h> 36 #include <plat/dma.h> 37 #include <mach/hardware.h> 38 #include <plat/board.h> 39 #include <plat/mmc.h> 40 #include <plat/cpu.h> 41 42 /* OMAP HSMMC Host Controller Registers */ 43 #define OMAP_HSMMC_SYSCONFIG 0x0010 44 #define OMAP_HSMMC_SYSSTATUS 0x0014 45 #define OMAP_HSMMC_CON 0x002C 46 #define OMAP_HSMMC_BLK 0x0104 47 #define OMAP_HSMMC_ARG 0x0108 48 #define OMAP_HSMMC_CMD 0x010C 49 #define OMAP_HSMMC_RSP10 0x0110 50 #define OMAP_HSMMC_RSP32 0x0114 51 #define OMAP_HSMMC_RSP54 0x0118 52 #define OMAP_HSMMC_RSP76 0x011C 53 #define OMAP_HSMMC_DATA 0x0120 54 #define OMAP_HSMMC_HCTL 0x0128 55 #define OMAP_HSMMC_SYSCTL 0x012C 56 #define OMAP_HSMMC_STAT 0x0130 57 #define OMAP_HSMMC_IE 0x0134 58 #define OMAP_HSMMC_ISE 0x0138 59 #define OMAP_HSMMC_CAPA 0x0140 60 61 #define VS18 (1 << 26) 62 #define VS30 (1 << 25) 63 #define SDVS18 (0x5 << 9) 64 #define SDVS30 (0x6 << 9) 65 #define SDVS33 (0x7 << 9) 66 #define SDVS_MASK 0x00000E00 67 #define SDVSCLR 0xFFFFF1FF 68 #define SDVSDET 0x00000400 69 #define AUTOIDLE 0x1 70 #define SDBP (1 << 8) 71 #define DTO 0xe 72 #define ICE 0x1 73 #define ICS 0x2 74 #define CEN (1 << 2) 75 #define CLKD_MASK 0x0000FFC0 76 #define CLKD_SHIFT 6 77 #define DTO_MASK 0x000F0000 78 #define DTO_SHIFT 16 79 #define INT_EN_MASK 0x307F0033 80 #define BWR_ENABLE (1 << 4) 81 #define BRR_ENABLE (1 << 5) 82 #define DTO_ENABLE (1 << 20) 83 #define INIT_STREAM (1 << 1) 84 #define DP_SELECT (1 << 21) 85 #define DDIR (1 << 4) 86 #define DMA_EN 0x1 87 #define MSBS (1 << 5) 88 #define BCE (1 << 1) 89 #define FOUR_BIT (1 << 1) 90 #define DW8 (1 << 5) 91 #define CC 0x1 92 #define TC 0x02 93 #define OD 0x1 94 #define ERR (1 << 15) 95 #define CMD_TIMEOUT (1 << 16) 96 #define DATA_TIMEOUT (1 << 20) 97 #define CMD_CRC (1 << 17) 98 #define DATA_CRC (1 << 21) 99 #define CARD_ERR (1 << 28) 100 #define STAT_CLEAR 0xFFFFFFFF 101 #define INIT_STREAM_CMD 0x00000000 102 #define DUAL_VOLT_OCR_BIT 7 103 #define SRC (1 << 25) 104 #define SRD (1 << 26) 105 #define SOFTRESET (1 << 1) 106 #define RESETDONE (1 << 0) 107 108 /* 109 * FIXME: Most likely all the data using these _DEVID defines should come 110 * from the platform_data, or implemented in controller and slot specific 111 * functions. 112 */ 113 #define OMAP_MMC1_DEVID 0 114 #define OMAP_MMC2_DEVID 1 115 #define OMAP_MMC3_DEVID 2 116 #define OMAP_MMC4_DEVID 3 117 #define OMAP_MMC5_DEVID 4 118 119 #define MMC_TIMEOUT_MS 20 120 #define OMAP_MMC_MASTER_CLOCK 96000000 121 #define DRIVER_NAME "mmci-omap-hs" 122 123 /* Timeouts for entering power saving states on inactivity, msec */ 124 #define OMAP_MMC_DISABLED_TIMEOUT 100 125 #define OMAP_MMC_SLEEP_TIMEOUT 1000 126 #define OMAP_MMC_OFF_TIMEOUT 8000 127 128 /* 129 * One controller can have multiple slots, like on some omap boards using 130 * omap.c controller driver. Luckily this is not currently done on any known 131 * omap_hsmmc.c device. 132 */ 133 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 134 135 /* 136 * MMC Host controller read/write API's 137 */ 138 #define OMAP_HSMMC_READ(base, reg) \ 139 __raw_readl((base) + OMAP_HSMMC_##reg) 140 141 #define OMAP_HSMMC_WRITE(base, reg, val) \ 142 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 143 144 struct omap_hsmmc_host { 145 struct device *dev; 146 struct mmc_host *mmc; 147 struct mmc_request *mrq; 148 struct mmc_command *cmd; 149 struct mmc_data *data; 150 struct clk *fclk; 151 struct clk *iclk; 152 struct clk *dbclk; 153 /* 154 * vcc == configured supply 155 * vcc_aux == optional 156 * - MMC1, supply for DAT4..DAT7 157 * - MMC2/MMC2, external level shifter voltage supply, for 158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 159 */ 160 struct regulator *vcc; 161 struct regulator *vcc_aux; 162 struct work_struct mmc_carddetect_work; 163 void __iomem *base; 164 resource_size_t mapbase; 165 spinlock_t irq_lock; /* Prevent races with irq handler */ 166 unsigned int id; 167 unsigned int dma_len; 168 unsigned int dma_sg_idx; 169 unsigned char bus_mode; 170 unsigned char power_mode; 171 u32 *buffer; 172 u32 bytesleft; 173 int suspended; 174 int irq; 175 int use_dma, dma_ch; 176 int dma_line_tx, dma_line_rx; 177 int slot_id; 178 int got_dbclk; 179 int response_busy; 180 int context_loss; 181 int dpm_state; 182 int vdd; 183 int protect_card; 184 int reqs_blocked; 185 int use_reg; 186 int req_in_progress; 187 188 struct omap_mmc_platform_data *pdata; 189 }; 190 191 static int omap_hsmmc_card_detect(struct device *dev, int slot) 192 { 193 struct omap_mmc_platform_data *mmc = dev->platform_data; 194 195 /* NOTE: assumes card detect signal is active-low */ 196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 197 } 198 199 static int omap_hsmmc_get_wp(struct device *dev, int slot) 200 { 201 struct omap_mmc_platform_data *mmc = dev->platform_data; 202 203 /* NOTE: assumes write protect signal is active-high */ 204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 205 } 206 207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 208 { 209 struct omap_mmc_platform_data *mmc = dev->platform_data; 210 211 /* NOTE: assumes card detect signal is active-low */ 212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 213 } 214 215 #ifdef CONFIG_PM 216 217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 218 { 219 struct omap_mmc_platform_data *mmc = dev->platform_data; 220 221 disable_irq(mmc->slots[0].card_detect_irq); 222 return 0; 223 } 224 225 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 226 { 227 struct omap_mmc_platform_data *mmc = dev->platform_data; 228 229 enable_irq(mmc->slots[0].card_detect_irq); 230 return 0; 231 } 232 233 #else 234 235 #define omap_hsmmc_suspend_cdirq NULL 236 #define omap_hsmmc_resume_cdirq NULL 237 238 #endif 239 240 #ifdef CONFIG_REGULATOR 241 242 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 243 int vdd) 244 { 245 struct omap_hsmmc_host *host = 246 platform_get_drvdata(to_platform_device(dev)); 247 int ret; 248 249 if (mmc_slot(host).before_set_reg) 250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 251 252 if (power_on) 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 254 else 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 256 257 if (mmc_slot(host).after_set_reg) 258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 259 260 return ret; 261 } 262 263 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, 264 int vdd) 265 { 266 struct omap_hsmmc_host *host = 267 platform_get_drvdata(to_platform_device(dev)); 268 int ret = 0; 269 270 /* 271 * If we don't see a Vcc regulator, assume it's a fixed 272 * voltage always-on regulator. 273 */ 274 if (!host->vcc) 275 return 0; 276 277 if (mmc_slot(host).before_set_reg) 278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 279 280 /* 281 * Assume Vcc regulator is used only to power the card ... OMAP 282 * VDDS is used to power the pins, optionally with a transceiver to 283 * support cards using voltages other than VDDS (1.8V nominal). When a 284 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 285 * 286 * In some cases this regulator won't support enable/disable; 287 * e.g. it's a fixed rail for a WLAN chip. 288 * 289 * In other cases vcc_aux switches interface power. Example, for 290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 291 * chips/cards need an interface voltage rail too. 292 */ 293 if (power_on) { 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 295 /* Enable interface voltage rail, if needed */ 296 if (ret == 0 && host->vcc_aux) { 297 ret = regulator_enable(host->vcc_aux); 298 if (ret < 0) 299 ret = mmc_regulator_set_ocr(host->mmc, 300 host->vcc, 0); 301 } 302 } else { 303 /* Shut down the rail */ 304 if (host->vcc_aux) 305 ret = regulator_disable(host->vcc_aux); 306 if (!ret) { 307 /* Then proceed to shut down the local regulator */ 308 ret = mmc_regulator_set_ocr(host->mmc, 309 host->vcc, 0); 310 } 311 } 312 313 if (mmc_slot(host).after_set_reg) 314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 315 316 return ret; 317 } 318 319 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 320 int vdd, int cardsleep) 321 { 322 struct omap_hsmmc_host *host = 323 platform_get_drvdata(to_platform_device(dev)); 324 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 325 326 return regulator_set_mode(host->vcc, mode); 327 } 328 329 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, 330 int vdd, int cardsleep) 331 { 332 struct omap_hsmmc_host *host = 333 platform_get_drvdata(to_platform_device(dev)); 334 int err, mode; 335 336 /* 337 * If we don't see a Vcc regulator, assume it's a fixed 338 * voltage always-on regulator. 339 */ 340 if (!host->vcc) 341 return 0; 342 343 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 344 345 if (!host->vcc_aux) 346 return regulator_set_mode(host->vcc, mode); 347 348 if (cardsleep) { 349 /* VCC can be turned off if card is asleep */ 350 if (sleep) 351 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 352 else 353 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 354 } else 355 err = regulator_set_mode(host->vcc, mode); 356 if (err) 357 return err; 358 359 if (!mmc_slot(host).vcc_aux_disable_is_sleep) 360 return regulator_set_mode(host->vcc_aux, mode); 361 362 if (sleep) 363 return regulator_disable(host->vcc_aux); 364 else 365 return regulator_enable(host->vcc_aux); 366 } 367 368 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 369 { 370 struct regulator *reg; 371 int ret = 0; 372 int ocr_value = 0; 373 374 switch (host->id) { 375 case OMAP_MMC1_DEVID: 376 /* On-chip level shifting via PBIAS0/PBIAS1 */ 377 mmc_slot(host).set_power = omap_hsmmc_1_set_power; 378 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 379 break; 380 case OMAP_MMC2_DEVID: 381 case OMAP_MMC3_DEVID: 382 /* Off-chip level shifting, or none */ 383 mmc_slot(host).set_power = omap_hsmmc_23_set_power; 384 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; 385 break; 386 default: 387 pr_err("MMC%d configuration not supported!\n", host->id); 388 return -EINVAL; 389 } 390 391 reg = regulator_get(host->dev, "vmmc"); 392 if (IS_ERR(reg)) { 393 dev_dbg(host->dev, "vmmc regulator missing\n"); 394 /* 395 * HACK: until fixed.c regulator is usable, 396 * we don't require a main regulator 397 * for MMC2 or MMC3 398 */ 399 if (host->id == OMAP_MMC1_DEVID) { 400 ret = PTR_ERR(reg); 401 goto err; 402 } 403 } else { 404 host->vcc = reg; 405 ocr_value = mmc_regulator_get_ocrmask(reg); 406 if (!mmc_slot(host).ocr_mask) { 407 mmc_slot(host).ocr_mask = ocr_value; 408 } else { 409 if (!(mmc_slot(host).ocr_mask & ocr_value)) { 410 pr_err("MMC%d ocrmask %x is not supported\n", 411 host->id, mmc_slot(host).ocr_mask); 412 mmc_slot(host).ocr_mask = 0; 413 return -EINVAL; 414 } 415 } 416 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); 417 418 /* Allow an aux regulator */ 419 reg = regulator_get(host->dev, "vmmc_aux"); 420 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 421 422 /* 423 * UGLY HACK: workaround regulator framework bugs. 424 * When the bootloader leaves a supply active, it's 425 * initialized with zero usecount ... and we can't 426 * disable it without first enabling it. Until the 427 * framework is fixed, we need a workaround like this 428 * (which is safe for MMC, but not in general). 429 */ 430 if (regulator_is_enabled(host->vcc) > 0) { 431 regulator_enable(host->vcc); 432 regulator_disable(host->vcc); 433 } 434 if (host->vcc_aux) { 435 if (regulator_is_enabled(reg) > 0) { 436 regulator_enable(reg); 437 regulator_disable(reg); 438 } 439 } 440 } 441 442 return 0; 443 444 err: 445 mmc_slot(host).set_power = NULL; 446 mmc_slot(host).set_sleep = NULL; 447 return ret; 448 } 449 450 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 451 { 452 regulator_put(host->vcc); 453 regulator_put(host->vcc_aux); 454 mmc_slot(host).set_power = NULL; 455 mmc_slot(host).set_sleep = NULL; 456 } 457 458 static inline int omap_hsmmc_have_reg(void) 459 { 460 return 1; 461 } 462 463 #else 464 465 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 466 { 467 return -EINVAL; 468 } 469 470 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 471 { 472 } 473 474 static inline int omap_hsmmc_have_reg(void) 475 { 476 return 0; 477 } 478 479 #endif 480 481 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 482 { 483 int ret; 484 485 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 486 if (pdata->slots[0].cover) 487 pdata->slots[0].get_cover_state = 488 omap_hsmmc_get_cover_state; 489 else 490 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 491 pdata->slots[0].card_detect_irq = 492 gpio_to_irq(pdata->slots[0].switch_pin); 493 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 494 if (ret) 495 return ret; 496 ret = gpio_direction_input(pdata->slots[0].switch_pin); 497 if (ret) 498 goto err_free_sp; 499 } else 500 pdata->slots[0].switch_pin = -EINVAL; 501 502 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 503 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 504 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 505 if (ret) 506 goto err_free_cd; 507 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 508 if (ret) 509 goto err_free_wp; 510 } else 511 pdata->slots[0].gpio_wp = -EINVAL; 512 513 return 0; 514 515 err_free_wp: 516 gpio_free(pdata->slots[0].gpio_wp); 517 err_free_cd: 518 if (gpio_is_valid(pdata->slots[0].switch_pin)) 519 err_free_sp: 520 gpio_free(pdata->slots[0].switch_pin); 521 return ret; 522 } 523 524 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 525 { 526 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 527 gpio_free(pdata->slots[0].gpio_wp); 528 if (gpio_is_valid(pdata->slots[0].switch_pin)) 529 gpio_free(pdata->slots[0].switch_pin); 530 } 531 532 /* 533 * Stop clock to the card 534 */ 535 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 536 { 537 OMAP_HSMMC_WRITE(host->base, SYSCTL, 538 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 539 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 540 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 541 } 542 543 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 544 struct mmc_command *cmd) 545 { 546 unsigned int irq_mask; 547 548 if (host->use_dma) 549 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 550 else 551 irq_mask = INT_EN_MASK; 552 553 /* Disable timeout for erases */ 554 if (cmd->opcode == MMC_ERASE) 555 irq_mask &= ~DTO_ENABLE; 556 557 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 558 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 559 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 560 } 561 562 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 563 { 564 OMAP_HSMMC_WRITE(host->base, ISE, 0); 565 OMAP_HSMMC_WRITE(host->base, IE, 0); 566 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 567 } 568 569 #ifdef CONFIG_PM 570 571 /* 572 * Restore the MMC host context, if it was lost as result of a 573 * power state change. 574 */ 575 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 576 { 577 struct mmc_ios *ios = &host->mmc->ios; 578 struct omap_mmc_platform_data *pdata = host->pdata; 579 int context_loss = 0; 580 u32 hctl, capa, con; 581 u16 dsor = 0; 582 unsigned long timeout; 583 584 if (pdata->get_context_loss_count) { 585 context_loss = pdata->get_context_loss_count(host->dev); 586 if (context_loss < 0) 587 return 1; 588 } 589 590 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 591 context_loss == host->context_loss ? "not " : ""); 592 if (host->context_loss == context_loss) 593 return 1; 594 595 /* Wait for hardware reset */ 596 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 597 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 598 && time_before(jiffies, timeout)) 599 ; 600 601 /* Do software reset */ 602 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 603 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 604 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 605 && time_before(jiffies, timeout)) 606 ; 607 608 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 609 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 610 611 if (host->id == OMAP_MMC1_DEVID) { 612 if (host->power_mode != MMC_POWER_OFF && 613 (1 << ios->vdd) <= MMC_VDD_23_24) 614 hctl = SDVS18; 615 else 616 hctl = SDVS30; 617 capa = VS30 | VS18; 618 } else { 619 hctl = SDVS18; 620 capa = VS18; 621 } 622 623 OMAP_HSMMC_WRITE(host->base, HCTL, 624 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 625 626 OMAP_HSMMC_WRITE(host->base, CAPA, 627 OMAP_HSMMC_READ(host->base, CAPA) | capa); 628 629 OMAP_HSMMC_WRITE(host->base, HCTL, 630 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 631 632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 633 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 634 && time_before(jiffies, timeout)) 635 ; 636 637 omap_hsmmc_disable_irq(host); 638 639 /* Do not initialize card-specific things if the power is off */ 640 if (host->power_mode == MMC_POWER_OFF) 641 goto out; 642 643 con = OMAP_HSMMC_READ(host->base, CON); 644 switch (ios->bus_width) { 645 case MMC_BUS_WIDTH_8: 646 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 647 break; 648 case MMC_BUS_WIDTH_4: 649 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 650 OMAP_HSMMC_WRITE(host->base, HCTL, 651 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 652 break; 653 case MMC_BUS_WIDTH_1: 654 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 655 OMAP_HSMMC_WRITE(host->base, HCTL, 656 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 657 break; 658 } 659 660 if (ios->clock) { 661 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 662 if (dsor < 1) 663 dsor = 1; 664 665 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 666 dsor++; 667 668 if (dsor > 250) 669 dsor = 250; 670 } 671 672 OMAP_HSMMC_WRITE(host->base, SYSCTL, 673 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 674 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 675 OMAP_HSMMC_WRITE(host->base, SYSCTL, 676 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 677 678 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 679 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 680 && time_before(jiffies, timeout)) 681 ; 682 683 OMAP_HSMMC_WRITE(host->base, SYSCTL, 684 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 685 686 con = OMAP_HSMMC_READ(host->base, CON); 687 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 688 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 689 else 690 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 691 out: 692 host->context_loss = context_loss; 693 694 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 695 return 0; 696 } 697 698 /* 699 * Save the MMC host context (store the number of power state changes so far). 700 */ 701 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 702 { 703 struct omap_mmc_platform_data *pdata = host->pdata; 704 int context_loss; 705 706 if (pdata->get_context_loss_count) { 707 context_loss = pdata->get_context_loss_count(host->dev); 708 if (context_loss < 0) 709 return; 710 host->context_loss = context_loss; 711 } 712 } 713 714 #else 715 716 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 717 { 718 return 0; 719 } 720 721 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 722 { 723 } 724 725 #endif 726 727 /* 728 * Send init stream sequence to card 729 * before sending IDLE command 730 */ 731 static void send_init_stream(struct omap_hsmmc_host *host) 732 { 733 int reg = 0; 734 unsigned long timeout; 735 736 if (host->protect_card) 737 return; 738 739 disable_irq(host->irq); 740 741 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 742 OMAP_HSMMC_WRITE(host->base, CON, 743 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 744 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 745 746 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 747 while ((reg != CC) && time_before(jiffies, timeout)) 748 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 749 750 OMAP_HSMMC_WRITE(host->base, CON, 751 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 752 753 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 754 OMAP_HSMMC_READ(host->base, STAT); 755 756 enable_irq(host->irq); 757 } 758 759 static inline 760 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 761 { 762 int r = 1; 763 764 if (mmc_slot(host).get_cover_state) 765 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 766 return r; 767 } 768 769 static ssize_t 770 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 771 char *buf) 772 { 773 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 774 struct omap_hsmmc_host *host = mmc_priv(mmc); 775 776 return sprintf(buf, "%s\n", 777 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 778 } 779 780 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 781 782 static ssize_t 783 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 784 char *buf) 785 { 786 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 787 struct omap_hsmmc_host *host = mmc_priv(mmc); 788 789 return sprintf(buf, "%s\n", mmc_slot(host).name); 790 } 791 792 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 793 794 /* 795 * Configure the response type and send the cmd. 796 */ 797 static void 798 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 799 struct mmc_data *data) 800 { 801 int cmdreg = 0, resptype = 0, cmdtype = 0; 802 803 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 804 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 805 host->cmd = cmd; 806 807 omap_hsmmc_enable_irq(host, cmd); 808 809 host->response_busy = 0; 810 if (cmd->flags & MMC_RSP_PRESENT) { 811 if (cmd->flags & MMC_RSP_136) 812 resptype = 1; 813 else if (cmd->flags & MMC_RSP_BUSY) { 814 resptype = 3; 815 host->response_busy = 1; 816 } else 817 resptype = 2; 818 } 819 820 /* 821 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 822 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 823 * a val of 0x3, rest 0x0. 824 */ 825 if (cmd == host->mrq->stop) 826 cmdtype = 0x3; 827 828 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 829 830 if (data) { 831 cmdreg |= DP_SELECT | MSBS | BCE; 832 if (data->flags & MMC_DATA_READ) 833 cmdreg |= DDIR; 834 else 835 cmdreg &= ~(DDIR); 836 } 837 838 if (host->use_dma) 839 cmdreg |= DMA_EN; 840 841 host->req_in_progress = 1; 842 843 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 844 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 845 } 846 847 static int 848 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 849 { 850 if (data->flags & MMC_DATA_WRITE) 851 return DMA_TO_DEVICE; 852 else 853 return DMA_FROM_DEVICE; 854 } 855 856 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 857 { 858 int dma_ch; 859 860 spin_lock(&host->irq_lock); 861 host->req_in_progress = 0; 862 dma_ch = host->dma_ch; 863 spin_unlock(&host->irq_lock); 864 865 omap_hsmmc_disable_irq(host); 866 /* Do not complete the request if DMA is still in progress */ 867 if (mrq->data && host->use_dma && dma_ch != -1) 868 return; 869 host->mrq = NULL; 870 mmc_request_done(host->mmc, mrq); 871 } 872 873 /* 874 * Notify the transfer complete to MMC core 875 */ 876 static void 877 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 878 { 879 if (!data) { 880 struct mmc_request *mrq = host->mrq; 881 882 /* TC before CC from CMD6 - don't know why, but it happens */ 883 if (host->cmd && host->cmd->opcode == 6 && 884 host->response_busy) { 885 host->response_busy = 0; 886 return; 887 } 888 889 omap_hsmmc_request_done(host, mrq); 890 return; 891 } 892 893 host->data = NULL; 894 895 if (!data->error) 896 data->bytes_xfered += data->blocks * (data->blksz); 897 else 898 data->bytes_xfered = 0; 899 900 if (!data->stop) { 901 omap_hsmmc_request_done(host, data->mrq); 902 return; 903 } 904 omap_hsmmc_start_command(host, data->stop, NULL); 905 } 906 907 /* 908 * Notify the core about command completion 909 */ 910 static void 911 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 912 { 913 host->cmd = NULL; 914 915 if (cmd->flags & MMC_RSP_PRESENT) { 916 if (cmd->flags & MMC_RSP_136) { 917 /* response type 2 */ 918 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 919 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 920 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 921 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 922 } else { 923 /* response types 1, 1b, 3, 4, 5, 6 */ 924 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 925 } 926 } 927 if ((host->data == NULL && !host->response_busy) || cmd->error) 928 omap_hsmmc_request_done(host, cmd->mrq); 929 } 930 931 /* 932 * DMA clean up for command errors 933 */ 934 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 935 { 936 int dma_ch; 937 938 host->data->error = errno; 939 940 spin_lock(&host->irq_lock); 941 dma_ch = host->dma_ch; 942 host->dma_ch = -1; 943 spin_unlock(&host->irq_lock); 944 945 if (host->use_dma && dma_ch != -1) { 946 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 947 omap_hsmmc_get_dma_dir(host, host->data)); 948 omap_free_dma(dma_ch); 949 } 950 host->data = NULL; 951 } 952 953 /* 954 * Readable error output 955 */ 956 #ifdef CONFIG_MMC_DEBUG 957 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 958 { 959 /* --- means reserved bit without definition at documentation */ 960 static const char *omap_hsmmc_status_bits[] = { 961 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 962 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 963 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 964 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 965 }; 966 char res[256]; 967 char *buf = res; 968 int len, i; 969 970 len = sprintf(buf, "MMC IRQ 0x%x :", status); 971 buf += len; 972 973 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 974 if (status & (1 << i)) { 975 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 976 buf += len; 977 } 978 979 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 980 } 981 #endif /* CONFIG_MMC_DEBUG */ 982 983 /* 984 * MMC controller internal state machines reset 985 * 986 * Used to reset command or data internal state machines, using respectively 987 * SRC or SRD bit of SYSCTL register 988 * Can be called from interrupt context 989 */ 990 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 991 unsigned long bit) 992 { 993 unsigned long i = 0; 994 unsigned long limit = (loops_per_jiffy * 995 msecs_to_jiffies(MMC_TIMEOUT_MS)); 996 997 OMAP_HSMMC_WRITE(host->base, SYSCTL, 998 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 999 1000 /* 1001 * OMAP4 ES2 and greater has an updated reset logic. 1002 * Monitor a 0->1 transition first 1003 */ 1004 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1005 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 1006 && (i++ < limit)) 1007 cpu_relax(); 1008 } 1009 i = 0; 1010 1011 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 1012 (i++ < limit)) 1013 cpu_relax(); 1014 1015 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1016 dev_err(mmc_dev(host->mmc), 1017 "Timeout waiting on controller reset in %s\n", 1018 __func__); 1019 } 1020 1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1022 { 1023 struct mmc_data *data; 1024 int end_cmd = 0, end_trans = 0; 1025 1026 if (!host->req_in_progress) { 1027 do { 1028 OMAP_HSMMC_WRITE(host->base, STAT, status); 1029 /* Flush posted write */ 1030 status = OMAP_HSMMC_READ(host->base, STAT); 1031 } while (status & INT_EN_MASK); 1032 return; 1033 } 1034 1035 data = host->data; 1036 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1037 1038 if (status & ERR) { 1039 #ifdef CONFIG_MMC_DEBUG 1040 omap_hsmmc_report_irq(host, status); 1041 #endif 1042 if ((status & CMD_TIMEOUT) || 1043 (status & CMD_CRC)) { 1044 if (host->cmd) { 1045 if (status & CMD_TIMEOUT) { 1046 omap_hsmmc_reset_controller_fsm(host, 1047 SRC); 1048 host->cmd->error = -ETIMEDOUT; 1049 } else { 1050 host->cmd->error = -EILSEQ; 1051 } 1052 end_cmd = 1; 1053 } 1054 if (host->data || host->response_busy) { 1055 if (host->data) 1056 omap_hsmmc_dma_cleanup(host, 1057 -ETIMEDOUT); 1058 host->response_busy = 0; 1059 omap_hsmmc_reset_controller_fsm(host, SRD); 1060 } 1061 } 1062 if ((status & DATA_TIMEOUT) || 1063 (status & DATA_CRC)) { 1064 if (host->data || host->response_busy) { 1065 int err = (status & DATA_TIMEOUT) ? 1066 -ETIMEDOUT : -EILSEQ; 1067 1068 if (host->data) 1069 omap_hsmmc_dma_cleanup(host, err); 1070 else 1071 host->mrq->cmd->error = err; 1072 host->response_busy = 0; 1073 omap_hsmmc_reset_controller_fsm(host, SRD); 1074 end_trans = 1; 1075 } 1076 } 1077 if (status & CARD_ERR) { 1078 dev_dbg(mmc_dev(host->mmc), 1079 "Ignoring card err CMD%d\n", host->cmd->opcode); 1080 if (host->cmd) 1081 end_cmd = 1; 1082 if (host->data) 1083 end_trans = 1; 1084 } 1085 } 1086 1087 OMAP_HSMMC_WRITE(host->base, STAT, status); 1088 1089 if (end_cmd || ((status & CC) && host->cmd)) 1090 omap_hsmmc_cmd_done(host, host->cmd); 1091 if ((end_trans || (status & TC)) && host->mrq) 1092 omap_hsmmc_xfer_done(host, data); 1093 } 1094 1095 /* 1096 * MMC controller IRQ handler 1097 */ 1098 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1099 { 1100 struct omap_hsmmc_host *host = dev_id; 1101 int status; 1102 1103 status = OMAP_HSMMC_READ(host->base, STAT); 1104 do { 1105 omap_hsmmc_do_irq(host, status); 1106 /* Flush posted write */ 1107 status = OMAP_HSMMC_READ(host->base, STAT); 1108 } while (status & INT_EN_MASK); 1109 1110 return IRQ_HANDLED; 1111 } 1112 1113 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1114 { 1115 unsigned long i; 1116 1117 OMAP_HSMMC_WRITE(host->base, HCTL, 1118 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1119 for (i = 0; i < loops_per_jiffy; i++) { 1120 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1121 break; 1122 cpu_relax(); 1123 } 1124 } 1125 1126 /* 1127 * Switch MMC interface voltage ... only relevant for MMC1. 1128 * 1129 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1130 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1131 * Some chips, like eMMC ones, use internal transceivers. 1132 */ 1133 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1134 { 1135 u32 reg_val = 0; 1136 int ret; 1137 1138 /* Disable the clocks */ 1139 clk_disable(host->fclk); 1140 clk_disable(host->iclk); 1141 if (host->got_dbclk) 1142 clk_disable(host->dbclk); 1143 1144 /* Turn the power off */ 1145 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1146 1147 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1148 if (!ret) 1149 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1150 vdd); 1151 clk_enable(host->iclk); 1152 clk_enable(host->fclk); 1153 if (host->got_dbclk) 1154 clk_enable(host->dbclk); 1155 1156 if (ret != 0) 1157 goto err; 1158 1159 OMAP_HSMMC_WRITE(host->base, HCTL, 1160 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1161 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1162 1163 /* 1164 * If a MMC dual voltage card is detected, the set_ios fn calls 1165 * this fn with VDD bit set for 1.8V. Upon card removal from the 1166 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1167 * 1168 * Cope with a bit of slop in the range ... per data sheets: 1169 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1170 * but recommended values are 1.71V to 1.89V 1171 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1172 * but recommended values are 2.7V to 3.3V 1173 * 1174 * Board setup code shouldn't permit anything very out-of-range. 1175 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1176 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1177 */ 1178 if ((1 << vdd) <= MMC_VDD_23_24) 1179 reg_val |= SDVS18; 1180 else 1181 reg_val |= SDVS30; 1182 1183 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1184 set_sd_bus_power(host); 1185 1186 return 0; 1187 err: 1188 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1189 return ret; 1190 } 1191 1192 /* Protect the card while the cover is open */ 1193 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1194 { 1195 if (!mmc_slot(host).get_cover_state) 1196 return; 1197 1198 host->reqs_blocked = 0; 1199 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1200 if (host->protect_card) { 1201 printk(KERN_INFO "%s: cover is closed, " 1202 "card is now accessible\n", 1203 mmc_hostname(host->mmc)); 1204 host->protect_card = 0; 1205 } 1206 } else { 1207 if (!host->protect_card) { 1208 printk(KERN_INFO "%s: cover is open, " 1209 "card is now inaccessible\n", 1210 mmc_hostname(host->mmc)); 1211 host->protect_card = 1; 1212 } 1213 } 1214 } 1215 1216 /* 1217 * Work Item to notify the core about card insertion/removal 1218 */ 1219 static void omap_hsmmc_detect(struct work_struct *work) 1220 { 1221 struct omap_hsmmc_host *host = 1222 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1223 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1224 int carddetect; 1225 1226 if (host->suspended) 1227 return; 1228 1229 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1230 1231 if (slot->card_detect) 1232 carddetect = slot->card_detect(host->dev, host->slot_id); 1233 else { 1234 omap_hsmmc_protect_card(host); 1235 carddetect = -ENOSYS; 1236 } 1237 1238 if (carddetect) 1239 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1240 else 1241 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1242 } 1243 1244 /* 1245 * ISR for handling card insertion and removal 1246 */ 1247 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1248 { 1249 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1250 1251 if (host->suspended) 1252 return IRQ_HANDLED; 1253 schedule_work(&host->mmc_carddetect_work); 1254 1255 return IRQ_HANDLED; 1256 } 1257 1258 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 1259 struct mmc_data *data) 1260 { 1261 int sync_dev; 1262 1263 if (data->flags & MMC_DATA_WRITE) 1264 sync_dev = host->dma_line_tx; 1265 else 1266 sync_dev = host->dma_line_rx; 1267 return sync_dev; 1268 } 1269 1270 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 1271 struct mmc_data *data, 1272 struct scatterlist *sgl) 1273 { 1274 int blksz, nblk, dma_ch; 1275 1276 dma_ch = host->dma_ch; 1277 if (data->flags & MMC_DATA_WRITE) { 1278 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1279 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1280 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1281 sg_dma_address(sgl), 0, 0); 1282 } else { 1283 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1284 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1285 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1286 sg_dma_address(sgl), 0, 0); 1287 } 1288 1289 blksz = host->data->blksz; 1290 nblk = sg_dma_len(sgl) / blksz; 1291 1292 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 1293 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 1294 omap_hsmmc_get_dma_sync_dev(host, data), 1295 !(data->flags & MMC_DATA_WRITE)); 1296 1297 omap_start_dma(dma_ch); 1298 } 1299 1300 /* 1301 * DMA call back function 1302 */ 1303 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1304 { 1305 struct omap_hsmmc_host *host = cb_data; 1306 struct mmc_data *data = host->mrq->data; 1307 int dma_ch, req_in_progress; 1308 1309 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1310 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1311 ch_status); 1312 return; 1313 } 1314 1315 spin_lock(&host->irq_lock); 1316 if (host->dma_ch < 0) { 1317 spin_unlock(&host->irq_lock); 1318 return; 1319 } 1320 1321 host->dma_sg_idx++; 1322 if (host->dma_sg_idx < host->dma_len) { 1323 /* Fire up the next transfer. */ 1324 omap_hsmmc_config_dma_params(host, data, 1325 data->sg + host->dma_sg_idx); 1326 spin_unlock(&host->irq_lock); 1327 return; 1328 } 1329 1330 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 1331 omap_hsmmc_get_dma_dir(host, data)); 1332 1333 req_in_progress = host->req_in_progress; 1334 dma_ch = host->dma_ch; 1335 host->dma_ch = -1; 1336 spin_unlock(&host->irq_lock); 1337 1338 omap_free_dma(dma_ch); 1339 1340 /* If DMA has finished after TC, complete the request */ 1341 if (!req_in_progress) { 1342 struct mmc_request *mrq = host->mrq; 1343 1344 host->mrq = NULL; 1345 mmc_request_done(host->mmc, mrq); 1346 } 1347 } 1348 1349 /* 1350 * Routine to configure and start DMA for the MMC card 1351 */ 1352 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1353 struct mmc_request *req) 1354 { 1355 int dma_ch = 0, ret = 0, i; 1356 struct mmc_data *data = req->data; 1357 1358 /* Sanity check: all the SG entries must be aligned by block size. */ 1359 for (i = 0; i < data->sg_len; i++) { 1360 struct scatterlist *sgl; 1361 1362 sgl = data->sg + i; 1363 if (sgl->length % data->blksz) 1364 return -EINVAL; 1365 } 1366 if ((data->blksz % 4) != 0) 1367 /* REVISIT: The MMC buffer increments only when MSB is written. 1368 * Return error for blksz which is non multiple of four. 1369 */ 1370 return -EINVAL; 1371 1372 BUG_ON(host->dma_ch != -1); 1373 1374 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 1375 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1376 if (ret != 0) { 1377 dev_err(mmc_dev(host->mmc), 1378 "%s: omap_request_dma() failed with %d\n", 1379 mmc_hostname(host->mmc), ret); 1380 return ret; 1381 } 1382 1383 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1384 data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 1385 host->dma_ch = dma_ch; 1386 host->dma_sg_idx = 0; 1387 1388 omap_hsmmc_config_dma_params(host, data, data->sg); 1389 1390 return 0; 1391 } 1392 1393 static void set_data_timeout(struct omap_hsmmc_host *host, 1394 unsigned int timeout_ns, 1395 unsigned int timeout_clks) 1396 { 1397 unsigned int timeout, cycle_ns; 1398 uint32_t reg, clkd, dto = 0; 1399 1400 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1401 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1402 if (clkd == 0) 1403 clkd = 1; 1404 1405 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1406 timeout = timeout_ns / cycle_ns; 1407 timeout += timeout_clks; 1408 if (timeout) { 1409 while ((timeout & 0x80000000) == 0) { 1410 dto += 1; 1411 timeout <<= 1; 1412 } 1413 dto = 31 - dto; 1414 timeout <<= 1; 1415 if (timeout && dto) 1416 dto += 1; 1417 if (dto >= 13) 1418 dto -= 13; 1419 else 1420 dto = 0; 1421 if (dto > 14) 1422 dto = 14; 1423 } 1424 1425 reg &= ~DTO_MASK; 1426 reg |= dto << DTO_SHIFT; 1427 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1428 } 1429 1430 /* 1431 * Configure block length for MMC/SD cards and initiate the transfer. 1432 */ 1433 static int 1434 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1435 { 1436 int ret; 1437 host->data = req->data; 1438 1439 if (req->data == NULL) { 1440 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1441 /* 1442 * Set an arbitrary 100ms data timeout for commands with 1443 * busy signal. 1444 */ 1445 if (req->cmd->flags & MMC_RSP_BUSY) 1446 set_data_timeout(host, 100000000U, 0); 1447 return 0; 1448 } 1449 1450 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1451 | (req->data->blocks << 16)); 1452 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1453 1454 if (host->use_dma) { 1455 ret = omap_hsmmc_start_dma_transfer(host, req); 1456 if (ret != 0) { 1457 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1458 return ret; 1459 } 1460 } 1461 return 0; 1462 } 1463 1464 /* 1465 * Request function. for read/write operation 1466 */ 1467 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1468 { 1469 struct omap_hsmmc_host *host = mmc_priv(mmc); 1470 int err; 1471 1472 BUG_ON(host->req_in_progress); 1473 BUG_ON(host->dma_ch != -1); 1474 if (host->protect_card) { 1475 if (host->reqs_blocked < 3) { 1476 /* 1477 * Ensure the controller is left in a consistent 1478 * state by resetting the command and data state 1479 * machines. 1480 */ 1481 omap_hsmmc_reset_controller_fsm(host, SRD); 1482 omap_hsmmc_reset_controller_fsm(host, SRC); 1483 host->reqs_blocked += 1; 1484 } 1485 req->cmd->error = -EBADF; 1486 if (req->data) 1487 req->data->error = -EBADF; 1488 req->cmd->retries = 0; 1489 mmc_request_done(mmc, req); 1490 return; 1491 } else if (host->reqs_blocked) 1492 host->reqs_blocked = 0; 1493 WARN_ON(host->mrq != NULL); 1494 host->mrq = req; 1495 err = omap_hsmmc_prepare_data(host, req); 1496 if (err) { 1497 req->cmd->error = err; 1498 if (req->data) 1499 req->data->error = err; 1500 host->mrq = NULL; 1501 mmc_request_done(mmc, req); 1502 return; 1503 } 1504 1505 omap_hsmmc_start_command(host, req->cmd, req->data); 1506 } 1507 1508 /* Routine to configure clock values. Exposed API to core */ 1509 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1510 { 1511 struct omap_hsmmc_host *host = mmc_priv(mmc); 1512 u16 dsor = 0; 1513 unsigned long regval; 1514 unsigned long timeout; 1515 u32 con; 1516 int do_send_init_stream = 0; 1517 1518 mmc_host_enable(host->mmc); 1519 1520 if (ios->power_mode != host->power_mode) { 1521 switch (ios->power_mode) { 1522 case MMC_POWER_OFF: 1523 mmc_slot(host).set_power(host->dev, host->slot_id, 1524 0, 0); 1525 host->vdd = 0; 1526 break; 1527 case MMC_POWER_UP: 1528 mmc_slot(host).set_power(host->dev, host->slot_id, 1529 1, ios->vdd); 1530 host->vdd = ios->vdd; 1531 break; 1532 case MMC_POWER_ON: 1533 do_send_init_stream = 1; 1534 break; 1535 } 1536 host->power_mode = ios->power_mode; 1537 } 1538 1539 /* FIXME: set registers based only on changes to ios */ 1540 1541 con = OMAP_HSMMC_READ(host->base, CON); 1542 switch (mmc->ios.bus_width) { 1543 case MMC_BUS_WIDTH_8: 1544 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 1545 break; 1546 case MMC_BUS_WIDTH_4: 1547 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1548 OMAP_HSMMC_WRITE(host->base, HCTL, 1549 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1550 break; 1551 case MMC_BUS_WIDTH_1: 1552 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1553 OMAP_HSMMC_WRITE(host->base, HCTL, 1554 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1555 break; 1556 } 1557 1558 if (host->id == OMAP_MMC1_DEVID) { 1559 /* Only MMC1 can interface at 3V without some flavor 1560 * of external transceiver; but they all handle 1.8V. 1561 */ 1562 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1563 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1564 /* 1565 * The mmc_select_voltage fn of the core does 1566 * not seem to set the power_mode to 1567 * MMC_POWER_UP upon recalculating the voltage. 1568 * vdd 1.8v. 1569 */ 1570 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1571 dev_dbg(mmc_dev(host->mmc), 1572 "Switch operation failed\n"); 1573 } 1574 } 1575 1576 if (ios->clock) { 1577 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1578 if (dsor < 1) 1579 dsor = 1; 1580 1581 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1582 dsor++; 1583 1584 if (dsor > 250) 1585 dsor = 250; 1586 } 1587 omap_hsmmc_stop_clock(host); 1588 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1589 regval = regval & ~(CLKD_MASK); 1590 regval = regval | (dsor << 6) | (DTO << 16); 1591 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1592 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1593 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1594 1595 /* Wait till the ICS bit is set */ 1596 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 1597 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1598 && time_before(jiffies, timeout)) 1599 msleep(1); 1600 1601 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1602 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1603 1604 if (do_send_init_stream) 1605 send_init_stream(host); 1606 1607 con = OMAP_HSMMC_READ(host->base, CON); 1608 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1609 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1610 else 1611 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 1612 1613 if (host->power_mode == MMC_POWER_OFF) 1614 mmc_host_disable(host->mmc); 1615 else 1616 mmc_host_lazy_disable(host->mmc); 1617 } 1618 1619 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1620 { 1621 struct omap_hsmmc_host *host = mmc_priv(mmc); 1622 1623 if (!mmc_slot(host).card_detect) 1624 return -ENOSYS; 1625 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1626 } 1627 1628 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1629 { 1630 struct omap_hsmmc_host *host = mmc_priv(mmc); 1631 1632 if (!mmc_slot(host).get_ro) 1633 return -ENOSYS; 1634 return mmc_slot(host).get_ro(host->dev, 0); 1635 } 1636 1637 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1638 { 1639 struct omap_hsmmc_host *host = mmc_priv(mmc); 1640 1641 if (mmc_slot(host).init_card) 1642 mmc_slot(host).init_card(card); 1643 } 1644 1645 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1646 { 1647 u32 hctl, capa, value; 1648 1649 /* Only MMC1 supports 3.0V */ 1650 if (host->id == OMAP_MMC1_DEVID) { 1651 hctl = SDVS30; 1652 capa = VS30 | VS18; 1653 } else { 1654 hctl = SDVS18; 1655 capa = VS18; 1656 } 1657 1658 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1659 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1660 1661 value = OMAP_HSMMC_READ(host->base, CAPA); 1662 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1663 1664 /* Set the controller to AUTO IDLE mode */ 1665 value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 1666 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 1667 1668 /* Set SD bus power bit */ 1669 set_sd_bus_power(host); 1670 } 1671 1672 /* 1673 * Dynamic power saving handling, FSM: 1674 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 1675 * ^___________| | | 1676 * |______________________|______________________| 1677 * 1678 * ENABLED: mmc host is fully functional 1679 * DISABLED: fclk is off 1680 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1681 * REGSLEEP: fclk is off, voltage regulator is asleep 1682 * OFF: fclk is off, voltage regulator is off 1683 * 1684 * Transition handlers return the timeout for the next state transition 1685 * or negative error. 1686 */ 1687 1688 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1689 1690 /* Handler for [ENABLED -> DISABLED] transition */ 1691 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1692 { 1693 omap_hsmmc_context_save(host); 1694 clk_disable(host->fclk); 1695 host->dpm_state = DISABLED; 1696 1697 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1698 1699 if (host->power_mode == MMC_POWER_OFF) 1700 return 0; 1701 1702 return OMAP_MMC_SLEEP_TIMEOUT; 1703 } 1704 1705 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 1706 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1707 { 1708 int err, new_state; 1709 1710 if (!mmc_try_claim_host(host->mmc)) 1711 return 0; 1712 1713 clk_enable(host->fclk); 1714 omap_hsmmc_context_restore(host); 1715 if (mmc_card_can_sleep(host->mmc)) { 1716 err = mmc_card_sleep(host->mmc); 1717 if (err < 0) { 1718 clk_disable(host->fclk); 1719 mmc_release_host(host->mmc); 1720 return err; 1721 } 1722 new_state = CARDSLEEP; 1723 } else { 1724 new_state = REGSLEEP; 1725 } 1726 if (mmc_slot(host).set_sleep) 1727 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 1728 new_state == CARDSLEEP); 1729 /* FIXME: turn off bus power and perhaps interrupts too */ 1730 clk_disable(host->fclk); 1731 host->dpm_state = new_state; 1732 1733 mmc_release_host(host->mmc); 1734 1735 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 1736 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1737 1738 if (mmc_slot(host).no_off) 1739 return 0; 1740 1741 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1742 mmc_slot(host).card_detect || 1743 (mmc_slot(host).get_cover_state && 1744 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 1745 return OMAP_MMC_OFF_TIMEOUT; 1746 1747 return 0; 1748 } 1749 1750 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 1751 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 1752 { 1753 if (!mmc_try_claim_host(host->mmc)) 1754 return 0; 1755 1756 if (mmc_slot(host).no_off) 1757 return 0; 1758 1759 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1760 mmc_slot(host).card_detect || 1761 (mmc_slot(host).get_cover_state && 1762 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 1763 mmc_release_host(host->mmc); 1764 return 0; 1765 } 1766 1767 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1768 host->vdd = 0; 1769 host->power_mode = MMC_POWER_OFF; 1770 1771 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 1772 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1773 1774 host->dpm_state = OFF; 1775 1776 mmc_release_host(host->mmc); 1777 1778 return 0; 1779 } 1780 1781 /* Handler for [DISABLED -> ENABLED] transition */ 1782 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1783 { 1784 int err; 1785 1786 err = clk_enable(host->fclk); 1787 if (err < 0) 1788 return err; 1789 1790 omap_hsmmc_context_restore(host); 1791 host->dpm_state = ENABLED; 1792 1793 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1794 1795 return 0; 1796 } 1797 1798 /* Handler for [SLEEP -> ENABLED] transition */ 1799 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 1800 { 1801 if (!mmc_try_claim_host(host->mmc)) 1802 return 0; 1803 1804 clk_enable(host->fclk); 1805 omap_hsmmc_context_restore(host); 1806 if (mmc_slot(host).set_sleep) 1807 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 1808 host->vdd, host->dpm_state == CARDSLEEP); 1809 if (mmc_card_can_sleep(host->mmc)) 1810 mmc_card_awake(host->mmc); 1811 1812 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 1813 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1814 1815 host->dpm_state = ENABLED; 1816 1817 mmc_release_host(host->mmc); 1818 1819 return 0; 1820 } 1821 1822 /* Handler for [OFF -> ENABLED] transition */ 1823 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1824 { 1825 clk_enable(host->fclk); 1826 1827 omap_hsmmc_context_restore(host); 1828 omap_hsmmc_conf_bus_power(host); 1829 mmc_power_restore_host(host->mmc); 1830 1831 host->dpm_state = ENABLED; 1832 1833 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1834 1835 return 0; 1836 } 1837 1838 /* 1839 * Bring MMC host to ENABLED from any other PM state. 1840 */ 1841 static int omap_hsmmc_enable(struct mmc_host *mmc) 1842 { 1843 struct omap_hsmmc_host *host = mmc_priv(mmc); 1844 1845 switch (host->dpm_state) { 1846 case DISABLED: 1847 return omap_hsmmc_disabled_to_enabled(host); 1848 case CARDSLEEP: 1849 case REGSLEEP: 1850 return omap_hsmmc_sleep_to_enabled(host); 1851 case OFF: 1852 return omap_hsmmc_off_to_enabled(host); 1853 default: 1854 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1855 return -EINVAL; 1856 } 1857 } 1858 1859 /* 1860 * Bring MMC host in PM state (one level deeper). 1861 */ 1862 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1863 { 1864 struct omap_hsmmc_host *host = mmc_priv(mmc); 1865 1866 switch (host->dpm_state) { 1867 case ENABLED: { 1868 int delay; 1869 1870 delay = omap_hsmmc_enabled_to_disabled(host); 1871 if (lazy || delay < 0) 1872 return delay; 1873 return 0; 1874 } 1875 case DISABLED: 1876 return omap_hsmmc_disabled_to_sleep(host); 1877 case CARDSLEEP: 1878 case REGSLEEP: 1879 return omap_hsmmc_sleep_to_off(host); 1880 default: 1881 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1882 return -EINVAL; 1883 } 1884 } 1885 1886 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1887 { 1888 struct omap_hsmmc_host *host = mmc_priv(mmc); 1889 int err; 1890 1891 err = clk_enable(host->fclk); 1892 if (err) 1893 return err; 1894 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 1895 omap_hsmmc_context_restore(host); 1896 return 0; 1897 } 1898 1899 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1900 { 1901 struct omap_hsmmc_host *host = mmc_priv(mmc); 1902 1903 omap_hsmmc_context_save(host); 1904 clk_disable(host->fclk); 1905 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1906 return 0; 1907 } 1908 1909 static const struct mmc_host_ops omap_hsmmc_ops = { 1910 .enable = omap_hsmmc_enable_fclk, 1911 .disable = omap_hsmmc_disable_fclk, 1912 .request = omap_hsmmc_request, 1913 .set_ios = omap_hsmmc_set_ios, 1914 .get_cd = omap_hsmmc_get_cd, 1915 .get_ro = omap_hsmmc_get_ro, 1916 .init_card = omap_hsmmc_init_card, 1917 /* NYET -- enable_sdio_irq */ 1918 }; 1919 1920 static const struct mmc_host_ops omap_hsmmc_ps_ops = { 1921 .enable = omap_hsmmc_enable, 1922 .disable = omap_hsmmc_disable, 1923 .request = omap_hsmmc_request, 1924 .set_ios = omap_hsmmc_set_ios, 1925 .get_cd = omap_hsmmc_get_cd, 1926 .get_ro = omap_hsmmc_get_ro, 1927 .init_card = omap_hsmmc_init_card, 1928 /* NYET -- enable_sdio_irq */ 1929 }; 1930 1931 #ifdef CONFIG_DEBUG_FS 1932 1933 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1934 { 1935 struct mmc_host *mmc = s->private; 1936 struct omap_hsmmc_host *host = mmc_priv(mmc); 1937 int context_loss = 0; 1938 1939 if (host->pdata->get_context_loss_count) 1940 context_loss = host->pdata->get_context_loss_count(host->dev); 1941 1942 seq_printf(s, "mmc%d:\n" 1943 " enabled:\t%d\n" 1944 " dpm_state:\t%d\n" 1945 " nesting_cnt:\t%d\n" 1946 " ctx_loss:\t%d:%d\n" 1947 "\nregs:\n", 1948 mmc->index, mmc->enabled ? 1 : 0, 1949 host->dpm_state, mmc->nesting_cnt, 1950 host->context_loss, context_loss); 1951 1952 if (host->suspended || host->dpm_state == OFF) { 1953 seq_printf(s, "host suspended, can't read registers\n"); 1954 return 0; 1955 } 1956 1957 if (clk_enable(host->fclk) != 0) { 1958 seq_printf(s, "can't read the regs\n"); 1959 return 0; 1960 } 1961 1962 seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1963 OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1964 seq_printf(s, "CON:\t\t0x%08x\n", 1965 OMAP_HSMMC_READ(host->base, CON)); 1966 seq_printf(s, "HCTL:\t\t0x%08x\n", 1967 OMAP_HSMMC_READ(host->base, HCTL)); 1968 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1969 OMAP_HSMMC_READ(host->base, SYSCTL)); 1970 seq_printf(s, "IE:\t\t0x%08x\n", 1971 OMAP_HSMMC_READ(host->base, IE)); 1972 seq_printf(s, "ISE:\t\t0x%08x\n", 1973 OMAP_HSMMC_READ(host->base, ISE)); 1974 seq_printf(s, "CAPA:\t\t0x%08x\n", 1975 OMAP_HSMMC_READ(host->base, CAPA)); 1976 1977 clk_disable(host->fclk); 1978 1979 return 0; 1980 } 1981 1982 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1983 { 1984 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1985 } 1986 1987 static const struct file_operations mmc_regs_fops = { 1988 .open = omap_hsmmc_regs_open, 1989 .read = seq_read, 1990 .llseek = seq_lseek, 1991 .release = single_release, 1992 }; 1993 1994 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1995 { 1996 if (mmc->debugfs_root) 1997 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1998 mmc, &mmc_regs_fops); 1999 } 2000 2001 #else 2002 2003 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 2004 { 2005 } 2006 2007 #endif 2008 2009 static int __init omap_hsmmc_probe(struct platform_device *pdev) 2010 { 2011 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 2012 struct mmc_host *mmc; 2013 struct omap_hsmmc_host *host = NULL; 2014 struct resource *res; 2015 int ret, irq; 2016 2017 if (pdata == NULL) { 2018 dev_err(&pdev->dev, "Platform Data is missing\n"); 2019 return -ENXIO; 2020 } 2021 2022 if (pdata->nr_slots == 0) { 2023 dev_err(&pdev->dev, "No Slots\n"); 2024 return -ENXIO; 2025 } 2026 2027 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2028 irq = platform_get_irq(pdev, 0); 2029 if (res == NULL || irq < 0) 2030 return -ENXIO; 2031 2032 res->start += pdata->reg_offset; 2033 res->end += pdata->reg_offset; 2034 res = request_mem_region(res->start, res->end - res->start + 1, 2035 pdev->name); 2036 if (res == NULL) 2037 return -EBUSY; 2038 2039 ret = omap_hsmmc_gpio_init(pdata); 2040 if (ret) 2041 goto err; 2042 2043 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2044 if (!mmc) { 2045 ret = -ENOMEM; 2046 goto err_alloc; 2047 } 2048 2049 host = mmc_priv(mmc); 2050 host->mmc = mmc; 2051 host->pdata = pdata; 2052 host->dev = &pdev->dev; 2053 host->use_dma = 1; 2054 host->dev->dma_mask = &pdata->dma_mask; 2055 host->dma_ch = -1; 2056 host->irq = irq; 2057 host->id = pdev->id; 2058 host->slot_id = 0; 2059 host->mapbase = res->start; 2060 host->base = ioremap(host->mapbase, SZ_4K); 2061 host->power_mode = MMC_POWER_OFF; 2062 2063 platform_set_drvdata(pdev, host); 2064 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2065 2066 if (mmc_slot(host).power_saving) 2067 mmc->ops = &omap_hsmmc_ps_ops; 2068 else 2069 mmc->ops = &omap_hsmmc_ops; 2070 2071 /* 2072 * If regulator_disable can only put vcc_aux to sleep then there is 2073 * no off state. 2074 */ 2075 if (mmc_slot(host).vcc_aux_disable_is_sleep) 2076 mmc_slot(host).no_off = 1; 2077 2078 mmc->f_min = 400000; 2079 mmc->f_max = 52000000; 2080 2081 spin_lock_init(&host->irq_lock); 2082 2083 host->iclk = clk_get(&pdev->dev, "ick"); 2084 if (IS_ERR(host->iclk)) { 2085 ret = PTR_ERR(host->iclk); 2086 host->iclk = NULL; 2087 goto err1; 2088 } 2089 host->fclk = clk_get(&pdev->dev, "fck"); 2090 if (IS_ERR(host->fclk)) { 2091 ret = PTR_ERR(host->fclk); 2092 host->fclk = NULL; 2093 clk_put(host->iclk); 2094 goto err1; 2095 } 2096 2097 omap_hsmmc_context_save(host); 2098 2099 mmc->caps |= MMC_CAP_DISABLE; 2100 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 2101 /* we start off in DISABLED state */ 2102 host->dpm_state = DISABLED; 2103 2104 if (mmc_host_enable(host->mmc) != 0) { 2105 clk_put(host->iclk); 2106 clk_put(host->fclk); 2107 goto err1; 2108 } 2109 2110 if (clk_enable(host->iclk) != 0) { 2111 mmc_host_disable(host->mmc); 2112 clk_put(host->iclk); 2113 clk_put(host->fclk); 2114 goto err1; 2115 } 2116 2117 if (cpu_is_omap2430()) { 2118 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 2119 /* 2120 * MMC can still work without debounce clock. 2121 */ 2122 if (IS_ERR(host->dbclk)) 2123 dev_warn(mmc_dev(host->mmc), 2124 "Failed to get debounce clock\n"); 2125 else 2126 host->got_dbclk = 1; 2127 2128 if (host->got_dbclk) 2129 if (clk_enable(host->dbclk) != 0) 2130 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 2131 " clk failed\n"); 2132 } 2133 2134 /* Since we do only SG emulation, we can have as many segs 2135 * as we want. */ 2136 mmc->max_segs = 1024; 2137 2138 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2139 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2140 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2141 mmc->max_seg_size = mmc->max_req_size; 2142 2143 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2144 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2145 2146 mmc->caps |= mmc_slot(host).caps; 2147 if (mmc->caps & MMC_CAP_8_BIT_DATA) 2148 mmc->caps |= MMC_CAP_4_BIT_DATA; 2149 2150 if (mmc_slot(host).nonremovable) 2151 mmc->caps |= MMC_CAP_NONREMOVABLE; 2152 2153 omap_hsmmc_conf_bus_power(host); 2154 2155 /* Select DMA lines */ 2156 switch (host->id) { 2157 case OMAP_MMC1_DEVID: 2158 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 2159 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2160 break; 2161 case OMAP_MMC2_DEVID: 2162 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2163 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2164 break; 2165 case OMAP_MMC3_DEVID: 2166 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2167 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2168 break; 2169 case OMAP_MMC4_DEVID: 2170 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 2171 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 2172 break; 2173 case OMAP_MMC5_DEVID: 2174 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 2175 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 2176 break; 2177 default: 2178 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2179 goto err_irq; 2180 } 2181 2182 /* Request IRQ for MMC operations */ 2183 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2184 mmc_hostname(mmc), host); 2185 if (ret) { 2186 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2187 goto err_irq; 2188 } 2189 2190 if (pdata->init != NULL) { 2191 if (pdata->init(&pdev->dev) != 0) { 2192 dev_dbg(mmc_dev(host->mmc), 2193 "Unable to configure MMC IRQs\n"); 2194 goto err_irq_cd_init; 2195 } 2196 } 2197 2198 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2199 ret = omap_hsmmc_reg_get(host); 2200 if (ret) 2201 goto err_reg; 2202 host->use_reg = 1; 2203 } 2204 2205 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2206 2207 /* Request IRQ for card detect */ 2208 if ((mmc_slot(host).card_detect_irq)) { 2209 ret = request_irq(mmc_slot(host).card_detect_irq, 2210 omap_hsmmc_cd_handler, 2211 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2212 | IRQF_DISABLED, 2213 mmc_hostname(mmc), host); 2214 if (ret) { 2215 dev_dbg(mmc_dev(host->mmc), 2216 "Unable to grab MMC CD IRQ\n"); 2217 goto err_irq_cd; 2218 } 2219 pdata->suspend = omap_hsmmc_suspend_cdirq; 2220 pdata->resume = omap_hsmmc_resume_cdirq; 2221 } 2222 2223 omap_hsmmc_disable_irq(host); 2224 2225 mmc_host_lazy_disable(host->mmc); 2226 2227 omap_hsmmc_protect_card(host); 2228 2229 mmc_add_host(mmc); 2230 2231 if (mmc_slot(host).name != NULL) { 2232 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2233 if (ret < 0) 2234 goto err_slot_name; 2235 } 2236 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2237 ret = device_create_file(&mmc->class_dev, 2238 &dev_attr_cover_switch); 2239 if (ret < 0) 2240 goto err_slot_name; 2241 } 2242 2243 omap_hsmmc_debugfs(mmc); 2244 2245 return 0; 2246 2247 err_slot_name: 2248 mmc_remove_host(mmc); 2249 free_irq(mmc_slot(host).card_detect_irq, host); 2250 err_irq_cd: 2251 if (host->use_reg) 2252 omap_hsmmc_reg_put(host); 2253 err_reg: 2254 if (host->pdata->cleanup) 2255 host->pdata->cleanup(&pdev->dev); 2256 err_irq_cd_init: 2257 free_irq(host->irq, host); 2258 err_irq: 2259 mmc_host_disable(host->mmc); 2260 clk_disable(host->iclk); 2261 clk_put(host->fclk); 2262 clk_put(host->iclk); 2263 if (host->got_dbclk) { 2264 clk_disable(host->dbclk); 2265 clk_put(host->dbclk); 2266 } 2267 err1: 2268 iounmap(host->base); 2269 platform_set_drvdata(pdev, NULL); 2270 mmc_free_host(mmc); 2271 err_alloc: 2272 omap_hsmmc_gpio_free(pdata); 2273 err: 2274 release_mem_region(res->start, res->end - res->start + 1); 2275 return ret; 2276 } 2277 2278 static int omap_hsmmc_remove(struct platform_device *pdev) 2279 { 2280 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2281 struct resource *res; 2282 2283 if (host) { 2284 mmc_host_enable(host->mmc); 2285 mmc_remove_host(host->mmc); 2286 if (host->use_reg) 2287 omap_hsmmc_reg_put(host); 2288 if (host->pdata->cleanup) 2289 host->pdata->cleanup(&pdev->dev); 2290 free_irq(host->irq, host); 2291 if (mmc_slot(host).card_detect_irq) 2292 free_irq(mmc_slot(host).card_detect_irq, host); 2293 flush_work_sync(&host->mmc_carddetect_work); 2294 2295 mmc_host_disable(host->mmc); 2296 clk_disable(host->iclk); 2297 clk_put(host->fclk); 2298 clk_put(host->iclk); 2299 if (host->got_dbclk) { 2300 clk_disable(host->dbclk); 2301 clk_put(host->dbclk); 2302 } 2303 2304 mmc_free_host(host->mmc); 2305 iounmap(host->base); 2306 omap_hsmmc_gpio_free(pdev->dev.platform_data); 2307 } 2308 2309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2310 if (res) 2311 release_mem_region(res->start, res->end - res->start + 1); 2312 platform_set_drvdata(pdev, NULL); 2313 2314 return 0; 2315 } 2316 2317 #ifdef CONFIG_PM 2318 static int omap_hsmmc_suspend(struct device *dev) 2319 { 2320 int ret = 0; 2321 struct platform_device *pdev = to_platform_device(dev); 2322 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2323 2324 if (host && host->suspended) 2325 return 0; 2326 2327 if (host) { 2328 host->suspended = 1; 2329 if (host->pdata->suspend) { 2330 ret = host->pdata->suspend(&pdev->dev, 2331 host->slot_id); 2332 if (ret) { 2333 dev_dbg(mmc_dev(host->mmc), 2334 "Unable to handle MMC board" 2335 " level suspend\n"); 2336 host->suspended = 0; 2337 return ret; 2338 } 2339 } 2340 cancel_work_sync(&host->mmc_carddetect_work); 2341 ret = mmc_suspend_host(host->mmc); 2342 mmc_host_enable(host->mmc); 2343 if (ret == 0) { 2344 omap_hsmmc_disable_irq(host); 2345 OMAP_HSMMC_WRITE(host->base, HCTL, 2346 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2347 mmc_host_disable(host->mmc); 2348 clk_disable(host->iclk); 2349 if (host->got_dbclk) 2350 clk_disable(host->dbclk); 2351 } else { 2352 host->suspended = 0; 2353 if (host->pdata->resume) { 2354 ret = host->pdata->resume(&pdev->dev, 2355 host->slot_id); 2356 if (ret) 2357 dev_dbg(mmc_dev(host->mmc), 2358 "Unmask interrupt failed\n"); 2359 } 2360 mmc_host_disable(host->mmc); 2361 } 2362 2363 } 2364 return ret; 2365 } 2366 2367 /* Routine to resume the MMC device */ 2368 static int omap_hsmmc_resume(struct device *dev) 2369 { 2370 int ret = 0; 2371 struct platform_device *pdev = to_platform_device(dev); 2372 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2373 2374 if (host && !host->suspended) 2375 return 0; 2376 2377 if (host) { 2378 ret = clk_enable(host->iclk); 2379 if (ret) 2380 goto clk_en_err; 2381 2382 if (mmc_host_enable(host->mmc) != 0) { 2383 clk_disable(host->iclk); 2384 goto clk_en_err; 2385 } 2386 2387 if (host->got_dbclk) 2388 clk_enable(host->dbclk); 2389 2390 omap_hsmmc_conf_bus_power(host); 2391 2392 if (host->pdata->resume) { 2393 ret = host->pdata->resume(&pdev->dev, host->slot_id); 2394 if (ret) 2395 dev_dbg(mmc_dev(host->mmc), 2396 "Unmask interrupt failed\n"); 2397 } 2398 2399 omap_hsmmc_protect_card(host); 2400 2401 /* Notify the core to resume the host */ 2402 ret = mmc_resume_host(host->mmc); 2403 if (ret == 0) 2404 host->suspended = 0; 2405 2406 mmc_host_lazy_disable(host->mmc); 2407 } 2408 2409 return ret; 2410 2411 clk_en_err: 2412 dev_dbg(mmc_dev(host->mmc), 2413 "Failed to enable MMC clocks during resume\n"); 2414 return ret; 2415 } 2416 2417 #else 2418 #define omap_hsmmc_suspend NULL 2419 #define omap_hsmmc_resume NULL 2420 #endif 2421 2422 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2423 .suspend = omap_hsmmc_suspend, 2424 .resume = omap_hsmmc_resume, 2425 }; 2426 2427 static struct platform_driver omap_hsmmc_driver = { 2428 .remove = omap_hsmmc_remove, 2429 .driver = { 2430 .name = DRIVER_NAME, 2431 .owner = THIS_MODULE, 2432 .pm = &omap_hsmmc_dev_pm_ops, 2433 }, 2434 }; 2435 2436 static int __init omap_hsmmc_init(void) 2437 { 2438 /* Register the MMC driver */ 2439 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2440 } 2441 2442 static void __exit omap_hsmmc_cleanup(void) 2443 { 2444 /* Unregister MMC driver */ 2445 platform_driver_unregister(&omap_hsmmc_driver); 2446 } 2447 2448 module_init(omap_hsmmc_init); 2449 module_exit(omap_hsmmc_cleanup); 2450 2451 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2452 MODULE_LICENSE("GPL"); 2453 MODULE_ALIAS("platform:" DRIVER_NAME); 2454 MODULE_AUTHOR("Texas Instruments Inc"); 2455