1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/platform_device.h> 24 #include <linux/workqueue.h> 25 #include <linux/timer.h> 26 #include <linux/clk.h> 27 #include <linux/mmc/host.h> 28 #include <linux/io.h> 29 #include <linux/semaphore.h> 30 #include <mach/dma.h> 31 #include <mach/hardware.h> 32 #include <mach/board.h> 33 #include <mach/mmc.h> 34 #include <mach/cpu.h> 35 36 /* OMAP HSMMC Host Controller Registers */ 37 #define OMAP_HSMMC_SYSCONFIG 0x0010 38 #define OMAP_HSMMC_CON 0x002C 39 #define OMAP_HSMMC_BLK 0x0104 40 #define OMAP_HSMMC_ARG 0x0108 41 #define OMAP_HSMMC_CMD 0x010C 42 #define OMAP_HSMMC_RSP10 0x0110 43 #define OMAP_HSMMC_RSP32 0x0114 44 #define OMAP_HSMMC_RSP54 0x0118 45 #define OMAP_HSMMC_RSP76 0x011C 46 #define OMAP_HSMMC_DATA 0x0120 47 #define OMAP_HSMMC_HCTL 0x0128 48 #define OMAP_HSMMC_SYSCTL 0x012C 49 #define OMAP_HSMMC_STAT 0x0130 50 #define OMAP_HSMMC_IE 0x0134 51 #define OMAP_HSMMC_ISE 0x0138 52 #define OMAP_HSMMC_CAPA 0x0140 53 54 #define VS18 (1 << 26) 55 #define VS30 (1 << 25) 56 #define SDVS18 (0x5 << 9) 57 #define SDVS30 (0x6 << 9) 58 #define SDVS33 (0x7 << 9) 59 #define SDVSCLR 0xFFFFF1FF 60 #define SDVSDET 0x00000400 61 #define AUTOIDLE 0x1 62 #define SDBP (1 << 8) 63 #define DTO 0xe 64 #define ICE 0x1 65 #define ICS 0x2 66 #define CEN (1 << 2) 67 #define CLKD_MASK 0x0000FFC0 68 #define CLKD_SHIFT 6 69 #define DTO_MASK 0x000F0000 70 #define DTO_SHIFT 16 71 #define INT_EN_MASK 0x307F0033 72 #define INIT_STREAM (1 << 1) 73 #define DP_SELECT (1 << 21) 74 #define DDIR (1 << 4) 75 #define DMA_EN 0x1 76 #define MSBS (1 << 5) 77 #define BCE (1 << 1) 78 #define FOUR_BIT (1 << 1) 79 #define CC 0x1 80 #define TC 0x02 81 #define OD 0x1 82 #define ERR (1 << 15) 83 #define CMD_TIMEOUT (1 << 16) 84 #define DATA_TIMEOUT (1 << 20) 85 #define CMD_CRC (1 << 17) 86 #define DATA_CRC (1 << 21) 87 #define CARD_ERR (1 << 28) 88 #define STAT_CLEAR 0xFFFFFFFF 89 #define INIT_STREAM_CMD 0x00000000 90 #define DUAL_VOLT_OCR_BIT 7 91 #define SRC (1 << 25) 92 #define SRD (1 << 26) 93 94 /* 95 * FIXME: Most likely all the data using these _DEVID defines should come 96 * from the platform_data, or implemented in controller and slot specific 97 * functions. 98 */ 99 #define OMAP_MMC1_DEVID 0 100 #define OMAP_MMC2_DEVID 1 101 102 #define OMAP_MMC_DATADIR_NONE 0 103 #define OMAP_MMC_DATADIR_READ 1 104 #define OMAP_MMC_DATADIR_WRITE 2 105 #define MMC_TIMEOUT_MS 20 106 #define OMAP_MMC_MASTER_CLOCK 96000000 107 #define DRIVER_NAME "mmci-omap-hs" 108 109 /* 110 * One controller can have multiple slots, like on some omap boards using 111 * omap.c controller driver. Luckily this is not currently done on any known 112 * omap_hsmmc.c device. 113 */ 114 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 115 116 /* 117 * MMC Host controller read/write API's 118 */ 119 #define OMAP_HSMMC_READ(base, reg) \ 120 __raw_readl((base) + OMAP_HSMMC_##reg) 121 122 #define OMAP_HSMMC_WRITE(base, reg, val) \ 123 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 124 125 struct mmc_omap_host { 126 struct device *dev; 127 struct mmc_host *mmc; 128 struct mmc_request *mrq; 129 struct mmc_command *cmd; 130 struct mmc_data *data; 131 struct clk *fclk; 132 struct clk *iclk; 133 struct clk *dbclk; 134 struct semaphore sem; 135 struct work_struct mmc_carddetect_work; 136 void __iomem *base; 137 resource_size_t mapbase; 138 unsigned int id; 139 unsigned int dma_len; 140 unsigned int dma_dir; 141 unsigned char bus_mode; 142 unsigned char datadir; 143 u32 *buffer; 144 u32 bytesleft; 145 int suspended; 146 int irq; 147 int carddetect; 148 int use_dma, dma_ch; 149 int initstr; 150 int slot_id; 151 int dbclk_enabled; 152 struct omap_mmc_platform_data *pdata; 153 }; 154 155 /* 156 * Stop clock to the card 157 */ 158 static void omap_mmc_stop_clock(struct mmc_omap_host *host) 159 { 160 OMAP_HSMMC_WRITE(host->base, SYSCTL, 161 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 162 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 163 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 164 } 165 166 /* 167 * Send init stream sequence to card 168 * before sending IDLE command 169 */ 170 static void send_init_stream(struct mmc_omap_host *host) 171 { 172 int reg = 0; 173 unsigned long timeout; 174 175 disable_irq(host->irq); 176 OMAP_HSMMC_WRITE(host->base, CON, 177 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 178 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 179 180 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 181 while ((reg != CC) && time_before(jiffies, timeout)) 182 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 183 184 OMAP_HSMMC_WRITE(host->base, CON, 185 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 186 enable_irq(host->irq); 187 } 188 189 static inline 190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host) 191 { 192 int r = 1; 193 194 if (host->pdata->slots[host->slot_id].get_cover_state) 195 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev, 196 host->slot_id); 197 return r; 198 } 199 200 static ssize_t 201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 202 char *buf) 203 { 204 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 205 struct mmc_omap_host *host = mmc_priv(mmc); 206 207 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" : 208 "open"); 209 } 210 211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 212 213 static ssize_t 214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 215 char *buf) 216 { 217 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 218 struct mmc_omap_host *host = mmc_priv(mmc); 219 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id]; 220 221 return sprintf(buf, "slot:%s\n", slot.name); 222 } 223 224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 225 226 /* 227 * Configure the response type and send the cmd. 228 */ 229 static void 230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd, 231 struct mmc_data *data) 232 { 233 int cmdreg = 0, resptype = 0, cmdtype = 0; 234 235 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 236 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 237 host->cmd = cmd; 238 239 /* 240 * Clear status bits and enable interrupts 241 */ 242 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 243 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 244 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 245 246 if (cmd->flags & MMC_RSP_PRESENT) { 247 if (cmd->flags & MMC_RSP_136) 248 resptype = 1; 249 else 250 resptype = 2; 251 } 252 253 /* 254 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 255 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 256 * a val of 0x3, rest 0x0. 257 */ 258 if (cmd == host->mrq->stop) 259 cmdtype = 0x3; 260 261 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 262 263 if (data) { 264 cmdreg |= DP_SELECT | MSBS | BCE; 265 if (data->flags & MMC_DATA_READ) 266 cmdreg |= DDIR; 267 else 268 cmdreg &= ~(DDIR); 269 } 270 271 if (host->use_dma) 272 cmdreg |= DMA_EN; 273 274 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 275 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 276 } 277 278 /* 279 * Notify the transfer complete to MMC core 280 */ 281 static void 282 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 283 { 284 host->data = NULL; 285 286 if (host->use_dma && host->dma_ch != -1) 287 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 288 host->dma_dir); 289 290 host->datadir = OMAP_MMC_DATADIR_NONE; 291 292 if (!data->error) 293 data->bytes_xfered += data->blocks * (data->blksz); 294 else 295 data->bytes_xfered = 0; 296 297 if (!data->stop) { 298 host->mrq = NULL; 299 mmc_request_done(host->mmc, data->mrq); 300 return; 301 } 302 mmc_omap_start_command(host, data->stop, NULL); 303 } 304 305 /* 306 * Notify the core about command completion 307 */ 308 static void 309 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 310 { 311 host->cmd = NULL; 312 313 if (cmd->flags & MMC_RSP_PRESENT) { 314 if (cmd->flags & MMC_RSP_136) { 315 /* response type 2 */ 316 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 317 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 318 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 319 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 320 } else { 321 /* response types 1, 1b, 3, 4, 5, 6 */ 322 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 323 } 324 } 325 if (host->data == NULL || cmd->error) { 326 host->mrq = NULL; 327 mmc_request_done(host->mmc, cmd->mrq); 328 } 329 } 330 331 /* 332 * DMA clean up for command errors 333 */ 334 static void mmc_dma_cleanup(struct mmc_omap_host *host) 335 { 336 host->data->error = -ETIMEDOUT; 337 338 if (host->use_dma && host->dma_ch != -1) { 339 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 340 host->dma_dir); 341 omap_free_dma(host->dma_ch); 342 host->dma_ch = -1; 343 up(&host->sem); 344 } 345 host->data = NULL; 346 host->datadir = OMAP_MMC_DATADIR_NONE; 347 } 348 349 /* 350 * Readable error output 351 */ 352 #ifdef CONFIG_MMC_DEBUG 353 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status) 354 { 355 /* --- means reserved bit without definition at documentation */ 356 static const char *mmc_omap_status_bits[] = { 357 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 358 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 359 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 360 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 361 }; 362 char res[256]; 363 char *buf = res; 364 int len, i; 365 366 len = sprintf(buf, "MMC IRQ 0x%x :", status); 367 buf += len; 368 369 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 370 if (status & (1 << i)) { 371 len = sprintf(buf, " %s", mmc_omap_status_bits[i]); 372 buf += len; 373 } 374 375 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 376 } 377 #endif /* CONFIG_MMC_DEBUG */ 378 379 /* 380 * MMC controller internal state machines reset 381 * 382 * Used to reset command or data internal state machines, using respectively 383 * SRC or SRD bit of SYSCTL register 384 * Can be called from interrupt context 385 */ 386 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host, 387 unsigned long bit) 388 { 389 unsigned long i = 0; 390 unsigned long limit = (loops_per_jiffy * 391 msecs_to_jiffies(MMC_TIMEOUT_MS)); 392 393 OMAP_HSMMC_WRITE(host->base, SYSCTL, 394 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 395 396 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 397 (i++ < limit)) 398 cpu_relax(); 399 400 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 401 dev_err(mmc_dev(host->mmc), 402 "Timeout waiting on controller reset in %s\n", 403 __func__); 404 } 405 406 /* 407 * MMC controller IRQ handler 408 */ 409 static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 410 { 411 struct mmc_omap_host *host = dev_id; 412 struct mmc_data *data; 413 int end_cmd = 0, end_trans = 0, status; 414 415 if (host->cmd == NULL && host->data == NULL) { 416 OMAP_HSMMC_WRITE(host->base, STAT, 417 OMAP_HSMMC_READ(host->base, STAT)); 418 return IRQ_HANDLED; 419 } 420 421 data = host->data; 422 status = OMAP_HSMMC_READ(host->base, STAT); 423 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 424 425 if (status & ERR) { 426 #ifdef CONFIG_MMC_DEBUG 427 mmc_omap_report_irq(host, status); 428 #endif 429 if ((status & CMD_TIMEOUT) || 430 (status & CMD_CRC)) { 431 if (host->cmd) { 432 if (status & CMD_TIMEOUT) { 433 mmc_omap_reset_controller_fsm(host, SRC); 434 host->cmd->error = -ETIMEDOUT; 435 } else { 436 host->cmd->error = -EILSEQ; 437 } 438 end_cmd = 1; 439 } 440 if (host->data) { 441 mmc_dma_cleanup(host); 442 mmc_omap_reset_controller_fsm(host, SRD); 443 } 444 } 445 if ((status & DATA_TIMEOUT) || 446 (status & DATA_CRC)) { 447 if (host->data) { 448 if (status & DATA_TIMEOUT) 449 mmc_dma_cleanup(host); 450 else 451 host->data->error = -EILSEQ; 452 mmc_omap_reset_controller_fsm(host, SRD); 453 end_trans = 1; 454 } 455 } 456 if (status & CARD_ERR) { 457 dev_dbg(mmc_dev(host->mmc), 458 "Ignoring card err CMD%d\n", host->cmd->opcode); 459 if (host->cmd) 460 end_cmd = 1; 461 if (host->data) 462 end_trans = 1; 463 } 464 } 465 466 OMAP_HSMMC_WRITE(host->base, STAT, status); 467 468 if (end_cmd || (status & CC)) 469 mmc_omap_cmd_done(host, host->cmd); 470 if (end_trans || (status & TC)) 471 mmc_omap_xfer_done(host, data); 472 473 return IRQ_HANDLED; 474 } 475 476 /* 477 * Switch MMC interface voltage ... only relevant for MMC1. 478 * 479 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 480 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 481 * Some chips, like eMMC ones, use internal transceivers. 482 */ 483 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd) 484 { 485 u32 reg_val = 0; 486 int ret; 487 488 if (host->id != OMAP_MMC1_DEVID) 489 return 0; 490 491 /* Disable the clocks */ 492 clk_disable(host->fclk); 493 clk_disable(host->iclk); 494 clk_disable(host->dbclk); 495 496 /* Turn the power off */ 497 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 498 if (ret != 0) 499 goto err; 500 501 /* Turn the power ON with given VDD 1.8 or 3.0v */ 502 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 503 if (ret != 0) 504 goto err; 505 506 clk_enable(host->fclk); 507 clk_enable(host->iclk); 508 clk_enable(host->dbclk); 509 510 OMAP_HSMMC_WRITE(host->base, HCTL, 511 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 512 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 513 514 /* 515 * If a MMC dual voltage card is detected, the set_ios fn calls 516 * this fn with VDD bit set for 1.8V. Upon card removal from the 517 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 518 * 519 * Cope with a bit of slop in the range ... per data sheets: 520 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 521 * but recommended values are 1.71V to 1.89V 522 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 523 * but recommended values are 2.7V to 3.3V 524 * 525 * Board setup code shouldn't permit anything very out-of-range. 526 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 527 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 528 */ 529 if ((1 << vdd) <= MMC_VDD_23_24) 530 reg_val |= SDVS18; 531 else 532 reg_val |= SDVS30; 533 534 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 535 536 OMAP_HSMMC_WRITE(host->base, HCTL, 537 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 538 539 return 0; 540 err: 541 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 542 return ret; 543 } 544 545 /* 546 * Work Item to notify the core about card insertion/removal 547 */ 548 static void mmc_omap_detect(struct work_struct *work) 549 { 550 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 551 mmc_carddetect_work); 552 struct omap_mmc_slot_data *slot = &mmc_slot(host); 553 554 host->carddetect = slot->card_detect(slot->card_detect_irq); 555 556 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 557 if (host->carddetect) { 558 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 559 } else { 560 mmc_omap_reset_controller_fsm(host, SRD); 561 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 562 } 563 } 564 565 /* 566 * ISR for handling card insertion and removal 567 */ 568 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id) 569 { 570 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id; 571 572 schedule_work(&host->mmc_carddetect_work); 573 574 return IRQ_HANDLED; 575 } 576 577 /* 578 * DMA call back function 579 */ 580 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) 581 { 582 struct mmc_omap_host *host = data; 583 584 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) 585 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); 586 587 if (host->dma_ch < 0) 588 return; 589 590 omap_free_dma(host->dma_ch); 591 host->dma_ch = -1; 592 /* 593 * DMA Callback: run in interrupt context. 594 * mutex_unlock will through a kernel warning if used. 595 */ 596 up(&host->sem); 597 } 598 599 /* 600 * Configure dma src and destination parameters 601 */ 602 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host, 603 struct mmc_data *data) 604 { 605 if (sync_dir == 0) { 606 omap_set_dma_dest_params(host->dma_ch, 0, 607 OMAP_DMA_AMODE_CONSTANT, 608 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 609 omap_set_dma_src_params(host->dma_ch, 0, 610 OMAP_DMA_AMODE_POST_INC, 611 sg_dma_address(&data->sg[0]), 0, 0); 612 } else { 613 omap_set_dma_src_params(host->dma_ch, 0, 614 OMAP_DMA_AMODE_CONSTANT, 615 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 616 omap_set_dma_dest_params(host->dma_ch, 0, 617 OMAP_DMA_AMODE_POST_INC, 618 sg_dma_address(&data->sg[0]), 0, 0); 619 } 620 return 0; 621 } 622 /* 623 * Routine to configure and start DMA for the MMC card 624 */ 625 static int 626 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req) 627 { 628 int sync_dev, sync_dir = 0; 629 int dma_ch = 0, ret = 0, err = 1; 630 struct mmc_data *data = req->data; 631 632 /* 633 * If for some reason the DMA transfer is still active, 634 * we wait for timeout period and free the dma 635 */ 636 if (host->dma_ch != -1) { 637 set_current_state(TASK_UNINTERRUPTIBLE); 638 schedule_timeout(100); 639 if (down_trylock(&host->sem)) { 640 omap_free_dma(host->dma_ch); 641 host->dma_ch = -1; 642 up(&host->sem); 643 return err; 644 } 645 } else { 646 if (down_trylock(&host->sem)) 647 return err; 648 } 649 650 if (!(data->flags & MMC_DATA_WRITE)) { 651 host->dma_dir = DMA_FROM_DEVICE; 652 if (host->id == OMAP_MMC1_DEVID) 653 sync_dev = OMAP24XX_DMA_MMC1_RX; 654 else 655 sync_dev = OMAP24XX_DMA_MMC2_RX; 656 } else { 657 host->dma_dir = DMA_TO_DEVICE; 658 if (host->id == OMAP_MMC1_DEVID) 659 sync_dev = OMAP24XX_DMA_MMC1_TX; 660 else 661 sync_dev = OMAP24XX_DMA_MMC2_TX; 662 } 663 664 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb, 665 host, &dma_ch); 666 if (ret != 0) { 667 dev_dbg(mmc_dev(host->mmc), 668 "%s: omap_request_dma() failed with %d\n", 669 mmc_hostname(host->mmc), ret); 670 return ret; 671 } 672 673 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 674 data->sg_len, host->dma_dir); 675 host->dma_ch = dma_ch; 676 677 if (!(data->flags & MMC_DATA_WRITE)) 678 mmc_omap_config_dma_param(1, host, data); 679 else 680 mmc_omap_config_dma_param(0, host, data); 681 682 if ((data->blksz % 4) == 0) 683 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 684 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME, 685 sync_dev, sync_dir); 686 else 687 /* REVISIT: The MMC buffer increments only when MSB is written. 688 * Return error for blksz which is non multiple of four. 689 */ 690 return -EINVAL; 691 692 omap_start_dma(dma_ch); 693 return 0; 694 } 695 696 static void set_data_timeout(struct mmc_omap_host *host, 697 struct mmc_request *req) 698 { 699 unsigned int timeout, cycle_ns; 700 uint32_t reg, clkd, dto = 0; 701 702 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 703 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 704 if (clkd == 0) 705 clkd = 1; 706 707 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 708 timeout = req->data->timeout_ns / cycle_ns; 709 timeout += req->data->timeout_clks; 710 if (timeout) { 711 while ((timeout & 0x80000000) == 0) { 712 dto += 1; 713 timeout <<= 1; 714 } 715 dto = 31 - dto; 716 timeout <<= 1; 717 if (timeout && dto) 718 dto += 1; 719 if (dto >= 13) 720 dto -= 13; 721 else 722 dto = 0; 723 if (dto > 14) 724 dto = 14; 725 } 726 727 reg &= ~DTO_MASK; 728 reg |= dto << DTO_SHIFT; 729 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 730 } 731 732 /* 733 * Configure block length for MMC/SD cards and initiate the transfer. 734 */ 735 static int 736 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 737 { 738 int ret; 739 host->data = req->data; 740 741 if (req->data == NULL) { 742 host->datadir = OMAP_MMC_DATADIR_NONE; 743 OMAP_HSMMC_WRITE(host->base, BLK, 0); 744 return 0; 745 } 746 747 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 748 | (req->data->blocks << 16)); 749 set_data_timeout(host, req); 750 751 host->datadir = (req->data->flags & MMC_DATA_WRITE) ? 752 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ; 753 754 if (host->use_dma) { 755 ret = mmc_omap_start_dma_transfer(host, req); 756 if (ret != 0) { 757 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 758 return ret; 759 } 760 } 761 return 0; 762 } 763 764 /* 765 * Request function. for read/write operation 766 */ 767 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 768 { 769 struct mmc_omap_host *host = mmc_priv(mmc); 770 771 WARN_ON(host->mrq != NULL); 772 host->mrq = req; 773 mmc_omap_prepare_data(host, req); 774 mmc_omap_start_command(host, req->cmd, req->data); 775 } 776 777 778 /* Routine to configure clock values. Exposed API to core */ 779 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 780 { 781 struct mmc_omap_host *host = mmc_priv(mmc); 782 u16 dsor = 0; 783 unsigned long regval; 784 unsigned long timeout; 785 786 switch (ios->power_mode) { 787 case MMC_POWER_OFF: 788 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 789 /* 790 * Reset interface voltage to 3V if it's 1.8V now; 791 * only relevant on MMC-1, the others always use 1.8V. 792 * 793 * REVISIT: If we are able to detect cards after unplugging 794 * a 1.8V card, this code should not be needed. 795 */ 796 if (host->id != OMAP_MMC1_DEVID) 797 break; 798 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) { 799 int vdd = fls(host->mmc->ocr_avail) - 1; 800 if (omap_mmc_switch_opcond(host, vdd) != 0) 801 host->mmc->ios.vdd = vdd; 802 } 803 break; 804 case MMC_POWER_UP: 805 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); 806 break; 807 } 808 809 switch (mmc->ios.bus_width) { 810 case MMC_BUS_WIDTH_4: 811 OMAP_HSMMC_WRITE(host->base, HCTL, 812 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 813 break; 814 case MMC_BUS_WIDTH_1: 815 OMAP_HSMMC_WRITE(host->base, HCTL, 816 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 817 break; 818 } 819 820 if (host->id == OMAP_MMC1_DEVID) { 821 /* Only MMC1 can interface at 3V without some flavor 822 * of external transceiver; but they all handle 1.8V. 823 */ 824 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 825 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 826 /* 827 * The mmc_select_voltage fn of the core does 828 * not seem to set the power_mode to 829 * MMC_POWER_UP upon recalculating the voltage. 830 * vdd 1.8v. 831 */ 832 if (omap_mmc_switch_opcond(host, ios->vdd) != 0) 833 dev_dbg(mmc_dev(host->mmc), 834 "Switch operation failed\n"); 835 } 836 } 837 838 if (ios->clock) { 839 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 840 if (dsor < 1) 841 dsor = 1; 842 843 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 844 dsor++; 845 846 if (dsor > 250) 847 dsor = 250; 848 } 849 omap_mmc_stop_clock(host); 850 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 851 regval = regval & ~(CLKD_MASK); 852 regval = regval | (dsor << 6) | (DTO << 16); 853 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 854 OMAP_HSMMC_WRITE(host->base, SYSCTL, 855 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 856 857 /* Wait till the ICS bit is set */ 858 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 859 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 860 && time_before(jiffies, timeout)) 861 msleep(1); 862 863 OMAP_HSMMC_WRITE(host->base, SYSCTL, 864 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 865 866 if (ios->power_mode == MMC_POWER_ON) 867 send_init_stream(host); 868 869 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 870 OMAP_HSMMC_WRITE(host->base, CON, 871 OMAP_HSMMC_READ(host->base, CON) | OD); 872 } 873 874 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 875 { 876 struct mmc_omap_host *host = mmc_priv(mmc); 877 struct omap_mmc_platform_data *pdata = host->pdata; 878 879 if (!pdata->slots[0].card_detect) 880 return -ENOSYS; 881 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq); 882 } 883 884 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 885 { 886 struct mmc_omap_host *host = mmc_priv(mmc); 887 struct omap_mmc_platform_data *pdata = host->pdata; 888 889 if (!pdata->slots[0].get_ro) 890 return -ENOSYS; 891 return pdata->slots[0].get_ro(host->dev, 0); 892 } 893 894 static struct mmc_host_ops mmc_omap_ops = { 895 .request = omap_mmc_request, 896 .set_ios = omap_mmc_set_ios, 897 .get_cd = omap_hsmmc_get_cd, 898 .get_ro = omap_hsmmc_get_ro, 899 /* NYET -- enable_sdio_irq */ 900 }; 901 902 static int __init omap_mmc_probe(struct platform_device *pdev) 903 { 904 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 905 struct mmc_host *mmc; 906 struct mmc_omap_host *host = NULL; 907 struct resource *res; 908 int ret = 0, irq; 909 u32 hctl, capa; 910 911 if (pdata == NULL) { 912 dev_err(&pdev->dev, "Platform Data is missing\n"); 913 return -ENXIO; 914 } 915 916 if (pdata->nr_slots == 0) { 917 dev_err(&pdev->dev, "No Slots\n"); 918 return -ENXIO; 919 } 920 921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 922 irq = platform_get_irq(pdev, 0); 923 if (res == NULL || irq < 0) 924 return -ENXIO; 925 926 res = request_mem_region(res->start, res->end - res->start + 1, 927 pdev->name); 928 if (res == NULL) 929 return -EBUSY; 930 931 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); 932 if (!mmc) { 933 ret = -ENOMEM; 934 goto err; 935 } 936 937 host = mmc_priv(mmc); 938 host->mmc = mmc; 939 host->pdata = pdata; 940 host->dev = &pdev->dev; 941 host->use_dma = 1; 942 host->dev->dma_mask = &pdata->dma_mask; 943 host->dma_ch = -1; 944 host->irq = irq; 945 host->id = pdev->id; 946 host->slot_id = 0; 947 host->mapbase = res->start; 948 host->base = ioremap(host->mapbase, SZ_4K); 949 950 platform_set_drvdata(pdev, host); 951 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect); 952 953 mmc->ops = &mmc_omap_ops; 954 mmc->f_min = 400000; 955 mmc->f_max = 52000000; 956 957 sema_init(&host->sem, 1); 958 959 host->iclk = clk_get(&pdev->dev, "ick"); 960 if (IS_ERR(host->iclk)) { 961 ret = PTR_ERR(host->iclk); 962 host->iclk = NULL; 963 goto err1; 964 } 965 host->fclk = clk_get(&pdev->dev, "fck"); 966 if (IS_ERR(host->fclk)) { 967 ret = PTR_ERR(host->fclk); 968 host->fclk = NULL; 969 clk_put(host->iclk); 970 goto err1; 971 } 972 973 if (clk_enable(host->fclk) != 0) { 974 clk_put(host->iclk); 975 clk_put(host->fclk); 976 goto err1; 977 } 978 979 if (clk_enable(host->iclk) != 0) { 980 clk_disable(host->fclk); 981 clk_put(host->iclk); 982 clk_put(host->fclk); 983 goto err1; 984 } 985 986 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 987 /* 988 * MMC can still work without debounce clock. 989 */ 990 if (IS_ERR(host->dbclk)) 991 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); 992 else 993 if (clk_enable(host->dbclk) != 0) 994 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 995 " clk failed\n"); 996 else 997 host->dbclk_enabled = 1; 998 999 #ifdef CONFIG_MMC_BLOCK_BOUNCE 1000 mmc->max_phys_segs = 1; 1001 mmc->max_hw_segs = 1; 1002 #endif 1003 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1004 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1005 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1006 mmc->max_seg_size = mmc->max_req_size; 1007 1008 mmc->ocr_avail = mmc_slot(host).ocr_mask; 1009 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; 1010 1011 if (pdata->slots[host->slot_id].wires >= 4) 1012 mmc->caps |= MMC_CAP_4_BIT_DATA; 1013 1014 /* Only MMC1 supports 3.0V */ 1015 if (host->id == OMAP_MMC1_DEVID) { 1016 hctl = SDVS30; 1017 capa = VS30 | VS18; 1018 } else { 1019 hctl = SDVS18; 1020 capa = VS18; 1021 } 1022 1023 OMAP_HSMMC_WRITE(host->base, HCTL, 1024 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 1025 1026 OMAP_HSMMC_WRITE(host->base, CAPA, 1027 OMAP_HSMMC_READ(host->base, CAPA) | capa); 1028 1029 /* Set the controller to AUTO IDLE mode */ 1030 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 1031 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 1032 1033 /* Set SD bus power bit */ 1034 OMAP_HSMMC_WRITE(host->base, HCTL, 1035 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1036 1037 /* Request IRQ for MMC operations */ 1038 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, 1039 mmc_hostname(mmc), host); 1040 if (ret) { 1041 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1042 goto err_irq; 1043 } 1044 1045 if (pdata->init != NULL) { 1046 if (pdata->init(&pdev->dev) != 0) { 1047 dev_dbg(mmc_dev(host->mmc), 1048 "Unable to configure MMC IRQs\n"); 1049 goto err_irq_cd_init; 1050 } 1051 } 1052 1053 /* Request IRQ for card detect */ 1054 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) { 1055 ret = request_irq(mmc_slot(host).card_detect_irq, 1056 omap_mmc_cd_handler, 1057 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 1058 | IRQF_DISABLED, 1059 mmc_hostname(mmc), host); 1060 if (ret) { 1061 dev_dbg(mmc_dev(host->mmc), 1062 "Unable to grab MMC CD IRQ\n"); 1063 goto err_irq_cd; 1064 } 1065 } 1066 1067 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 1068 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 1069 1070 mmc_add_host(mmc); 1071 1072 if (host->pdata->slots[host->slot_id].name != NULL) { 1073 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1074 if (ret < 0) 1075 goto err_slot_name; 1076 } 1077 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect && 1078 host->pdata->slots[host->slot_id].get_cover_state) { 1079 ret = device_create_file(&mmc->class_dev, 1080 &dev_attr_cover_switch); 1081 if (ret < 0) 1082 goto err_cover_switch; 1083 } 1084 1085 return 0; 1086 1087 err_cover_switch: 1088 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1089 err_slot_name: 1090 mmc_remove_host(mmc); 1091 err_irq_cd: 1092 free_irq(mmc_slot(host).card_detect_irq, host); 1093 err_irq_cd_init: 1094 free_irq(host->irq, host); 1095 err_irq: 1096 clk_disable(host->fclk); 1097 clk_disable(host->iclk); 1098 clk_put(host->fclk); 1099 clk_put(host->iclk); 1100 if (host->dbclk_enabled) { 1101 clk_disable(host->dbclk); 1102 clk_put(host->dbclk); 1103 } 1104 1105 err1: 1106 iounmap(host->base); 1107 err: 1108 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); 1109 release_mem_region(res->start, res->end - res->start + 1); 1110 if (host) 1111 mmc_free_host(mmc); 1112 return ret; 1113 } 1114 1115 static int omap_mmc_remove(struct platform_device *pdev) 1116 { 1117 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1118 struct resource *res; 1119 1120 if (host) { 1121 mmc_remove_host(host->mmc); 1122 if (host->pdata->cleanup) 1123 host->pdata->cleanup(&pdev->dev); 1124 free_irq(host->irq, host); 1125 if (mmc_slot(host).card_detect_irq) 1126 free_irq(mmc_slot(host).card_detect_irq, host); 1127 flush_scheduled_work(); 1128 1129 clk_disable(host->fclk); 1130 clk_disable(host->iclk); 1131 clk_put(host->fclk); 1132 clk_put(host->iclk); 1133 if (host->dbclk_enabled) { 1134 clk_disable(host->dbclk); 1135 clk_put(host->dbclk); 1136 } 1137 1138 mmc_free_host(host->mmc); 1139 iounmap(host->base); 1140 } 1141 1142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1143 if (res) 1144 release_mem_region(res->start, res->end - res->start + 1); 1145 platform_set_drvdata(pdev, NULL); 1146 1147 return 0; 1148 } 1149 1150 #ifdef CONFIG_PM 1151 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) 1152 { 1153 int ret = 0; 1154 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1155 1156 if (host && host->suspended) 1157 return 0; 1158 1159 if (host) { 1160 ret = mmc_suspend_host(host->mmc, state); 1161 if (ret == 0) { 1162 host->suspended = 1; 1163 1164 OMAP_HSMMC_WRITE(host->base, ISE, 0); 1165 OMAP_HSMMC_WRITE(host->base, IE, 0); 1166 1167 if (host->pdata->suspend) { 1168 ret = host->pdata->suspend(&pdev->dev, 1169 host->slot_id); 1170 if (ret) 1171 dev_dbg(mmc_dev(host->mmc), 1172 "Unable to handle MMC board" 1173 " level suspend\n"); 1174 } 1175 1176 if (host->id == OMAP_MMC1_DEVID 1177 && !(OMAP_HSMMC_READ(host->base, HCTL) 1178 & SDVSDET)) { 1179 OMAP_HSMMC_WRITE(host->base, HCTL, 1180 OMAP_HSMMC_READ(host->base, HCTL) 1181 & SDVSCLR); 1182 OMAP_HSMMC_WRITE(host->base, HCTL, 1183 OMAP_HSMMC_READ(host->base, HCTL) 1184 | SDVS30); 1185 OMAP_HSMMC_WRITE(host->base, HCTL, 1186 OMAP_HSMMC_READ(host->base, HCTL) 1187 | SDBP); 1188 } 1189 1190 clk_disable(host->fclk); 1191 clk_disable(host->iclk); 1192 clk_disable(host->dbclk); 1193 } 1194 1195 } 1196 return ret; 1197 } 1198 1199 /* Routine to resume the MMC device */ 1200 static int omap_mmc_resume(struct platform_device *pdev) 1201 { 1202 int ret = 0; 1203 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1204 1205 if (host && !host->suspended) 1206 return 0; 1207 1208 if (host) { 1209 1210 ret = clk_enable(host->fclk); 1211 if (ret) 1212 goto clk_en_err; 1213 1214 ret = clk_enable(host->iclk); 1215 if (ret) { 1216 clk_disable(host->fclk); 1217 clk_put(host->fclk); 1218 goto clk_en_err; 1219 } 1220 1221 if (clk_enable(host->dbclk) != 0) 1222 dev_dbg(mmc_dev(host->mmc), 1223 "Enabling debounce clk failed\n"); 1224 1225 if (host->pdata->resume) { 1226 ret = host->pdata->resume(&pdev->dev, host->slot_id); 1227 if (ret) 1228 dev_dbg(mmc_dev(host->mmc), 1229 "Unmask interrupt failed\n"); 1230 } 1231 1232 /* Notify the core to resume the host */ 1233 ret = mmc_resume_host(host->mmc); 1234 if (ret == 0) 1235 host->suspended = 0; 1236 } 1237 1238 return ret; 1239 1240 clk_en_err: 1241 dev_dbg(mmc_dev(host->mmc), 1242 "Failed to enable MMC clocks during resume\n"); 1243 return ret; 1244 } 1245 1246 #else 1247 #define omap_mmc_suspend NULL 1248 #define omap_mmc_resume NULL 1249 #endif 1250 1251 static struct platform_driver omap_mmc_driver = { 1252 .probe = omap_mmc_probe, 1253 .remove = omap_mmc_remove, 1254 .suspend = omap_mmc_suspend, 1255 .resume = omap_mmc_resume, 1256 .driver = { 1257 .name = DRIVER_NAME, 1258 .owner = THIS_MODULE, 1259 }, 1260 }; 1261 1262 static int __init omap_mmc_init(void) 1263 { 1264 /* Register the MMC driver */ 1265 return platform_driver_register(&omap_mmc_driver); 1266 } 1267 1268 static void __exit omap_mmc_cleanup(void) 1269 { 1270 /* Unregister MMC driver */ 1271 platform_driver_unregister(&omap_mmc_driver); 1272 } 1273 1274 module_init(omap_mmc_init); 1275 module_exit(omap_mmc_cleanup); 1276 1277 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 1278 MODULE_LICENSE("GPL"); 1279 MODULE_ALIAS("platform:" DRIVER_NAME); 1280 MODULE_AUTHOR("Texas Instruments Inc"); 1281