1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/sizes.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/timer.h> 30 #include <linux/clk.h> 31 #include <linux/of.h> 32 #include <linux/of_irq.h> 33 #include <linux/of_device.h> 34 #include <linux/mmc/host.h> 35 #include <linux/mmc/core.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/slot-gpio.h> 38 #include <linux/io.h> 39 #include <linux/irq.h> 40 #include <linux/regulator/consumer.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/pm_wakeirq.h> 44 #include <linux/platform_data/hsmmc-omap.h> 45 46 /* OMAP HSMMC Host Controller Registers */ 47 #define OMAP_HSMMC_SYSSTATUS 0x0014 48 #define OMAP_HSMMC_CON 0x002C 49 #define OMAP_HSMMC_SDMASA 0x0100 50 #define OMAP_HSMMC_BLK 0x0104 51 #define OMAP_HSMMC_ARG 0x0108 52 #define OMAP_HSMMC_CMD 0x010C 53 #define OMAP_HSMMC_RSP10 0x0110 54 #define OMAP_HSMMC_RSP32 0x0114 55 #define OMAP_HSMMC_RSP54 0x0118 56 #define OMAP_HSMMC_RSP76 0x011C 57 #define OMAP_HSMMC_DATA 0x0120 58 #define OMAP_HSMMC_PSTATE 0x0124 59 #define OMAP_HSMMC_HCTL 0x0128 60 #define OMAP_HSMMC_SYSCTL 0x012C 61 #define OMAP_HSMMC_STAT 0x0130 62 #define OMAP_HSMMC_IE 0x0134 63 #define OMAP_HSMMC_ISE 0x0138 64 #define OMAP_HSMMC_AC12 0x013C 65 #define OMAP_HSMMC_CAPA 0x0140 66 67 #define VS18 (1 << 26) 68 #define VS30 (1 << 25) 69 #define HSS (1 << 21) 70 #define SDVS18 (0x5 << 9) 71 #define SDVS30 (0x6 << 9) 72 #define SDVS33 (0x7 << 9) 73 #define SDVS_MASK 0x00000E00 74 #define SDVSCLR 0xFFFFF1FF 75 #define SDVSDET 0x00000400 76 #define AUTOIDLE 0x1 77 #define SDBP (1 << 8) 78 #define DTO 0xe 79 #define ICE 0x1 80 #define ICS 0x2 81 #define CEN (1 << 2) 82 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 83 #define CLKD_MASK 0x0000FFC0 84 #define CLKD_SHIFT 6 85 #define DTO_MASK 0x000F0000 86 #define DTO_SHIFT 16 87 #define INIT_STREAM (1 << 1) 88 #define ACEN_ACMD23 (2 << 2) 89 #define DP_SELECT (1 << 21) 90 #define DDIR (1 << 4) 91 #define DMAE 0x1 92 #define MSBS (1 << 5) 93 #define BCE (1 << 1) 94 #define FOUR_BIT (1 << 1) 95 #define HSPE (1 << 2) 96 #define IWE (1 << 24) 97 #define DDR (1 << 19) 98 #define CLKEXTFREE (1 << 16) 99 #define CTPL (1 << 11) 100 #define DW8 (1 << 5) 101 #define OD 0x1 102 #define STAT_CLEAR 0xFFFFFFFF 103 #define INIT_STREAM_CMD 0x00000000 104 #define DUAL_VOLT_OCR_BIT 7 105 #define SRC (1 << 25) 106 #define SRD (1 << 26) 107 #define SOFTRESET (1 << 1) 108 109 /* PSTATE */ 110 #define DLEV_DAT(x) (1 << (20 + (x))) 111 112 /* Interrupt masks for IE and ISE register */ 113 #define CC_EN (1 << 0) 114 #define TC_EN (1 << 1) 115 #define BWR_EN (1 << 4) 116 #define BRR_EN (1 << 5) 117 #define CIRQ_EN (1 << 8) 118 #define ERR_EN (1 << 15) 119 #define CTO_EN (1 << 16) 120 #define CCRC_EN (1 << 17) 121 #define CEB_EN (1 << 18) 122 #define CIE_EN (1 << 19) 123 #define DTO_EN (1 << 20) 124 #define DCRC_EN (1 << 21) 125 #define DEB_EN (1 << 22) 126 #define ACE_EN (1 << 24) 127 #define CERR_EN (1 << 28) 128 #define BADA_EN (1 << 29) 129 130 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 132 BRR_EN | BWR_EN | TC_EN | CC_EN) 133 134 #define CNI (1 << 7) 135 #define ACIE (1 << 4) 136 #define ACEB (1 << 3) 137 #define ACCE (1 << 2) 138 #define ACTO (1 << 1) 139 #define ACNE (1 << 0) 140 141 #define MMC_AUTOSUSPEND_DELAY 100 142 #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 143 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 144 #define OMAP_MMC_MIN_CLOCK 400000 145 #define OMAP_MMC_MAX_CLOCK 52000000 146 #define DRIVER_NAME "omap_hsmmc" 147 148 /* 149 * One controller can have multiple slots, like on some omap boards using 150 * omap.c controller driver. Luckily this is not currently done on any known 151 * omap_hsmmc.c device. 152 */ 153 #define mmc_pdata(host) host->pdata 154 155 /* 156 * MMC Host controller read/write API's 157 */ 158 #define OMAP_HSMMC_READ(base, reg) \ 159 __raw_readl((base) + OMAP_HSMMC_##reg) 160 161 #define OMAP_HSMMC_WRITE(base, reg, val) \ 162 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 163 164 struct omap_hsmmc_next { 165 unsigned int dma_len; 166 s32 cookie; 167 }; 168 169 struct omap_hsmmc_host { 170 struct device *dev; 171 struct mmc_host *mmc; 172 struct mmc_request *mrq; 173 struct mmc_command *cmd; 174 struct mmc_data *data; 175 struct clk *fclk; 176 struct clk *dbclk; 177 struct regulator *pbias; 178 bool pbias_enabled; 179 void __iomem *base; 180 int vqmmc_enabled; 181 resource_size_t mapbase; 182 spinlock_t irq_lock; /* Prevent races with irq handler */ 183 unsigned int dma_len; 184 unsigned int dma_sg_idx; 185 unsigned char bus_mode; 186 unsigned char power_mode; 187 int suspended; 188 u32 con; 189 u32 hctl; 190 u32 sysctl; 191 u32 capa; 192 int irq; 193 int wake_irq; 194 int use_dma, dma_ch; 195 struct dma_chan *tx_chan; 196 struct dma_chan *rx_chan; 197 int response_busy; 198 int context_loss; 199 int reqs_blocked; 200 int req_in_progress; 201 unsigned long clk_rate; 202 unsigned int flags; 203 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 204 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 205 struct omap_hsmmc_next next_data; 206 struct omap_hsmmc_platform_data *pdata; 207 }; 208 209 struct omap_mmc_of_data { 210 u32 reg_offset; 211 u8 controller_flags; 212 }; 213 214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 215 216 static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 217 { 218 int ret; 219 struct omap_hsmmc_host *host = mmc_priv(mmc); 220 struct mmc_ios *ios = &mmc->ios; 221 222 if (!IS_ERR(mmc->supply.vmmc)) { 223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 224 if (ret) 225 return ret; 226 } 227 228 /* Enable interface voltage rail, if needed */ 229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 230 ret = regulator_enable(mmc->supply.vqmmc); 231 if (ret) { 232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 233 goto err_vqmmc; 234 } 235 host->vqmmc_enabled = 1; 236 } 237 238 return 0; 239 240 err_vqmmc: 241 if (!IS_ERR(mmc->supply.vmmc)) 242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 243 244 return ret; 245 } 246 247 static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 248 { 249 int ret; 250 int status; 251 struct omap_hsmmc_host *host = mmc_priv(mmc); 252 253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 254 ret = regulator_disable(mmc->supply.vqmmc); 255 if (ret) { 256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 257 return ret; 258 } 259 host->vqmmc_enabled = 0; 260 } 261 262 if (!IS_ERR(mmc->supply.vmmc)) { 263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 264 if (ret) 265 goto err_set_ocr; 266 } 267 268 return 0; 269 270 err_set_ocr: 271 if (!IS_ERR(mmc->supply.vqmmc)) { 272 status = regulator_enable(mmc->supply.vqmmc); 273 if (status) 274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 275 } 276 277 return ret; 278 } 279 280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on) 281 { 282 int ret; 283 284 if (IS_ERR(host->pbias)) 285 return 0; 286 287 if (power_on) { 288 if (host->pbias_enabled == 0) { 289 ret = regulator_enable(host->pbias); 290 if (ret) { 291 dev_err(host->dev, "pbias reg enable fail\n"); 292 return ret; 293 } 294 host->pbias_enabled = 1; 295 } 296 } else { 297 if (host->pbias_enabled == 1) { 298 ret = regulator_disable(host->pbias); 299 if (ret) { 300 dev_err(host->dev, "pbias reg disable fail\n"); 301 return ret; 302 } 303 host->pbias_enabled = 0; 304 } 305 } 306 307 return 0; 308 } 309 310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on) 311 { 312 struct mmc_host *mmc = host->mmc; 313 int ret = 0; 314 315 /* 316 * If we don't see a Vcc regulator, assume it's a fixed 317 * voltage always-on regulator. 318 */ 319 if (IS_ERR(mmc->supply.vmmc)) 320 return 0; 321 322 ret = omap_hsmmc_set_pbias(host, false); 323 if (ret) 324 return ret; 325 326 /* 327 * Assume Vcc regulator is used only to power the card ... OMAP 328 * VDDS is used to power the pins, optionally with a transceiver to 329 * support cards using voltages other than VDDS (1.8V nominal). When a 330 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 331 * 332 * In some cases this regulator won't support enable/disable; 333 * e.g. it's a fixed rail for a WLAN chip. 334 * 335 * In other cases vcc_aux switches interface power. Example, for 336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 337 * chips/cards need an interface voltage rail too. 338 */ 339 if (power_on) { 340 ret = omap_hsmmc_enable_supply(mmc); 341 if (ret) 342 return ret; 343 344 ret = omap_hsmmc_set_pbias(host, true); 345 if (ret) 346 goto err_set_voltage; 347 } else { 348 ret = omap_hsmmc_disable_supply(mmc); 349 if (ret) 350 return ret; 351 } 352 353 return 0; 354 355 err_set_voltage: 356 omap_hsmmc_disable_supply(mmc); 357 358 return ret; 359 } 360 361 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 362 { 363 int ret; 364 365 if (IS_ERR(reg)) 366 return 0; 367 368 if (regulator_is_enabled(reg)) { 369 ret = regulator_enable(reg); 370 if (ret) 371 return ret; 372 373 ret = regulator_disable(reg); 374 if (ret) 375 return ret; 376 } 377 378 return 0; 379 } 380 381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 382 { 383 struct mmc_host *mmc = host->mmc; 384 int ret; 385 386 /* 387 * disable regulators enabled during boot and get the usecount 388 * right so that regulators can be enabled/disabled by checking 389 * the return value of regulator_is_enabled 390 */ 391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 392 if (ret) { 393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 394 return ret; 395 } 396 397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 398 if (ret) { 399 dev_err(host->dev, 400 "fail to disable boot enabled vmmc_aux reg\n"); 401 return ret; 402 } 403 404 ret = omap_hsmmc_disable_boot_regulator(host->pbias); 405 if (ret) { 406 dev_err(host->dev, 407 "failed to disable boot enabled pbias reg\n"); 408 return ret; 409 } 410 411 return 0; 412 } 413 414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 415 { 416 int ret; 417 struct mmc_host *mmc = host->mmc; 418 419 420 ret = mmc_regulator_get_supply(mmc); 421 if (ret) 422 return ret; 423 424 /* Allow an aux regulator */ 425 if (IS_ERR(mmc->supply.vqmmc)) { 426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 427 "vmmc_aux"); 428 if (IS_ERR(mmc->supply.vqmmc)) { 429 ret = PTR_ERR(mmc->supply.vqmmc); 430 if ((ret != -ENODEV) && host->dev->of_node) 431 return ret; 432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 433 PTR_ERR(mmc->supply.vqmmc)); 434 } 435 } 436 437 host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 438 if (IS_ERR(host->pbias)) { 439 ret = PTR_ERR(host->pbias); 440 if ((ret != -ENODEV) && host->dev->of_node) { 441 dev_err(host->dev, 442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 443 return ret; 444 } 445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 446 PTR_ERR(host->pbias)); 447 } 448 449 /* For eMMC do not power off when not in sleep state */ 450 if (mmc_pdata(host)->no_regulator_off_init) 451 return 0; 452 453 ret = omap_hsmmc_disable_boot_regulators(host); 454 if (ret) 455 return ret; 456 457 return 0; 458 } 459 460 /* 461 * Start clock to the card 462 */ 463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 464 { 465 OMAP_HSMMC_WRITE(host->base, SYSCTL, 466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 467 } 468 469 /* 470 * Stop clock to the card 471 */ 472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 473 { 474 OMAP_HSMMC_WRITE(host->base, SYSCTL, 475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 478 } 479 480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 481 struct mmc_command *cmd) 482 { 483 u32 irq_mask = INT_EN_MASK; 484 unsigned long flags; 485 486 if (host->use_dma) 487 irq_mask &= ~(BRR_EN | BWR_EN); 488 489 /* Disable timeout for erases */ 490 if (cmd->opcode == MMC_ERASE) 491 irq_mask &= ~DTO_EN; 492 493 spin_lock_irqsave(&host->irq_lock, flags); 494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 496 497 /* latch pending CIRQ, but don't signal MMC core */ 498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 499 irq_mask |= CIRQ_EN; 500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 501 spin_unlock_irqrestore(&host->irq_lock, flags); 502 } 503 504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 505 { 506 u32 irq_mask = 0; 507 unsigned long flags; 508 509 spin_lock_irqsave(&host->irq_lock, flags); 510 /* no transfer running but need to keep cirq if enabled */ 511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 512 irq_mask |= CIRQ_EN; 513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 516 spin_unlock_irqrestore(&host->irq_lock, flags); 517 } 518 519 /* Calculate divisor for the given clock frequency */ 520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 521 { 522 u16 dsor = 0; 523 524 if (ios->clock) { 525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 526 if (dsor > CLKD_MAX) 527 dsor = CLKD_MAX; 528 } 529 530 return dsor; 531 } 532 533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 534 { 535 struct mmc_ios *ios = &host->mmc->ios; 536 unsigned long regval; 537 unsigned long timeout; 538 unsigned long clkdiv; 539 540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 541 542 omap_hsmmc_stop_clock(host); 543 544 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 545 regval = regval & ~(CLKD_MASK | DTO_MASK); 546 clkdiv = calc_divisor(host, ios); 547 regval = regval | (clkdiv << 6) | (DTO << 16); 548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 549 OMAP_HSMMC_WRITE(host->base, SYSCTL, 550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 551 552 /* Wait till the ICS bit is set */ 553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 555 && time_before(jiffies, timeout)) 556 cpu_relax(); 557 558 /* 559 * Enable High-Speed Support 560 * Pre-Requisites 561 * - Controller should support High-Speed-Enable Bit 562 * - Controller should not be using DDR Mode 563 * - Controller should advertise that it supports High Speed 564 * in capabilities register 565 * - MMC/SD clock coming out of controller > 25MHz 566 */ 567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 568 (ios->timing != MMC_TIMING_MMC_DDR52) && 569 (ios->timing != MMC_TIMING_UHS_DDR50) && 570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 571 regval = OMAP_HSMMC_READ(host->base, HCTL); 572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 573 regval |= HSPE; 574 else 575 regval &= ~HSPE; 576 577 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 578 } 579 580 omap_hsmmc_start_clock(host); 581 } 582 583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 584 { 585 struct mmc_ios *ios = &host->mmc->ios; 586 u32 con; 587 588 con = OMAP_HSMMC_READ(host->base, CON); 589 if (ios->timing == MMC_TIMING_MMC_DDR52 || 590 ios->timing == MMC_TIMING_UHS_DDR50) 591 con |= DDR; /* configure in DDR mode */ 592 else 593 con &= ~DDR; 594 switch (ios->bus_width) { 595 case MMC_BUS_WIDTH_8: 596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 597 break; 598 case MMC_BUS_WIDTH_4: 599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 600 OMAP_HSMMC_WRITE(host->base, HCTL, 601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 602 break; 603 case MMC_BUS_WIDTH_1: 604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 605 OMAP_HSMMC_WRITE(host->base, HCTL, 606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 607 break; 608 } 609 } 610 611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 612 { 613 struct mmc_ios *ios = &host->mmc->ios; 614 u32 con; 615 616 con = OMAP_HSMMC_READ(host->base, CON); 617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 618 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 619 else 620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 621 } 622 623 #ifdef CONFIG_PM 624 625 /* 626 * Restore the MMC host context, if it was lost as result of a 627 * power state change. 628 */ 629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 630 { 631 struct mmc_ios *ios = &host->mmc->ios; 632 u32 hctl, capa; 633 unsigned long timeout; 634 635 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 638 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 639 return 0; 640 641 host->context_loss++; 642 643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 644 if (host->power_mode != MMC_POWER_OFF && 645 (1 << ios->vdd) <= MMC_VDD_23_24) 646 hctl = SDVS18; 647 else 648 hctl = SDVS30; 649 capa = VS30 | VS18; 650 } else { 651 hctl = SDVS18; 652 capa = VS18; 653 } 654 655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 656 hctl |= IWE; 657 658 OMAP_HSMMC_WRITE(host->base, HCTL, 659 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 660 661 OMAP_HSMMC_WRITE(host->base, CAPA, 662 OMAP_HSMMC_READ(host->base, CAPA) | capa); 663 664 OMAP_HSMMC_WRITE(host->base, HCTL, 665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 666 667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 669 && time_before(jiffies, timeout)) 670 ; 671 672 OMAP_HSMMC_WRITE(host->base, ISE, 0); 673 OMAP_HSMMC_WRITE(host->base, IE, 0); 674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 675 676 /* Do not initialize card-specific things if the power is off */ 677 if (host->power_mode == MMC_POWER_OFF) 678 goto out; 679 680 omap_hsmmc_set_bus_width(host); 681 682 omap_hsmmc_set_clock(host); 683 684 omap_hsmmc_set_bus_mode(host); 685 686 out: 687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 688 host->context_loss); 689 return 0; 690 } 691 692 /* 693 * Save the MMC host context (store the number of power state changes so far). 694 */ 695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 696 { 697 host->con = OMAP_HSMMC_READ(host->base, CON); 698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 700 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 701 } 702 703 #else 704 705 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 706 { 707 return 0; 708 } 709 710 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 711 { 712 } 713 714 #endif 715 716 /* 717 * Send init stream sequence to card 718 * before sending IDLE command 719 */ 720 static void send_init_stream(struct omap_hsmmc_host *host) 721 { 722 int reg = 0; 723 unsigned long timeout; 724 725 disable_irq(host->irq); 726 727 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 728 OMAP_HSMMC_WRITE(host->base, CON, 729 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 730 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 731 732 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 733 while ((reg != CC_EN) && time_before(jiffies, timeout)) 734 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 735 736 OMAP_HSMMC_WRITE(host->base, CON, 737 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 738 739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 740 OMAP_HSMMC_READ(host->base, STAT); 741 742 enable_irq(host->irq); 743 } 744 745 static ssize_t 746 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 747 char *buf) 748 { 749 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 750 struct omap_hsmmc_host *host = mmc_priv(mmc); 751 752 return sprintf(buf, "%s\n", mmc_pdata(host)->name); 753 } 754 755 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 756 757 /* 758 * Configure the response type and send the cmd. 759 */ 760 static void 761 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 762 struct mmc_data *data) 763 { 764 int cmdreg = 0, resptype = 0, cmdtype = 0; 765 766 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 767 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 768 host->cmd = cmd; 769 770 omap_hsmmc_enable_irq(host, cmd); 771 772 host->response_busy = 0; 773 if (cmd->flags & MMC_RSP_PRESENT) { 774 if (cmd->flags & MMC_RSP_136) 775 resptype = 1; 776 else if (cmd->flags & MMC_RSP_BUSY) { 777 resptype = 3; 778 host->response_busy = 1; 779 } else 780 resptype = 2; 781 } 782 783 /* 784 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 785 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 786 * a val of 0x3, rest 0x0. 787 */ 788 if (cmd == host->mrq->stop) 789 cmdtype = 0x3; 790 791 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 792 793 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 794 host->mrq->sbc) { 795 cmdreg |= ACEN_ACMD23; 796 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 797 } 798 if (data) { 799 cmdreg |= DP_SELECT | MSBS | BCE; 800 if (data->flags & MMC_DATA_READ) 801 cmdreg |= DDIR; 802 else 803 cmdreg &= ~(DDIR); 804 } 805 806 if (host->use_dma) 807 cmdreg |= DMAE; 808 809 host->req_in_progress = 1; 810 811 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 812 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 813 } 814 815 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 816 struct mmc_data *data) 817 { 818 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 819 } 820 821 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 822 { 823 int dma_ch; 824 unsigned long flags; 825 826 spin_lock_irqsave(&host->irq_lock, flags); 827 host->req_in_progress = 0; 828 dma_ch = host->dma_ch; 829 spin_unlock_irqrestore(&host->irq_lock, flags); 830 831 omap_hsmmc_disable_irq(host); 832 /* Do not complete the request if DMA is still in progress */ 833 if (mrq->data && host->use_dma && dma_ch != -1) 834 return; 835 host->mrq = NULL; 836 mmc_request_done(host->mmc, mrq); 837 } 838 839 /* 840 * Notify the transfer complete to MMC core 841 */ 842 static void 843 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 844 { 845 if (!data) { 846 struct mmc_request *mrq = host->mrq; 847 848 /* TC before CC from CMD6 - don't know why, but it happens */ 849 if (host->cmd && host->cmd->opcode == 6 && 850 host->response_busy) { 851 host->response_busy = 0; 852 return; 853 } 854 855 omap_hsmmc_request_done(host, mrq); 856 return; 857 } 858 859 host->data = NULL; 860 861 if (!data->error) 862 data->bytes_xfered += data->blocks * (data->blksz); 863 else 864 data->bytes_xfered = 0; 865 866 if (data->stop && (data->error || !host->mrq->sbc)) 867 omap_hsmmc_start_command(host, data->stop, NULL); 868 else 869 omap_hsmmc_request_done(host, data->mrq); 870 } 871 872 /* 873 * Notify the core about command completion 874 */ 875 static void 876 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 877 { 878 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 879 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 880 host->cmd = NULL; 881 omap_hsmmc_start_dma_transfer(host); 882 omap_hsmmc_start_command(host, host->mrq->cmd, 883 host->mrq->data); 884 return; 885 } 886 887 host->cmd = NULL; 888 889 if (cmd->flags & MMC_RSP_PRESENT) { 890 if (cmd->flags & MMC_RSP_136) { 891 /* response type 2 */ 892 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 893 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 894 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 895 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 896 } else { 897 /* response types 1, 1b, 3, 4, 5, 6 */ 898 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 899 } 900 } 901 if ((host->data == NULL && !host->response_busy) || cmd->error) 902 omap_hsmmc_request_done(host, host->mrq); 903 } 904 905 /* 906 * DMA clean up for command errors 907 */ 908 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 909 { 910 int dma_ch; 911 unsigned long flags; 912 913 host->data->error = errno; 914 915 spin_lock_irqsave(&host->irq_lock, flags); 916 dma_ch = host->dma_ch; 917 host->dma_ch = -1; 918 spin_unlock_irqrestore(&host->irq_lock, flags); 919 920 if (host->use_dma && dma_ch != -1) { 921 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 922 923 dmaengine_terminate_all(chan); 924 dma_unmap_sg(chan->device->dev, 925 host->data->sg, host->data->sg_len, 926 mmc_get_dma_dir(host->data)); 927 928 host->data->host_cookie = 0; 929 } 930 host->data = NULL; 931 } 932 933 /* 934 * Readable error output 935 */ 936 #ifdef CONFIG_MMC_DEBUG 937 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 938 { 939 /* --- means reserved bit without definition at documentation */ 940 static const char *omap_hsmmc_status_bits[] = { 941 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 942 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 943 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 944 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 945 }; 946 char res[256]; 947 char *buf = res; 948 int len, i; 949 950 len = sprintf(buf, "MMC IRQ 0x%x :", status); 951 buf += len; 952 953 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 954 if (status & (1 << i)) { 955 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 956 buf += len; 957 } 958 959 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 960 } 961 #else 962 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 963 u32 status) 964 { 965 } 966 #endif /* CONFIG_MMC_DEBUG */ 967 968 /* 969 * MMC controller internal state machines reset 970 * 971 * Used to reset command or data internal state machines, using respectively 972 * SRC or SRD bit of SYSCTL register 973 * Can be called from interrupt context 974 */ 975 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 976 unsigned long bit) 977 { 978 unsigned long i = 0; 979 unsigned long limit = MMC_TIMEOUT_US; 980 981 OMAP_HSMMC_WRITE(host->base, SYSCTL, 982 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 983 984 /* 985 * OMAP4 ES2 and greater has an updated reset logic. 986 * Monitor a 0->1 transition first 987 */ 988 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 989 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 990 && (i++ < limit)) 991 udelay(1); 992 } 993 i = 0; 994 995 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 996 (i++ < limit)) 997 udelay(1); 998 999 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1000 dev_err(mmc_dev(host->mmc), 1001 "Timeout waiting on controller reset in %s\n", 1002 __func__); 1003 } 1004 1005 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1006 int err, int end_cmd) 1007 { 1008 if (end_cmd) { 1009 omap_hsmmc_reset_controller_fsm(host, SRC); 1010 if (host->cmd) 1011 host->cmd->error = err; 1012 } 1013 1014 if (host->data) { 1015 omap_hsmmc_reset_controller_fsm(host, SRD); 1016 omap_hsmmc_dma_cleanup(host, err); 1017 } else if (host->mrq && host->mrq->cmd) 1018 host->mrq->cmd->error = err; 1019 } 1020 1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1022 { 1023 struct mmc_data *data; 1024 int end_cmd = 0, end_trans = 0; 1025 int error = 0; 1026 1027 data = host->data; 1028 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1029 1030 if (status & ERR_EN) { 1031 omap_hsmmc_dbg_report_irq(host, status); 1032 1033 if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1034 end_cmd = 1; 1035 if (host->data || host->response_busy) { 1036 end_trans = !end_cmd; 1037 host->response_busy = 0; 1038 } 1039 if (status & (CTO_EN | DTO_EN)) 1040 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1041 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 1042 BADA_EN)) 1043 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1044 1045 if (status & ACE_EN) { 1046 u32 ac12; 1047 ac12 = OMAP_HSMMC_READ(host->base, AC12); 1048 if (!(ac12 & ACNE) && host->mrq->sbc) { 1049 end_cmd = 1; 1050 if (ac12 & ACTO) 1051 error = -ETIMEDOUT; 1052 else if (ac12 & (ACCE | ACEB | ACIE)) 1053 error = -EILSEQ; 1054 host->mrq->sbc->error = error; 1055 hsmmc_command_incomplete(host, error, end_cmd); 1056 } 1057 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1058 } 1059 } 1060 1061 OMAP_HSMMC_WRITE(host->base, STAT, status); 1062 if (end_cmd || ((status & CC_EN) && host->cmd)) 1063 omap_hsmmc_cmd_done(host, host->cmd); 1064 if ((end_trans || (status & TC_EN)) && host->mrq) 1065 omap_hsmmc_xfer_done(host, data); 1066 } 1067 1068 /* 1069 * MMC controller IRQ handler 1070 */ 1071 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1072 { 1073 struct omap_hsmmc_host *host = dev_id; 1074 int status; 1075 1076 status = OMAP_HSMMC_READ(host->base, STAT); 1077 while (status & (INT_EN_MASK | CIRQ_EN)) { 1078 if (host->req_in_progress) 1079 omap_hsmmc_do_irq(host, status); 1080 1081 if (status & CIRQ_EN) 1082 mmc_signal_sdio_irq(host->mmc); 1083 1084 /* Flush posted write */ 1085 status = OMAP_HSMMC_READ(host->base, STAT); 1086 } 1087 1088 return IRQ_HANDLED; 1089 } 1090 1091 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1092 { 1093 unsigned long i; 1094 1095 OMAP_HSMMC_WRITE(host->base, HCTL, 1096 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1097 for (i = 0; i < loops_per_jiffy; i++) { 1098 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1099 break; 1100 cpu_relax(); 1101 } 1102 } 1103 1104 /* 1105 * Switch MMC interface voltage ... only relevant for MMC1. 1106 * 1107 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1108 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1109 * Some chips, like eMMC ones, use internal transceivers. 1110 */ 1111 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1112 { 1113 u32 reg_val = 0; 1114 int ret; 1115 1116 /* Disable the clocks */ 1117 if (host->dbclk) 1118 clk_disable_unprepare(host->dbclk); 1119 1120 /* Turn the power off */ 1121 ret = omap_hsmmc_set_power(host, 0); 1122 1123 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1124 if (!ret) 1125 ret = omap_hsmmc_set_power(host, 1); 1126 if (host->dbclk) 1127 clk_prepare_enable(host->dbclk); 1128 1129 if (ret != 0) 1130 goto err; 1131 1132 OMAP_HSMMC_WRITE(host->base, HCTL, 1133 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1134 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1135 1136 /* 1137 * If a MMC dual voltage card is detected, the set_ios fn calls 1138 * this fn with VDD bit set for 1.8V. Upon card removal from the 1139 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1140 * 1141 * Cope with a bit of slop in the range ... per data sheets: 1142 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1143 * but recommended values are 1.71V to 1.89V 1144 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1145 * but recommended values are 2.7V to 3.3V 1146 * 1147 * Board setup code shouldn't permit anything very out-of-range. 1148 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1149 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1150 */ 1151 if ((1 << vdd) <= MMC_VDD_23_24) 1152 reg_val |= SDVS18; 1153 else 1154 reg_val |= SDVS30; 1155 1156 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1157 set_sd_bus_power(host); 1158 1159 return 0; 1160 err: 1161 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1162 return ret; 1163 } 1164 1165 static void omap_hsmmc_dma_callback(void *param) 1166 { 1167 struct omap_hsmmc_host *host = param; 1168 struct dma_chan *chan; 1169 struct mmc_data *data; 1170 int req_in_progress; 1171 1172 spin_lock_irq(&host->irq_lock); 1173 if (host->dma_ch < 0) { 1174 spin_unlock_irq(&host->irq_lock); 1175 return; 1176 } 1177 1178 data = host->mrq->data; 1179 chan = omap_hsmmc_get_dma_chan(host, data); 1180 if (!data->host_cookie) 1181 dma_unmap_sg(chan->device->dev, 1182 data->sg, data->sg_len, 1183 mmc_get_dma_dir(data)); 1184 1185 req_in_progress = host->req_in_progress; 1186 host->dma_ch = -1; 1187 spin_unlock_irq(&host->irq_lock); 1188 1189 /* If DMA has finished after TC, complete the request */ 1190 if (!req_in_progress) { 1191 struct mmc_request *mrq = host->mrq; 1192 1193 host->mrq = NULL; 1194 mmc_request_done(host->mmc, mrq); 1195 } 1196 } 1197 1198 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1199 struct mmc_data *data, 1200 struct omap_hsmmc_next *next, 1201 struct dma_chan *chan) 1202 { 1203 int dma_len; 1204 1205 if (!next && data->host_cookie && 1206 data->host_cookie != host->next_data.cookie) { 1207 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1208 " host->next_data.cookie %d\n", 1209 __func__, data->host_cookie, host->next_data.cookie); 1210 data->host_cookie = 0; 1211 } 1212 1213 /* Check if next job is already prepared */ 1214 if (next || data->host_cookie != host->next_data.cookie) { 1215 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1216 mmc_get_dma_dir(data)); 1217 1218 } else { 1219 dma_len = host->next_data.dma_len; 1220 host->next_data.dma_len = 0; 1221 } 1222 1223 1224 if (dma_len == 0) 1225 return -EINVAL; 1226 1227 if (next) { 1228 next->dma_len = dma_len; 1229 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1230 } else 1231 host->dma_len = dma_len; 1232 1233 return 0; 1234 } 1235 1236 /* 1237 * Routine to configure and start DMA for the MMC card 1238 */ 1239 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 1240 struct mmc_request *req) 1241 { 1242 struct dma_async_tx_descriptor *tx; 1243 int ret = 0, i; 1244 struct mmc_data *data = req->data; 1245 struct dma_chan *chan; 1246 struct dma_slave_config cfg = { 1247 .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1248 .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1249 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1250 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1251 .src_maxburst = data->blksz / 4, 1252 .dst_maxburst = data->blksz / 4, 1253 }; 1254 1255 /* Sanity check: all the SG entries must be aligned by block size. */ 1256 for (i = 0; i < data->sg_len; i++) { 1257 struct scatterlist *sgl; 1258 1259 sgl = data->sg + i; 1260 if (sgl->length % data->blksz) 1261 return -EINVAL; 1262 } 1263 if ((data->blksz % 4) != 0) 1264 /* REVISIT: The MMC buffer increments only when MSB is written. 1265 * Return error for blksz which is non multiple of four. 1266 */ 1267 return -EINVAL; 1268 1269 BUG_ON(host->dma_ch != -1); 1270 1271 chan = omap_hsmmc_get_dma_chan(host, data); 1272 1273 ret = dmaengine_slave_config(chan, &cfg); 1274 if (ret) 1275 return ret; 1276 1277 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1278 if (ret) 1279 return ret; 1280 1281 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1282 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1283 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1284 if (!tx) { 1285 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1286 /* FIXME: cleanup */ 1287 return -1; 1288 } 1289 1290 tx->callback = omap_hsmmc_dma_callback; 1291 tx->callback_param = host; 1292 1293 /* Does not fail */ 1294 dmaengine_submit(tx); 1295 1296 host->dma_ch = 1; 1297 1298 return 0; 1299 } 1300 1301 static void set_data_timeout(struct omap_hsmmc_host *host, 1302 unsigned long long timeout_ns, 1303 unsigned int timeout_clks) 1304 { 1305 unsigned long long timeout = timeout_ns; 1306 unsigned int cycle_ns; 1307 uint32_t reg, clkd, dto = 0; 1308 1309 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1310 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1311 if (clkd == 0) 1312 clkd = 1; 1313 1314 cycle_ns = 1000000000 / (host->clk_rate / clkd); 1315 do_div(timeout, cycle_ns); 1316 timeout += timeout_clks; 1317 if (timeout) { 1318 while ((timeout & 0x80000000) == 0) { 1319 dto += 1; 1320 timeout <<= 1; 1321 } 1322 dto = 31 - dto; 1323 timeout <<= 1; 1324 if (timeout && dto) 1325 dto += 1; 1326 if (dto >= 13) 1327 dto -= 13; 1328 else 1329 dto = 0; 1330 if (dto > 14) 1331 dto = 14; 1332 } 1333 1334 reg &= ~DTO_MASK; 1335 reg |= dto << DTO_SHIFT; 1336 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1337 } 1338 1339 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 1340 { 1341 struct mmc_request *req = host->mrq; 1342 struct dma_chan *chan; 1343 1344 if (!req->data) 1345 return; 1346 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1347 | (req->data->blocks << 16)); 1348 set_data_timeout(host, req->data->timeout_ns, 1349 req->data->timeout_clks); 1350 chan = omap_hsmmc_get_dma_chan(host, req->data); 1351 dma_async_issue_pending(chan); 1352 } 1353 1354 /* 1355 * Configure block length for MMC/SD cards and initiate the transfer. 1356 */ 1357 static int 1358 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1359 { 1360 int ret; 1361 unsigned long long timeout; 1362 1363 host->data = req->data; 1364 1365 if (req->data == NULL) { 1366 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1367 if (req->cmd->flags & MMC_RSP_BUSY) { 1368 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 1369 1370 /* 1371 * Set an arbitrary 100ms data timeout for commands with 1372 * busy signal and no indication of busy_timeout. 1373 */ 1374 if (!timeout) 1375 timeout = 100000000U; 1376 1377 set_data_timeout(host, timeout, 0); 1378 } 1379 return 0; 1380 } 1381 1382 if (host->use_dma) { 1383 ret = omap_hsmmc_setup_dma_transfer(host, req); 1384 if (ret != 0) { 1385 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1386 return ret; 1387 } 1388 } 1389 return 0; 1390 } 1391 1392 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1393 int err) 1394 { 1395 struct omap_hsmmc_host *host = mmc_priv(mmc); 1396 struct mmc_data *data = mrq->data; 1397 1398 if (host->use_dma && data->host_cookie) { 1399 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1400 1401 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1402 mmc_get_dma_dir(data)); 1403 data->host_cookie = 0; 1404 } 1405 } 1406 1407 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1408 { 1409 struct omap_hsmmc_host *host = mmc_priv(mmc); 1410 1411 if (mrq->data->host_cookie) { 1412 mrq->data->host_cookie = 0; 1413 return ; 1414 } 1415 1416 if (host->use_dma) { 1417 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1418 1419 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1420 &host->next_data, c)) 1421 mrq->data->host_cookie = 0; 1422 } 1423 } 1424 1425 /* 1426 * Request function. for read/write operation 1427 */ 1428 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1429 { 1430 struct omap_hsmmc_host *host = mmc_priv(mmc); 1431 int err; 1432 1433 BUG_ON(host->req_in_progress); 1434 BUG_ON(host->dma_ch != -1); 1435 if (host->reqs_blocked) 1436 host->reqs_blocked = 0; 1437 WARN_ON(host->mrq != NULL); 1438 host->mrq = req; 1439 host->clk_rate = clk_get_rate(host->fclk); 1440 err = omap_hsmmc_prepare_data(host, req); 1441 if (err) { 1442 req->cmd->error = err; 1443 if (req->data) 1444 req->data->error = err; 1445 host->mrq = NULL; 1446 mmc_request_done(mmc, req); 1447 return; 1448 } 1449 if (req->sbc && !(host->flags & AUTO_CMD23)) { 1450 omap_hsmmc_start_command(host, req->sbc, NULL); 1451 return; 1452 } 1453 1454 omap_hsmmc_start_dma_transfer(host); 1455 omap_hsmmc_start_command(host, req->cmd, req->data); 1456 } 1457 1458 /* Routine to configure clock values. Exposed API to core */ 1459 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1460 { 1461 struct omap_hsmmc_host *host = mmc_priv(mmc); 1462 int do_send_init_stream = 0; 1463 1464 if (ios->power_mode != host->power_mode) { 1465 switch (ios->power_mode) { 1466 case MMC_POWER_OFF: 1467 omap_hsmmc_set_power(host, 0); 1468 break; 1469 case MMC_POWER_UP: 1470 omap_hsmmc_set_power(host, 1); 1471 break; 1472 case MMC_POWER_ON: 1473 do_send_init_stream = 1; 1474 break; 1475 } 1476 host->power_mode = ios->power_mode; 1477 } 1478 1479 /* FIXME: set registers based only on changes to ios */ 1480 1481 omap_hsmmc_set_bus_width(host); 1482 1483 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1484 /* Only MMC1 can interface at 3V without some flavor 1485 * of external transceiver; but they all handle 1.8V. 1486 */ 1487 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1488 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1489 /* 1490 * The mmc_select_voltage fn of the core does 1491 * not seem to set the power_mode to 1492 * MMC_POWER_UP upon recalculating the voltage. 1493 * vdd 1.8v. 1494 */ 1495 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1496 dev_dbg(mmc_dev(host->mmc), 1497 "Switch operation failed\n"); 1498 } 1499 } 1500 1501 omap_hsmmc_set_clock(host); 1502 1503 if (do_send_init_stream) 1504 send_init_stream(host); 1505 1506 omap_hsmmc_set_bus_mode(host); 1507 } 1508 1509 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1510 { 1511 struct omap_hsmmc_host *host = mmc_priv(mmc); 1512 1513 if (mmc_pdata(host)->init_card) 1514 mmc_pdata(host)->init_card(card); 1515 } 1516 1517 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1518 { 1519 struct omap_hsmmc_host *host = mmc_priv(mmc); 1520 u32 irq_mask, con; 1521 unsigned long flags; 1522 1523 spin_lock_irqsave(&host->irq_lock, flags); 1524 1525 con = OMAP_HSMMC_READ(host->base, CON); 1526 irq_mask = OMAP_HSMMC_READ(host->base, ISE); 1527 if (enable) { 1528 host->flags |= HSMMC_SDIO_IRQ_ENABLED; 1529 irq_mask |= CIRQ_EN; 1530 con |= CTPL | CLKEXTFREE; 1531 } else { 1532 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 1533 irq_mask &= ~CIRQ_EN; 1534 con &= ~(CTPL | CLKEXTFREE); 1535 } 1536 OMAP_HSMMC_WRITE(host->base, CON, con); 1537 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 1538 1539 /* 1540 * if enable, piggy back detection on current request 1541 * but always disable immediately 1542 */ 1543 if (!host->req_in_progress || !enable) 1544 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 1545 1546 /* flush posted write */ 1547 OMAP_HSMMC_READ(host->base, IE); 1548 1549 spin_unlock_irqrestore(&host->irq_lock, flags); 1550 } 1551 1552 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 1553 { 1554 int ret; 1555 1556 /* 1557 * For omaps with wake-up path, wakeirq will be irq from pinctrl and 1558 * for other omaps, wakeirq will be from GPIO (dat line remuxed to 1559 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 1560 * with functional clock disabled. 1561 */ 1562 if (!host->dev->of_node || !host->wake_irq) 1563 return -ENODEV; 1564 1565 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 1566 if (ret) { 1567 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 1568 goto err; 1569 } 1570 1571 /* 1572 * Some omaps don't have wake-up path from deeper idle states 1573 * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 1574 */ 1575 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1576 struct pinctrl *p = devm_pinctrl_get(host->dev); 1577 if (IS_ERR(p)) { 1578 ret = PTR_ERR(p); 1579 goto err_free_irq; 1580 } 1581 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1582 dev_info(host->dev, "missing default pinctrl state\n"); 1583 devm_pinctrl_put(p); 1584 ret = -EINVAL; 1585 goto err_free_irq; 1586 } 1587 1588 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1589 dev_info(host->dev, "missing idle pinctrl state\n"); 1590 devm_pinctrl_put(p); 1591 ret = -EINVAL; 1592 goto err_free_irq; 1593 } 1594 devm_pinctrl_put(p); 1595 } 1596 1597 OMAP_HSMMC_WRITE(host->base, HCTL, 1598 OMAP_HSMMC_READ(host->base, HCTL) | IWE); 1599 return 0; 1600 1601 err_free_irq: 1602 dev_pm_clear_wake_irq(host->dev); 1603 err: 1604 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 1605 host->wake_irq = 0; 1606 return ret; 1607 } 1608 1609 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1610 { 1611 u32 hctl, capa, value; 1612 1613 /* Only MMC1 supports 3.0V */ 1614 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1615 hctl = SDVS30; 1616 capa = VS30 | VS18; 1617 } else { 1618 hctl = SDVS18; 1619 capa = VS18; 1620 } 1621 1622 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1623 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1624 1625 value = OMAP_HSMMC_READ(host->base, CAPA); 1626 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1627 1628 /* Set SD bus power bit */ 1629 set_sd_bus_power(host); 1630 } 1631 1632 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1633 unsigned int direction, int blk_size) 1634 { 1635 /* This controller can't do multiblock reads due to hw bugs */ 1636 if (direction == MMC_DATA_READ) 1637 return 1; 1638 1639 return blk_size; 1640 } 1641 1642 static struct mmc_host_ops omap_hsmmc_ops = { 1643 .post_req = omap_hsmmc_post_req, 1644 .pre_req = omap_hsmmc_pre_req, 1645 .request = omap_hsmmc_request, 1646 .set_ios = omap_hsmmc_set_ios, 1647 .get_cd = mmc_gpio_get_cd, 1648 .get_ro = mmc_gpio_get_ro, 1649 .init_card = omap_hsmmc_init_card, 1650 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1651 }; 1652 1653 #ifdef CONFIG_DEBUG_FS 1654 1655 static int mmc_regs_show(struct seq_file *s, void *data) 1656 { 1657 struct mmc_host *mmc = s->private; 1658 struct omap_hsmmc_host *host = mmc_priv(mmc); 1659 1660 seq_printf(s, "mmc%d:\n", mmc->index); 1661 seq_printf(s, "sdio irq mode\t%s\n", 1662 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1663 1664 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1665 seq_printf(s, "sdio irq \t%s\n", 1666 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1667 : "disabled"); 1668 } 1669 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 1670 1671 pm_runtime_get_sync(host->dev); 1672 seq_puts(s, "\nregs:\n"); 1673 seq_printf(s, "CON:\t\t0x%08x\n", 1674 OMAP_HSMMC_READ(host->base, CON)); 1675 seq_printf(s, "PSTATE:\t\t0x%08x\n", 1676 OMAP_HSMMC_READ(host->base, PSTATE)); 1677 seq_printf(s, "HCTL:\t\t0x%08x\n", 1678 OMAP_HSMMC_READ(host->base, HCTL)); 1679 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1680 OMAP_HSMMC_READ(host->base, SYSCTL)); 1681 seq_printf(s, "IE:\t\t0x%08x\n", 1682 OMAP_HSMMC_READ(host->base, IE)); 1683 seq_printf(s, "ISE:\t\t0x%08x\n", 1684 OMAP_HSMMC_READ(host->base, ISE)); 1685 seq_printf(s, "CAPA:\t\t0x%08x\n", 1686 OMAP_HSMMC_READ(host->base, CAPA)); 1687 1688 pm_runtime_mark_last_busy(host->dev); 1689 pm_runtime_put_autosuspend(host->dev); 1690 1691 return 0; 1692 } 1693 1694 DEFINE_SHOW_ATTRIBUTE(mmc_regs); 1695 1696 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1697 { 1698 if (mmc->debugfs_root) 1699 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1700 mmc, &mmc_regs_fops); 1701 } 1702 1703 #else 1704 1705 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1706 { 1707 } 1708 1709 #endif 1710 1711 #ifdef CONFIG_OF 1712 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 1713 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1714 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1715 }; 1716 1717 static const struct omap_mmc_of_data omap4_mmc_of_data = { 1718 .reg_offset = 0x100, 1719 }; 1720 static const struct omap_mmc_of_data am33xx_mmc_of_data = { 1721 .reg_offset = 0x100, 1722 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 1723 }; 1724 1725 static const struct of_device_id omap_mmc_of_match[] = { 1726 { 1727 .compatible = "ti,omap2-hsmmc", 1728 }, 1729 { 1730 .compatible = "ti,omap3-pre-es3-hsmmc", 1731 .data = &omap3_pre_es3_mmc_of_data, 1732 }, 1733 { 1734 .compatible = "ti,omap3-hsmmc", 1735 }, 1736 { 1737 .compatible = "ti,omap4-hsmmc", 1738 .data = &omap4_mmc_of_data, 1739 }, 1740 { 1741 .compatible = "ti,am33xx-hsmmc", 1742 .data = &am33xx_mmc_of_data, 1743 }, 1744 {}, 1745 }; 1746 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1747 1748 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1749 { 1750 struct omap_hsmmc_platform_data *pdata, *legacy; 1751 struct device_node *np = dev->of_node; 1752 1753 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1754 if (!pdata) 1755 return ERR_PTR(-ENOMEM); /* out of memory */ 1756 1757 legacy = dev_get_platdata(dev); 1758 if (legacy && legacy->name) 1759 pdata->name = legacy->name; 1760 1761 if (of_find_property(np, "ti,dual-volt", NULL)) 1762 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1763 1764 if (of_find_property(np, "ti,non-removable", NULL)) { 1765 pdata->nonremovable = true; 1766 pdata->no_regulator_off_init = true; 1767 } 1768 1769 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1770 pdata->features |= HSMMC_HAS_UPDATED_RESET; 1771 1772 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1773 pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1774 1775 return pdata; 1776 } 1777 #else 1778 static inline struct omap_hsmmc_platform_data 1779 *of_get_hsmmc_pdata(struct device *dev) 1780 { 1781 return ERR_PTR(-EINVAL); 1782 } 1783 #endif 1784 1785 static int omap_hsmmc_probe(struct platform_device *pdev) 1786 { 1787 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1788 struct mmc_host *mmc; 1789 struct omap_hsmmc_host *host = NULL; 1790 struct resource *res; 1791 int ret, irq; 1792 const struct of_device_id *match; 1793 const struct omap_mmc_of_data *data; 1794 void __iomem *base; 1795 1796 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1797 if (match) { 1798 pdata = of_get_hsmmc_pdata(&pdev->dev); 1799 1800 if (IS_ERR(pdata)) 1801 return PTR_ERR(pdata); 1802 1803 if (match->data) { 1804 data = match->data; 1805 pdata->reg_offset = data->reg_offset; 1806 pdata->controller_flags |= data->controller_flags; 1807 } 1808 } 1809 1810 if (pdata == NULL) { 1811 dev_err(&pdev->dev, "Platform Data is missing\n"); 1812 return -ENXIO; 1813 } 1814 1815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1816 irq = platform_get_irq(pdev, 0); 1817 if (res == NULL || irq < 0) 1818 return -ENXIO; 1819 1820 base = devm_ioremap_resource(&pdev->dev, res); 1821 if (IS_ERR(base)) 1822 return PTR_ERR(base); 1823 1824 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1825 if (!mmc) { 1826 ret = -ENOMEM; 1827 goto err; 1828 } 1829 1830 ret = mmc_of_parse(mmc); 1831 if (ret) 1832 goto err1; 1833 1834 host = mmc_priv(mmc); 1835 host->mmc = mmc; 1836 host->pdata = pdata; 1837 host->dev = &pdev->dev; 1838 host->use_dma = 1; 1839 host->dma_ch = -1; 1840 host->irq = irq; 1841 host->mapbase = res->start + pdata->reg_offset; 1842 host->base = base + pdata->reg_offset; 1843 host->power_mode = MMC_POWER_OFF; 1844 host->next_data.cookie = 1; 1845 host->pbias_enabled = 0; 1846 host->vqmmc_enabled = 0; 1847 1848 platform_set_drvdata(pdev, host); 1849 1850 if (pdev->dev.of_node) 1851 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1852 1853 mmc->ops = &omap_hsmmc_ops; 1854 1855 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1856 1857 if (pdata->max_freq > 0) 1858 mmc->f_max = pdata->max_freq; 1859 else if (mmc->f_max == 0) 1860 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1861 1862 spin_lock_init(&host->irq_lock); 1863 1864 host->fclk = devm_clk_get(&pdev->dev, "fck"); 1865 if (IS_ERR(host->fclk)) { 1866 ret = PTR_ERR(host->fclk); 1867 host->fclk = NULL; 1868 goto err1; 1869 } 1870 1871 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1872 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1873 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 1874 } 1875 1876 device_init_wakeup(&pdev->dev, true); 1877 pm_runtime_enable(host->dev); 1878 pm_runtime_get_sync(host->dev); 1879 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1880 pm_runtime_use_autosuspend(host->dev); 1881 1882 omap_hsmmc_context_save(host); 1883 1884 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 1885 /* 1886 * MMC can still work without debounce clock. 1887 */ 1888 if (IS_ERR(host->dbclk)) { 1889 host->dbclk = NULL; 1890 } else if (clk_prepare_enable(host->dbclk) != 0) { 1891 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1892 host->dbclk = NULL; 1893 } 1894 1895 /* Set this to a value that allows allocating an entire descriptor 1896 * list within a page (zero order allocation). */ 1897 mmc->max_segs = 64; 1898 1899 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1900 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1901 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1902 1903 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1904 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; 1905 1906 mmc->caps |= mmc_pdata(host)->caps; 1907 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1908 mmc->caps |= MMC_CAP_4_BIT_DATA; 1909 1910 if (mmc_pdata(host)->nonremovable) 1911 mmc->caps |= MMC_CAP_NONREMOVABLE; 1912 1913 mmc->pm_caps |= mmc_pdata(host)->pm_caps; 1914 1915 omap_hsmmc_conf_bus_power(host); 1916 1917 host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 1918 if (IS_ERR(host->rx_chan)) { 1919 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 1920 ret = PTR_ERR(host->rx_chan); 1921 goto err_irq; 1922 } 1923 1924 host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 1925 if (IS_ERR(host->tx_chan)) { 1926 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 1927 ret = PTR_ERR(host->tx_chan); 1928 goto err_irq; 1929 } 1930 1931 /* 1932 * Limit the maximum segment size to the lower of the request size 1933 * and the DMA engine device segment size limits. In reality, with 1934 * 32-bit transfers, the DMA engine can do longer segments than this 1935 * but there is no way to represent that in the DMA model - if we 1936 * increase this figure here, we get warnings from the DMA API debug. 1937 */ 1938 mmc->max_seg_size = min3(mmc->max_req_size, 1939 dma_get_max_seg_size(host->rx_chan->device->dev), 1940 dma_get_max_seg_size(host->tx_chan->device->dev)); 1941 1942 /* Request IRQ for MMC operations */ 1943 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 1944 mmc_hostname(mmc), host); 1945 if (ret) { 1946 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1947 goto err_irq; 1948 } 1949 1950 ret = omap_hsmmc_reg_get(host); 1951 if (ret) 1952 goto err_irq; 1953 1954 if (!mmc->ocr_avail) 1955 mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 1956 1957 omap_hsmmc_disable_irq(host); 1958 1959 /* 1960 * For now, only support SDIO interrupt if we have a separate 1961 * wake-up interrupt configured from device tree. This is because 1962 * the wake-up interrupt is needed for idle state and some 1963 * platforms need special quirks. And we don't want to add new 1964 * legacy mux platform init code callbacks any longer as we 1965 * are moving to DT based booting anyways. 1966 */ 1967 ret = omap_hsmmc_configure_wake_irq(host); 1968 if (!ret) 1969 mmc->caps |= MMC_CAP_SDIO_IRQ; 1970 1971 mmc_add_host(mmc); 1972 1973 if (mmc_pdata(host)->name != NULL) { 1974 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1975 if (ret < 0) 1976 goto err_slot_name; 1977 } 1978 1979 omap_hsmmc_debugfs(mmc); 1980 pm_runtime_mark_last_busy(host->dev); 1981 pm_runtime_put_autosuspend(host->dev); 1982 1983 return 0; 1984 1985 err_slot_name: 1986 mmc_remove_host(mmc); 1987 err_irq: 1988 device_init_wakeup(&pdev->dev, false); 1989 if (!IS_ERR_OR_NULL(host->tx_chan)) 1990 dma_release_channel(host->tx_chan); 1991 if (!IS_ERR_OR_NULL(host->rx_chan)) 1992 dma_release_channel(host->rx_chan); 1993 pm_runtime_dont_use_autosuspend(host->dev); 1994 pm_runtime_put_sync(host->dev); 1995 pm_runtime_disable(host->dev); 1996 if (host->dbclk) 1997 clk_disable_unprepare(host->dbclk); 1998 err1: 1999 mmc_free_host(mmc); 2000 err: 2001 return ret; 2002 } 2003 2004 static int omap_hsmmc_remove(struct platform_device *pdev) 2005 { 2006 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2007 2008 pm_runtime_get_sync(host->dev); 2009 mmc_remove_host(host->mmc); 2010 2011 dma_release_channel(host->tx_chan); 2012 dma_release_channel(host->rx_chan); 2013 2014 dev_pm_clear_wake_irq(host->dev); 2015 pm_runtime_dont_use_autosuspend(host->dev); 2016 pm_runtime_put_sync(host->dev); 2017 pm_runtime_disable(host->dev); 2018 device_init_wakeup(&pdev->dev, false); 2019 if (host->dbclk) 2020 clk_disable_unprepare(host->dbclk); 2021 2022 mmc_free_host(host->mmc); 2023 2024 return 0; 2025 } 2026 2027 #ifdef CONFIG_PM_SLEEP 2028 static int omap_hsmmc_suspend(struct device *dev) 2029 { 2030 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2031 2032 if (!host) 2033 return 0; 2034 2035 pm_runtime_get_sync(host->dev); 2036 2037 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2038 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2039 OMAP_HSMMC_WRITE(host->base, IE, 0); 2040 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2041 OMAP_HSMMC_WRITE(host->base, HCTL, 2042 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2043 } 2044 2045 if (host->dbclk) 2046 clk_disable_unprepare(host->dbclk); 2047 2048 pm_runtime_put_sync(host->dev); 2049 return 0; 2050 } 2051 2052 /* Routine to resume the MMC device */ 2053 static int omap_hsmmc_resume(struct device *dev) 2054 { 2055 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2056 2057 if (!host) 2058 return 0; 2059 2060 pm_runtime_get_sync(host->dev); 2061 2062 if (host->dbclk) 2063 clk_prepare_enable(host->dbclk); 2064 2065 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2066 omap_hsmmc_conf_bus_power(host); 2067 2068 pm_runtime_mark_last_busy(host->dev); 2069 pm_runtime_put_autosuspend(host->dev); 2070 return 0; 2071 } 2072 #endif 2073 2074 static int omap_hsmmc_runtime_suspend(struct device *dev) 2075 { 2076 struct omap_hsmmc_host *host; 2077 unsigned long flags; 2078 int ret = 0; 2079 2080 host = dev_get_drvdata(dev); 2081 omap_hsmmc_context_save(host); 2082 dev_dbg(dev, "disabled\n"); 2083 2084 spin_lock_irqsave(&host->irq_lock, flags); 2085 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2086 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2087 /* disable sdio irq handling to prevent race */ 2088 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2089 OMAP_HSMMC_WRITE(host->base, IE, 0); 2090 2091 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2092 /* 2093 * dat1 line low, pending sdio irq 2094 * race condition: possible irq handler running on 2095 * multi-core, abort 2096 */ 2097 dev_dbg(dev, "pending sdio irq, abort suspend\n"); 2098 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2099 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2100 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2101 pm_runtime_mark_last_busy(dev); 2102 ret = -EBUSY; 2103 goto abort; 2104 } 2105 2106 pinctrl_pm_select_idle_state(dev); 2107 } else { 2108 pinctrl_pm_select_idle_state(dev); 2109 } 2110 2111 abort: 2112 spin_unlock_irqrestore(&host->irq_lock, flags); 2113 return ret; 2114 } 2115 2116 static int omap_hsmmc_runtime_resume(struct device *dev) 2117 { 2118 struct omap_hsmmc_host *host; 2119 unsigned long flags; 2120 2121 host = dev_get_drvdata(dev); 2122 omap_hsmmc_context_restore(host); 2123 dev_dbg(dev, "enabled\n"); 2124 2125 spin_lock_irqsave(&host->irq_lock, flags); 2126 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2127 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2128 2129 pinctrl_pm_select_default_state(host->dev); 2130 2131 /* irq lost, if pinmux incorrect */ 2132 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2133 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2134 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2135 } else { 2136 pinctrl_pm_select_default_state(host->dev); 2137 } 2138 spin_unlock_irqrestore(&host->irq_lock, flags); 2139 return 0; 2140 } 2141 2142 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2143 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2144 .runtime_suspend = omap_hsmmc_runtime_suspend, 2145 .runtime_resume = omap_hsmmc_runtime_resume, 2146 }; 2147 2148 static struct platform_driver omap_hsmmc_driver = { 2149 .probe = omap_hsmmc_probe, 2150 .remove = omap_hsmmc_remove, 2151 .driver = { 2152 .name = DRIVER_NAME, 2153 .pm = &omap_hsmmc_dev_pm_ops, 2154 .of_match_table = of_match_ptr(omap_mmc_of_match), 2155 }, 2156 }; 2157 2158 module_platform_driver(omap_hsmmc_driver); 2159 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2160 MODULE_LICENSE("GPL"); 2161 MODULE_ALIAS("platform:" DRIVER_NAME); 2162 MODULE_AUTHOR("Texas Instruments Inc"); 2163