xref: /openbmc/linux/drivers/mmc/host/omap_hsmmc.c (revision b6dcefde)
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *	Syed Mohammed Khasim	<x0khasim@ti.com>
10  *	Madhusudhan		<madhu.cr@ti.com>
11  *	Mohit Jalori		<mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17 
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/io.h>
32 #include <linux/semaphore.h>
33 #include <plat/dma.h>
34 #include <mach/hardware.h>
35 #include <plat/board.h>
36 #include <plat/mmc.h>
37 #include <plat/cpu.h>
38 
39 /* OMAP HSMMC Host Controller Registers */
40 #define OMAP_HSMMC_SYSCONFIG	0x0010
41 #define OMAP_HSMMC_SYSSTATUS	0x0014
42 #define OMAP_HSMMC_CON		0x002C
43 #define OMAP_HSMMC_BLK		0x0104
44 #define OMAP_HSMMC_ARG		0x0108
45 #define OMAP_HSMMC_CMD		0x010C
46 #define OMAP_HSMMC_RSP10	0x0110
47 #define OMAP_HSMMC_RSP32	0x0114
48 #define OMAP_HSMMC_RSP54	0x0118
49 #define OMAP_HSMMC_RSP76	0x011C
50 #define OMAP_HSMMC_DATA		0x0120
51 #define OMAP_HSMMC_HCTL		0x0128
52 #define OMAP_HSMMC_SYSCTL	0x012C
53 #define OMAP_HSMMC_STAT		0x0130
54 #define OMAP_HSMMC_IE		0x0134
55 #define OMAP_HSMMC_ISE		0x0138
56 #define OMAP_HSMMC_CAPA		0x0140
57 
58 #define VS18			(1 << 26)
59 #define VS30			(1 << 25)
60 #define SDVS18			(0x5 << 9)
61 #define SDVS30			(0x6 << 9)
62 #define SDVS33			(0x7 << 9)
63 #define SDVS_MASK		0x00000E00
64 #define SDVSCLR			0xFFFFF1FF
65 #define SDVSDET			0x00000400
66 #define AUTOIDLE		0x1
67 #define SDBP			(1 << 8)
68 #define DTO			0xe
69 #define ICE			0x1
70 #define ICS			0x2
71 #define CEN			(1 << 2)
72 #define CLKD_MASK		0x0000FFC0
73 #define CLKD_SHIFT		6
74 #define DTO_MASK		0x000F0000
75 #define DTO_SHIFT		16
76 #define INT_EN_MASK		0x307F0033
77 #define BWR_ENABLE		(1 << 4)
78 #define BRR_ENABLE		(1 << 5)
79 #define INIT_STREAM		(1 << 1)
80 #define DP_SELECT		(1 << 21)
81 #define DDIR			(1 << 4)
82 #define DMA_EN			0x1
83 #define MSBS			(1 << 5)
84 #define BCE			(1 << 1)
85 #define FOUR_BIT		(1 << 1)
86 #define DW8			(1 << 5)
87 #define CC			0x1
88 #define TC			0x02
89 #define OD			0x1
90 #define ERR			(1 << 15)
91 #define CMD_TIMEOUT		(1 << 16)
92 #define DATA_TIMEOUT		(1 << 20)
93 #define CMD_CRC			(1 << 17)
94 #define DATA_CRC		(1 << 21)
95 #define CARD_ERR		(1 << 28)
96 #define STAT_CLEAR		0xFFFFFFFF
97 #define INIT_STREAM_CMD		0x00000000
98 #define DUAL_VOLT_OCR_BIT	7
99 #define SRC			(1 << 25)
100 #define SRD			(1 << 26)
101 #define SOFTRESET		(1 << 1)
102 #define RESETDONE		(1 << 0)
103 
104 /*
105  * FIXME: Most likely all the data using these _DEVID defines should come
106  * from the platform_data, or implemented in controller and slot specific
107  * functions.
108  */
109 #define OMAP_MMC1_DEVID		0
110 #define OMAP_MMC2_DEVID		1
111 #define OMAP_MMC3_DEVID		2
112 #define OMAP_MMC4_DEVID		3
113 #define OMAP_MMC5_DEVID		4
114 
115 #define MMC_TIMEOUT_MS		20
116 #define OMAP_MMC_MASTER_CLOCK	96000000
117 #define DRIVER_NAME		"mmci-omap-hs"
118 
119 /* Timeouts for entering power saving states on inactivity, msec */
120 #define OMAP_MMC_DISABLED_TIMEOUT	100
121 #define OMAP_MMC_SLEEP_TIMEOUT		1000
122 #define OMAP_MMC_OFF_TIMEOUT		8000
123 
124 /*
125  * One controller can have multiple slots, like on some omap boards using
126  * omap.c controller driver. Luckily this is not currently done on any known
127  * omap_hsmmc.c device.
128  */
129 #define mmc_slot(host)		(host->pdata->slots[host->slot_id])
130 
131 /*
132  * MMC Host controller read/write API's
133  */
134 #define OMAP_HSMMC_READ(base, reg)	\
135 	__raw_readl((base) + OMAP_HSMMC_##reg)
136 
137 #define OMAP_HSMMC_WRITE(base, reg, val) \
138 	__raw_writel((val), (base) + OMAP_HSMMC_##reg)
139 
140 struct omap_hsmmc_host {
141 	struct	device		*dev;
142 	struct	mmc_host	*mmc;
143 	struct	mmc_request	*mrq;
144 	struct	mmc_command	*cmd;
145 	struct	mmc_data	*data;
146 	struct	clk		*fclk;
147 	struct	clk		*iclk;
148 	struct	clk		*dbclk;
149 	struct	semaphore	sem;
150 	struct	work_struct	mmc_carddetect_work;
151 	void	__iomem		*base;
152 	resource_size_t		mapbase;
153 	spinlock_t		irq_lock; /* Prevent races with irq handler */
154 	unsigned long		flags;
155 	unsigned int		id;
156 	unsigned int		dma_len;
157 	unsigned int		dma_sg_idx;
158 	unsigned char		bus_mode;
159 	unsigned char		power_mode;
160 	u32			*buffer;
161 	u32			bytesleft;
162 	int			suspended;
163 	int			irq;
164 	int			use_dma, dma_ch;
165 	int			dma_line_tx, dma_line_rx;
166 	int			slot_id;
167 	int			got_dbclk;
168 	int			response_busy;
169 	int			context_loss;
170 	int			dpm_state;
171 	int			vdd;
172 	int			protect_card;
173 	int			reqs_blocked;
174 
175 	struct	omap_mmc_platform_data	*pdata;
176 };
177 
178 /*
179  * Stop clock to the card
180  */
181 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
182 {
183 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
184 		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
185 	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
186 		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
187 }
188 
189 #ifdef CONFIG_PM
190 
191 /*
192  * Restore the MMC host context, if it was lost as result of a
193  * power state change.
194  */
195 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
196 {
197 	struct mmc_ios *ios = &host->mmc->ios;
198 	struct omap_mmc_platform_data *pdata = host->pdata;
199 	int context_loss = 0;
200 	u32 hctl, capa, con;
201 	u16 dsor = 0;
202 	unsigned long timeout;
203 
204 	if (pdata->get_context_loss_count) {
205 		context_loss = pdata->get_context_loss_count(host->dev);
206 		if (context_loss < 0)
207 			return 1;
208 	}
209 
210 	dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
211 		context_loss == host->context_loss ? "not " : "");
212 	if (host->context_loss == context_loss)
213 		return 1;
214 
215 	/* Wait for hardware reset */
216 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
217 	while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
218 		&& time_before(jiffies, timeout))
219 		;
220 
221 	/* Do software reset */
222 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
223 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
224 	while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
225 		&& time_before(jiffies, timeout))
226 		;
227 
228 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
229 			OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
230 
231 	if (host->id == OMAP_MMC1_DEVID) {
232 		if (host->power_mode != MMC_POWER_OFF &&
233 		    (1 << ios->vdd) <= MMC_VDD_23_24)
234 			hctl = SDVS18;
235 		else
236 			hctl = SDVS30;
237 		capa = VS30 | VS18;
238 	} else {
239 		hctl = SDVS18;
240 		capa = VS18;
241 	}
242 
243 	OMAP_HSMMC_WRITE(host->base, HCTL,
244 			OMAP_HSMMC_READ(host->base, HCTL) | hctl);
245 
246 	OMAP_HSMMC_WRITE(host->base, CAPA,
247 			OMAP_HSMMC_READ(host->base, CAPA) | capa);
248 
249 	OMAP_HSMMC_WRITE(host->base, HCTL,
250 			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
251 
252 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
253 	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
254 		&& time_before(jiffies, timeout))
255 		;
256 
257 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
258 	OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
259 	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
260 
261 	/* Do not initialize card-specific things if the power is off */
262 	if (host->power_mode == MMC_POWER_OFF)
263 		goto out;
264 
265 	con = OMAP_HSMMC_READ(host->base, CON);
266 	switch (ios->bus_width) {
267 	case MMC_BUS_WIDTH_8:
268 		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
269 		break;
270 	case MMC_BUS_WIDTH_4:
271 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
272 		OMAP_HSMMC_WRITE(host->base, HCTL,
273 			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
274 		break;
275 	case MMC_BUS_WIDTH_1:
276 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
277 		OMAP_HSMMC_WRITE(host->base, HCTL,
278 			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
279 		break;
280 	}
281 
282 	if (ios->clock) {
283 		dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
284 		if (dsor < 1)
285 			dsor = 1;
286 
287 		if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
288 			dsor++;
289 
290 		if (dsor > 250)
291 			dsor = 250;
292 	}
293 
294 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
295 		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
296 	OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
297 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
298 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
299 
300 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
301 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
302 		&& time_before(jiffies, timeout))
303 		;
304 
305 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
306 		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
307 
308 	con = OMAP_HSMMC_READ(host->base, CON);
309 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
310 		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
311 	else
312 		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
313 out:
314 	host->context_loss = context_loss;
315 
316 	dev_dbg(mmc_dev(host->mmc), "context is restored\n");
317 	return 0;
318 }
319 
320 /*
321  * Save the MMC host context (store the number of power state changes so far).
322  */
323 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
324 {
325 	struct omap_mmc_platform_data *pdata = host->pdata;
326 	int context_loss;
327 
328 	if (pdata->get_context_loss_count) {
329 		context_loss = pdata->get_context_loss_count(host->dev);
330 		if (context_loss < 0)
331 			return;
332 		host->context_loss = context_loss;
333 	}
334 }
335 
336 #else
337 
338 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
339 {
340 	return 0;
341 }
342 
343 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
344 {
345 }
346 
347 #endif
348 
349 /*
350  * Send init stream sequence to card
351  * before sending IDLE command
352  */
353 static void send_init_stream(struct omap_hsmmc_host *host)
354 {
355 	int reg = 0;
356 	unsigned long timeout;
357 
358 	if (host->protect_card)
359 		return;
360 
361 	disable_irq(host->irq);
362 	OMAP_HSMMC_WRITE(host->base, CON,
363 		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
364 	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
365 
366 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
367 	while ((reg != CC) && time_before(jiffies, timeout))
368 		reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
369 
370 	OMAP_HSMMC_WRITE(host->base, CON,
371 		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
372 
373 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
374 	OMAP_HSMMC_READ(host->base, STAT);
375 
376 	enable_irq(host->irq);
377 }
378 
379 static inline
380 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
381 {
382 	int r = 1;
383 
384 	if (mmc_slot(host).get_cover_state)
385 		r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
386 	return r;
387 }
388 
389 static ssize_t
390 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
391 			   char *buf)
392 {
393 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
394 	struct omap_hsmmc_host *host = mmc_priv(mmc);
395 
396 	return sprintf(buf, "%s\n",
397 			omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
398 }
399 
400 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
401 
402 static ssize_t
403 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
404 			char *buf)
405 {
406 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
407 	struct omap_hsmmc_host *host = mmc_priv(mmc);
408 
409 	return sprintf(buf, "%s\n", mmc_slot(host).name);
410 }
411 
412 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
413 
414 /*
415  * Configure the response type and send the cmd.
416  */
417 static void
418 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
419 	struct mmc_data *data)
420 {
421 	int cmdreg = 0, resptype = 0, cmdtype = 0;
422 
423 	dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
424 		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
425 	host->cmd = cmd;
426 
427 	/*
428 	 * Clear status bits and enable interrupts
429 	 */
430 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
431 	OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
432 
433 	if (host->use_dma)
434 		OMAP_HSMMC_WRITE(host->base, IE,
435 				 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
436 	else
437 		OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
438 
439 	host->response_busy = 0;
440 	if (cmd->flags & MMC_RSP_PRESENT) {
441 		if (cmd->flags & MMC_RSP_136)
442 			resptype = 1;
443 		else if (cmd->flags & MMC_RSP_BUSY) {
444 			resptype = 3;
445 			host->response_busy = 1;
446 		} else
447 			resptype = 2;
448 	}
449 
450 	/*
451 	 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
452 	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
453 	 * a val of 0x3, rest 0x0.
454 	 */
455 	if (cmd == host->mrq->stop)
456 		cmdtype = 0x3;
457 
458 	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
459 
460 	if (data) {
461 		cmdreg |= DP_SELECT | MSBS | BCE;
462 		if (data->flags & MMC_DATA_READ)
463 			cmdreg |= DDIR;
464 		else
465 			cmdreg &= ~(DDIR);
466 	}
467 
468 	if (host->use_dma)
469 		cmdreg |= DMA_EN;
470 
471 	/*
472 	 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
473 	 * by the interrupt handler, otherwise (i.e. for a new request) it is
474 	 * unlocked here.
475 	 */
476 	if (!in_interrupt())
477 		spin_unlock_irqrestore(&host->irq_lock, host->flags);
478 
479 	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
480 	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
481 }
482 
483 static int
484 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
485 {
486 	if (data->flags & MMC_DATA_WRITE)
487 		return DMA_TO_DEVICE;
488 	else
489 		return DMA_FROM_DEVICE;
490 }
491 
492 /*
493  * Notify the transfer complete to MMC core
494  */
495 static void
496 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
497 {
498 	if (!data) {
499 		struct mmc_request *mrq = host->mrq;
500 
501 		/* TC before CC from CMD6 - don't know why, but it happens */
502 		if (host->cmd && host->cmd->opcode == 6 &&
503 		    host->response_busy) {
504 			host->response_busy = 0;
505 			return;
506 		}
507 
508 		host->mrq = NULL;
509 		mmc_request_done(host->mmc, mrq);
510 		return;
511 	}
512 
513 	host->data = NULL;
514 
515 	if (host->use_dma && host->dma_ch != -1)
516 		dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
517 			omap_hsmmc_get_dma_dir(host, data));
518 
519 	if (!data->error)
520 		data->bytes_xfered += data->blocks * (data->blksz);
521 	else
522 		data->bytes_xfered = 0;
523 
524 	if (!data->stop) {
525 		host->mrq = NULL;
526 		mmc_request_done(host->mmc, data->mrq);
527 		return;
528 	}
529 	omap_hsmmc_start_command(host, data->stop, NULL);
530 }
531 
532 /*
533  * Notify the core about command completion
534  */
535 static void
536 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
537 {
538 	host->cmd = NULL;
539 
540 	if (cmd->flags & MMC_RSP_PRESENT) {
541 		if (cmd->flags & MMC_RSP_136) {
542 			/* response type 2 */
543 			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
544 			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
545 			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
546 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
547 		} else {
548 			/* response types 1, 1b, 3, 4, 5, 6 */
549 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
550 		}
551 	}
552 	if ((host->data == NULL && !host->response_busy) || cmd->error) {
553 		host->mrq = NULL;
554 		mmc_request_done(host->mmc, cmd->mrq);
555 	}
556 }
557 
558 /*
559  * DMA clean up for command errors
560  */
561 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
562 {
563 	host->data->error = errno;
564 
565 	if (host->use_dma && host->dma_ch != -1) {
566 		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
567 			omap_hsmmc_get_dma_dir(host, host->data));
568 		omap_free_dma(host->dma_ch);
569 		host->dma_ch = -1;
570 		up(&host->sem);
571 	}
572 	host->data = NULL;
573 }
574 
575 /*
576  * Readable error output
577  */
578 #ifdef CONFIG_MMC_DEBUG
579 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
580 {
581 	/* --- means reserved bit without definition at documentation */
582 	static const char *omap_hsmmc_status_bits[] = {
583 		"CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
584 		"OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
585 		"CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
586 		"---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
587 	};
588 	char res[256];
589 	char *buf = res;
590 	int len, i;
591 
592 	len = sprintf(buf, "MMC IRQ 0x%x :", status);
593 	buf += len;
594 
595 	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
596 		if (status & (1 << i)) {
597 			len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
598 			buf += len;
599 		}
600 
601 	dev_dbg(mmc_dev(host->mmc), "%s\n", res);
602 }
603 #endif  /* CONFIG_MMC_DEBUG */
604 
605 /*
606  * MMC controller internal state machines reset
607  *
608  * Used to reset command or data internal state machines, using respectively
609  *  SRC or SRD bit of SYSCTL register
610  * Can be called from interrupt context
611  */
612 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
613 						   unsigned long bit)
614 {
615 	unsigned long i = 0;
616 	unsigned long limit = (loops_per_jiffy *
617 				msecs_to_jiffies(MMC_TIMEOUT_MS));
618 
619 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
620 			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
621 
622 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
623 		(i++ < limit))
624 		cpu_relax();
625 
626 	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
627 		dev_err(mmc_dev(host->mmc),
628 			"Timeout waiting on controller reset in %s\n",
629 			__func__);
630 }
631 
632 /*
633  * MMC controller IRQ handler
634  */
635 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
636 {
637 	struct omap_hsmmc_host *host = dev_id;
638 	struct mmc_data *data;
639 	int end_cmd = 0, end_trans = 0, status;
640 
641 	spin_lock(&host->irq_lock);
642 
643 	if (host->mrq == NULL) {
644 		OMAP_HSMMC_WRITE(host->base, STAT,
645 			OMAP_HSMMC_READ(host->base, STAT));
646 		/* Flush posted write */
647 		OMAP_HSMMC_READ(host->base, STAT);
648 		spin_unlock(&host->irq_lock);
649 		return IRQ_HANDLED;
650 	}
651 
652 	data = host->data;
653 	status = OMAP_HSMMC_READ(host->base, STAT);
654 	dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
655 
656 	if (status & ERR) {
657 #ifdef CONFIG_MMC_DEBUG
658 		omap_hsmmc_report_irq(host, status);
659 #endif
660 		if ((status & CMD_TIMEOUT) ||
661 			(status & CMD_CRC)) {
662 			if (host->cmd) {
663 				if (status & CMD_TIMEOUT) {
664 					omap_hsmmc_reset_controller_fsm(host,
665 									SRC);
666 					host->cmd->error = -ETIMEDOUT;
667 				} else {
668 					host->cmd->error = -EILSEQ;
669 				}
670 				end_cmd = 1;
671 			}
672 			if (host->data || host->response_busy) {
673 				if (host->data)
674 					omap_hsmmc_dma_cleanup(host,
675 								-ETIMEDOUT);
676 				host->response_busy = 0;
677 				omap_hsmmc_reset_controller_fsm(host, SRD);
678 			}
679 		}
680 		if ((status & DATA_TIMEOUT) ||
681 			(status & DATA_CRC)) {
682 			if (host->data || host->response_busy) {
683 				int err = (status & DATA_TIMEOUT) ?
684 						-ETIMEDOUT : -EILSEQ;
685 
686 				if (host->data)
687 					omap_hsmmc_dma_cleanup(host, err);
688 				else
689 					host->mrq->cmd->error = err;
690 				host->response_busy = 0;
691 				omap_hsmmc_reset_controller_fsm(host, SRD);
692 				end_trans = 1;
693 			}
694 		}
695 		if (status & CARD_ERR) {
696 			dev_dbg(mmc_dev(host->mmc),
697 				"Ignoring card err CMD%d\n", host->cmd->opcode);
698 			if (host->cmd)
699 				end_cmd = 1;
700 			if (host->data)
701 				end_trans = 1;
702 		}
703 	}
704 
705 	OMAP_HSMMC_WRITE(host->base, STAT, status);
706 	/* Flush posted write */
707 	OMAP_HSMMC_READ(host->base, STAT);
708 
709 	if (end_cmd || ((status & CC) && host->cmd))
710 		omap_hsmmc_cmd_done(host, host->cmd);
711 	if ((end_trans || (status & TC)) && host->mrq)
712 		omap_hsmmc_xfer_done(host, data);
713 
714 	spin_unlock(&host->irq_lock);
715 
716 	return IRQ_HANDLED;
717 }
718 
719 static void set_sd_bus_power(struct omap_hsmmc_host *host)
720 {
721 	unsigned long i;
722 
723 	OMAP_HSMMC_WRITE(host->base, HCTL,
724 			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
725 	for (i = 0; i < loops_per_jiffy; i++) {
726 		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
727 			break;
728 		cpu_relax();
729 	}
730 }
731 
732 /*
733  * Switch MMC interface voltage ... only relevant for MMC1.
734  *
735  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
736  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
737  * Some chips, like eMMC ones, use internal transceivers.
738  */
739 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
740 {
741 	u32 reg_val = 0;
742 	int ret;
743 
744 	/* Disable the clocks */
745 	clk_disable(host->fclk);
746 	clk_disable(host->iclk);
747 	if (host->got_dbclk)
748 		clk_disable(host->dbclk);
749 
750 	/* Turn the power off */
751 	ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
752 
753 	/* Turn the power ON with given VDD 1.8 or 3.0v */
754 	if (!ret)
755 		ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
756 					       vdd);
757 	clk_enable(host->iclk);
758 	clk_enable(host->fclk);
759 	if (host->got_dbclk)
760 		clk_enable(host->dbclk);
761 
762 	if (ret != 0)
763 		goto err;
764 
765 	OMAP_HSMMC_WRITE(host->base, HCTL,
766 		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
767 	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
768 
769 	/*
770 	 * If a MMC dual voltage card is detected, the set_ios fn calls
771 	 * this fn with VDD bit set for 1.8V. Upon card removal from the
772 	 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
773 	 *
774 	 * Cope with a bit of slop in the range ... per data sheets:
775 	 *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
776 	 *    but recommended values are 1.71V to 1.89V
777 	 *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
778 	 *    but recommended values are 2.7V to 3.3V
779 	 *
780 	 * Board setup code shouldn't permit anything very out-of-range.
781 	 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
782 	 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
783 	 */
784 	if ((1 << vdd) <= MMC_VDD_23_24)
785 		reg_val |= SDVS18;
786 	else
787 		reg_val |= SDVS30;
788 
789 	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
790 	set_sd_bus_power(host);
791 
792 	return 0;
793 err:
794 	dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
795 	return ret;
796 }
797 
798 /* Protect the card while the cover is open */
799 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
800 {
801 	if (!mmc_slot(host).get_cover_state)
802 		return;
803 
804 	host->reqs_blocked = 0;
805 	if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
806 		if (host->protect_card) {
807 			printk(KERN_INFO "%s: cover is closed, "
808 					 "card is now accessible\n",
809 					 mmc_hostname(host->mmc));
810 			host->protect_card = 0;
811 		}
812 	} else {
813 		if (!host->protect_card) {
814 			printk(KERN_INFO "%s: cover is open, "
815 					 "card is now inaccessible\n",
816 					 mmc_hostname(host->mmc));
817 			host->protect_card = 1;
818 		}
819 	}
820 }
821 
822 /*
823  * Work Item to notify the core about card insertion/removal
824  */
825 static void omap_hsmmc_detect(struct work_struct *work)
826 {
827 	struct omap_hsmmc_host *host =
828 		container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
829 	struct omap_mmc_slot_data *slot = &mmc_slot(host);
830 	int carddetect;
831 
832 	if (host->suspended)
833 		return;
834 
835 	sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
836 
837 	if (slot->card_detect)
838 		carddetect = slot->card_detect(slot->card_detect_irq);
839 	else {
840 		omap_hsmmc_protect_card(host);
841 		carddetect = -ENOSYS;
842 	}
843 
844 	if (carddetect) {
845 		mmc_detect_change(host->mmc, (HZ * 200) / 1000);
846 	} else {
847 		mmc_host_enable(host->mmc);
848 		omap_hsmmc_reset_controller_fsm(host, SRD);
849 		mmc_host_lazy_disable(host->mmc);
850 
851 		mmc_detect_change(host->mmc, (HZ * 50) / 1000);
852 	}
853 }
854 
855 /*
856  * ISR for handling card insertion and removal
857  */
858 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
859 {
860 	struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
861 
862 	if (host->suspended)
863 		return IRQ_HANDLED;
864 	schedule_work(&host->mmc_carddetect_work);
865 
866 	return IRQ_HANDLED;
867 }
868 
869 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
870 				     struct mmc_data *data)
871 {
872 	int sync_dev;
873 
874 	if (data->flags & MMC_DATA_WRITE)
875 		sync_dev = host->dma_line_tx;
876 	else
877 		sync_dev = host->dma_line_rx;
878 	return sync_dev;
879 }
880 
881 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
882 				       struct mmc_data *data,
883 				       struct scatterlist *sgl)
884 {
885 	int blksz, nblk, dma_ch;
886 
887 	dma_ch = host->dma_ch;
888 	if (data->flags & MMC_DATA_WRITE) {
889 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
890 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
891 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
892 			sg_dma_address(sgl), 0, 0);
893 	} else {
894 		omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
895 			(host->mapbase + OMAP_HSMMC_DATA), 0, 0);
896 		omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
897 			sg_dma_address(sgl), 0, 0);
898 	}
899 
900 	blksz = host->data->blksz;
901 	nblk = sg_dma_len(sgl) / blksz;
902 
903 	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
904 			blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
905 			omap_hsmmc_get_dma_sync_dev(host, data),
906 			!(data->flags & MMC_DATA_WRITE));
907 
908 	omap_start_dma(dma_ch);
909 }
910 
911 /*
912  * DMA call back function
913  */
914 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
915 {
916 	struct omap_hsmmc_host *host = data;
917 
918 	if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
919 		dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
920 
921 	if (host->dma_ch < 0)
922 		return;
923 
924 	host->dma_sg_idx++;
925 	if (host->dma_sg_idx < host->dma_len) {
926 		/* Fire up the next transfer. */
927 		omap_hsmmc_config_dma_params(host, host->data,
928 					   host->data->sg + host->dma_sg_idx);
929 		return;
930 	}
931 
932 	omap_free_dma(host->dma_ch);
933 	host->dma_ch = -1;
934 	/*
935 	 * DMA Callback: run in interrupt context.
936 	 * mutex_unlock will throw a kernel warning if used.
937 	 */
938 	up(&host->sem);
939 }
940 
941 /*
942  * Routine to configure and start DMA for the MMC card
943  */
944 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
945 					struct mmc_request *req)
946 {
947 	int dma_ch = 0, ret = 0, err = 1, i;
948 	struct mmc_data *data = req->data;
949 
950 	/* Sanity check: all the SG entries must be aligned by block size. */
951 	for (i = 0; i < data->sg_len; i++) {
952 		struct scatterlist *sgl;
953 
954 		sgl = data->sg + i;
955 		if (sgl->length % data->blksz)
956 			return -EINVAL;
957 	}
958 	if ((data->blksz % 4) != 0)
959 		/* REVISIT: The MMC buffer increments only when MSB is written.
960 		 * Return error for blksz which is non multiple of four.
961 		 */
962 		return -EINVAL;
963 
964 	/*
965 	 * If for some reason the DMA transfer is still active,
966 	 * we wait for timeout period and free the dma
967 	 */
968 	if (host->dma_ch != -1) {
969 		set_current_state(TASK_UNINTERRUPTIBLE);
970 		schedule_timeout(100);
971 		if (down_trylock(&host->sem)) {
972 			omap_free_dma(host->dma_ch);
973 			host->dma_ch = -1;
974 			up(&host->sem);
975 			return err;
976 		}
977 	} else {
978 		if (down_trylock(&host->sem))
979 			return err;
980 	}
981 
982 	ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
983 			       "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
984 	if (ret != 0) {
985 		dev_err(mmc_dev(host->mmc),
986 			"%s: omap_request_dma() failed with %d\n",
987 			mmc_hostname(host->mmc), ret);
988 		return ret;
989 	}
990 
991 	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
992 			data->sg_len, omap_hsmmc_get_dma_dir(host, data));
993 	host->dma_ch = dma_ch;
994 	host->dma_sg_idx = 0;
995 
996 	omap_hsmmc_config_dma_params(host, data, data->sg);
997 
998 	return 0;
999 }
1000 
1001 static void set_data_timeout(struct omap_hsmmc_host *host,
1002 			     unsigned int timeout_ns,
1003 			     unsigned int timeout_clks)
1004 {
1005 	unsigned int timeout, cycle_ns;
1006 	uint32_t reg, clkd, dto = 0;
1007 
1008 	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1009 	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1010 	if (clkd == 0)
1011 		clkd = 1;
1012 
1013 	cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1014 	timeout = timeout_ns / cycle_ns;
1015 	timeout += timeout_clks;
1016 	if (timeout) {
1017 		while ((timeout & 0x80000000) == 0) {
1018 			dto += 1;
1019 			timeout <<= 1;
1020 		}
1021 		dto = 31 - dto;
1022 		timeout <<= 1;
1023 		if (timeout && dto)
1024 			dto += 1;
1025 		if (dto >= 13)
1026 			dto -= 13;
1027 		else
1028 			dto = 0;
1029 		if (dto > 14)
1030 			dto = 14;
1031 	}
1032 
1033 	reg &= ~DTO_MASK;
1034 	reg |= dto << DTO_SHIFT;
1035 	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1036 }
1037 
1038 /*
1039  * Configure block length for MMC/SD cards and initiate the transfer.
1040  */
1041 static int
1042 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1043 {
1044 	int ret;
1045 	host->data = req->data;
1046 
1047 	if (req->data == NULL) {
1048 		OMAP_HSMMC_WRITE(host->base, BLK, 0);
1049 		/*
1050 		 * Set an arbitrary 100ms data timeout for commands with
1051 		 * busy signal.
1052 		 */
1053 		if (req->cmd->flags & MMC_RSP_BUSY)
1054 			set_data_timeout(host, 100000000U, 0);
1055 		return 0;
1056 	}
1057 
1058 	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1059 					| (req->data->blocks << 16));
1060 	set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1061 
1062 	if (host->use_dma) {
1063 		ret = omap_hsmmc_start_dma_transfer(host, req);
1064 		if (ret != 0) {
1065 			dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1066 			return ret;
1067 		}
1068 	}
1069 	return 0;
1070 }
1071 
1072 /*
1073  * Request function. for read/write operation
1074  */
1075 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1076 {
1077 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1078 	int err;
1079 
1080 	/*
1081 	 * Prevent races with the interrupt handler because of unexpected
1082 	 * interrupts, but not if we are already in interrupt context i.e.
1083 	 * retries.
1084 	 */
1085 	if (!in_interrupt()) {
1086 		spin_lock_irqsave(&host->irq_lock, host->flags);
1087 		/*
1088 		 * Protect the card from I/O if there is a possibility
1089 		 * it can be removed.
1090 		 */
1091 		if (host->protect_card) {
1092 			if (host->reqs_blocked < 3) {
1093 				/*
1094 				 * Ensure the controller is left in a consistent
1095 				 * state by resetting the command and data state
1096 				 * machines.
1097 				 */
1098 				omap_hsmmc_reset_controller_fsm(host, SRD);
1099 				omap_hsmmc_reset_controller_fsm(host, SRC);
1100 				host->reqs_blocked += 1;
1101 			}
1102 			req->cmd->error = -EBADF;
1103 			if (req->data)
1104 				req->data->error = -EBADF;
1105 			spin_unlock_irqrestore(&host->irq_lock, host->flags);
1106 			mmc_request_done(mmc, req);
1107 			return;
1108 		} else if (host->reqs_blocked)
1109 			host->reqs_blocked = 0;
1110 	}
1111 	WARN_ON(host->mrq != NULL);
1112 	host->mrq = req;
1113 	err = omap_hsmmc_prepare_data(host, req);
1114 	if (err) {
1115 		req->cmd->error = err;
1116 		if (req->data)
1117 			req->data->error = err;
1118 		host->mrq = NULL;
1119 		if (!in_interrupt())
1120 			spin_unlock_irqrestore(&host->irq_lock, host->flags);
1121 		mmc_request_done(mmc, req);
1122 		return;
1123 	}
1124 
1125 	omap_hsmmc_start_command(host, req->cmd, req->data);
1126 }
1127 
1128 /* Routine to configure clock values. Exposed API to core */
1129 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1130 {
1131 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1132 	u16 dsor = 0;
1133 	unsigned long regval;
1134 	unsigned long timeout;
1135 	u32 con;
1136 	int do_send_init_stream = 0;
1137 
1138 	mmc_host_enable(host->mmc);
1139 
1140 	if (ios->power_mode != host->power_mode) {
1141 		switch (ios->power_mode) {
1142 		case MMC_POWER_OFF:
1143 			mmc_slot(host).set_power(host->dev, host->slot_id,
1144 						 0, 0);
1145 			host->vdd = 0;
1146 			break;
1147 		case MMC_POWER_UP:
1148 			mmc_slot(host).set_power(host->dev, host->slot_id,
1149 						 1, ios->vdd);
1150 			host->vdd = ios->vdd;
1151 			break;
1152 		case MMC_POWER_ON:
1153 			do_send_init_stream = 1;
1154 			break;
1155 		}
1156 		host->power_mode = ios->power_mode;
1157 	}
1158 
1159 	/* FIXME: set registers based only on changes to ios */
1160 
1161 	con = OMAP_HSMMC_READ(host->base, CON);
1162 	switch (mmc->ios.bus_width) {
1163 	case MMC_BUS_WIDTH_8:
1164 		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1165 		break;
1166 	case MMC_BUS_WIDTH_4:
1167 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1168 		OMAP_HSMMC_WRITE(host->base, HCTL,
1169 			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1170 		break;
1171 	case MMC_BUS_WIDTH_1:
1172 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1173 		OMAP_HSMMC_WRITE(host->base, HCTL,
1174 			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1175 		break;
1176 	}
1177 
1178 	if (host->id == OMAP_MMC1_DEVID) {
1179 		/* Only MMC1 can interface at 3V without some flavor
1180 		 * of external transceiver; but they all handle 1.8V.
1181 		 */
1182 		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1183 			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
1184 				/*
1185 				 * The mmc_select_voltage fn of the core does
1186 				 * not seem to set the power_mode to
1187 				 * MMC_POWER_UP upon recalculating the voltage.
1188 				 * vdd 1.8v.
1189 				 */
1190 			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1191 				dev_dbg(mmc_dev(host->mmc),
1192 						"Switch operation failed\n");
1193 		}
1194 	}
1195 
1196 	if (ios->clock) {
1197 		dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1198 		if (dsor < 1)
1199 			dsor = 1;
1200 
1201 		if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1202 			dsor++;
1203 
1204 		if (dsor > 250)
1205 			dsor = 250;
1206 	}
1207 	omap_hsmmc_stop_clock(host);
1208 	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1209 	regval = regval & ~(CLKD_MASK);
1210 	regval = regval | (dsor << 6) | (DTO << 16);
1211 	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1212 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
1213 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1214 
1215 	/* Wait till the ICS bit is set */
1216 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1217 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1218 		&& time_before(jiffies, timeout))
1219 		msleep(1);
1220 
1221 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
1222 		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1223 
1224 	if (do_send_init_stream)
1225 		send_init_stream(host);
1226 
1227 	con = OMAP_HSMMC_READ(host->base, CON);
1228 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1229 		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1230 	else
1231 		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1232 
1233 	if (host->power_mode == MMC_POWER_OFF)
1234 		mmc_host_disable(host->mmc);
1235 	else
1236 		mmc_host_lazy_disable(host->mmc);
1237 }
1238 
1239 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1240 {
1241 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1242 
1243 	if (!mmc_slot(host).card_detect)
1244 		return -ENOSYS;
1245 	return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
1246 }
1247 
1248 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1249 {
1250 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1251 
1252 	if (!mmc_slot(host).get_ro)
1253 		return -ENOSYS;
1254 	return mmc_slot(host).get_ro(host->dev, 0);
1255 }
1256 
1257 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1258 {
1259 	u32 hctl, capa, value;
1260 
1261 	/* Only MMC1 supports 3.0V */
1262 	if (host->id == OMAP_MMC1_DEVID) {
1263 		hctl = SDVS30;
1264 		capa = VS30 | VS18;
1265 	} else {
1266 		hctl = SDVS18;
1267 		capa = VS18;
1268 	}
1269 
1270 	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1271 	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1272 
1273 	value = OMAP_HSMMC_READ(host->base, CAPA);
1274 	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1275 
1276 	/* Set the controller to AUTO IDLE mode */
1277 	value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1278 	OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1279 
1280 	/* Set SD bus power bit */
1281 	set_sd_bus_power(host);
1282 }
1283 
1284 /*
1285  * Dynamic power saving handling, FSM:
1286  *   ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1287  *     ^___________|          |                      |
1288  *     |______________________|______________________|
1289  *
1290  * ENABLED:   mmc host is fully functional
1291  * DISABLED:  fclk is off
1292  * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1293  * REGSLEEP:  fclk is off, voltage regulator is asleep
1294  * OFF:       fclk is off, voltage regulator is off
1295  *
1296  * Transition handlers return the timeout for the next state transition
1297  * or negative error.
1298  */
1299 
1300 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1301 
1302 /* Handler for [ENABLED -> DISABLED] transition */
1303 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1304 {
1305 	omap_hsmmc_context_save(host);
1306 	clk_disable(host->fclk);
1307 	host->dpm_state = DISABLED;
1308 
1309 	dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1310 
1311 	if (host->power_mode == MMC_POWER_OFF)
1312 		return 0;
1313 
1314 	return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1315 }
1316 
1317 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1318 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1319 {
1320 	int err, new_state;
1321 
1322 	if (!mmc_try_claim_host(host->mmc))
1323 		return 0;
1324 
1325 	clk_enable(host->fclk);
1326 	omap_hsmmc_context_restore(host);
1327 	if (mmc_card_can_sleep(host->mmc)) {
1328 		err = mmc_card_sleep(host->mmc);
1329 		if (err < 0) {
1330 			clk_disable(host->fclk);
1331 			mmc_release_host(host->mmc);
1332 			return err;
1333 		}
1334 		new_state = CARDSLEEP;
1335 	} else {
1336 		new_state = REGSLEEP;
1337 	}
1338 	if (mmc_slot(host).set_sleep)
1339 		mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1340 					 new_state == CARDSLEEP);
1341 	/* FIXME: turn off bus power and perhaps interrupts too */
1342 	clk_disable(host->fclk);
1343 	host->dpm_state = new_state;
1344 
1345 	mmc_release_host(host->mmc);
1346 
1347 	dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1348 		host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1349 
1350 	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1351 	    mmc_slot(host).card_detect ||
1352 	    (mmc_slot(host).get_cover_state &&
1353 	     mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1354 		return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1355 
1356 	return 0;
1357 }
1358 
1359 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1360 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1361 {
1362 	if (!mmc_try_claim_host(host->mmc))
1363 		return 0;
1364 
1365 	if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1366 	      mmc_slot(host).card_detect ||
1367 	      (mmc_slot(host).get_cover_state &&
1368 	       mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1369 		mmc_release_host(host->mmc);
1370 		return 0;
1371 	}
1372 
1373 	mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1374 	host->vdd = 0;
1375 	host->power_mode = MMC_POWER_OFF;
1376 
1377 	dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1378 		host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1379 
1380 	host->dpm_state = OFF;
1381 
1382 	mmc_release_host(host->mmc);
1383 
1384 	return 0;
1385 }
1386 
1387 /* Handler for [DISABLED -> ENABLED] transition */
1388 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1389 {
1390 	int err;
1391 
1392 	err = clk_enable(host->fclk);
1393 	if (err < 0)
1394 		return err;
1395 
1396 	omap_hsmmc_context_restore(host);
1397 	host->dpm_state = ENABLED;
1398 
1399 	dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1400 
1401 	return 0;
1402 }
1403 
1404 /* Handler for [SLEEP -> ENABLED] transition */
1405 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1406 {
1407 	if (!mmc_try_claim_host(host->mmc))
1408 		return 0;
1409 
1410 	clk_enable(host->fclk);
1411 	omap_hsmmc_context_restore(host);
1412 	if (mmc_slot(host).set_sleep)
1413 		mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1414 			 host->vdd, host->dpm_state == CARDSLEEP);
1415 	if (mmc_card_can_sleep(host->mmc))
1416 		mmc_card_awake(host->mmc);
1417 
1418 	dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1419 		host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1420 
1421 	host->dpm_state = ENABLED;
1422 
1423 	mmc_release_host(host->mmc);
1424 
1425 	return 0;
1426 }
1427 
1428 /* Handler for [OFF -> ENABLED] transition */
1429 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1430 {
1431 	clk_enable(host->fclk);
1432 
1433 	omap_hsmmc_context_restore(host);
1434 	omap_hsmmc_conf_bus_power(host);
1435 	mmc_power_restore_host(host->mmc);
1436 
1437 	host->dpm_state = ENABLED;
1438 
1439 	dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1440 
1441 	return 0;
1442 }
1443 
1444 /*
1445  * Bring MMC host to ENABLED from any other PM state.
1446  */
1447 static int omap_hsmmc_enable(struct mmc_host *mmc)
1448 {
1449 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1450 
1451 	switch (host->dpm_state) {
1452 	case DISABLED:
1453 		return omap_hsmmc_disabled_to_enabled(host);
1454 	case CARDSLEEP:
1455 	case REGSLEEP:
1456 		return omap_hsmmc_sleep_to_enabled(host);
1457 	case OFF:
1458 		return omap_hsmmc_off_to_enabled(host);
1459 	default:
1460 		dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1461 		return -EINVAL;
1462 	}
1463 }
1464 
1465 /*
1466  * Bring MMC host in PM state (one level deeper).
1467  */
1468 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1469 {
1470 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1471 
1472 	switch (host->dpm_state) {
1473 	case ENABLED: {
1474 		int delay;
1475 
1476 		delay = omap_hsmmc_enabled_to_disabled(host);
1477 		if (lazy || delay < 0)
1478 			return delay;
1479 		return 0;
1480 	}
1481 	case DISABLED:
1482 		return omap_hsmmc_disabled_to_sleep(host);
1483 	case CARDSLEEP:
1484 	case REGSLEEP:
1485 		return omap_hsmmc_sleep_to_off(host);
1486 	default:
1487 		dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1488 		return -EINVAL;
1489 	}
1490 }
1491 
1492 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1493 {
1494 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1495 	int err;
1496 
1497 	err = clk_enable(host->fclk);
1498 	if (err)
1499 		return err;
1500 	dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1501 	omap_hsmmc_context_restore(host);
1502 	return 0;
1503 }
1504 
1505 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1506 {
1507 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1508 
1509 	omap_hsmmc_context_save(host);
1510 	clk_disable(host->fclk);
1511 	dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1512 	return 0;
1513 }
1514 
1515 static const struct mmc_host_ops omap_hsmmc_ops = {
1516 	.enable = omap_hsmmc_enable_fclk,
1517 	.disable = omap_hsmmc_disable_fclk,
1518 	.request = omap_hsmmc_request,
1519 	.set_ios = omap_hsmmc_set_ios,
1520 	.get_cd = omap_hsmmc_get_cd,
1521 	.get_ro = omap_hsmmc_get_ro,
1522 	/* NYET -- enable_sdio_irq */
1523 };
1524 
1525 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1526 	.enable = omap_hsmmc_enable,
1527 	.disable = omap_hsmmc_disable,
1528 	.request = omap_hsmmc_request,
1529 	.set_ios = omap_hsmmc_set_ios,
1530 	.get_cd = omap_hsmmc_get_cd,
1531 	.get_ro = omap_hsmmc_get_ro,
1532 	/* NYET -- enable_sdio_irq */
1533 };
1534 
1535 #ifdef CONFIG_DEBUG_FS
1536 
1537 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1538 {
1539 	struct mmc_host *mmc = s->private;
1540 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1541 	int context_loss = 0;
1542 
1543 	if (host->pdata->get_context_loss_count)
1544 		context_loss = host->pdata->get_context_loss_count(host->dev);
1545 
1546 	seq_printf(s, "mmc%d:\n"
1547 			" enabled:\t%d\n"
1548 			" dpm_state:\t%d\n"
1549 			" nesting_cnt:\t%d\n"
1550 			" ctx_loss:\t%d:%d\n"
1551 			"\nregs:\n",
1552 			mmc->index, mmc->enabled ? 1 : 0,
1553 			host->dpm_state, mmc->nesting_cnt,
1554 			host->context_loss, context_loss);
1555 
1556 	if (host->suspended || host->dpm_state == OFF) {
1557 		seq_printf(s, "host suspended, can't read registers\n");
1558 		return 0;
1559 	}
1560 
1561 	if (clk_enable(host->fclk) != 0) {
1562 		seq_printf(s, "can't read the regs\n");
1563 		return 0;
1564 	}
1565 
1566 	seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1567 			OMAP_HSMMC_READ(host->base, SYSCONFIG));
1568 	seq_printf(s, "CON:\t\t0x%08x\n",
1569 			OMAP_HSMMC_READ(host->base, CON));
1570 	seq_printf(s, "HCTL:\t\t0x%08x\n",
1571 			OMAP_HSMMC_READ(host->base, HCTL));
1572 	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1573 			OMAP_HSMMC_READ(host->base, SYSCTL));
1574 	seq_printf(s, "IE:\t\t0x%08x\n",
1575 			OMAP_HSMMC_READ(host->base, IE));
1576 	seq_printf(s, "ISE:\t\t0x%08x\n",
1577 			OMAP_HSMMC_READ(host->base, ISE));
1578 	seq_printf(s, "CAPA:\t\t0x%08x\n",
1579 			OMAP_HSMMC_READ(host->base, CAPA));
1580 
1581 	clk_disable(host->fclk);
1582 
1583 	return 0;
1584 }
1585 
1586 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1587 {
1588 	return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1589 }
1590 
1591 static const struct file_operations mmc_regs_fops = {
1592 	.open           = omap_hsmmc_regs_open,
1593 	.read           = seq_read,
1594 	.llseek         = seq_lseek,
1595 	.release        = single_release,
1596 };
1597 
1598 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1599 {
1600 	if (mmc->debugfs_root)
1601 		debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1602 			mmc, &mmc_regs_fops);
1603 }
1604 
1605 #else
1606 
1607 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1608 {
1609 }
1610 
1611 #endif
1612 
1613 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1614 {
1615 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1616 	struct mmc_host *mmc;
1617 	struct omap_hsmmc_host *host = NULL;
1618 	struct resource *res;
1619 	int ret = 0, irq;
1620 
1621 	if (pdata == NULL) {
1622 		dev_err(&pdev->dev, "Platform Data is missing\n");
1623 		return -ENXIO;
1624 	}
1625 
1626 	if (pdata->nr_slots == 0) {
1627 		dev_err(&pdev->dev, "No Slots\n");
1628 		return -ENXIO;
1629 	}
1630 
1631 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1632 	irq = platform_get_irq(pdev, 0);
1633 	if (res == NULL || irq < 0)
1634 		return -ENXIO;
1635 
1636 	res = request_mem_region(res->start, res->end - res->start + 1,
1637 							pdev->name);
1638 	if (res == NULL)
1639 		return -EBUSY;
1640 
1641 	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1642 	if (!mmc) {
1643 		ret = -ENOMEM;
1644 		goto err;
1645 	}
1646 
1647 	host		= mmc_priv(mmc);
1648 	host->mmc	= mmc;
1649 	host->pdata	= pdata;
1650 	host->dev	= &pdev->dev;
1651 	host->use_dma	= 1;
1652 	host->dev->dma_mask = &pdata->dma_mask;
1653 	host->dma_ch	= -1;
1654 	host->irq	= irq;
1655 	host->id	= pdev->id;
1656 	host->slot_id	= 0;
1657 	host->mapbase	= res->start;
1658 	host->base	= ioremap(host->mapbase, SZ_4K);
1659 	host->power_mode = -1;
1660 
1661 	platform_set_drvdata(pdev, host);
1662 	INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1663 
1664 	if (mmc_slot(host).power_saving)
1665 		mmc->ops	= &omap_hsmmc_ps_ops;
1666 	else
1667 		mmc->ops	= &omap_hsmmc_ops;
1668 
1669 	mmc->f_min	= 400000;
1670 	mmc->f_max	= 52000000;
1671 
1672 	sema_init(&host->sem, 1);
1673 	spin_lock_init(&host->irq_lock);
1674 
1675 	host->iclk = clk_get(&pdev->dev, "ick");
1676 	if (IS_ERR(host->iclk)) {
1677 		ret = PTR_ERR(host->iclk);
1678 		host->iclk = NULL;
1679 		goto err1;
1680 	}
1681 	host->fclk = clk_get(&pdev->dev, "fck");
1682 	if (IS_ERR(host->fclk)) {
1683 		ret = PTR_ERR(host->fclk);
1684 		host->fclk = NULL;
1685 		clk_put(host->iclk);
1686 		goto err1;
1687 	}
1688 
1689 	omap_hsmmc_context_save(host);
1690 
1691 	mmc->caps |= MMC_CAP_DISABLE;
1692 	mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1693 	/* we start off in DISABLED state */
1694 	host->dpm_state = DISABLED;
1695 
1696 	if (mmc_host_enable(host->mmc) != 0) {
1697 		clk_put(host->iclk);
1698 		clk_put(host->fclk);
1699 		goto err1;
1700 	}
1701 
1702 	if (clk_enable(host->iclk) != 0) {
1703 		mmc_host_disable(host->mmc);
1704 		clk_put(host->iclk);
1705 		clk_put(host->fclk);
1706 		goto err1;
1707 	}
1708 
1709 	if (cpu_is_omap2430()) {
1710 		host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1711 		/*
1712 		 * MMC can still work without debounce clock.
1713 		 */
1714 		if (IS_ERR(host->dbclk))
1715 			dev_warn(mmc_dev(host->mmc),
1716 				"Failed to get debounce clock\n");
1717 		else
1718 			host->got_dbclk = 1;
1719 
1720 		if (host->got_dbclk)
1721 			if (clk_enable(host->dbclk) != 0)
1722 				dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1723 							" clk failed\n");
1724 	}
1725 
1726 	/* Since we do only SG emulation, we can have as many segs
1727 	 * as we want. */
1728 	mmc->max_phys_segs = 1024;
1729 	mmc->max_hw_segs = 1024;
1730 
1731 	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1732 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1733 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1734 	mmc->max_seg_size = mmc->max_req_size;
1735 
1736 	mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1737 		     MMC_CAP_WAIT_WHILE_BUSY;
1738 
1739 	if (mmc_slot(host).wires >= 8)
1740 		mmc->caps |= MMC_CAP_8_BIT_DATA;
1741 	else if (mmc_slot(host).wires >= 4)
1742 		mmc->caps |= MMC_CAP_4_BIT_DATA;
1743 
1744 	if (mmc_slot(host).nonremovable)
1745 		mmc->caps |= MMC_CAP_NONREMOVABLE;
1746 
1747 	omap_hsmmc_conf_bus_power(host);
1748 
1749 	/* Select DMA lines */
1750 	switch (host->id) {
1751 	case OMAP_MMC1_DEVID:
1752 		host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1753 		host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1754 		break;
1755 	case OMAP_MMC2_DEVID:
1756 		host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1757 		host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1758 		break;
1759 	case OMAP_MMC3_DEVID:
1760 		host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1761 		host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1762 		break;
1763 	case OMAP_MMC4_DEVID:
1764 		host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
1765 		host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
1766 		break;
1767 	case OMAP_MMC5_DEVID:
1768 		host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
1769 		host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
1770 		break;
1771 	default:
1772 		dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1773 		goto err_irq;
1774 	}
1775 
1776 	/* Request IRQ for MMC operations */
1777 	ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
1778 			mmc_hostname(mmc), host);
1779 	if (ret) {
1780 		dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1781 		goto err_irq;
1782 	}
1783 
1784 	/* initialize power supplies, gpios, etc */
1785 	if (pdata->init != NULL) {
1786 		if (pdata->init(&pdev->dev) != 0) {
1787 			dev_dbg(mmc_dev(host->mmc),
1788 				"Unable to configure MMC IRQs\n");
1789 			goto err_irq_cd_init;
1790 		}
1791 	}
1792 	mmc->ocr_avail = mmc_slot(host).ocr_mask;
1793 
1794 	/* Request IRQ for card detect */
1795 	if ((mmc_slot(host).card_detect_irq)) {
1796 		ret = request_irq(mmc_slot(host).card_detect_irq,
1797 				  omap_hsmmc_cd_handler,
1798 				  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1799 					  | IRQF_DISABLED,
1800 				  mmc_hostname(mmc), host);
1801 		if (ret) {
1802 			dev_dbg(mmc_dev(host->mmc),
1803 				"Unable to grab MMC CD IRQ\n");
1804 			goto err_irq_cd;
1805 		}
1806 	}
1807 
1808 	OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1809 	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1810 
1811 	mmc_host_lazy_disable(host->mmc);
1812 
1813 	omap_hsmmc_protect_card(host);
1814 
1815 	mmc_add_host(mmc);
1816 
1817 	if (mmc_slot(host).name != NULL) {
1818 		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1819 		if (ret < 0)
1820 			goto err_slot_name;
1821 	}
1822 	if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1823 		ret = device_create_file(&mmc->class_dev,
1824 					&dev_attr_cover_switch);
1825 		if (ret < 0)
1826 			goto err_cover_switch;
1827 	}
1828 
1829 	omap_hsmmc_debugfs(mmc);
1830 
1831 	return 0;
1832 
1833 err_cover_switch:
1834 	device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1835 err_slot_name:
1836 	mmc_remove_host(mmc);
1837 err_irq_cd:
1838 	free_irq(mmc_slot(host).card_detect_irq, host);
1839 err_irq_cd_init:
1840 	free_irq(host->irq, host);
1841 err_irq:
1842 	mmc_host_disable(host->mmc);
1843 	clk_disable(host->iclk);
1844 	clk_put(host->fclk);
1845 	clk_put(host->iclk);
1846 	if (host->got_dbclk) {
1847 		clk_disable(host->dbclk);
1848 		clk_put(host->dbclk);
1849 	}
1850 
1851 err1:
1852 	iounmap(host->base);
1853 err:
1854 	dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1855 	release_mem_region(res->start, res->end - res->start + 1);
1856 	if (host)
1857 		mmc_free_host(mmc);
1858 	return ret;
1859 }
1860 
1861 static int omap_hsmmc_remove(struct platform_device *pdev)
1862 {
1863 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1864 	struct resource *res;
1865 
1866 	if (host) {
1867 		mmc_host_enable(host->mmc);
1868 		mmc_remove_host(host->mmc);
1869 		if (host->pdata->cleanup)
1870 			host->pdata->cleanup(&pdev->dev);
1871 		free_irq(host->irq, host);
1872 		if (mmc_slot(host).card_detect_irq)
1873 			free_irq(mmc_slot(host).card_detect_irq, host);
1874 		flush_scheduled_work();
1875 
1876 		mmc_host_disable(host->mmc);
1877 		clk_disable(host->iclk);
1878 		clk_put(host->fclk);
1879 		clk_put(host->iclk);
1880 		if (host->got_dbclk) {
1881 			clk_disable(host->dbclk);
1882 			clk_put(host->dbclk);
1883 		}
1884 
1885 		mmc_free_host(host->mmc);
1886 		iounmap(host->base);
1887 	}
1888 
1889 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1890 	if (res)
1891 		release_mem_region(res->start, res->end - res->start + 1);
1892 	platform_set_drvdata(pdev, NULL);
1893 
1894 	return 0;
1895 }
1896 
1897 #ifdef CONFIG_PM
1898 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
1899 {
1900 	int ret = 0;
1901 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1902 
1903 	if (host && host->suspended)
1904 		return 0;
1905 
1906 	if (host) {
1907 		host->suspended = 1;
1908 		if (host->pdata->suspend) {
1909 			ret = host->pdata->suspend(&pdev->dev,
1910 							host->slot_id);
1911 			if (ret) {
1912 				dev_dbg(mmc_dev(host->mmc),
1913 					"Unable to handle MMC board"
1914 					" level suspend\n");
1915 				host->suspended = 0;
1916 				return ret;
1917 			}
1918 		}
1919 		cancel_work_sync(&host->mmc_carddetect_work);
1920 		mmc_host_enable(host->mmc);
1921 		ret = mmc_suspend_host(host->mmc, state);
1922 		if (ret == 0) {
1923 			OMAP_HSMMC_WRITE(host->base, ISE, 0);
1924 			OMAP_HSMMC_WRITE(host->base, IE, 0);
1925 
1926 
1927 			OMAP_HSMMC_WRITE(host->base, HCTL,
1928 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1929 			mmc_host_disable(host->mmc);
1930 			clk_disable(host->iclk);
1931 			if (host->got_dbclk)
1932 				clk_disable(host->dbclk);
1933 		} else {
1934 			host->suspended = 0;
1935 			if (host->pdata->resume) {
1936 				ret = host->pdata->resume(&pdev->dev,
1937 							  host->slot_id);
1938 				if (ret)
1939 					dev_dbg(mmc_dev(host->mmc),
1940 						"Unmask interrupt failed\n");
1941 			}
1942 			mmc_host_disable(host->mmc);
1943 		}
1944 
1945 	}
1946 	return ret;
1947 }
1948 
1949 /* Routine to resume the MMC device */
1950 static int omap_hsmmc_resume(struct platform_device *pdev)
1951 {
1952 	int ret = 0;
1953 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1954 
1955 	if (host && !host->suspended)
1956 		return 0;
1957 
1958 	if (host) {
1959 		ret = clk_enable(host->iclk);
1960 		if (ret)
1961 			goto clk_en_err;
1962 
1963 		if (mmc_host_enable(host->mmc) != 0) {
1964 			clk_disable(host->iclk);
1965 			goto clk_en_err;
1966 		}
1967 
1968 		if (host->got_dbclk)
1969 			clk_enable(host->dbclk);
1970 
1971 		omap_hsmmc_conf_bus_power(host);
1972 
1973 		if (host->pdata->resume) {
1974 			ret = host->pdata->resume(&pdev->dev, host->slot_id);
1975 			if (ret)
1976 				dev_dbg(mmc_dev(host->mmc),
1977 					"Unmask interrupt failed\n");
1978 		}
1979 
1980 		omap_hsmmc_protect_card(host);
1981 
1982 		/* Notify the core to resume the host */
1983 		ret = mmc_resume_host(host->mmc);
1984 		if (ret == 0)
1985 			host->suspended = 0;
1986 
1987 		mmc_host_lazy_disable(host->mmc);
1988 	}
1989 
1990 	return ret;
1991 
1992 clk_en_err:
1993 	dev_dbg(mmc_dev(host->mmc),
1994 		"Failed to enable MMC clocks during resume\n");
1995 	return ret;
1996 }
1997 
1998 #else
1999 #define omap_hsmmc_suspend	NULL
2000 #define omap_hsmmc_resume		NULL
2001 #endif
2002 
2003 static struct platform_driver omap_hsmmc_driver = {
2004 	.remove		= omap_hsmmc_remove,
2005 	.suspend	= omap_hsmmc_suspend,
2006 	.resume		= omap_hsmmc_resume,
2007 	.driver		= {
2008 		.name = DRIVER_NAME,
2009 		.owner = THIS_MODULE,
2010 	},
2011 };
2012 
2013 static int __init omap_hsmmc_init(void)
2014 {
2015 	/* Register the MMC driver */
2016 	return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2017 }
2018 
2019 static void __exit omap_hsmmc_cleanup(void)
2020 {
2021 	/* Unregister MMC driver */
2022 	platform_driver_unregister(&omap_hsmmc_driver);
2023 }
2024 
2025 module_init(omap_hsmmc_init);
2026 module_exit(omap_hsmmc_cleanup);
2027 
2028 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2029 MODULE_LICENSE("GPL");
2030 MODULE_ALIAS("platform:" DRIVER_NAME);
2031 MODULE_AUTHOR("Texas Instruments Inc");
2032