1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/debugfs.h> 21 #include <linux/seq_file.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/platform_device.h> 26 #include <linux/workqueue.h> 27 #include <linux/timer.h> 28 #include <linux/clk.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/core.h> 31 #include <linux/io.h> 32 #include <linux/semaphore.h> 33 #include <linux/gpio.h> 34 #include <linux/regulator/consumer.h> 35 #include <plat/dma.h> 36 #include <mach/hardware.h> 37 #include <plat/board.h> 38 #include <plat/mmc.h> 39 #include <plat/cpu.h> 40 41 /* OMAP HSMMC Host Controller Registers */ 42 #define OMAP_HSMMC_SYSCONFIG 0x0010 43 #define OMAP_HSMMC_SYSSTATUS 0x0014 44 #define OMAP_HSMMC_CON 0x002C 45 #define OMAP_HSMMC_BLK 0x0104 46 #define OMAP_HSMMC_ARG 0x0108 47 #define OMAP_HSMMC_CMD 0x010C 48 #define OMAP_HSMMC_RSP10 0x0110 49 #define OMAP_HSMMC_RSP32 0x0114 50 #define OMAP_HSMMC_RSP54 0x0118 51 #define OMAP_HSMMC_RSP76 0x011C 52 #define OMAP_HSMMC_DATA 0x0120 53 #define OMAP_HSMMC_HCTL 0x0128 54 #define OMAP_HSMMC_SYSCTL 0x012C 55 #define OMAP_HSMMC_STAT 0x0130 56 #define OMAP_HSMMC_IE 0x0134 57 #define OMAP_HSMMC_ISE 0x0138 58 #define OMAP_HSMMC_CAPA 0x0140 59 60 #define VS18 (1 << 26) 61 #define VS30 (1 << 25) 62 #define SDVS18 (0x5 << 9) 63 #define SDVS30 (0x6 << 9) 64 #define SDVS33 (0x7 << 9) 65 #define SDVS_MASK 0x00000E00 66 #define SDVSCLR 0xFFFFF1FF 67 #define SDVSDET 0x00000400 68 #define AUTOIDLE 0x1 69 #define SDBP (1 << 8) 70 #define DTO 0xe 71 #define ICE 0x1 72 #define ICS 0x2 73 #define CEN (1 << 2) 74 #define CLKD_MASK 0x0000FFC0 75 #define CLKD_SHIFT 6 76 #define DTO_MASK 0x000F0000 77 #define DTO_SHIFT 16 78 #define INT_EN_MASK 0x307F0033 79 #define BWR_ENABLE (1 << 4) 80 #define BRR_ENABLE (1 << 5) 81 #define INIT_STREAM (1 << 1) 82 #define DP_SELECT (1 << 21) 83 #define DDIR (1 << 4) 84 #define DMA_EN 0x1 85 #define MSBS (1 << 5) 86 #define BCE (1 << 1) 87 #define FOUR_BIT (1 << 1) 88 #define DW8 (1 << 5) 89 #define CC 0x1 90 #define TC 0x02 91 #define OD 0x1 92 #define ERR (1 << 15) 93 #define CMD_TIMEOUT (1 << 16) 94 #define DATA_TIMEOUT (1 << 20) 95 #define CMD_CRC (1 << 17) 96 #define DATA_CRC (1 << 21) 97 #define CARD_ERR (1 << 28) 98 #define STAT_CLEAR 0xFFFFFFFF 99 #define INIT_STREAM_CMD 0x00000000 100 #define DUAL_VOLT_OCR_BIT 7 101 #define SRC (1 << 25) 102 #define SRD (1 << 26) 103 #define SOFTRESET (1 << 1) 104 #define RESETDONE (1 << 0) 105 106 /* 107 * FIXME: Most likely all the data using these _DEVID defines should come 108 * from the platform_data, or implemented in controller and slot specific 109 * functions. 110 */ 111 #define OMAP_MMC1_DEVID 0 112 #define OMAP_MMC2_DEVID 1 113 #define OMAP_MMC3_DEVID 2 114 #define OMAP_MMC4_DEVID 3 115 #define OMAP_MMC5_DEVID 4 116 117 #define MMC_TIMEOUT_MS 20 118 #define OMAP_MMC_MASTER_CLOCK 96000000 119 #define DRIVER_NAME "mmci-omap-hs" 120 121 /* Timeouts for entering power saving states on inactivity, msec */ 122 #define OMAP_MMC_DISABLED_TIMEOUT 100 123 #define OMAP_MMC_SLEEP_TIMEOUT 1000 124 #define OMAP_MMC_OFF_TIMEOUT 8000 125 126 /* 127 * One controller can have multiple slots, like on some omap boards using 128 * omap.c controller driver. Luckily this is not currently done on any known 129 * omap_hsmmc.c device. 130 */ 131 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 132 133 /* 134 * MMC Host controller read/write API's 135 */ 136 #define OMAP_HSMMC_READ(base, reg) \ 137 __raw_readl((base) + OMAP_HSMMC_##reg) 138 139 #define OMAP_HSMMC_WRITE(base, reg, val) \ 140 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 141 142 struct omap_hsmmc_host { 143 struct device *dev; 144 struct mmc_host *mmc; 145 struct mmc_request *mrq; 146 struct mmc_command *cmd; 147 struct mmc_data *data; 148 struct clk *fclk; 149 struct clk *iclk; 150 struct clk *dbclk; 151 /* 152 * vcc == configured supply 153 * vcc_aux == optional 154 * - MMC1, supply for DAT4..DAT7 155 * - MMC2/MMC2, external level shifter voltage supply, for 156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 157 */ 158 struct regulator *vcc; 159 struct regulator *vcc_aux; 160 struct work_struct mmc_carddetect_work; 161 void __iomem *base; 162 resource_size_t mapbase; 163 spinlock_t irq_lock; /* Prevent races with irq handler */ 164 unsigned int id; 165 unsigned int dma_len; 166 unsigned int dma_sg_idx; 167 unsigned char bus_mode; 168 unsigned char power_mode; 169 u32 *buffer; 170 u32 bytesleft; 171 int suspended; 172 int irq; 173 int use_dma, dma_ch; 174 int dma_line_tx, dma_line_rx; 175 int slot_id; 176 int got_dbclk; 177 int response_busy; 178 int context_loss; 179 int dpm_state; 180 int vdd; 181 int protect_card; 182 int reqs_blocked; 183 int use_reg; 184 int req_in_progress; 185 186 struct omap_mmc_platform_data *pdata; 187 }; 188 189 static int omap_hsmmc_card_detect(struct device *dev, int slot) 190 { 191 struct omap_mmc_platform_data *mmc = dev->platform_data; 192 193 /* NOTE: assumes card detect signal is active-low */ 194 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 195 } 196 197 static int omap_hsmmc_get_wp(struct device *dev, int slot) 198 { 199 struct omap_mmc_platform_data *mmc = dev->platform_data; 200 201 /* NOTE: assumes write protect signal is active-high */ 202 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 203 } 204 205 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 206 { 207 struct omap_mmc_platform_data *mmc = dev->platform_data; 208 209 /* NOTE: assumes card detect signal is active-low */ 210 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 211 } 212 213 #ifdef CONFIG_PM 214 215 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 216 { 217 struct omap_mmc_platform_data *mmc = dev->platform_data; 218 219 disable_irq(mmc->slots[0].card_detect_irq); 220 return 0; 221 } 222 223 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 224 { 225 struct omap_mmc_platform_data *mmc = dev->platform_data; 226 227 enable_irq(mmc->slots[0].card_detect_irq); 228 return 0; 229 } 230 231 #else 232 233 #define omap_hsmmc_suspend_cdirq NULL 234 #define omap_hsmmc_resume_cdirq NULL 235 236 #endif 237 238 #ifdef CONFIG_REGULATOR 239 240 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 241 int vdd) 242 { 243 struct omap_hsmmc_host *host = 244 platform_get_drvdata(to_platform_device(dev)); 245 int ret; 246 247 if (mmc_slot(host).before_set_reg) 248 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 249 250 if (power_on) 251 ret = mmc_regulator_set_ocr(host->vcc, vdd); 252 else 253 ret = mmc_regulator_set_ocr(host->vcc, 0); 254 255 if (mmc_slot(host).after_set_reg) 256 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 257 258 return ret; 259 } 260 261 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, 262 int vdd) 263 { 264 struct omap_hsmmc_host *host = 265 platform_get_drvdata(to_platform_device(dev)); 266 int ret = 0; 267 268 /* 269 * If we don't see a Vcc regulator, assume it's a fixed 270 * voltage always-on regulator. 271 */ 272 if (!host->vcc) 273 return 0; 274 275 if (mmc_slot(host).before_set_reg) 276 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 277 278 /* 279 * Assume Vcc regulator is used only to power the card ... OMAP 280 * VDDS is used to power the pins, optionally with a transceiver to 281 * support cards using voltages other than VDDS (1.8V nominal). When a 282 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 283 * 284 * In some cases this regulator won't support enable/disable; 285 * e.g. it's a fixed rail for a WLAN chip. 286 * 287 * In other cases vcc_aux switches interface power. Example, for 288 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 289 * chips/cards need an interface voltage rail too. 290 */ 291 if (power_on) { 292 ret = mmc_regulator_set_ocr(host->vcc, vdd); 293 /* Enable interface voltage rail, if needed */ 294 if (ret == 0 && host->vcc_aux) { 295 ret = regulator_enable(host->vcc_aux); 296 if (ret < 0) 297 ret = mmc_regulator_set_ocr(host->vcc, 0); 298 } 299 } else { 300 if (host->vcc_aux) 301 ret = regulator_disable(host->vcc_aux); 302 if (ret == 0) 303 ret = mmc_regulator_set_ocr(host->vcc, 0); 304 } 305 306 if (mmc_slot(host).after_set_reg) 307 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 308 309 return ret; 310 } 311 312 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 313 int vdd, int cardsleep) 314 { 315 struct omap_hsmmc_host *host = 316 platform_get_drvdata(to_platform_device(dev)); 317 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 318 319 return regulator_set_mode(host->vcc, mode); 320 } 321 322 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, 323 int vdd, int cardsleep) 324 { 325 struct omap_hsmmc_host *host = 326 platform_get_drvdata(to_platform_device(dev)); 327 int err, mode; 328 329 /* 330 * If we don't see a Vcc regulator, assume it's a fixed 331 * voltage always-on regulator. 332 */ 333 if (!host->vcc) 334 return 0; 335 336 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 337 338 if (!host->vcc_aux) 339 return regulator_set_mode(host->vcc, mode); 340 341 if (cardsleep) { 342 /* VCC can be turned off if card is asleep */ 343 if (sleep) 344 err = mmc_regulator_set_ocr(host->vcc, 0); 345 else 346 err = mmc_regulator_set_ocr(host->vcc, vdd); 347 } else 348 err = regulator_set_mode(host->vcc, mode); 349 if (err) 350 return err; 351 352 if (!mmc_slot(host).vcc_aux_disable_is_sleep) 353 return regulator_set_mode(host->vcc_aux, mode); 354 355 if (sleep) 356 return regulator_disable(host->vcc_aux); 357 else 358 return regulator_enable(host->vcc_aux); 359 } 360 361 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 362 { 363 struct regulator *reg; 364 int ret = 0; 365 366 switch (host->id) { 367 case OMAP_MMC1_DEVID: 368 /* On-chip level shifting via PBIAS0/PBIAS1 */ 369 mmc_slot(host).set_power = omap_hsmmc_1_set_power; 370 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 371 break; 372 case OMAP_MMC2_DEVID: 373 case OMAP_MMC3_DEVID: 374 /* Off-chip level shifting, or none */ 375 mmc_slot(host).set_power = omap_hsmmc_23_set_power; 376 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; 377 break; 378 default: 379 pr_err("MMC%d configuration not supported!\n", host->id); 380 return -EINVAL; 381 } 382 383 reg = regulator_get(host->dev, "vmmc"); 384 if (IS_ERR(reg)) { 385 dev_dbg(host->dev, "vmmc regulator missing\n"); 386 /* 387 * HACK: until fixed.c regulator is usable, 388 * we don't require a main regulator 389 * for MMC2 or MMC3 390 */ 391 if (host->id == OMAP_MMC1_DEVID) { 392 ret = PTR_ERR(reg); 393 goto err; 394 } 395 } else { 396 host->vcc = reg; 397 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); 398 399 /* Allow an aux regulator */ 400 reg = regulator_get(host->dev, "vmmc_aux"); 401 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 402 403 /* 404 * UGLY HACK: workaround regulator framework bugs. 405 * When the bootloader leaves a supply active, it's 406 * initialized with zero usecount ... and we can't 407 * disable it without first enabling it. Until the 408 * framework is fixed, we need a workaround like this 409 * (which is safe for MMC, but not in general). 410 */ 411 if (regulator_is_enabled(host->vcc) > 0) { 412 regulator_enable(host->vcc); 413 regulator_disable(host->vcc); 414 } 415 if (host->vcc_aux) { 416 if (regulator_is_enabled(reg) > 0) { 417 regulator_enable(reg); 418 regulator_disable(reg); 419 } 420 } 421 } 422 423 return 0; 424 425 err: 426 mmc_slot(host).set_power = NULL; 427 mmc_slot(host).set_sleep = NULL; 428 return ret; 429 } 430 431 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 432 { 433 regulator_put(host->vcc); 434 regulator_put(host->vcc_aux); 435 mmc_slot(host).set_power = NULL; 436 mmc_slot(host).set_sleep = NULL; 437 } 438 439 static inline int omap_hsmmc_have_reg(void) 440 { 441 return 1; 442 } 443 444 #else 445 446 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 447 { 448 return -EINVAL; 449 } 450 451 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 452 { 453 } 454 455 static inline int omap_hsmmc_have_reg(void) 456 { 457 return 0; 458 } 459 460 #endif 461 462 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 463 { 464 int ret; 465 466 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 467 pdata->suspend = omap_hsmmc_suspend_cdirq; 468 pdata->resume = omap_hsmmc_resume_cdirq; 469 if (pdata->slots[0].cover) 470 pdata->slots[0].get_cover_state = 471 omap_hsmmc_get_cover_state; 472 else 473 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 474 pdata->slots[0].card_detect_irq = 475 gpio_to_irq(pdata->slots[0].switch_pin); 476 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 477 if (ret) 478 return ret; 479 ret = gpio_direction_input(pdata->slots[0].switch_pin); 480 if (ret) 481 goto err_free_sp; 482 } else 483 pdata->slots[0].switch_pin = -EINVAL; 484 485 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 486 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 487 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 488 if (ret) 489 goto err_free_cd; 490 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 491 if (ret) 492 goto err_free_wp; 493 } else 494 pdata->slots[0].gpio_wp = -EINVAL; 495 496 return 0; 497 498 err_free_wp: 499 gpio_free(pdata->slots[0].gpio_wp); 500 err_free_cd: 501 if (gpio_is_valid(pdata->slots[0].switch_pin)) 502 err_free_sp: 503 gpio_free(pdata->slots[0].switch_pin); 504 return ret; 505 } 506 507 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 508 { 509 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 510 gpio_free(pdata->slots[0].gpio_wp); 511 if (gpio_is_valid(pdata->slots[0].switch_pin)) 512 gpio_free(pdata->slots[0].switch_pin); 513 } 514 515 /* 516 * Stop clock to the card 517 */ 518 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 519 { 520 OMAP_HSMMC_WRITE(host->base, SYSCTL, 521 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 522 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 523 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 524 } 525 526 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host) 527 { 528 unsigned int irq_mask; 529 530 if (host->use_dma) 531 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 532 else 533 irq_mask = INT_EN_MASK; 534 535 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 536 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 537 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 538 } 539 540 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 541 { 542 OMAP_HSMMC_WRITE(host->base, ISE, 0); 543 OMAP_HSMMC_WRITE(host->base, IE, 0); 544 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 545 } 546 547 #ifdef CONFIG_PM 548 549 /* 550 * Restore the MMC host context, if it was lost as result of a 551 * power state change. 552 */ 553 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 554 { 555 struct mmc_ios *ios = &host->mmc->ios; 556 struct omap_mmc_platform_data *pdata = host->pdata; 557 int context_loss = 0; 558 u32 hctl, capa, con; 559 u16 dsor = 0; 560 unsigned long timeout; 561 562 if (pdata->get_context_loss_count) { 563 context_loss = pdata->get_context_loss_count(host->dev); 564 if (context_loss < 0) 565 return 1; 566 } 567 568 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 569 context_loss == host->context_loss ? "not " : ""); 570 if (host->context_loss == context_loss) 571 return 1; 572 573 /* Wait for hardware reset */ 574 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 575 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 576 && time_before(jiffies, timeout)) 577 ; 578 579 /* Do software reset */ 580 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 583 && time_before(jiffies, timeout)) 584 ; 585 586 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 587 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 588 589 if (host->id == OMAP_MMC1_DEVID) { 590 if (host->power_mode != MMC_POWER_OFF && 591 (1 << ios->vdd) <= MMC_VDD_23_24) 592 hctl = SDVS18; 593 else 594 hctl = SDVS30; 595 capa = VS30 | VS18; 596 } else { 597 hctl = SDVS18; 598 capa = VS18; 599 } 600 601 OMAP_HSMMC_WRITE(host->base, HCTL, 602 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 603 604 OMAP_HSMMC_WRITE(host->base, CAPA, 605 OMAP_HSMMC_READ(host->base, CAPA) | capa); 606 607 OMAP_HSMMC_WRITE(host->base, HCTL, 608 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 609 610 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 611 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 612 && time_before(jiffies, timeout)) 613 ; 614 615 omap_hsmmc_disable_irq(host); 616 617 /* Do not initialize card-specific things if the power is off */ 618 if (host->power_mode == MMC_POWER_OFF) 619 goto out; 620 621 con = OMAP_HSMMC_READ(host->base, CON); 622 switch (ios->bus_width) { 623 case MMC_BUS_WIDTH_8: 624 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 625 break; 626 case MMC_BUS_WIDTH_4: 627 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 628 OMAP_HSMMC_WRITE(host->base, HCTL, 629 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 630 break; 631 case MMC_BUS_WIDTH_1: 632 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 633 OMAP_HSMMC_WRITE(host->base, HCTL, 634 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 635 break; 636 } 637 638 if (ios->clock) { 639 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 640 if (dsor < 1) 641 dsor = 1; 642 643 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 644 dsor++; 645 646 if (dsor > 250) 647 dsor = 250; 648 } 649 650 OMAP_HSMMC_WRITE(host->base, SYSCTL, 651 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 652 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 653 OMAP_HSMMC_WRITE(host->base, SYSCTL, 654 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 655 656 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 657 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 658 && time_before(jiffies, timeout)) 659 ; 660 661 OMAP_HSMMC_WRITE(host->base, SYSCTL, 662 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 663 664 con = OMAP_HSMMC_READ(host->base, CON); 665 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 666 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 667 else 668 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 669 out: 670 host->context_loss = context_loss; 671 672 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 673 return 0; 674 } 675 676 /* 677 * Save the MMC host context (store the number of power state changes so far). 678 */ 679 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 680 { 681 struct omap_mmc_platform_data *pdata = host->pdata; 682 int context_loss; 683 684 if (pdata->get_context_loss_count) { 685 context_loss = pdata->get_context_loss_count(host->dev); 686 if (context_loss < 0) 687 return; 688 host->context_loss = context_loss; 689 } 690 } 691 692 #else 693 694 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 695 { 696 return 0; 697 } 698 699 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 700 { 701 } 702 703 #endif 704 705 /* 706 * Send init stream sequence to card 707 * before sending IDLE command 708 */ 709 static void send_init_stream(struct omap_hsmmc_host *host) 710 { 711 int reg = 0; 712 unsigned long timeout; 713 714 if (host->protect_card) 715 return; 716 717 disable_irq(host->irq); 718 719 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 720 OMAP_HSMMC_WRITE(host->base, CON, 721 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 722 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 723 724 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 725 while ((reg != CC) && time_before(jiffies, timeout)) 726 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 727 728 OMAP_HSMMC_WRITE(host->base, CON, 729 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 730 731 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 732 OMAP_HSMMC_READ(host->base, STAT); 733 734 enable_irq(host->irq); 735 } 736 737 static inline 738 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 739 { 740 int r = 1; 741 742 if (mmc_slot(host).get_cover_state) 743 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 744 return r; 745 } 746 747 static ssize_t 748 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 749 char *buf) 750 { 751 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 752 struct omap_hsmmc_host *host = mmc_priv(mmc); 753 754 return sprintf(buf, "%s\n", 755 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 756 } 757 758 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 759 760 static ssize_t 761 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 762 char *buf) 763 { 764 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 765 struct omap_hsmmc_host *host = mmc_priv(mmc); 766 767 return sprintf(buf, "%s\n", mmc_slot(host).name); 768 } 769 770 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 771 772 /* 773 * Configure the response type and send the cmd. 774 */ 775 static void 776 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 777 struct mmc_data *data) 778 { 779 int cmdreg = 0, resptype = 0, cmdtype = 0; 780 781 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 782 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 783 host->cmd = cmd; 784 785 omap_hsmmc_enable_irq(host); 786 787 host->response_busy = 0; 788 if (cmd->flags & MMC_RSP_PRESENT) { 789 if (cmd->flags & MMC_RSP_136) 790 resptype = 1; 791 else if (cmd->flags & MMC_RSP_BUSY) { 792 resptype = 3; 793 host->response_busy = 1; 794 } else 795 resptype = 2; 796 } 797 798 /* 799 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 800 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 801 * a val of 0x3, rest 0x0. 802 */ 803 if (cmd == host->mrq->stop) 804 cmdtype = 0x3; 805 806 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 807 808 if (data) { 809 cmdreg |= DP_SELECT | MSBS | BCE; 810 if (data->flags & MMC_DATA_READ) 811 cmdreg |= DDIR; 812 else 813 cmdreg &= ~(DDIR); 814 } 815 816 if (host->use_dma) 817 cmdreg |= DMA_EN; 818 819 host->req_in_progress = 1; 820 821 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 822 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 823 } 824 825 static int 826 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 827 { 828 if (data->flags & MMC_DATA_WRITE) 829 return DMA_TO_DEVICE; 830 else 831 return DMA_FROM_DEVICE; 832 } 833 834 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 835 { 836 int dma_ch; 837 838 spin_lock(&host->irq_lock); 839 host->req_in_progress = 0; 840 dma_ch = host->dma_ch; 841 spin_unlock(&host->irq_lock); 842 843 omap_hsmmc_disable_irq(host); 844 /* Do not complete the request if DMA is still in progress */ 845 if (mrq->data && host->use_dma && dma_ch != -1) 846 return; 847 host->mrq = NULL; 848 mmc_request_done(host->mmc, mrq); 849 } 850 851 /* 852 * Notify the transfer complete to MMC core 853 */ 854 static void 855 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 856 { 857 if (!data) { 858 struct mmc_request *mrq = host->mrq; 859 860 /* TC before CC from CMD6 - don't know why, but it happens */ 861 if (host->cmd && host->cmd->opcode == 6 && 862 host->response_busy) { 863 host->response_busy = 0; 864 return; 865 } 866 867 omap_hsmmc_request_done(host, mrq); 868 return; 869 } 870 871 host->data = NULL; 872 873 if (!data->error) 874 data->bytes_xfered += data->blocks * (data->blksz); 875 else 876 data->bytes_xfered = 0; 877 878 if (!data->stop) { 879 omap_hsmmc_request_done(host, data->mrq); 880 return; 881 } 882 omap_hsmmc_start_command(host, data->stop, NULL); 883 } 884 885 /* 886 * Notify the core about command completion 887 */ 888 static void 889 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 890 { 891 host->cmd = NULL; 892 893 if (cmd->flags & MMC_RSP_PRESENT) { 894 if (cmd->flags & MMC_RSP_136) { 895 /* response type 2 */ 896 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 897 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 898 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 899 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 900 } else { 901 /* response types 1, 1b, 3, 4, 5, 6 */ 902 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 903 } 904 } 905 if ((host->data == NULL && !host->response_busy) || cmd->error) 906 omap_hsmmc_request_done(host, cmd->mrq); 907 } 908 909 /* 910 * DMA clean up for command errors 911 */ 912 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 913 { 914 int dma_ch; 915 916 host->data->error = errno; 917 918 spin_lock(&host->irq_lock); 919 dma_ch = host->dma_ch; 920 host->dma_ch = -1; 921 spin_unlock(&host->irq_lock); 922 923 if (host->use_dma && dma_ch != -1) { 924 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 925 omap_hsmmc_get_dma_dir(host, host->data)); 926 omap_free_dma(dma_ch); 927 } 928 host->data = NULL; 929 } 930 931 /* 932 * Readable error output 933 */ 934 #ifdef CONFIG_MMC_DEBUG 935 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 936 { 937 /* --- means reserved bit without definition at documentation */ 938 static const char *omap_hsmmc_status_bits[] = { 939 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 940 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 941 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 942 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 943 }; 944 char res[256]; 945 char *buf = res; 946 int len, i; 947 948 len = sprintf(buf, "MMC IRQ 0x%x :", status); 949 buf += len; 950 951 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 952 if (status & (1 << i)) { 953 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 954 buf += len; 955 } 956 957 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 958 } 959 #endif /* CONFIG_MMC_DEBUG */ 960 961 /* 962 * MMC controller internal state machines reset 963 * 964 * Used to reset command or data internal state machines, using respectively 965 * SRC or SRD bit of SYSCTL register 966 * Can be called from interrupt context 967 */ 968 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 969 unsigned long bit) 970 { 971 unsigned long i = 0; 972 unsigned long limit = (loops_per_jiffy * 973 msecs_to_jiffies(MMC_TIMEOUT_MS)); 974 975 OMAP_HSMMC_WRITE(host->base, SYSCTL, 976 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 977 978 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 979 (i++ < limit)) 980 cpu_relax(); 981 982 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 983 dev_err(mmc_dev(host->mmc), 984 "Timeout waiting on controller reset in %s\n", 985 __func__); 986 } 987 988 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 989 { 990 struct mmc_data *data; 991 int end_cmd = 0, end_trans = 0; 992 993 if (!host->req_in_progress) { 994 do { 995 OMAP_HSMMC_WRITE(host->base, STAT, status); 996 /* Flush posted write */ 997 status = OMAP_HSMMC_READ(host->base, STAT); 998 } while (status & INT_EN_MASK); 999 return; 1000 } 1001 1002 data = host->data; 1003 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1004 1005 if (status & ERR) { 1006 #ifdef CONFIG_MMC_DEBUG 1007 omap_hsmmc_report_irq(host, status); 1008 #endif 1009 if ((status & CMD_TIMEOUT) || 1010 (status & CMD_CRC)) { 1011 if (host->cmd) { 1012 if (status & CMD_TIMEOUT) { 1013 omap_hsmmc_reset_controller_fsm(host, 1014 SRC); 1015 host->cmd->error = -ETIMEDOUT; 1016 } else { 1017 host->cmd->error = -EILSEQ; 1018 } 1019 end_cmd = 1; 1020 } 1021 if (host->data || host->response_busy) { 1022 if (host->data) 1023 omap_hsmmc_dma_cleanup(host, 1024 -ETIMEDOUT); 1025 host->response_busy = 0; 1026 omap_hsmmc_reset_controller_fsm(host, SRD); 1027 } 1028 } 1029 if ((status & DATA_TIMEOUT) || 1030 (status & DATA_CRC)) { 1031 if (host->data || host->response_busy) { 1032 int err = (status & DATA_TIMEOUT) ? 1033 -ETIMEDOUT : -EILSEQ; 1034 1035 if (host->data) 1036 omap_hsmmc_dma_cleanup(host, err); 1037 else 1038 host->mrq->cmd->error = err; 1039 host->response_busy = 0; 1040 omap_hsmmc_reset_controller_fsm(host, SRD); 1041 end_trans = 1; 1042 } 1043 } 1044 if (status & CARD_ERR) { 1045 dev_dbg(mmc_dev(host->mmc), 1046 "Ignoring card err CMD%d\n", host->cmd->opcode); 1047 if (host->cmd) 1048 end_cmd = 1; 1049 if (host->data) 1050 end_trans = 1; 1051 } 1052 } 1053 1054 OMAP_HSMMC_WRITE(host->base, STAT, status); 1055 1056 if (end_cmd || ((status & CC) && host->cmd)) 1057 omap_hsmmc_cmd_done(host, host->cmd); 1058 if ((end_trans || (status & TC)) && host->mrq) 1059 omap_hsmmc_xfer_done(host, data); 1060 } 1061 1062 /* 1063 * MMC controller IRQ handler 1064 */ 1065 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1066 { 1067 struct omap_hsmmc_host *host = dev_id; 1068 int status; 1069 1070 status = OMAP_HSMMC_READ(host->base, STAT); 1071 do { 1072 omap_hsmmc_do_irq(host, status); 1073 /* Flush posted write */ 1074 status = OMAP_HSMMC_READ(host->base, STAT); 1075 } while (status & INT_EN_MASK); 1076 1077 return IRQ_HANDLED; 1078 } 1079 1080 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1081 { 1082 unsigned long i; 1083 1084 OMAP_HSMMC_WRITE(host->base, HCTL, 1085 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1086 for (i = 0; i < loops_per_jiffy; i++) { 1087 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1088 break; 1089 cpu_relax(); 1090 } 1091 } 1092 1093 /* 1094 * Switch MMC interface voltage ... only relevant for MMC1. 1095 * 1096 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1097 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1098 * Some chips, like eMMC ones, use internal transceivers. 1099 */ 1100 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1101 { 1102 u32 reg_val = 0; 1103 int ret; 1104 1105 /* Disable the clocks */ 1106 clk_disable(host->fclk); 1107 clk_disable(host->iclk); 1108 if (host->got_dbclk) 1109 clk_disable(host->dbclk); 1110 1111 /* Turn the power off */ 1112 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1113 1114 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1115 if (!ret) 1116 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1117 vdd); 1118 clk_enable(host->iclk); 1119 clk_enable(host->fclk); 1120 if (host->got_dbclk) 1121 clk_enable(host->dbclk); 1122 1123 if (ret != 0) 1124 goto err; 1125 1126 OMAP_HSMMC_WRITE(host->base, HCTL, 1127 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1128 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1129 1130 /* 1131 * If a MMC dual voltage card is detected, the set_ios fn calls 1132 * this fn with VDD bit set for 1.8V. Upon card removal from the 1133 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1134 * 1135 * Cope with a bit of slop in the range ... per data sheets: 1136 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1137 * but recommended values are 1.71V to 1.89V 1138 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1139 * but recommended values are 2.7V to 3.3V 1140 * 1141 * Board setup code shouldn't permit anything very out-of-range. 1142 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1143 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1144 */ 1145 if ((1 << vdd) <= MMC_VDD_23_24) 1146 reg_val |= SDVS18; 1147 else 1148 reg_val |= SDVS30; 1149 1150 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1151 set_sd_bus_power(host); 1152 1153 return 0; 1154 err: 1155 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1156 return ret; 1157 } 1158 1159 /* Protect the card while the cover is open */ 1160 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1161 { 1162 if (!mmc_slot(host).get_cover_state) 1163 return; 1164 1165 host->reqs_blocked = 0; 1166 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1167 if (host->protect_card) { 1168 printk(KERN_INFO "%s: cover is closed, " 1169 "card is now accessible\n", 1170 mmc_hostname(host->mmc)); 1171 host->protect_card = 0; 1172 } 1173 } else { 1174 if (!host->protect_card) { 1175 printk(KERN_INFO "%s: cover is open, " 1176 "card is now inaccessible\n", 1177 mmc_hostname(host->mmc)); 1178 host->protect_card = 1; 1179 } 1180 } 1181 } 1182 1183 /* 1184 * Work Item to notify the core about card insertion/removal 1185 */ 1186 static void omap_hsmmc_detect(struct work_struct *work) 1187 { 1188 struct omap_hsmmc_host *host = 1189 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1190 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1191 int carddetect; 1192 1193 if (host->suspended) 1194 return; 1195 1196 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1197 1198 if (slot->card_detect) 1199 carddetect = slot->card_detect(host->dev, host->slot_id); 1200 else { 1201 omap_hsmmc_protect_card(host); 1202 carddetect = -ENOSYS; 1203 } 1204 1205 if (carddetect) 1206 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1207 else 1208 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1209 } 1210 1211 /* 1212 * ISR for handling card insertion and removal 1213 */ 1214 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1215 { 1216 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1217 1218 if (host->suspended) 1219 return IRQ_HANDLED; 1220 schedule_work(&host->mmc_carddetect_work); 1221 1222 return IRQ_HANDLED; 1223 } 1224 1225 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 1226 struct mmc_data *data) 1227 { 1228 int sync_dev; 1229 1230 if (data->flags & MMC_DATA_WRITE) 1231 sync_dev = host->dma_line_tx; 1232 else 1233 sync_dev = host->dma_line_rx; 1234 return sync_dev; 1235 } 1236 1237 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 1238 struct mmc_data *data, 1239 struct scatterlist *sgl) 1240 { 1241 int blksz, nblk, dma_ch; 1242 1243 dma_ch = host->dma_ch; 1244 if (data->flags & MMC_DATA_WRITE) { 1245 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1246 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1247 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1248 sg_dma_address(sgl), 0, 0); 1249 } else { 1250 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1251 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1252 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1253 sg_dma_address(sgl), 0, 0); 1254 } 1255 1256 blksz = host->data->blksz; 1257 nblk = sg_dma_len(sgl) / blksz; 1258 1259 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 1260 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 1261 omap_hsmmc_get_dma_sync_dev(host, data), 1262 !(data->flags & MMC_DATA_WRITE)); 1263 1264 omap_start_dma(dma_ch); 1265 } 1266 1267 /* 1268 * DMA call back function 1269 */ 1270 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1271 { 1272 struct omap_hsmmc_host *host = cb_data; 1273 struct mmc_data *data = host->mrq->data; 1274 int dma_ch, req_in_progress; 1275 1276 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) 1277 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); 1278 1279 spin_lock(&host->irq_lock); 1280 if (host->dma_ch < 0) { 1281 spin_unlock(&host->irq_lock); 1282 return; 1283 } 1284 1285 host->dma_sg_idx++; 1286 if (host->dma_sg_idx < host->dma_len) { 1287 /* Fire up the next transfer. */ 1288 omap_hsmmc_config_dma_params(host, data, 1289 data->sg + host->dma_sg_idx); 1290 spin_unlock(&host->irq_lock); 1291 return; 1292 } 1293 1294 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 1295 omap_hsmmc_get_dma_dir(host, data)); 1296 1297 req_in_progress = host->req_in_progress; 1298 dma_ch = host->dma_ch; 1299 host->dma_ch = -1; 1300 spin_unlock(&host->irq_lock); 1301 1302 omap_free_dma(dma_ch); 1303 1304 /* If DMA has finished after TC, complete the request */ 1305 if (!req_in_progress) { 1306 struct mmc_request *mrq = host->mrq; 1307 1308 host->mrq = NULL; 1309 mmc_request_done(host->mmc, mrq); 1310 } 1311 } 1312 1313 /* 1314 * Routine to configure and start DMA for the MMC card 1315 */ 1316 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1317 struct mmc_request *req) 1318 { 1319 int dma_ch = 0, ret = 0, i; 1320 struct mmc_data *data = req->data; 1321 1322 /* Sanity check: all the SG entries must be aligned by block size. */ 1323 for (i = 0; i < data->sg_len; i++) { 1324 struct scatterlist *sgl; 1325 1326 sgl = data->sg + i; 1327 if (sgl->length % data->blksz) 1328 return -EINVAL; 1329 } 1330 if ((data->blksz % 4) != 0) 1331 /* REVISIT: The MMC buffer increments only when MSB is written. 1332 * Return error for blksz which is non multiple of four. 1333 */ 1334 return -EINVAL; 1335 1336 BUG_ON(host->dma_ch != -1); 1337 1338 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 1339 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1340 if (ret != 0) { 1341 dev_err(mmc_dev(host->mmc), 1342 "%s: omap_request_dma() failed with %d\n", 1343 mmc_hostname(host->mmc), ret); 1344 return ret; 1345 } 1346 1347 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1348 data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 1349 host->dma_ch = dma_ch; 1350 host->dma_sg_idx = 0; 1351 1352 omap_hsmmc_config_dma_params(host, data, data->sg); 1353 1354 return 0; 1355 } 1356 1357 static void set_data_timeout(struct omap_hsmmc_host *host, 1358 unsigned int timeout_ns, 1359 unsigned int timeout_clks) 1360 { 1361 unsigned int timeout, cycle_ns; 1362 uint32_t reg, clkd, dto = 0; 1363 1364 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1365 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1366 if (clkd == 0) 1367 clkd = 1; 1368 1369 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1370 timeout = timeout_ns / cycle_ns; 1371 timeout += timeout_clks; 1372 if (timeout) { 1373 while ((timeout & 0x80000000) == 0) { 1374 dto += 1; 1375 timeout <<= 1; 1376 } 1377 dto = 31 - dto; 1378 timeout <<= 1; 1379 if (timeout && dto) 1380 dto += 1; 1381 if (dto >= 13) 1382 dto -= 13; 1383 else 1384 dto = 0; 1385 if (dto > 14) 1386 dto = 14; 1387 } 1388 1389 reg &= ~DTO_MASK; 1390 reg |= dto << DTO_SHIFT; 1391 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1392 } 1393 1394 /* 1395 * Configure block length for MMC/SD cards and initiate the transfer. 1396 */ 1397 static int 1398 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1399 { 1400 int ret; 1401 host->data = req->data; 1402 1403 if (req->data == NULL) { 1404 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1405 /* 1406 * Set an arbitrary 100ms data timeout for commands with 1407 * busy signal. 1408 */ 1409 if (req->cmd->flags & MMC_RSP_BUSY) 1410 set_data_timeout(host, 100000000U, 0); 1411 return 0; 1412 } 1413 1414 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1415 | (req->data->blocks << 16)); 1416 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1417 1418 if (host->use_dma) { 1419 ret = omap_hsmmc_start_dma_transfer(host, req); 1420 if (ret != 0) { 1421 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1422 return ret; 1423 } 1424 } 1425 return 0; 1426 } 1427 1428 /* 1429 * Request function. for read/write operation 1430 */ 1431 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1432 { 1433 struct omap_hsmmc_host *host = mmc_priv(mmc); 1434 int err; 1435 1436 BUG_ON(host->req_in_progress); 1437 BUG_ON(host->dma_ch != -1); 1438 if (host->protect_card) { 1439 if (host->reqs_blocked < 3) { 1440 /* 1441 * Ensure the controller is left in a consistent 1442 * state by resetting the command and data state 1443 * machines. 1444 */ 1445 omap_hsmmc_reset_controller_fsm(host, SRD); 1446 omap_hsmmc_reset_controller_fsm(host, SRC); 1447 host->reqs_blocked += 1; 1448 } 1449 req->cmd->error = -EBADF; 1450 if (req->data) 1451 req->data->error = -EBADF; 1452 req->cmd->retries = 0; 1453 mmc_request_done(mmc, req); 1454 return; 1455 } else if (host->reqs_blocked) 1456 host->reqs_blocked = 0; 1457 WARN_ON(host->mrq != NULL); 1458 host->mrq = req; 1459 err = omap_hsmmc_prepare_data(host, req); 1460 if (err) { 1461 req->cmd->error = err; 1462 if (req->data) 1463 req->data->error = err; 1464 host->mrq = NULL; 1465 mmc_request_done(mmc, req); 1466 return; 1467 } 1468 1469 omap_hsmmc_start_command(host, req->cmd, req->data); 1470 } 1471 1472 /* Routine to configure clock values. Exposed API to core */ 1473 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1474 { 1475 struct omap_hsmmc_host *host = mmc_priv(mmc); 1476 u16 dsor = 0; 1477 unsigned long regval; 1478 unsigned long timeout; 1479 u32 con; 1480 int do_send_init_stream = 0; 1481 1482 mmc_host_enable(host->mmc); 1483 1484 if (ios->power_mode != host->power_mode) { 1485 switch (ios->power_mode) { 1486 case MMC_POWER_OFF: 1487 mmc_slot(host).set_power(host->dev, host->slot_id, 1488 0, 0); 1489 host->vdd = 0; 1490 break; 1491 case MMC_POWER_UP: 1492 mmc_slot(host).set_power(host->dev, host->slot_id, 1493 1, ios->vdd); 1494 host->vdd = ios->vdd; 1495 break; 1496 case MMC_POWER_ON: 1497 do_send_init_stream = 1; 1498 break; 1499 } 1500 host->power_mode = ios->power_mode; 1501 } 1502 1503 /* FIXME: set registers based only on changes to ios */ 1504 1505 con = OMAP_HSMMC_READ(host->base, CON); 1506 switch (mmc->ios.bus_width) { 1507 case MMC_BUS_WIDTH_8: 1508 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 1509 break; 1510 case MMC_BUS_WIDTH_4: 1511 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1512 OMAP_HSMMC_WRITE(host->base, HCTL, 1513 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1514 break; 1515 case MMC_BUS_WIDTH_1: 1516 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1517 OMAP_HSMMC_WRITE(host->base, HCTL, 1518 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1519 break; 1520 } 1521 1522 if (host->id == OMAP_MMC1_DEVID) { 1523 /* Only MMC1 can interface at 3V without some flavor 1524 * of external transceiver; but they all handle 1.8V. 1525 */ 1526 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1527 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1528 /* 1529 * The mmc_select_voltage fn of the core does 1530 * not seem to set the power_mode to 1531 * MMC_POWER_UP upon recalculating the voltage. 1532 * vdd 1.8v. 1533 */ 1534 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1535 dev_dbg(mmc_dev(host->mmc), 1536 "Switch operation failed\n"); 1537 } 1538 } 1539 1540 if (ios->clock) { 1541 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1542 if (dsor < 1) 1543 dsor = 1; 1544 1545 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1546 dsor++; 1547 1548 if (dsor > 250) 1549 dsor = 250; 1550 } 1551 omap_hsmmc_stop_clock(host); 1552 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1553 regval = regval & ~(CLKD_MASK); 1554 regval = regval | (dsor << 6) | (DTO << 16); 1555 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1556 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1557 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1558 1559 /* Wait till the ICS bit is set */ 1560 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 1561 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1562 && time_before(jiffies, timeout)) 1563 msleep(1); 1564 1565 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1566 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1567 1568 if (do_send_init_stream) 1569 send_init_stream(host); 1570 1571 con = OMAP_HSMMC_READ(host->base, CON); 1572 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1573 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1574 else 1575 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 1576 1577 if (host->power_mode == MMC_POWER_OFF) 1578 mmc_host_disable(host->mmc); 1579 else 1580 mmc_host_lazy_disable(host->mmc); 1581 } 1582 1583 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1584 { 1585 struct omap_hsmmc_host *host = mmc_priv(mmc); 1586 1587 if (!mmc_slot(host).card_detect) 1588 return -ENOSYS; 1589 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1590 } 1591 1592 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1593 { 1594 struct omap_hsmmc_host *host = mmc_priv(mmc); 1595 1596 if (!mmc_slot(host).get_ro) 1597 return -ENOSYS; 1598 return mmc_slot(host).get_ro(host->dev, 0); 1599 } 1600 1601 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1602 { 1603 u32 hctl, capa, value; 1604 1605 /* Only MMC1 supports 3.0V */ 1606 if (host->id == OMAP_MMC1_DEVID) { 1607 hctl = SDVS30; 1608 capa = VS30 | VS18; 1609 } else { 1610 hctl = SDVS18; 1611 capa = VS18; 1612 } 1613 1614 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1615 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1616 1617 value = OMAP_HSMMC_READ(host->base, CAPA); 1618 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1619 1620 /* Set the controller to AUTO IDLE mode */ 1621 value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 1622 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 1623 1624 /* Set SD bus power bit */ 1625 set_sd_bus_power(host); 1626 } 1627 1628 /* 1629 * Dynamic power saving handling, FSM: 1630 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 1631 * ^___________| | | 1632 * |______________________|______________________| 1633 * 1634 * ENABLED: mmc host is fully functional 1635 * DISABLED: fclk is off 1636 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1637 * REGSLEEP: fclk is off, voltage regulator is asleep 1638 * OFF: fclk is off, voltage regulator is off 1639 * 1640 * Transition handlers return the timeout for the next state transition 1641 * or negative error. 1642 */ 1643 1644 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1645 1646 /* Handler for [ENABLED -> DISABLED] transition */ 1647 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1648 { 1649 omap_hsmmc_context_save(host); 1650 clk_disable(host->fclk); 1651 host->dpm_state = DISABLED; 1652 1653 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1654 1655 if (host->power_mode == MMC_POWER_OFF) 1656 return 0; 1657 1658 return OMAP_MMC_SLEEP_TIMEOUT; 1659 } 1660 1661 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 1662 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1663 { 1664 int err, new_state; 1665 1666 if (!mmc_try_claim_host(host->mmc)) 1667 return 0; 1668 1669 clk_enable(host->fclk); 1670 omap_hsmmc_context_restore(host); 1671 if (mmc_card_can_sleep(host->mmc)) { 1672 err = mmc_card_sleep(host->mmc); 1673 if (err < 0) { 1674 clk_disable(host->fclk); 1675 mmc_release_host(host->mmc); 1676 return err; 1677 } 1678 new_state = CARDSLEEP; 1679 } else { 1680 new_state = REGSLEEP; 1681 } 1682 if (mmc_slot(host).set_sleep) 1683 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 1684 new_state == CARDSLEEP); 1685 /* FIXME: turn off bus power and perhaps interrupts too */ 1686 clk_disable(host->fclk); 1687 host->dpm_state = new_state; 1688 1689 mmc_release_host(host->mmc); 1690 1691 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 1692 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1693 1694 if (mmc_slot(host).no_off) 1695 return 0; 1696 1697 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1698 mmc_slot(host).card_detect || 1699 (mmc_slot(host).get_cover_state && 1700 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 1701 return OMAP_MMC_OFF_TIMEOUT; 1702 1703 return 0; 1704 } 1705 1706 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 1707 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 1708 { 1709 if (!mmc_try_claim_host(host->mmc)) 1710 return 0; 1711 1712 if (mmc_slot(host).no_off) 1713 return 0; 1714 1715 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1716 mmc_slot(host).card_detect || 1717 (mmc_slot(host).get_cover_state && 1718 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 1719 mmc_release_host(host->mmc); 1720 return 0; 1721 } 1722 1723 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1724 host->vdd = 0; 1725 host->power_mode = MMC_POWER_OFF; 1726 1727 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 1728 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1729 1730 host->dpm_state = OFF; 1731 1732 mmc_release_host(host->mmc); 1733 1734 return 0; 1735 } 1736 1737 /* Handler for [DISABLED -> ENABLED] transition */ 1738 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1739 { 1740 int err; 1741 1742 err = clk_enable(host->fclk); 1743 if (err < 0) 1744 return err; 1745 1746 omap_hsmmc_context_restore(host); 1747 host->dpm_state = ENABLED; 1748 1749 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1750 1751 return 0; 1752 } 1753 1754 /* Handler for [SLEEP -> ENABLED] transition */ 1755 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 1756 { 1757 if (!mmc_try_claim_host(host->mmc)) 1758 return 0; 1759 1760 clk_enable(host->fclk); 1761 omap_hsmmc_context_restore(host); 1762 if (mmc_slot(host).set_sleep) 1763 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 1764 host->vdd, host->dpm_state == CARDSLEEP); 1765 if (mmc_card_can_sleep(host->mmc)) 1766 mmc_card_awake(host->mmc); 1767 1768 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 1769 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1770 1771 host->dpm_state = ENABLED; 1772 1773 mmc_release_host(host->mmc); 1774 1775 return 0; 1776 } 1777 1778 /* Handler for [OFF -> ENABLED] transition */ 1779 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1780 { 1781 clk_enable(host->fclk); 1782 1783 omap_hsmmc_context_restore(host); 1784 omap_hsmmc_conf_bus_power(host); 1785 mmc_power_restore_host(host->mmc); 1786 1787 host->dpm_state = ENABLED; 1788 1789 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1790 1791 return 0; 1792 } 1793 1794 /* 1795 * Bring MMC host to ENABLED from any other PM state. 1796 */ 1797 static int omap_hsmmc_enable(struct mmc_host *mmc) 1798 { 1799 struct omap_hsmmc_host *host = mmc_priv(mmc); 1800 1801 switch (host->dpm_state) { 1802 case DISABLED: 1803 return omap_hsmmc_disabled_to_enabled(host); 1804 case CARDSLEEP: 1805 case REGSLEEP: 1806 return omap_hsmmc_sleep_to_enabled(host); 1807 case OFF: 1808 return omap_hsmmc_off_to_enabled(host); 1809 default: 1810 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1811 return -EINVAL; 1812 } 1813 } 1814 1815 /* 1816 * Bring MMC host in PM state (one level deeper). 1817 */ 1818 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1819 { 1820 struct omap_hsmmc_host *host = mmc_priv(mmc); 1821 1822 switch (host->dpm_state) { 1823 case ENABLED: { 1824 int delay; 1825 1826 delay = omap_hsmmc_enabled_to_disabled(host); 1827 if (lazy || delay < 0) 1828 return delay; 1829 return 0; 1830 } 1831 case DISABLED: 1832 return omap_hsmmc_disabled_to_sleep(host); 1833 case CARDSLEEP: 1834 case REGSLEEP: 1835 return omap_hsmmc_sleep_to_off(host); 1836 default: 1837 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1838 return -EINVAL; 1839 } 1840 } 1841 1842 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1843 { 1844 struct omap_hsmmc_host *host = mmc_priv(mmc); 1845 int err; 1846 1847 err = clk_enable(host->fclk); 1848 if (err) 1849 return err; 1850 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 1851 omap_hsmmc_context_restore(host); 1852 return 0; 1853 } 1854 1855 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1856 { 1857 struct omap_hsmmc_host *host = mmc_priv(mmc); 1858 1859 omap_hsmmc_context_save(host); 1860 clk_disable(host->fclk); 1861 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1862 return 0; 1863 } 1864 1865 static const struct mmc_host_ops omap_hsmmc_ops = { 1866 .enable = omap_hsmmc_enable_fclk, 1867 .disable = omap_hsmmc_disable_fclk, 1868 .request = omap_hsmmc_request, 1869 .set_ios = omap_hsmmc_set_ios, 1870 .get_cd = omap_hsmmc_get_cd, 1871 .get_ro = omap_hsmmc_get_ro, 1872 /* NYET -- enable_sdio_irq */ 1873 }; 1874 1875 static const struct mmc_host_ops omap_hsmmc_ps_ops = { 1876 .enable = omap_hsmmc_enable, 1877 .disable = omap_hsmmc_disable, 1878 .request = omap_hsmmc_request, 1879 .set_ios = omap_hsmmc_set_ios, 1880 .get_cd = omap_hsmmc_get_cd, 1881 .get_ro = omap_hsmmc_get_ro, 1882 /* NYET -- enable_sdio_irq */ 1883 }; 1884 1885 #ifdef CONFIG_DEBUG_FS 1886 1887 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1888 { 1889 struct mmc_host *mmc = s->private; 1890 struct omap_hsmmc_host *host = mmc_priv(mmc); 1891 int context_loss = 0; 1892 1893 if (host->pdata->get_context_loss_count) 1894 context_loss = host->pdata->get_context_loss_count(host->dev); 1895 1896 seq_printf(s, "mmc%d:\n" 1897 " enabled:\t%d\n" 1898 " dpm_state:\t%d\n" 1899 " nesting_cnt:\t%d\n" 1900 " ctx_loss:\t%d:%d\n" 1901 "\nregs:\n", 1902 mmc->index, mmc->enabled ? 1 : 0, 1903 host->dpm_state, mmc->nesting_cnt, 1904 host->context_loss, context_loss); 1905 1906 if (host->suspended || host->dpm_state == OFF) { 1907 seq_printf(s, "host suspended, can't read registers\n"); 1908 return 0; 1909 } 1910 1911 if (clk_enable(host->fclk) != 0) { 1912 seq_printf(s, "can't read the regs\n"); 1913 return 0; 1914 } 1915 1916 seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1917 OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1918 seq_printf(s, "CON:\t\t0x%08x\n", 1919 OMAP_HSMMC_READ(host->base, CON)); 1920 seq_printf(s, "HCTL:\t\t0x%08x\n", 1921 OMAP_HSMMC_READ(host->base, HCTL)); 1922 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1923 OMAP_HSMMC_READ(host->base, SYSCTL)); 1924 seq_printf(s, "IE:\t\t0x%08x\n", 1925 OMAP_HSMMC_READ(host->base, IE)); 1926 seq_printf(s, "ISE:\t\t0x%08x\n", 1927 OMAP_HSMMC_READ(host->base, ISE)); 1928 seq_printf(s, "CAPA:\t\t0x%08x\n", 1929 OMAP_HSMMC_READ(host->base, CAPA)); 1930 1931 clk_disable(host->fclk); 1932 1933 return 0; 1934 } 1935 1936 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1937 { 1938 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1939 } 1940 1941 static const struct file_operations mmc_regs_fops = { 1942 .open = omap_hsmmc_regs_open, 1943 .read = seq_read, 1944 .llseek = seq_lseek, 1945 .release = single_release, 1946 }; 1947 1948 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1949 { 1950 if (mmc->debugfs_root) 1951 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1952 mmc, &mmc_regs_fops); 1953 } 1954 1955 #else 1956 1957 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1958 { 1959 } 1960 1961 #endif 1962 1963 static int __init omap_hsmmc_probe(struct platform_device *pdev) 1964 { 1965 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1966 struct mmc_host *mmc; 1967 struct omap_hsmmc_host *host = NULL; 1968 struct resource *res; 1969 int ret, irq; 1970 1971 if (pdata == NULL) { 1972 dev_err(&pdev->dev, "Platform Data is missing\n"); 1973 return -ENXIO; 1974 } 1975 1976 if (pdata->nr_slots == 0) { 1977 dev_err(&pdev->dev, "No Slots\n"); 1978 return -ENXIO; 1979 } 1980 1981 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1982 irq = platform_get_irq(pdev, 0); 1983 if (res == NULL || irq < 0) 1984 return -ENXIO; 1985 1986 res = request_mem_region(res->start, res->end - res->start + 1, 1987 pdev->name); 1988 if (res == NULL) 1989 return -EBUSY; 1990 1991 ret = omap_hsmmc_gpio_init(pdata); 1992 if (ret) 1993 goto err; 1994 1995 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1996 if (!mmc) { 1997 ret = -ENOMEM; 1998 goto err_alloc; 1999 } 2000 2001 host = mmc_priv(mmc); 2002 host->mmc = mmc; 2003 host->pdata = pdata; 2004 host->dev = &pdev->dev; 2005 host->use_dma = 1; 2006 host->dev->dma_mask = &pdata->dma_mask; 2007 host->dma_ch = -1; 2008 host->irq = irq; 2009 host->id = pdev->id; 2010 host->slot_id = 0; 2011 host->mapbase = res->start; 2012 host->base = ioremap(host->mapbase, SZ_4K); 2013 host->power_mode = MMC_POWER_OFF; 2014 2015 platform_set_drvdata(pdev, host); 2016 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2017 2018 if (mmc_slot(host).power_saving) 2019 mmc->ops = &omap_hsmmc_ps_ops; 2020 else 2021 mmc->ops = &omap_hsmmc_ops; 2022 2023 /* 2024 * If regulator_disable can only put vcc_aux to sleep then there is 2025 * no off state. 2026 */ 2027 if (mmc_slot(host).vcc_aux_disable_is_sleep) 2028 mmc_slot(host).no_off = 1; 2029 2030 mmc->f_min = 400000; 2031 mmc->f_max = 52000000; 2032 2033 spin_lock_init(&host->irq_lock); 2034 2035 host->iclk = clk_get(&pdev->dev, "ick"); 2036 if (IS_ERR(host->iclk)) { 2037 ret = PTR_ERR(host->iclk); 2038 host->iclk = NULL; 2039 goto err1; 2040 } 2041 host->fclk = clk_get(&pdev->dev, "fck"); 2042 if (IS_ERR(host->fclk)) { 2043 ret = PTR_ERR(host->fclk); 2044 host->fclk = NULL; 2045 clk_put(host->iclk); 2046 goto err1; 2047 } 2048 2049 omap_hsmmc_context_save(host); 2050 2051 mmc->caps |= MMC_CAP_DISABLE; 2052 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 2053 /* we start off in DISABLED state */ 2054 host->dpm_state = DISABLED; 2055 2056 if (mmc_host_enable(host->mmc) != 0) { 2057 clk_put(host->iclk); 2058 clk_put(host->fclk); 2059 goto err1; 2060 } 2061 2062 if (clk_enable(host->iclk) != 0) { 2063 mmc_host_disable(host->mmc); 2064 clk_put(host->iclk); 2065 clk_put(host->fclk); 2066 goto err1; 2067 } 2068 2069 if (cpu_is_omap2430()) { 2070 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 2071 /* 2072 * MMC can still work without debounce clock. 2073 */ 2074 if (IS_ERR(host->dbclk)) 2075 dev_warn(mmc_dev(host->mmc), 2076 "Failed to get debounce clock\n"); 2077 else 2078 host->got_dbclk = 1; 2079 2080 if (host->got_dbclk) 2081 if (clk_enable(host->dbclk) != 0) 2082 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 2083 " clk failed\n"); 2084 } 2085 2086 /* Since we do only SG emulation, we can have as many segs 2087 * as we want. */ 2088 mmc->max_phys_segs = 1024; 2089 mmc->max_hw_segs = 1024; 2090 2091 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2092 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2093 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2094 mmc->max_seg_size = mmc->max_req_size; 2095 2096 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2097 MMC_CAP_WAIT_WHILE_BUSY; 2098 2099 if (mmc_slot(host).wires >= 8) 2100 mmc->caps |= MMC_CAP_8_BIT_DATA; 2101 else if (mmc_slot(host).wires >= 4) 2102 mmc->caps |= MMC_CAP_4_BIT_DATA; 2103 2104 if (mmc_slot(host).nonremovable) 2105 mmc->caps |= MMC_CAP_NONREMOVABLE; 2106 2107 omap_hsmmc_conf_bus_power(host); 2108 2109 /* Select DMA lines */ 2110 switch (host->id) { 2111 case OMAP_MMC1_DEVID: 2112 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 2113 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2114 break; 2115 case OMAP_MMC2_DEVID: 2116 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2117 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2118 break; 2119 case OMAP_MMC3_DEVID: 2120 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2121 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2122 break; 2123 case OMAP_MMC4_DEVID: 2124 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 2125 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 2126 break; 2127 case OMAP_MMC5_DEVID: 2128 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 2129 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 2130 break; 2131 default: 2132 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2133 goto err_irq; 2134 } 2135 2136 /* Request IRQ for MMC operations */ 2137 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2138 mmc_hostname(mmc), host); 2139 if (ret) { 2140 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2141 goto err_irq; 2142 } 2143 2144 if (pdata->init != NULL) { 2145 if (pdata->init(&pdev->dev) != 0) { 2146 dev_dbg(mmc_dev(host->mmc), 2147 "Unable to configure MMC IRQs\n"); 2148 goto err_irq_cd_init; 2149 } 2150 } 2151 2152 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2153 ret = omap_hsmmc_reg_get(host); 2154 if (ret) 2155 goto err_reg; 2156 host->use_reg = 1; 2157 } 2158 2159 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2160 2161 /* Request IRQ for card detect */ 2162 if ((mmc_slot(host).card_detect_irq)) { 2163 ret = request_irq(mmc_slot(host).card_detect_irq, 2164 omap_hsmmc_cd_handler, 2165 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2166 | IRQF_DISABLED, 2167 mmc_hostname(mmc), host); 2168 if (ret) { 2169 dev_dbg(mmc_dev(host->mmc), 2170 "Unable to grab MMC CD IRQ\n"); 2171 goto err_irq_cd; 2172 } 2173 } 2174 2175 omap_hsmmc_disable_irq(host); 2176 2177 mmc_host_lazy_disable(host->mmc); 2178 2179 omap_hsmmc_protect_card(host); 2180 2181 mmc_add_host(mmc); 2182 2183 if (mmc_slot(host).name != NULL) { 2184 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2185 if (ret < 0) 2186 goto err_slot_name; 2187 } 2188 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2189 ret = device_create_file(&mmc->class_dev, 2190 &dev_attr_cover_switch); 2191 if (ret < 0) 2192 goto err_slot_name; 2193 } 2194 2195 omap_hsmmc_debugfs(mmc); 2196 2197 return 0; 2198 2199 err_slot_name: 2200 mmc_remove_host(mmc); 2201 free_irq(mmc_slot(host).card_detect_irq, host); 2202 err_irq_cd: 2203 if (host->use_reg) 2204 omap_hsmmc_reg_put(host); 2205 err_reg: 2206 if (host->pdata->cleanup) 2207 host->pdata->cleanup(&pdev->dev); 2208 err_irq_cd_init: 2209 free_irq(host->irq, host); 2210 err_irq: 2211 mmc_host_disable(host->mmc); 2212 clk_disable(host->iclk); 2213 clk_put(host->fclk); 2214 clk_put(host->iclk); 2215 if (host->got_dbclk) { 2216 clk_disable(host->dbclk); 2217 clk_put(host->dbclk); 2218 } 2219 err1: 2220 iounmap(host->base); 2221 platform_set_drvdata(pdev, NULL); 2222 mmc_free_host(mmc); 2223 err_alloc: 2224 omap_hsmmc_gpio_free(pdata); 2225 err: 2226 release_mem_region(res->start, res->end - res->start + 1); 2227 return ret; 2228 } 2229 2230 static int omap_hsmmc_remove(struct platform_device *pdev) 2231 { 2232 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2233 struct resource *res; 2234 2235 if (host) { 2236 mmc_host_enable(host->mmc); 2237 mmc_remove_host(host->mmc); 2238 if (host->use_reg) 2239 omap_hsmmc_reg_put(host); 2240 if (host->pdata->cleanup) 2241 host->pdata->cleanup(&pdev->dev); 2242 free_irq(host->irq, host); 2243 if (mmc_slot(host).card_detect_irq) 2244 free_irq(mmc_slot(host).card_detect_irq, host); 2245 flush_scheduled_work(); 2246 2247 mmc_host_disable(host->mmc); 2248 clk_disable(host->iclk); 2249 clk_put(host->fclk); 2250 clk_put(host->iclk); 2251 if (host->got_dbclk) { 2252 clk_disable(host->dbclk); 2253 clk_put(host->dbclk); 2254 } 2255 2256 mmc_free_host(host->mmc); 2257 iounmap(host->base); 2258 omap_hsmmc_gpio_free(pdev->dev.platform_data); 2259 } 2260 2261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2262 if (res) 2263 release_mem_region(res->start, res->end - res->start + 1); 2264 platform_set_drvdata(pdev, NULL); 2265 2266 return 0; 2267 } 2268 2269 #ifdef CONFIG_PM 2270 static int omap_hsmmc_suspend(struct device *dev) 2271 { 2272 int ret = 0; 2273 struct platform_device *pdev = to_platform_device(dev); 2274 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2275 pm_message_t state = PMSG_SUSPEND; /* unused by MMC core */ 2276 2277 if (host && host->suspended) 2278 return 0; 2279 2280 if (host) { 2281 host->suspended = 1; 2282 if (host->pdata->suspend) { 2283 ret = host->pdata->suspend(&pdev->dev, 2284 host->slot_id); 2285 if (ret) { 2286 dev_dbg(mmc_dev(host->mmc), 2287 "Unable to handle MMC board" 2288 " level suspend\n"); 2289 host->suspended = 0; 2290 return ret; 2291 } 2292 } 2293 cancel_work_sync(&host->mmc_carddetect_work); 2294 mmc_host_enable(host->mmc); 2295 ret = mmc_suspend_host(host->mmc, state); 2296 if (ret == 0) { 2297 omap_hsmmc_disable_irq(host); 2298 OMAP_HSMMC_WRITE(host->base, HCTL, 2299 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2300 mmc_host_disable(host->mmc); 2301 clk_disable(host->iclk); 2302 if (host->got_dbclk) 2303 clk_disable(host->dbclk); 2304 } else { 2305 host->suspended = 0; 2306 if (host->pdata->resume) { 2307 ret = host->pdata->resume(&pdev->dev, 2308 host->slot_id); 2309 if (ret) 2310 dev_dbg(mmc_dev(host->mmc), 2311 "Unmask interrupt failed\n"); 2312 } 2313 mmc_host_disable(host->mmc); 2314 } 2315 2316 } 2317 return ret; 2318 } 2319 2320 /* Routine to resume the MMC device */ 2321 static int omap_hsmmc_resume(struct device *dev) 2322 { 2323 int ret = 0; 2324 struct platform_device *pdev = to_platform_device(dev); 2325 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2326 2327 if (host && !host->suspended) 2328 return 0; 2329 2330 if (host) { 2331 ret = clk_enable(host->iclk); 2332 if (ret) 2333 goto clk_en_err; 2334 2335 if (mmc_host_enable(host->mmc) != 0) { 2336 clk_disable(host->iclk); 2337 goto clk_en_err; 2338 } 2339 2340 if (host->got_dbclk) 2341 clk_enable(host->dbclk); 2342 2343 omap_hsmmc_conf_bus_power(host); 2344 2345 if (host->pdata->resume) { 2346 ret = host->pdata->resume(&pdev->dev, host->slot_id); 2347 if (ret) 2348 dev_dbg(mmc_dev(host->mmc), 2349 "Unmask interrupt failed\n"); 2350 } 2351 2352 omap_hsmmc_protect_card(host); 2353 2354 /* Notify the core to resume the host */ 2355 ret = mmc_resume_host(host->mmc); 2356 if (ret == 0) 2357 host->suspended = 0; 2358 2359 mmc_host_lazy_disable(host->mmc); 2360 } 2361 2362 return ret; 2363 2364 clk_en_err: 2365 dev_dbg(mmc_dev(host->mmc), 2366 "Failed to enable MMC clocks during resume\n"); 2367 return ret; 2368 } 2369 2370 #else 2371 #define omap_hsmmc_suspend NULL 2372 #define omap_hsmmc_resume NULL 2373 #endif 2374 2375 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2376 .suspend = omap_hsmmc_suspend, 2377 .resume = omap_hsmmc_resume, 2378 }; 2379 2380 static struct platform_driver omap_hsmmc_driver = { 2381 .remove = omap_hsmmc_remove, 2382 .driver = { 2383 .name = DRIVER_NAME, 2384 .owner = THIS_MODULE, 2385 .pm = &omap_hsmmc_dev_pm_ops, 2386 }, 2387 }; 2388 2389 static int __init omap_hsmmc_init(void) 2390 { 2391 /* Register the MMC driver */ 2392 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2393 } 2394 2395 static void __exit omap_hsmmc_cleanup(void) 2396 { 2397 /* Unregister MMC driver */ 2398 platform_driver_unregister(&omap_hsmmc_driver); 2399 } 2400 2401 module_init(omap_hsmmc_init); 2402 module_exit(omap_hsmmc_cleanup); 2403 2404 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2405 MODULE_LICENSE("GPL"); 2406 MODULE_ALIAS("platform:" DRIVER_NAME); 2407 MODULE_AUTHOR("Texas Instruments Inc"); 2408