1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/sizes.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/timer.h> 30 #include <linux/clk.h> 31 #include <linux/of.h> 32 #include <linux/of_gpio.h> 33 #include <linux/of_device.h> 34 #include <linux/omap-dma.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/core.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/io.h> 39 #include <linux/gpio.h> 40 #include <linux/regulator/consumer.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/platform_data/mmc-omap.h> 44 45 /* OMAP HSMMC Host Controller Registers */ 46 #define OMAP_HSMMC_SYSSTATUS 0x0014 47 #define OMAP_HSMMC_CON 0x002C 48 #define OMAP_HSMMC_SDMASA 0x0100 49 #define OMAP_HSMMC_BLK 0x0104 50 #define OMAP_HSMMC_ARG 0x0108 51 #define OMAP_HSMMC_CMD 0x010C 52 #define OMAP_HSMMC_RSP10 0x0110 53 #define OMAP_HSMMC_RSP32 0x0114 54 #define OMAP_HSMMC_RSP54 0x0118 55 #define OMAP_HSMMC_RSP76 0x011C 56 #define OMAP_HSMMC_DATA 0x0120 57 #define OMAP_HSMMC_HCTL 0x0128 58 #define OMAP_HSMMC_SYSCTL 0x012C 59 #define OMAP_HSMMC_STAT 0x0130 60 #define OMAP_HSMMC_IE 0x0134 61 #define OMAP_HSMMC_ISE 0x0138 62 #define OMAP_HSMMC_AC12 0x013C 63 #define OMAP_HSMMC_CAPA 0x0140 64 65 #define VS18 (1 << 26) 66 #define VS30 (1 << 25) 67 #define HSS (1 << 21) 68 #define SDVS18 (0x5 << 9) 69 #define SDVS30 (0x6 << 9) 70 #define SDVS33 (0x7 << 9) 71 #define SDVS_MASK 0x00000E00 72 #define SDVSCLR 0xFFFFF1FF 73 #define SDVSDET 0x00000400 74 #define AUTOIDLE 0x1 75 #define SDBP (1 << 8) 76 #define DTO 0xe 77 #define ICE 0x1 78 #define ICS 0x2 79 #define CEN (1 << 2) 80 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 81 #define CLKD_MASK 0x0000FFC0 82 #define CLKD_SHIFT 6 83 #define DTO_MASK 0x000F0000 84 #define DTO_SHIFT 16 85 #define INIT_STREAM (1 << 1) 86 #define ACEN_ACMD23 (2 << 2) 87 #define DP_SELECT (1 << 21) 88 #define DDIR (1 << 4) 89 #define DMAE 0x1 90 #define MSBS (1 << 5) 91 #define BCE (1 << 1) 92 #define FOUR_BIT (1 << 1) 93 #define HSPE (1 << 2) 94 #define DDR (1 << 19) 95 #define DW8 (1 << 5) 96 #define OD 0x1 97 #define STAT_CLEAR 0xFFFFFFFF 98 #define INIT_STREAM_CMD 0x00000000 99 #define DUAL_VOLT_OCR_BIT 7 100 #define SRC (1 << 25) 101 #define SRD (1 << 26) 102 #define SOFTRESET (1 << 1) 103 104 /* Interrupt masks for IE and ISE register */ 105 #define CC_EN (1 << 0) 106 #define TC_EN (1 << 1) 107 #define BWR_EN (1 << 4) 108 #define BRR_EN (1 << 5) 109 #define ERR_EN (1 << 15) 110 #define CTO_EN (1 << 16) 111 #define CCRC_EN (1 << 17) 112 #define CEB_EN (1 << 18) 113 #define CIE_EN (1 << 19) 114 #define DTO_EN (1 << 20) 115 #define DCRC_EN (1 << 21) 116 #define DEB_EN (1 << 22) 117 #define ACE_EN (1 << 24) 118 #define CERR_EN (1 << 28) 119 #define BADA_EN (1 << 29) 120 121 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 122 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 123 BRR_EN | BWR_EN | TC_EN | CC_EN) 124 125 #define CNI (1 << 7) 126 #define ACIE (1 << 4) 127 #define ACEB (1 << 3) 128 #define ACCE (1 << 2) 129 #define ACTO (1 << 1) 130 #define ACNE (1 << 0) 131 132 #define MMC_AUTOSUSPEND_DELAY 100 133 #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 134 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 135 #define OMAP_MMC_MIN_CLOCK 400000 136 #define OMAP_MMC_MAX_CLOCK 52000000 137 #define DRIVER_NAME "omap_hsmmc" 138 139 #define VDD_1V8 1800000 /* 180000 uV */ 140 #define VDD_3V0 3000000 /* 300000 uV */ 141 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 142 143 #define AUTO_CMD23 (1 << 1) /* Auto CMD23 support */ 144 /* 145 * One controller can have multiple slots, like on some omap boards using 146 * omap.c controller driver. Luckily this is not currently done on any known 147 * omap_hsmmc.c device. 148 */ 149 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 150 151 /* 152 * MMC Host controller read/write API's 153 */ 154 #define OMAP_HSMMC_READ(base, reg) \ 155 __raw_readl((base) + OMAP_HSMMC_##reg) 156 157 #define OMAP_HSMMC_WRITE(base, reg, val) \ 158 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 159 160 struct omap_hsmmc_next { 161 unsigned int dma_len; 162 s32 cookie; 163 }; 164 165 struct omap_hsmmc_host { 166 struct device *dev; 167 struct mmc_host *mmc; 168 struct mmc_request *mrq; 169 struct mmc_command *cmd; 170 struct mmc_data *data; 171 struct clk *fclk; 172 struct clk *dbclk; 173 /* 174 * vcc == configured supply 175 * vcc_aux == optional 176 * - MMC1, supply for DAT4..DAT7 177 * - MMC2/MMC2, external level shifter voltage supply, for 178 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 179 */ 180 struct regulator *vcc; 181 struct regulator *vcc_aux; 182 struct regulator *pbias; 183 bool pbias_enabled; 184 void __iomem *base; 185 resource_size_t mapbase; 186 spinlock_t irq_lock; /* Prevent races with irq handler */ 187 unsigned int dma_len; 188 unsigned int dma_sg_idx; 189 unsigned char bus_mode; 190 unsigned char power_mode; 191 int suspended; 192 u32 con; 193 u32 hctl; 194 u32 sysctl; 195 u32 capa; 196 int irq; 197 int use_dma, dma_ch; 198 struct dma_chan *tx_chan; 199 struct dma_chan *rx_chan; 200 int slot_id; 201 int response_busy; 202 int context_loss; 203 int protect_card; 204 int reqs_blocked; 205 int use_reg; 206 int req_in_progress; 207 unsigned long clk_rate; 208 unsigned int flags; 209 struct omap_hsmmc_next next_data; 210 struct omap_mmc_platform_data *pdata; 211 }; 212 213 struct omap_mmc_of_data { 214 u32 reg_offset; 215 u8 controller_flags; 216 }; 217 218 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 219 220 static int omap_hsmmc_card_detect(struct device *dev, int slot) 221 { 222 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 223 struct omap_mmc_platform_data *mmc = host->pdata; 224 225 /* NOTE: assumes card detect signal is active-low */ 226 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 227 } 228 229 static int omap_hsmmc_get_wp(struct device *dev, int slot) 230 { 231 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 232 struct omap_mmc_platform_data *mmc = host->pdata; 233 234 /* NOTE: assumes write protect signal is active-high */ 235 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 236 } 237 238 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 239 { 240 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 241 struct omap_mmc_platform_data *mmc = host->pdata; 242 243 /* NOTE: assumes card detect signal is active-low */ 244 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 245 } 246 247 #ifdef CONFIG_PM 248 249 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 250 { 251 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 252 struct omap_mmc_platform_data *mmc = host->pdata; 253 254 disable_irq(mmc->slots[0].card_detect_irq); 255 return 0; 256 } 257 258 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 259 { 260 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 261 struct omap_mmc_platform_data *mmc = host->pdata; 262 263 enable_irq(mmc->slots[0].card_detect_irq); 264 return 0; 265 } 266 267 #else 268 269 #define omap_hsmmc_suspend_cdirq NULL 270 #define omap_hsmmc_resume_cdirq NULL 271 272 #endif 273 274 #ifdef CONFIG_REGULATOR 275 276 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 277 int vdd) 278 { 279 struct omap_hsmmc_host *host = 280 platform_get_drvdata(to_platform_device(dev)); 281 int ret = 0; 282 283 /* 284 * If we don't see a Vcc regulator, assume it's a fixed 285 * voltage always-on regulator. 286 */ 287 if (!host->vcc) 288 return 0; 289 290 if (mmc_slot(host).before_set_reg) 291 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 292 293 if (host->pbias) { 294 if (host->pbias_enabled == 1) { 295 ret = regulator_disable(host->pbias); 296 if (!ret) 297 host->pbias_enabled = 0; 298 } 299 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 300 } 301 302 /* 303 * Assume Vcc regulator is used only to power the card ... OMAP 304 * VDDS is used to power the pins, optionally with a transceiver to 305 * support cards using voltages other than VDDS (1.8V nominal). When a 306 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 307 * 308 * In some cases this regulator won't support enable/disable; 309 * e.g. it's a fixed rail for a WLAN chip. 310 * 311 * In other cases vcc_aux switches interface power. Example, for 312 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 313 * chips/cards need an interface voltage rail too. 314 */ 315 if (power_on) { 316 if (host->vcc) 317 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 318 /* Enable interface voltage rail, if needed */ 319 if (ret == 0 && host->vcc_aux) { 320 ret = regulator_enable(host->vcc_aux); 321 if (ret < 0 && host->vcc) 322 ret = mmc_regulator_set_ocr(host->mmc, 323 host->vcc, 0); 324 } 325 } else { 326 /* Shut down the rail */ 327 if (host->vcc_aux) 328 ret = regulator_disable(host->vcc_aux); 329 if (host->vcc) { 330 /* Then proceed to shut down the local regulator */ 331 ret = mmc_regulator_set_ocr(host->mmc, 332 host->vcc, 0); 333 } 334 } 335 336 if (host->pbias) { 337 if (vdd <= VDD_165_195) 338 ret = regulator_set_voltage(host->pbias, VDD_1V8, 339 VDD_1V8); 340 else 341 ret = regulator_set_voltage(host->pbias, VDD_3V0, 342 VDD_3V0); 343 if (ret < 0) 344 goto error_set_power; 345 346 if (host->pbias_enabled == 0) { 347 ret = regulator_enable(host->pbias); 348 if (!ret) 349 host->pbias_enabled = 1; 350 } 351 } 352 353 if (mmc_slot(host).after_set_reg) 354 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 355 356 error_set_power: 357 return ret; 358 } 359 360 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 361 { 362 struct regulator *reg; 363 int ocr_value = 0; 364 365 reg = devm_regulator_get(host->dev, "vmmc"); 366 if (IS_ERR(reg)) { 367 dev_err(host->dev, "unable to get vmmc regulator %ld\n", 368 PTR_ERR(reg)); 369 return PTR_ERR(reg); 370 } else { 371 host->vcc = reg; 372 ocr_value = mmc_regulator_get_ocrmask(reg); 373 if (!mmc_slot(host).ocr_mask) { 374 mmc_slot(host).ocr_mask = ocr_value; 375 } else { 376 if (!(mmc_slot(host).ocr_mask & ocr_value)) { 377 dev_err(host->dev, "ocrmask %x is not supported\n", 378 mmc_slot(host).ocr_mask); 379 mmc_slot(host).ocr_mask = 0; 380 return -EINVAL; 381 } 382 } 383 } 384 mmc_slot(host).set_power = omap_hsmmc_set_power; 385 386 /* Allow an aux regulator */ 387 reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 388 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 389 390 reg = devm_regulator_get_optional(host->dev, "pbias"); 391 host->pbias = IS_ERR(reg) ? NULL : reg; 392 393 /* For eMMC do not power off when not in sleep state */ 394 if (mmc_slot(host).no_regulator_off_init) 395 return 0; 396 /* 397 * To disable boot_on regulator, enable regulator 398 * to increase usecount and then disable it. 399 */ 400 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 401 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 402 int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 403 404 mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 405 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 406 } 407 408 return 0; 409 } 410 411 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 412 { 413 mmc_slot(host).set_power = NULL; 414 } 415 416 static inline int omap_hsmmc_have_reg(void) 417 { 418 return 1; 419 } 420 421 #else 422 423 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 424 { 425 return -EINVAL; 426 } 427 428 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 429 { 430 } 431 432 static inline int omap_hsmmc_have_reg(void) 433 { 434 return 0; 435 } 436 437 #endif 438 439 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 440 { 441 int ret; 442 443 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 444 if (pdata->slots[0].cover) 445 pdata->slots[0].get_cover_state = 446 omap_hsmmc_get_cover_state; 447 else 448 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 449 pdata->slots[0].card_detect_irq = 450 gpio_to_irq(pdata->slots[0].switch_pin); 451 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 452 if (ret) 453 return ret; 454 ret = gpio_direction_input(pdata->slots[0].switch_pin); 455 if (ret) 456 goto err_free_sp; 457 } else 458 pdata->slots[0].switch_pin = -EINVAL; 459 460 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 461 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 462 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 463 if (ret) 464 goto err_free_cd; 465 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 466 if (ret) 467 goto err_free_wp; 468 } else 469 pdata->slots[0].gpio_wp = -EINVAL; 470 471 return 0; 472 473 err_free_wp: 474 gpio_free(pdata->slots[0].gpio_wp); 475 err_free_cd: 476 if (gpio_is_valid(pdata->slots[0].switch_pin)) 477 err_free_sp: 478 gpio_free(pdata->slots[0].switch_pin); 479 return ret; 480 } 481 482 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 483 { 484 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 485 gpio_free(pdata->slots[0].gpio_wp); 486 if (gpio_is_valid(pdata->slots[0].switch_pin)) 487 gpio_free(pdata->slots[0].switch_pin); 488 } 489 490 /* 491 * Start clock to the card 492 */ 493 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 494 { 495 OMAP_HSMMC_WRITE(host->base, SYSCTL, 496 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 497 } 498 499 /* 500 * Stop clock to the card 501 */ 502 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 503 { 504 OMAP_HSMMC_WRITE(host->base, SYSCTL, 505 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 506 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 507 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 508 } 509 510 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 511 struct mmc_command *cmd) 512 { 513 unsigned int irq_mask; 514 515 if (host->use_dma) 516 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 517 else 518 irq_mask = INT_EN_MASK; 519 520 /* Disable timeout for erases */ 521 if (cmd->opcode == MMC_ERASE) 522 irq_mask &= ~DTO_EN; 523 524 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 525 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 526 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 527 } 528 529 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 530 { 531 OMAP_HSMMC_WRITE(host->base, ISE, 0); 532 OMAP_HSMMC_WRITE(host->base, IE, 0); 533 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 534 } 535 536 /* Calculate divisor for the given clock frequency */ 537 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 538 { 539 u16 dsor = 0; 540 541 if (ios->clock) { 542 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 543 if (dsor > CLKD_MAX) 544 dsor = CLKD_MAX; 545 } 546 547 return dsor; 548 } 549 550 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 551 { 552 struct mmc_ios *ios = &host->mmc->ios; 553 unsigned long regval; 554 unsigned long timeout; 555 unsigned long clkdiv; 556 557 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 558 559 omap_hsmmc_stop_clock(host); 560 561 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 562 regval = regval & ~(CLKD_MASK | DTO_MASK); 563 clkdiv = calc_divisor(host, ios); 564 regval = regval | (clkdiv << 6) | (DTO << 16); 565 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 566 OMAP_HSMMC_WRITE(host->base, SYSCTL, 567 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 568 569 /* Wait till the ICS bit is set */ 570 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 571 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 572 && time_before(jiffies, timeout)) 573 cpu_relax(); 574 575 /* 576 * Enable High-Speed Support 577 * Pre-Requisites 578 * - Controller should support High-Speed-Enable Bit 579 * - Controller should not be using DDR Mode 580 * - Controller should advertise that it supports High Speed 581 * in capabilities register 582 * - MMC/SD clock coming out of controller > 25MHz 583 */ 584 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 585 (ios->timing != MMC_TIMING_MMC_DDR52) && 586 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 587 regval = OMAP_HSMMC_READ(host->base, HCTL); 588 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 589 regval |= HSPE; 590 else 591 regval &= ~HSPE; 592 593 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 594 } 595 596 omap_hsmmc_start_clock(host); 597 } 598 599 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 600 { 601 struct mmc_ios *ios = &host->mmc->ios; 602 u32 con; 603 604 con = OMAP_HSMMC_READ(host->base, CON); 605 if (ios->timing == MMC_TIMING_MMC_DDR52) 606 con |= DDR; /* configure in DDR mode */ 607 else 608 con &= ~DDR; 609 switch (ios->bus_width) { 610 case MMC_BUS_WIDTH_8: 611 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 612 break; 613 case MMC_BUS_WIDTH_4: 614 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 615 OMAP_HSMMC_WRITE(host->base, HCTL, 616 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 617 break; 618 case MMC_BUS_WIDTH_1: 619 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 620 OMAP_HSMMC_WRITE(host->base, HCTL, 621 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 622 break; 623 } 624 } 625 626 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 627 { 628 struct mmc_ios *ios = &host->mmc->ios; 629 u32 con; 630 631 con = OMAP_HSMMC_READ(host->base, CON); 632 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 633 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 634 else 635 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 636 } 637 638 #ifdef CONFIG_PM 639 640 /* 641 * Restore the MMC host context, if it was lost as result of a 642 * power state change. 643 */ 644 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 645 { 646 struct mmc_ios *ios = &host->mmc->ios; 647 u32 hctl, capa; 648 unsigned long timeout; 649 650 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 651 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 652 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 653 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 654 return 0; 655 656 host->context_loss++; 657 658 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 659 if (host->power_mode != MMC_POWER_OFF && 660 (1 << ios->vdd) <= MMC_VDD_23_24) 661 hctl = SDVS18; 662 else 663 hctl = SDVS30; 664 capa = VS30 | VS18; 665 } else { 666 hctl = SDVS18; 667 capa = VS18; 668 } 669 670 OMAP_HSMMC_WRITE(host->base, HCTL, 671 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 672 673 OMAP_HSMMC_WRITE(host->base, CAPA, 674 OMAP_HSMMC_READ(host->base, CAPA) | capa); 675 676 OMAP_HSMMC_WRITE(host->base, HCTL, 677 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 678 679 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 680 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 681 && time_before(jiffies, timeout)) 682 ; 683 684 omap_hsmmc_disable_irq(host); 685 686 /* Do not initialize card-specific things if the power is off */ 687 if (host->power_mode == MMC_POWER_OFF) 688 goto out; 689 690 omap_hsmmc_set_bus_width(host); 691 692 omap_hsmmc_set_clock(host); 693 694 omap_hsmmc_set_bus_mode(host); 695 696 out: 697 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 698 host->context_loss); 699 return 0; 700 } 701 702 /* 703 * Save the MMC host context (store the number of power state changes so far). 704 */ 705 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 706 { 707 host->con = OMAP_HSMMC_READ(host->base, CON); 708 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 709 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 710 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 711 } 712 713 #else 714 715 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 716 { 717 return 0; 718 } 719 720 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 721 { 722 } 723 724 #endif 725 726 /* 727 * Send init stream sequence to card 728 * before sending IDLE command 729 */ 730 static void send_init_stream(struct omap_hsmmc_host *host) 731 { 732 int reg = 0; 733 unsigned long timeout; 734 735 if (host->protect_card) 736 return; 737 738 disable_irq(host->irq); 739 740 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 741 OMAP_HSMMC_WRITE(host->base, CON, 742 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 743 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 744 745 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 746 while ((reg != CC_EN) && time_before(jiffies, timeout)) 747 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 748 749 OMAP_HSMMC_WRITE(host->base, CON, 750 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 751 752 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 753 OMAP_HSMMC_READ(host->base, STAT); 754 755 enable_irq(host->irq); 756 } 757 758 static inline 759 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 760 { 761 int r = 1; 762 763 if (mmc_slot(host).get_cover_state) 764 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 765 return r; 766 } 767 768 static ssize_t 769 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 770 char *buf) 771 { 772 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 773 struct omap_hsmmc_host *host = mmc_priv(mmc); 774 775 return sprintf(buf, "%s\n", 776 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 777 } 778 779 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 780 781 static ssize_t 782 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 783 char *buf) 784 { 785 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 786 struct omap_hsmmc_host *host = mmc_priv(mmc); 787 788 return sprintf(buf, "%s\n", mmc_slot(host).name); 789 } 790 791 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 792 793 /* 794 * Configure the response type and send the cmd. 795 */ 796 static void 797 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 798 struct mmc_data *data) 799 { 800 int cmdreg = 0, resptype = 0, cmdtype = 0; 801 802 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 803 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 804 host->cmd = cmd; 805 806 omap_hsmmc_enable_irq(host, cmd); 807 808 host->response_busy = 0; 809 if (cmd->flags & MMC_RSP_PRESENT) { 810 if (cmd->flags & MMC_RSP_136) 811 resptype = 1; 812 else if (cmd->flags & MMC_RSP_BUSY) { 813 resptype = 3; 814 host->response_busy = 1; 815 } else 816 resptype = 2; 817 } 818 819 /* 820 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 821 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 822 * a val of 0x3, rest 0x0. 823 */ 824 if (cmd == host->mrq->stop) 825 cmdtype = 0x3; 826 827 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 828 829 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 830 host->mrq->sbc) { 831 cmdreg |= ACEN_ACMD23; 832 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 833 } 834 if (data) { 835 cmdreg |= DP_SELECT | MSBS | BCE; 836 if (data->flags & MMC_DATA_READ) 837 cmdreg |= DDIR; 838 else 839 cmdreg &= ~(DDIR); 840 } 841 842 if (host->use_dma) 843 cmdreg |= DMAE; 844 845 host->req_in_progress = 1; 846 847 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 848 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 849 } 850 851 static int 852 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 853 { 854 if (data->flags & MMC_DATA_WRITE) 855 return DMA_TO_DEVICE; 856 else 857 return DMA_FROM_DEVICE; 858 } 859 860 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 861 struct mmc_data *data) 862 { 863 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 864 } 865 866 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 867 { 868 int dma_ch; 869 unsigned long flags; 870 871 spin_lock_irqsave(&host->irq_lock, flags); 872 host->req_in_progress = 0; 873 dma_ch = host->dma_ch; 874 spin_unlock_irqrestore(&host->irq_lock, flags); 875 876 omap_hsmmc_disable_irq(host); 877 /* Do not complete the request if DMA is still in progress */ 878 if (mrq->data && host->use_dma && dma_ch != -1) 879 return; 880 host->mrq = NULL; 881 mmc_request_done(host->mmc, mrq); 882 } 883 884 /* 885 * Notify the transfer complete to MMC core 886 */ 887 static void 888 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 889 { 890 if (!data) { 891 struct mmc_request *mrq = host->mrq; 892 893 /* TC before CC from CMD6 - don't know why, but it happens */ 894 if (host->cmd && host->cmd->opcode == 6 && 895 host->response_busy) { 896 host->response_busy = 0; 897 return; 898 } 899 900 omap_hsmmc_request_done(host, mrq); 901 return; 902 } 903 904 host->data = NULL; 905 906 if (!data->error) 907 data->bytes_xfered += data->blocks * (data->blksz); 908 else 909 data->bytes_xfered = 0; 910 911 if (data->stop && (data->error || !host->mrq->sbc)) 912 omap_hsmmc_start_command(host, data->stop, NULL); 913 else 914 omap_hsmmc_request_done(host, data->mrq); 915 } 916 917 /* 918 * Notify the core about command completion 919 */ 920 static void 921 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 922 { 923 host->cmd = NULL; 924 925 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 926 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 927 omap_hsmmc_start_dma_transfer(host); 928 omap_hsmmc_start_command(host, host->mrq->cmd, 929 host->mrq->data); 930 return; 931 } 932 933 if (cmd->flags & MMC_RSP_PRESENT) { 934 if (cmd->flags & MMC_RSP_136) { 935 /* response type 2 */ 936 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 937 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 938 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 939 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 940 } else { 941 /* response types 1, 1b, 3, 4, 5, 6 */ 942 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 943 } 944 } 945 if ((host->data == NULL && !host->response_busy) || cmd->error) 946 omap_hsmmc_request_done(host, host->mrq); 947 } 948 949 /* 950 * DMA clean up for command errors 951 */ 952 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 953 { 954 int dma_ch; 955 unsigned long flags; 956 957 host->data->error = errno; 958 959 spin_lock_irqsave(&host->irq_lock, flags); 960 dma_ch = host->dma_ch; 961 host->dma_ch = -1; 962 spin_unlock_irqrestore(&host->irq_lock, flags); 963 964 if (host->use_dma && dma_ch != -1) { 965 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 966 967 dmaengine_terminate_all(chan); 968 dma_unmap_sg(chan->device->dev, 969 host->data->sg, host->data->sg_len, 970 omap_hsmmc_get_dma_dir(host, host->data)); 971 972 host->data->host_cookie = 0; 973 } 974 host->data = NULL; 975 } 976 977 /* 978 * Readable error output 979 */ 980 #ifdef CONFIG_MMC_DEBUG 981 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 982 { 983 /* --- means reserved bit without definition at documentation */ 984 static const char *omap_hsmmc_status_bits[] = { 985 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 986 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 987 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 988 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 989 }; 990 char res[256]; 991 char *buf = res; 992 int len, i; 993 994 len = sprintf(buf, "MMC IRQ 0x%x :", status); 995 buf += len; 996 997 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 998 if (status & (1 << i)) { 999 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1000 buf += len; 1001 } 1002 1003 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1004 } 1005 #else 1006 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1007 u32 status) 1008 { 1009 } 1010 #endif /* CONFIG_MMC_DEBUG */ 1011 1012 /* 1013 * MMC controller internal state machines reset 1014 * 1015 * Used to reset command or data internal state machines, using respectively 1016 * SRC or SRD bit of SYSCTL register 1017 * Can be called from interrupt context 1018 */ 1019 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 1020 unsigned long bit) 1021 { 1022 unsigned long i = 0; 1023 unsigned long limit = MMC_TIMEOUT_US; 1024 1025 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1026 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 1027 1028 /* 1029 * OMAP4 ES2 and greater has an updated reset logic. 1030 * Monitor a 0->1 transition first 1031 */ 1032 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1033 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 1034 && (i++ < limit)) 1035 udelay(1); 1036 } 1037 i = 0; 1038 1039 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 1040 (i++ < limit)) 1041 udelay(1); 1042 1043 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1044 dev_err(mmc_dev(host->mmc), 1045 "Timeout waiting on controller reset in %s\n", 1046 __func__); 1047 } 1048 1049 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1050 int err, int end_cmd) 1051 { 1052 if (end_cmd) { 1053 omap_hsmmc_reset_controller_fsm(host, SRC); 1054 if (host->cmd) 1055 host->cmd->error = err; 1056 } 1057 1058 if (host->data) { 1059 omap_hsmmc_reset_controller_fsm(host, SRD); 1060 omap_hsmmc_dma_cleanup(host, err); 1061 } else if (host->mrq && host->mrq->cmd) 1062 host->mrq->cmd->error = err; 1063 } 1064 1065 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1066 { 1067 struct mmc_data *data; 1068 int end_cmd = 0, end_trans = 0; 1069 int error = 0; 1070 1071 data = host->data; 1072 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1073 1074 if (status & ERR_EN) { 1075 omap_hsmmc_dbg_report_irq(host, status); 1076 1077 if (status & (CTO_EN | CCRC_EN)) 1078 end_cmd = 1; 1079 if (status & (CTO_EN | DTO_EN)) 1080 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1081 else if (status & (CCRC_EN | DCRC_EN)) 1082 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1083 1084 if (status & ACE_EN) { 1085 u32 ac12; 1086 ac12 = OMAP_HSMMC_READ(host->base, AC12); 1087 if (!(ac12 & ACNE) && host->mrq->sbc) { 1088 end_cmd = 1; 1089 if (ac12 & ACTO) 1090 error = -ETIMEDOUT; 1091 else if (ac12 & (ACCE | ACEB | ACIE)) 1092 error = -EILSEQ; 1093 host->mrq->sbc->error = error; 1094 hsmmc_command_incomplete(host, error, end_cmd); 1095 } 1096 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1097 } 1098 if (host->data || host->response_busy) { 1099 end_trans = !end_cmd; 1100 host->response_busy = 0; 1101 } 1102 } 1103 1104 OMAP_HSMMC_WRITE(host->base, STAT, status); 1105 if (end_cmd || ((status & CC_EN) && host->cmd)) 1106 omap_hsmmc_cmd_done(host, host->cmd); 1107 if ((end_trans || (status & TC_EN)) && host->mrq) 1108 omap_hsmmc_xfer_done(host, data); 1109 } 1110 1111 /* 1112 * MMC controller IRQ handler 1113 */ 1114 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1115 { 1116 struct omap_hsmmc_host *host = dev_id; 1117 int status; 1118 1119 status = OMAP_HSMMC_READ(host->base, STAT); 1120 while (status & INT_EN_MASK && host->req_in_progress) { 1121 omap_hsmmc_do_irq(host, status); 1122 1123 /* Flush posted write */ 1124 status = OMAP_HSMMC_READ(host->base, STAT); 1125 } 1126 1127 return IRQ_HANDLED; 1128 } 1129 1130 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1131 { 1132 unsigned long i; 1133 1134 OMAP_HSMMC_WRITE(host->base, HCTL, 1135 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1136 for (i = 0; i < loops_per_jiffy; i++) { 1137 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1138 break; 1139 cpu_relax(); 1140 } 1141 } 1142 1143 /* 1144 * Switch MMC interface voltage ... only relevant for MMC1. 1145 * 1146 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1147 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1148 * Some chips, like eMMC ones, use internal transceivers. 1149 */ 1150 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1151 { 1152 u32 reg_val = 0; 1153 int ret; 1154 1155 /* Disable the clocks */ 1156 pm_runtime_put_sync(host->dev); 1157 if (host->dbclk) 1158 clk_disable_unprepare(host->dbclk); 1159 1160 /* Turn the power off */ 1161 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1162 1163 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1164 if (!ret) 1165 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1166 vdd); 1167 pm_runtime_get_sync(host->dev); 1168 if (host->dbclk) 1169 clk_prepare_enable(host->dbclk); 1170 1171 if (ret != 0) 1172 goto err; 1173 1174 OMAP_HSMMC_WRITE(host->base, HCTL, 1175 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1176 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1177 1178 /* 1179 * If a MMC dual voltage card is detected, the set_ios fn calls 1180 * this fn with VDD bit set for 1.8V. Upon card removal from the 1181 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1182 * 1183 * Cope with a bit of slop in the range ... per data sheets: 1184 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1185 * but recommended values are 1.71V to 1.89V 1186 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1187 * but recommended values are 2.7V to 3.3V 1188 * 1189 * Board setup code shouldn't permit anything very out-of-range. 1190 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1191 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1192 */ 1193 if ((1 << vdd) <= MMC_VDD_23_24) 1194 reg_val |= SDVS18; 1195 else 1196 reg_val |= SDVS30; 1197 1198 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1199 set_sd_bus_power(host); 1200 1201 return 0; 1202 err: 1203 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1204 return ret; 1205 } 1206 1207 /* Protect the card while the cover is open */ 1208 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1209 { 1210 if (!mmc_slot(host).get_cover_state) 1211 return; 1212 1213 host->reqs_blocked = 0; 1214 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1215 if (host->protect_card) { 1216 dev_info(host->dev, "%s: cover is closed, " 1217 "card is now accessible\n", 1218 mmc_hostname(host->mmc)); 1219 host->protect_card = 0; 1220 } 1221 } else { 1222 if (!host->protect_card) { 1223 dev_info(host->dev, "%s: cover is open, " 1224 "card is now inaccessible\n", 1225 mmc_hostname(host->mmc)); 1226 host->protect_card = 1; 1227 } 1228 } 1229 } 1230 1231 /* 1232 * irq handler to notify the core about card insertion/removal 1233 */ 1234 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1235 { 1236 struct omap_hsmmc_host *host = dev_id; 1237 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1238 int carddetect; 1239 1240 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1241 1242 if (slot->card_detect) 1243 carddetect = slot->card_detect(host->dev, host->slot_id); 1244 else { 1245 omap_hsmmc_protect_card(host); 1246 carddetect = -ENOSYS; 1247 } 1248 1249 if (carddetect) 1250 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1251 else 1252 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1253 return IRQ_HANDLED; 1254 } 1255 1256 static void omap_hsmmc_dma_callback(void *param) 1257 { 1258 struct omap_hsmmc_host *host = param; 1259 struct dma_chan *chan; 1260 struct mmc_data *data; 1261 int req_in_progress; 1262 1263 spin_lock_irq(&host->irq_lock); 1264 if (host->dma_ch < 0) { 1265 spin_unlock_irq(&host->irq_lock); 1266 return; 1267 } 1268 1269 data = host->mrq->data; 1270 chan = omap_hsmmc_get_dma_chan(host, data); 1271 if (!data->host_cookie) 1272 dma_unmap_sg(chan->device->dev, 1273 data->sg, data->sg_len, 1274 omap_hsmmc_get_dma_dir(host, data)); 1275 1276 req_in_progress = host->req_in_progress; 1277 host->dma_ch = -1; 1278 spin_unlock_irq(&host->irq_lock); 1279 1280 /* If DMA has finished after TC, complete the request */ 1281 if (!req_in_progress) { 1282 struct mmc_request *mrq = host->mrq; 1283 1284 host->mrq = NULL; 1285 mmc_request_done(host->mmc, mrq); 1286 } 1287 } 1288 1289 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1290 struct mmc_data *data, 1291 struct omap_hsmmc_next *next, 1292 struct dma_chan *chan) 1293 { 1294 int dma_len; 1295 1296 if (!next && data->host_cookie && 1297 data->host_cookie != host->next_data.cookie) { 1298 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1299 " host->next_data.cookie %d\n", 1300 __func__, data->host_cookie, host->next_data.cookie); 1301 data->host_cookie = 0; 1302 } 1303 1304 /* Check if next job is already prepared */ 1305 if (next || data->host_cookie != host->next_data.cookie) { 1306 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1307 omap_hsmmc_get_dma_dir(host, data)); 1308 1309 } else { 1310 dma_len = host->next_data.dma_len; 1311 host->next_data.dma_len = 0; 1312 } 1313 1314 1315 if (dma_len == 0) 1316 return -EINVAL; 1317 1318 if (next) { 1319 next->dma_len = dma_len; 1320 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1321 } else 1322 host->dma_len = dma_len; 1323 1324 return 0; 1325 } 1326 1327 /* 1328 * Routine to configure and start DMA for the MMC card 1329 */ 1330 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 1331 struct mmc_request *req) 1332 { 1333 struct dma_slave_config cfg; 1334 struct dma_async_tx_descriptor *tx; 1335 int ret = 0, i; 1336 struct mmc_data *data = req->data; 1337 struct dma_chan *chan; 1338 1339 /* Sanity check: all the SG entries must be aligned by block size. */ 1340 for (i = 0; i < data->sg_len; i++) { 1341 struct scatterlist *sgl; 1342 1343 sgl = data->sg + i; 1344 if (sgl->length % data->blksz) 1345 return -EINVAL; 1346 } 1347 if ((data->blksz % 4) != 0) 1348 /* REVISIT: The MMC buffer increments only when MSB is written. 1349 * Return error for blksz which is non multiple of four. 1350 */ 1351 return -EINVAL; 1352 1353 BUG_ON(host->dma_ch != -1); 1354 1355 chan = omap_hsmmc_get_dma_chan(host, data); 1356 1357 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1358 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1359 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1360 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1361 cfg.src_maxburst = data->blksz / 4; 1362 cfg.dst_maxburst = data->blksz / 4; 1363 1364 ret = dmaengine_slave_config(chan, &cfg); 1365 if (ret) 1366 return ret; 1367 1368 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1369 if (ret) 1370 return ret; 1371 1372 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1373 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1374 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1375 if (!tx) { 1376 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1377 /* FIXME: cleanup */ 1378 return -1; 1379 } 1380 1381 tx->callback = omap_hsmmc_dma_callback; 1382 tx->callback_param = host; 1383 1384 /* Does not fail */ 1385 dmaengine_submit(tx); 1386 1387 host->dma_ch = 1; 1388 1389 return 0; 1390 } 1391 1392 static void set_data_timeout(struct omap_hsmmc_host *host, 1393 unsigned int timeout_ns, 1394 unsigned int timeout_clks) 1395 { 1396 unsigned int timeout, cycle_ns; 1397 uint32_t reg, clkd, dto = 0; 1398 1399 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1400 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1401 if (clkd == 0) 1402 clkd = 1; 1403 1404 cycle_ns = 1000000000 / (host->clk_rate / clkd); 1405 timeout = timeout_ns / cycle_ns; 1406 timeout += timeout_clks; 1407 if (timeout) { 1408 while ((timeout & 0x80000000) == 0) { 1409 dto += 1; 1410 timeout <<= 1; 1411 } 1412 dto = 31 - dto; 1413 timeout <<= 1; 1414 if (timeout && dto) 1415 dto += 1; 1416 if (dto >= 13) 1417 dto -= 13; 1418 else 1419 dto = 0; 1420 if (dto > 14) 1421 dto = 14; 1422 } 1423 1424 reg &= ~DTO_MASK; 1425 reg |= dto << DTO_SHIFT; 1426 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1427 } 1428 1429 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 1430 { 1431 struct mmc_request *req = host->mrq; 1432 struct dma_chan *chan; 1433 1434 if (!req->data) 1435 return; 1436 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1437 | (req->data->blocks << 16)); 1438 set_data_timeout(host, req->data->timeout_ns, 1439 req->data->timeout_clks); 1440 chan = omap_hsmmc_get_dma_chan(host, req->data); 1441 dma_async_issue_pending(chan); 1442 } 1443 1444 /* 1445 * Configure block length for MMC/SD cards and initiate the transfer. 1446 */ 1447 static int 1448 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1449 { 1450 int ret; 1451 host->data = req->data; 1452 1453 if (req->data == NULL) { 1454 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1455 /* 1456 * Set an arbitrary 100ms data timeout for commands with 1457 * busy signal. 1458 */ 1459 if (req->cmd->flags & MMC_RSP_BUSY) 1460 set_data_timeout(host, 100000000U, 0); 1461 return 0; 1462 } 1463 1464 if (host->use_dma) { 1465 ret = omap_hsmmc_setup_dma_transfer(host, req); 1466 if (ret != 0) { 1467 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1468 return ret; 1469 } 1470 } 1471 return 0; 1472 } 1473 1474 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1475 int err) 1476 { 1477 struct omap_hsmmc_host *host = mmc_priv(mmc); 1478 struct mmc_data *data = mrq->data; 1479 1480 if (host->use_dma && data->host_cookie) { 1481 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1482 1483 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1484 omap_hsmmc_get_dma_dir(host, data)); 1485 data->host_cookie = 0; 1486 } 1487 } 1488 1489 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1490 bool is_first_req) 1491 { 1492 struct omap_hsmmc_host *host = mmc_priv(mmc); 1493 1494 if (mrq->data->host_cookie) { 1495 mrq->data->host_cookie = 0; 1496 return ; 1497 } 1498 1499 if (host->use_dma) { 1500 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1501 1502 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1503 &host->next_data, c)) 1504 mrq->data->host_cookie = 0; 1505 } 1506 } 1507 1508 /* 1509 * Request function. for read/write operation 1510 */ 1511 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1512 { 1513 struct omap_hsmmc_host *host = mmc_priv(mmc); 1514 int err; 1515 1516 BUG_ON(host->req_in_progress); 1517 BUG_ON(host->dma_ch != -1); 1518 if (host->protect_card) { 1519 if (host->reqs_blocked < 3) { 1520 /* 1521 * Ensure the controller is left in a consistent 1522 * state by resetting the command and data state 1523 * machines. 1524 */ 1525 omap_hsmmc_reset_controller_fsm(host, SRD); 1526 omap_hsmmc_reset_controller_fsm(host, SRC); 1527 host->reqs_blocked += 1; 1528 } 1529 req->cmd->error = -EBADF; 1530 if (req->data) 1531 req->data->error = -EBADF; 1532 req->cmd->retries = 0; 1533 mmc_request_done(mmc, req); 1534 return; 1535 } else if (host->reqs_blocked) 1536 host->reqs_blocked = 0; 1537 WARN_ON(host->mrq != NULL); 1538 host->mrq = req; 1539 host->clk_rate = clk_get_rate(host->fclk); 1540 err = omap_hsmmc_prepare_data(host, req); 1541 if (err) { 1542 req->cmd->error = err; 1543 if (req->data) 1544 req->data->error = err; 1545 host->mrq = NULL; 1546 mmc_request_done(mmc, req); 1547 return; 1548 } 1549 if (req->sbc && !(host->flags & AUTO_CMD23)) { 1550 omap_hsmmc_start_command(host, req->sbc, NULL); 1551 return; 1552 } 1553 1554 omap_hsmmc_start_dma_transfer(host); 1555 omap_hsmmc_start_command(host, req->cmd, req->data); 1556 } 1557 1558 /* Routine to configure clock values. Exposed API to core */ 1559 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1560 { 1561 struct omap_hsmmc_host *host = mmc_priv(mmc); 1562 int do_send_init_stream = 0; 1563 1564 pm_runtime_get_sync(host->dev); 1565 1566 if (ios->power_mode != host->power_mode) { 1567 switch (ios->power_mode) { 1568 case MMC_POWER_OFF: 1569 mmc_slot(host).set_power(host->dev, host->slot_id, 1570 0, 0); 1571 break; 1572 case MMC_POWER_UP: 1573 mmc_slot(host).set_power(host->dev, host->slot_id, 1574 1, ios->vdd); 1575 break; 1576 case MMC_POWER_ON: 1577 do_send_init_stream = 1; 1578 break; 1579 } 1580 host->power_mode = ios->power_mode; 1581 } 1582 1583 /* FIXME: set registers based only on changes to ios */ 1584 1585 omap_hsmmc_set_bus_width(host); 1586 1587 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1588 /* Only MMC1 can interface at 3V without some flavor 1589 * of external transceiver; but they all handle 1.8V. 1590 */ 1591 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1592 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1593 /* 1594 * The mmc_select_voltage fn of the core does 1595 * not seem to set the power_mode to 1596 * MMC_POWER_UP upon recalculating the voltage. 1597 * vdd 1.8v. 1598 */ 1599 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1600 dev_dbg(mmc_dev(host->mmc), 1601 "Switch operation failed\n"); 1602 } 1603 } 1604 1605 omap_hsmmc_set_clock(host); 1606 1607 if (do_send_init_stream) 1608 send_init_stream(host); 1609 1610 omap_hsmmc_set_bus_mode(host); 1611 1612 pm_runtime_put_autosuspend(host->dev); 1613 } 1614 1615 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1616 { 1617 struct omap_hsmmc_host *host = mmc_priv(mmc); 1618 1619 if (!mmc_slot(host).card_detect) 1620 return -ENOSYS; 1621 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1622 } 1623 1624 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1625 { 1626 struct omap_hsmmc_host *host = mmc_priv(mmc); 1627 1628 if (!mmc_slot(host).get_ro) 1629 return -ENOSYS; 1630 return mmc_slot(host).get_ro(host->dev, 0); 1631 } 1632 1633 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1634 { 1635 struct omap_hsmmc_host *host = mmc_priv(mmc); 1636 1637 if (mmc_slot(host).init_card) 1638 mmc_slot(host).init_card(card); 1639 } 1640 1641 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1642 { 1643 u32 hctl, capa, value; 1644 1645 /* Only MMC1 supports 3.0V */ 1646 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1647 hctl = SDVS30; 1648 capa = VS30 | VS18; 1649 } else { 1650 hctl = SDVS18; 1651 capa = VS18; 1652 } 1653 1654 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1655 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1656 1657 value = OMAP_HSMMC_READ(host->base, CAPA); 1658 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1659 1660 /* Set SD bus power bit */ 1661 set_sd_bus_power(host); 1662 } 1663 1664 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1665 { 1666 struct omap_hsmmc_host *host = mmc_priv(mmc); 1667 1668 pm_runtime_get_sync(host->dev); 1669 1670 return 0; 1671 } 1672 1673 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1674 { 1675 struct omap_hsmmc_host *host = mmc_priv(mmc); 1676 1677 pm_runtime_mark_last_busy(host->dev); 1678 pm_runtime_put_autosuspend(host->dev); 1679 1680 return 0; 1681 } 1682 1683 static const struct mmc_host_ops omap_hsmmc_ops = { 1684 .enable = omap_hsmmc_enable_fclk, 1685 .disable = omap_hsmmc_disable_fclk, 1686 .post_req = omap_hsmmc_post_req, 1687 .pre_req = omap_hsmmc_pre_req, 1688 .request = omap_hsmmc_request, 1689 .set_ios = omap_hsmmc_set_ios, 1690 .get_cd = omap_hsmmc_get_cd, 1691 .get_ro = omap_hsmmc_get_ro, 1692 .init_card = omap_hsmmc_init_card, 1693 /* NYET -- enable_sdio_irq */ 1694 }; 1695 1696 #ifdef CONFIG_DEBUG_FS 1697 1698 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1699 { 1700 struct mmc_host *mmc = s->private; 1701 struct omap_hsmmc_host *host = mmc_priv(mmc); 1702 1703 seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 1704 mmc->index, host->context_loss); 1705 1706 pm_runtime_get_sync(host->dev); 1707 1708 seq_printf(s, "CON:\t\t0x%08x\n", 1709 OMAP_HSMMC_READ(host->base, CON)); 1710 seq_printf(s, "HCTL:\t\t0x%08x\n", 1711 OMAP_HSMMC_READ(host->base, HCTL)); 1712 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1713 OMAP_HSMMC_READ(host->base, SYSCTL)); 1714 seq_printf(s, "IE:\t\t0x%08x\n", 1715 OMAP_HSMMC_READ(host->base, IE)); 1716 seq_printf(s, "ISE:\t\t0x%08x\n", 1717 OMAP_HSMMC_READ(host->base, ISE)); 1718 seq_printf(s, "CAPA:\t\t0x%08x\n", 1719 OMAP_HSMMC_READ(host->base, CAPA)); 1720 1721 pm_runtime_mark_last_busy(host->dev); 1722 pm_runtime_put_autosuspend(host->dev); 1723 1724 return 0; 1725 } 1726 1727 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1728 { 1729 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1730 } 1731 1732 static const struct file_operations mmc_regs_fops = { 1733 .open = omap_hsmmc_regs_open, 1734 .read = seq_read, 1735 .llseek = seq_lseek, 1736 .release = single_release, 1737 }; 1738 1739 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1740 { 1741 if (mmc->debugfs_root) 1742 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1743 mmc, &mmc_regs_fops); 1744 } 1745 1746 #else 1747 1748 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1749 { 1750 } 1751 1752 #endif 1753 1754 #ifdef CONFIG_OF 1755 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 1756 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1757 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1758 }; 1759 1760 static const struct omap_mmc_of_data omap4_mmc_of_data = { 1761 .reg_offset = 0x100, 1762 }; 1763 1764 static const struct of_device_id omap_mmc_of_match[] = { 1765 { 1766 .compatible = "ti,omap2-hsmmc", 1767 }, 1768 { 1769 .compatible = "ti,omap3-pre-es3-hsmmc", 1770 .data = &omap3_pre_es3_mmc_of_data, 1771 }, 1772 { 1773 .compatible = "ti,omap3-hsmmc", 1774 }, 1775 { 1776 .compatible = "ti,omap4-hsmmc", 1777 .data = &omap4_mmc_of_data, 1778 }, 1779 {}, 1780 }; 1781 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1782 1783 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1784 { 1785 struct omap_mmc_platform_data *pdata; 1786 struct device_node *np = dev->of_node; 1787 u32 bus_width, max_freq; 1788 int cd_gpio, wp_gpio; 1789 1790 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1791 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1792 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1793 return ERR_PTR(-EPROBE_DEFER); 1794 1795 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1796 if (!pdata) 1797 return ERR_PTR(-ENOMEM); /* out of memory */ 1798 1799 if (of_find_property(np, "ti,dual-volt", NULL)) 1800 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1801 1802 /* This driver only supports 1 slot */ 1803 pdata->nr_slots = 1; 1804 pdata->slots[0].switch_pin = cd_gpio; 1805 pdata->slots[0].gpio_wp = wp_gpio; 1806 1807 if (of_find_property(np, "ti,non-removable", NULL)) { 1808 pdata->slots[0].nonremovable = true; 1809 pdata->slots[0].no_regulator_off_init = true; 1810 } 1811 of_property_read_u32(np, "bus-width", &bus_width); 1812 if (bus_width == 4) 1813 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 1814 else if (bus_width == 8) 1815 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 1816 1817 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1818 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 1819 1820 if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1821 pdata->max_freq = max_freq; 1822 1823 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1824 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1825 1826 if (of_find_property(np, "keep-power-in-suspend", NULL)) 1827 pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; 1828 1829 if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1830 pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1831 1832 return pdata; 1833 } 1834 #else 1835 static inline struct omap_mmc_platform_data 1836 *of_get_hsmmc_pdata(struct device *dev) 1837 { 1838 return ERR_PTR(-EINVAL); 1839 } 1840 #endif 1841 1842 static int omap_hsmmc_probe(struct platform_device *pdev) 1843 { 1844 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1845 struct mmc_host *mmc; 1846 struct omap_hsmmc_host *host = NULL; 1847 struct resource *res; 1848 int ret, irq; 1849 const struct of_device_id *match; 1850 dma_cap_mask_t mask; 1851 unsigned tx_req, rx_req; 1852 struct pinctrl *pinctrl; 1853 const struct omap_mmc_of_data *data; 1854 1855 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1856 if (match) { 1857 pdata = of_get_hsmmc_pdata(&pdev->dev); 1858 1859 if (IS_ERR(pdata)) 1860 return PTR_ERR(pdata); 1861 1862 if (match->data) { 1863 data = match->data; 1864 pdata->reg_offset = data->reg_offset; 1865 pdata->controller_flags |= data->controller_flags; 1866 } 1867 } 1868 1869 if (pdata == NULL) { 1870 dev_err(&pdev->dev, "Platform Data is missing\n"); 1871 return -ENXIO; 1872 } 1873 1874 if (pdata->nr_slots == 0) { 1875 dev_err(&pdev->dev, "No Slots\n"); 1876 return -ENXIO; 1877 } 1878 1879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1880 irq = platform_get_irq(pdev, 0); 1881 if (res == NULL || irq < 0) 1882 return -ENXIO; 1883 1884 res = request_mem_region(res->start, resource_size(res), pdev->name); 1885 if (res == NULL) 1886 return -EBUSY; 1887 1888 ret = omap_hsmmc_gpio_init(pdata); 1889 if (ret) 1890 goto err; 1891 1892 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1893 if (!mmc) { 1894 ret = -ENOMEM; 1895 goto err_alloc; 1896 } 1897 1898 host = mmc_priv(mmc); 1899 host->mmc = mmc; 1900 host->pdata = pdata; 1901 host->dev = &pdev->dev; 1902 host->use_dma = 1; 1903 host->dma_ch = -1; 1904 host->irq = irq; 1905 host->slot_id = 0; 1906 host->mapbase = res->start + pdata->reg_offset; 1907 host->base = ioremap(host->mapbase, SZ_4K); 1908 host->power_mode = MMC_POWER_OFF; 1909 host->next_data.cookie = 1; 1910 host->pbias_enabled = 0; 1911 1912 platform_set_drvdata(pdev, host); 1913 1914 mmc->ops = &omap_hsmmc_ops; 1915 1916 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1917 1918 if (pdata->max_freq > 0) 1919 mmc->f_max = pdata->max_freq; 1920 else 1921 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1922 1923 spin_lock_init(&host->irq_lock); 1924 1925 host->fclk = devm_clk_get(&pdev->dev, "fck"); 1926 if (IS_ERR(host->fclk)) { 1927 ret = PTR_ERR(host->fclk); 1928 host->fclk = NULL; 1929 goto err1; 1930 } 1931 1932 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1933 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1934 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 1935 } 1936 1937 pm_runtime_enable(host->dev); 1938 pm_runtime_get_sync(host->dev); 1939 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1940 pm_runtime_use_autosuspend(host->dev); 1941 1942 omap_hsmmc_context_save(host); 1943 1944 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 1945 /* 1946 * MMC can still work without debounce clock. 1947 */ 1948 if (IS_ERR(host->dbclk)) { 1949 host->dbclk = NULL; 1950 } else if (clk_prepare_enable(host->dbclk) != 0) { 1951 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1952 host->dbclk = NULL; 1953 } 1954 1955 /* Since we do only SG emulation, we can have as many segs 1956 * as we want. */ 1957 mmc->max_segs = 1024; 1958 1959 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1960 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1961 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1962 mmc->max_seg_size = mmc->max_req_size; 1963 1964 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1965 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1966 1967 mmc->caps |= mmc_slot(host).caps; 1968 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1969 mmc->caps |= MMC_CAP_4_BIT_DATA; 1970 1971 if (mmc_slot(host).nonremovable) 1972 mmc->caps |= MMC_CAP_NONREMOVABLE; 1973 1974 mmc->pm_caps = mmc_slot(host).pm_caps; 1975 1976 omap_hsmmc_conf_bus_power(host); 1977 1978 if (!pdev->dev.of_node) { 1979 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1980 if (!res) { 1981 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 1982 ret = -ENXIO; 1983 goto err_irq; 1984 } 1985 tx_req = res->start; 1986 1987 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1988 if (!res) { 1989 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 1990 ret = -ENXIO; 1991 goto err_irq; 1992 } 1993 rx_req = res->start; 1994 } 1995 1996 dma_cap_zero(mask); 1997 dma_cap_set(DMA_SLAVE, mask); 1998 1999 host->rx_chan = 2000 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2001 &rx_req, &pdev->dev, "rx"); 2002 2003 if (!host->rx_chan) { 2004 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 2005 ret = -ENXIO; 2006 goto err_irq; 2007 } 2008 2009 host->tx_chan = 2010 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2011 &tx_req, &pdev->dev, "tx"); 2012 2013 if (!host->tx_chan) { 2014 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 2015 ret = -ENXIO; 2016 goto err_irq; 2017 } 2018 2019 /* Request IRQ for MMC operations */ 2020 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2021 mmc_hostname(mmc), host); 2022 if (ret) { 2023 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2024 goto err_irq; 2025 } 2026 2027 if (pdata->init != NULL) { 2028 if (pdata->init(&pdev->dev) != 0) { 2029 dev_err(mmc_dev(host->mmc), 2030 "Unable to configure MMC IRQs\n"); 2031 goto err_irq; 2032 } 2033 } 2034 2035 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2036 ret = omap_hsmmc_reg_get(host); 2037 if (ret) 2038 goto err_reg; 2039 host->use_reg = 1; 2040 } 2041 2042 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2043 2044 /* Request IRQ for card detect */ 2045 if ((mmc_slot(host).card_detect_irq)) { 2046 ret = devm_request_threaded_irq(&pdev->dev, 2047 mmc_slot(host).card_detect_irq, 2048 NULL, omap_hsmmc_detect, 2049 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2050 mmc_hostname(mmc), host); 2051 if (ret) { 2052 dev_err(mmc_dev(host->mmc), 2053 "Unable to grab MMC CD IRQ\n"); 2054 goto err_irq_cd; 2055 } 2056 pdata->suspend = omap_hsmmc_suspend_cdirq; 2057 pdata->resume = omap_hsmmc_resume_cdirq; 2058 } 2059 2060 omap_hsmmc_disable_irq(host); 2061 2062 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 2063 if (IS_ERR(pinctrl)) 2064 dev_warn(&pdev->dev, 2065 "pins are not configured from the driver\n"); 2066 2067 omap_hsmmc_protect_card(host); 2068 2069 mmc_add_host(mmc); 2070 2071 if (mmc_slot(host).name != NULL) { 2072 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2073 if (ret < 0) 2074 goto err_slot_name; 2075 } 2076 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2077 ret = device_create_file(&mmc->class_dev, 2078 &dev_attr_cover_switch); 2079 if (ret < 0) 2080 goto err_slot_name; 2081 } 2082 2083 omap_hsmmc_debugfs(mmc); 2084 pm_runtime_mark_last_busy(host->dev); 2085 pm_runtime_put_autosuspend(host->dev); 2086 2087 return 0; 2088 2089 err_slot_name: 2090 mmc_remove_host(mmc); 2091 err_irq_cd: 2092 if (host->use_reg) 2093 omap_hsmmc_reg_put(host); 2094 err_reg: 2095 if (host->pdata->cleanup) 2096 host->pdata->cleanup(&pdev->dev); 2097 err_irq: 2098 if (host->tx_chan) 2099 dma_release_channel(host->tx_chan); 2100 if (host->rx_chan) 2101 dma_release_channel(host->rx_chan); 2102 pm_runtime_put_sync(host->dev); 2103 pm_runtime_disable(host->dev); 2104 if (host->dbclk) 2105 clk_disable_unprepare(host->dbclk); 2106 err1: 2107 iounmap(host->base); 2108 mmc_free_host(mmc); 2109 err_alloc: 2110 omap_hsmmc_gpio_free(pdata); 2111 err: 2112 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2113 if (res) 2114 release_mem_region(res->start, resource_size(res)); 2115 return ret; 2116 } 2117 2118 static int omap_hsmmc_remove(struct platform_device *pdev) 2119 { 2120 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2121 struct resource *res; 2122 2123 pm_runtime_get_sync(host->dev); 2124 mmc_remove_host(host->mmc); 2125 if (host->use_reg) 2126 omap_hsmmc_reg_put(host); 2127 if (host->pdata->cleanup) 2128 host->pdata->cleanup(&pdev->dev); 2129 2130 if (host->tx_chan) 2131 dma_release_channel(host->tx_chan); 2132 if (host->rx_chan) 2133 dma_release_channel(host->rx_chan); 2134 2135 pm_runtime_put_sync(host->dev); 2136 pm_runtime_disable(host->dev); 2137 if (host->dbclk) 2138 clk_disable_unprepare(host->dbclk); 2139 2140 omap_hsmmc_gpio_free(host->pdata); 2141 iounmap(host->base); 2142 mmc_free_host(host->mmc); 2143 2144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2145 if (res) 2146 release_mem_region(res->start, resource_size(res)); 2147 2148 return 0; 2149 } 2150 2151 #ifdef CONFIG_PM 2152 static int omap_hsmmc_prepare(struct device *dev) 2153 { 2154 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2155 2156 if (host->pdata->suspend) 2157 return host->pdata->suspend(dev, host->slot_id); 2158 2159 return 0; 2160 } 2161 2162 static void omap_hsmmc_complete(struct device *dev) 2163 { 2164 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2165 2166 if (host->pdata->resume) 2167 host->pdata->resume(dev, host->slot_id); 2168 2169 } 2170 2171 static int omap_hsmmc_suspend(struct device *dev) 2172 { 2173 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2174 2175 if (!host) 2176 return 0; 2177 2178 pm_runtime_get_sync(host->dev); 2179 2180 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2181 omap_hsmmc_disable_irq(host); 2182 OMAP_HSMMC_WRITE(host->base, HCTL, 2183 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2184 } 2185 2186 if (host->dbclk) 2187 clk_disable_unprepare(host->dbclk); 2188 2189 pm_runtime_put_sync(host->dev); 2190 return 0; 2191 } 2192 2193 /* Routine to resume the MMC device */ 2194 static int omap_hsmmc_resume(struct device *dev) 2195 { 2196 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2197 2198 if (!host) 2199 return 0; 2200 2201 pm_runtime_get_sync(host->dev); 2202 2203 if (host->dbclk) 2204 clk_prepare_enable(host->dbclk); 2205 2206 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2207 omap_hsmmc_conf_bus_power(host); 2208 2209 omap_hsmmc_protect_card(host); 2210 2211 pm_runtime_mark_last_busy(host->dev); 2212 pm_runtime_put_autosuspend(host->dev); 2213 return 0; 2214 } 2215 2216 #else 2217 #define omap_hsmmc_prepare NULL 2218 #define omap_hsmmc_complete NULL 2219 #define omap_hsmmc_suspend NULL 2220 #define omap_hsmmc_resume NULL 2221 #endif 2222 2223 static int omap_hsmmc_runtime_suspend(struct device *dev) 2224 { 2225 struct omap_hsmmc_host *host; 2226 2227 host = platform_get_drvdata(to_platform_device(dev)); 2228 omap_hsmmc_context_save(host); 2229 dev_dbg(dev, "disabled\n"); 2230 2231 return 0; 2232 } 2233 2234 static int omap_hsmmc_runtime_resume(struct device *dev) 2235 { 2236 struct omap_hsmmc_host *host; 2237 2238 host = platform_get_drvdata(to_platform_device(dev)); 2239 omap_hsmmc_context_restore(host); 2240 dev_dbg(dev, "enabled\n"); 2241 2242 return 0; 2243 } 2244 2245 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2246 .suspend = omap_hsmmc_suspend, 2247 .resume = omap_hsmmc_resume, 2248 .prepare = omap_hsmmc_prepare, 2249 .complete = omap_hsmmc_complete, 2250 .runtime_suspend = omap_hsmmc_runtime_suspend, 2251 .runtime_resume = omap_hsmmc_runtime_resume, 2252 }; 2253 2254 static struct platform_driver omap_hsmmc_driver = { 2255 .probe = omap_hsmmc_probe, 2256 .remove = omap_hsmmc_remove, 2257 .driver = { 2258 .name = DRIVER_NAME, 2259 .owner = THIS_MODULE, 2260 .pm = &omap_hsmmc_dev_pm_ops, 2261 .of_match_table = of_match_ptr(omap_mmc_of_match), 2262 }, 2263 }; 2264 2265 module_platform_driver(omap_hsmmc_driver); 2266 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2267 MODULE_LICENSE("GPL"); 2268 MODULE_ALIAS("platform:" DRIVER_NAME); 2269 MODULE_AUTHOR("Texas Instruments Inc"); 2270