1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/sizes.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/timer.h> 30 #include <linux/clk.h> 31 #include <linux/of.h> 32 #include <linux/of_irq.h> 33 #include <linux/of_gpio.h> 34 #include <linux/of_device.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/core.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/mmc/slot-gpio.h> 39 #include <linux/io.h> 40 #include <linux/irq.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/pm_wakeirq.h> 46 #include <linux/platform_data/hsmmc-omap.h> 47 48 /* OMAP HSMMC Host Controller Registers */ 49 #define OMAP_HSMMC_SYSSTATUS 0x0014 50 #define OMAP_HSMMC_CON 0x002C 51 #define OMAP_HSMMC_SDMASA 0x0100 52 #define OMAP_HSMMC_BLK 0x0104 53 #define OMAP_HSMMC_ARG 0x0108 54 #define OMAP_HSMMC_CMD 0x010C 55 #define OMAP_HSMMC_RSP10 0x0110 56 #define OMAP_HSMMC_RSP32 0x0114 57 #define OMAP_HSMMC_RSP54 0x0118 58 #define OMAP_HSMMC_RSP76 0x011C 59 #define OMAP_HSMMC_DATA 0x0120 60 #define OMAP_HSMMC_PSTATE 0x0124 61 #define OMAP_HSMMC_HCTL 0x0128 62 #define OMAP_HSMMC_SYSCTL 0x012C 63 #define OMAP_HSMMC_STAT 0x0130 64 #define OMAP_HSMMC_IE 0x0134 65 #define OMAP_HSMMC_ISE 0x0138 66 #define OMAP_HSMMC_AC12 0x013C 67 #define OMAP_HSMMC_CAPA 0x0140 68 69 #define VS18 (1 << 26) 70 #define VS30 (1 << 25) 71 #define HSS (1 << 21) 72 #define SDVS18 (0x5 << 9) 73 #define SDVS30 (0x6 << 9) 74 #define SDVS33 (0x7 << 9) 75 #define SDVS_MASK 0x00000E00 76 #define SDVSCLR 0xFFFFF1FF 77 #define SDVSDET 0x00000400 78 #define AUTOIDLE 0x1 79 #define SDBP (1 << 8) 80 #define DTO 0xe 81 #define ICE 0x1 82 #define ICS 0x2 83 #define CEN (1 << 2) 84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85 #define CLKD_MASK 0x0000FFC0 86 #define CLKD_SHIFT 6 87 #define DTO_MASK 0x000F0000 88 #define DTO_SHIFT 16 89 #define INIT_STREAM (1 << 1) 90 #define ACEN_ACMD23 (2 << 2) 91 #define DP_SELECT (1 << 21) 92 #define DDIR (1 << 4) 93 #define DMAE 0x1 94 #define MSBS (1 << 5) 95 #define BCE (1 << 1) 96 #define FOUR_BIT (1 << 1) 97 #define HSPE (1 << 2) 98 #define IWE (1 << 24) 99 #define DDR (1 << 19) 100 #define CLKEXTFREE (1 << 16) 101 #define CTPL (1 << 11) 102 #define DW8 (1 << 5) 103 #define OD 0x1 104 #define STAT_CLEAR 0xFFFFFFFF 105 #define INIT_STREAM_CMD 0x00000000 106 #define DUAL_VOLT_OCR_BIT 7 107 #define SRC (1 << 25) 108 #define SRD (1 << 26) 109 #define SOFTRESET (1 << 1) 110 111 /* PSTATE */ 112 #define DLEV_DAT(x) (1 << (20 + (x))) 113 114 /* Interrupt masks for IE and ISE register */ 115 #define CC_EN (1 << 0) 116 #define TC_EN (1 << 1) 117 #define BWR_EN (1 << 4) 118 #define BRR_EN (1 << 5) 119 #define CIRQ_EN (1 << 8) 120 #define ERR_EN (1 << 15) 121 #define CTO_EN (1 << 16) 122 #define CCRC_EN (1 << 17) 123 #define CEB_EN (1 << 18) 124 #define CIE_EN (1 << 19) 125 #define DTO_EN (1 << 20) 126 #define DCRC_EN (1 << 21) 127 #define DEB_EN (1 << 22) 128 #define ACE_EN (1 << 24) 129 #define CERR_EN (1 << 28) 130 #define BADA_EN (1 << 29) 131 132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134 BRR_EN | BWR_EN | TC_EN | CC_EN) 135 136 #define CNI (1 << 7) 137 #define ACIE (1 << 4) 138 #define ACEB (1 << 3) 139 #define ACCE (1 << 2) 140 #define ACTO (1 << 1) 141 #define ACNE (1 << 0) 142 143 #define MMC_AUTOSUSPEND_DELAY 100 144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 146 #define OMAP_MMC_MIN_CLOCK 400000 147 #define OMAP_MMC_MAX_CLOCK 52000000 148 #define DRIVER_NAME "omap_hsmmc" 149 150 /* 151 * One controller can have multiple slots, like on some omap boards using 152 * omap.c controller driver. Luckily this is not currently done on any known 153 * omap_hsmmc.c device. 154 */ 155 #define mmc_pdata(host) host->pdata 156 157 /* 158 * MMC Host controller read/write API's 159 */ 160 #define OMAP_HSMMC_READ(base, reg) \ 161 __raw_readl((base) + OMAP_HSMMC_##reg) 162 163 #define OMAP_HSMMC_WRITE(base, reg, val) \ 164 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 165 166 struct omap_hsmmc_next { 167 unsigned int dma_len; 168 s32 cookie; 169 }; 170 171 struct omap_hsmmc_host { 172 struct device *dev; 173 struct mmc_host *mmc; 174 struct mmc_request *mrq; 175 struct mmc_command *cmd; 176 struct mmc_data *data; 177 struct clk *fclk; 178 struct clk *dbclk; 179 struct regulator *pbias; 180 bool pbias_enabled; 181 void __iomem *base; 182 int vqmmc_enabled; 183 resource_size_t mapbase; 184 spinlock_t irq_lock; /* Prevent races with irq handler */ 185 unsigned int dma_len; 186 unsigned int dma_sg_idx; 187 unsigned char bus_mode; 188 unsigned char power_mode; 189 int suspended; 190 u32 con; 191 u32 hctl; 192 u32 sysctl; 193 u32 capa; 194 int irq; 195 int wake_irq; 196 int use_dma, dma_ch; 197 struct dma_chan *tx_chan; 198 struct dma_chan *rx_chan; 199 int response_busy; 200 int context_loss; 201 int reqs_blocked; 202 int req_in_progress; 203 unsigned long clk_rate; 204 unsigned int flags; 205 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 206 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 207 struct omap_hsmmc_next next_data; 208 struct omap_hsmmc_platform_data *pdata; 209 int (*card_detect)(struct device *dev); 210 }; 211 212 struct omap_mmc_of_data { 213 u32 reg_offset; 214 u8 controller_flags; 215 }; 216 217 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 218 219 static int omap_hsmmc_card_detect(struct device *dev) 220 { 221 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 222 223 return mmc_gpio_get_cd(host->mmc); 224 } 225 226 static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 227 { 228 int ret; 229 struct omap_hsmmc_host *host = mmc_priv(mmc); 230 struct mmc_ios *ios = &mmc->ios; 231 232 if (!IS_ERR(mmc->supply.vmmc)) { 233 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 234 if (ret) 235 return ret; 236 } 237 238 /* Enable interface voltage rail, if needed */ 239 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 240 ret = regulator_enable(mmc->supply.vqmmc); 241 if (ret) { 242 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 243 goto err_vqmmc; 244 } 245 host->vqmmc_enabled = 1; 246 } 247 248 return 0; 249 250 err_vqmmc: 251 if (!IS_ERR(mmc->supply.vmmc)) 252 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 253 254 return ret; 255 } 256 257 static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 258 { 259 int ret; 260 int status; 261 struct omap_hsmmc_host *host = mmc_priv(mmc); 262 263 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 264 ret = regulator_disable(mmc->supply.vqmmc); 265 if (ret) { 266 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 267 return ret; 268 } 269 host->vqmmc_enabled = 0; 270 } 271 272 if (!IS_ERR(mmc->supply.vmmc)) { 273 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 274 if (ret) 275 goto err_set_ocr; 276 } 277 278 return 0; 279 280 err_set_ocr: 281 if (!IS_ERR(mmc->supply.vqmmc)) { 282 status = regulator_enable(mmc->supply.vqmmc); 283 if (status) 284 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 285 } 286 287 return ret; 288 } 289 290 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on) 291 { 292 int ret; 293 294 if (IS_ERR(host->pbias)) 295 return 0; 296 297 if (power_on) { 298 if (host->pbias_enabled == 0) { 299 ret = regulator_enable(host->pbias); 300 if (ret) { 301 dev_err(host->dev, "pbias reg enable fail\n"); 302 return ret; 303 } 304 host->pbias_enabled = 1; 305 } 306 } else { 307 if (host->pbias_enabled == 1) { 308 ret = regulator_disable(host->pbias); 309 if (ret) { 310 dev_err(host->dev, "pbias reg disable fail\n"); 311 return ret; 312 } 313 host->pbias_enabled = 0; 314 } 315 } 316 317 return 0; 318 } 319 320 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on) 321 { 322 struct mmc_host *mmc = host->mmc; 323 int ret = 0; 324 325 /* 326 * If we don't see a Vcc regulator, assume it's a fixed 327 * voltage always-on regulator. 328 */ 329 if (IS_ERR(mmc->supply.vmmc)) 330 return 0; 331 332 ret = omap_hsmmc_set_pbias(host, false); 333 if (ret) 334 return ret; 335 336 /* 337 * Assume Vcc regulator is used only to power the card ... OMAP 338 * VDDS is used to power the pins, optionally with a transceiver to 339 * support cards using voltages other than VDDS (1.8V nominal). When a 340 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 341 * 342 * In some cases this regulator won't support enable/disable; 343 * e.g. it's a fixed rail for a WLAN chip. 344 * 345 * In other cases vcc_aux switches interface power. Example, for 346 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 347 * chips/cards need an interface voltage rail too. 348 */ 349 if (power_on) { 350 ret = omap_hsmmc_enable_supply(mmc); 351 if (ret) 352 return ret; 353 354 ret = omap_hsmmc_set_pbias(host, true); 355 if (ret) 356 goto err_set_voltage; 357 } else { 358 ret = omap_hsmmc_disable_supply(mmc); 359 if (ret) 360 return ret; 361 } 362 363 return 0; 364 365 err_set_voltage: 366 omap_hsmmc_disable_supply(mmc); 367 368 return ret; 369 } 370 371 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 372 { 373 int ret; 374 375 if (IS_ERR(reg)) 376 return 0; 377 378 if (regulator_is_enabled(reg)) { 379 ret = regulator_enable(reg); 380 if (ret) 381 return ret; 382 383 ret = regulator_disable(reg); 384 if (ret) 385 return ret; 386 } 387 388 return 0; 389 } 390 391 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 392 { 393 struct mmc_host *mmc = host->mmc; 394 int ret; 395 396 /* 397 * disable regulators enabled during boot and get the usecount 398 * right so that regulators can be enabled/disabled by checking 399 * the return value of regulator_is_enabled 400 */ 401 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 402 if (ret) { 403 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 404 return ret; 405 } 406 407 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 408 if (ret) { 409 dev_err(host->dev, 410 "fail to disable boot enabled vmmc_aux reg\n"); 411 return ret; 412 } 413 414 ret = omap_hsmmc_disable_boot_regulator(host->pbias); 415 if (ret) { 416 dev_err(host->dev, 417 "failed to disable boot enabled pbias reg\n"); 418 return ret; 419 } 420 421 return 0; 422 } 423 424 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 425 { 426 int ret; 427 struct mmc_host *mmc = host->mmc; 428 429 430 ret = mmc_regulator_get_supply(mmc); 431 if (ret) 432 return ret; 433 434 /* Allow an aux regulator */ 435 if (IS_ERR(mmc->supply.vqmmc)) { 436 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 437 "vmmc_aux"); 438 if (IS_ERR(mmc->supply.vqmmc)) { 439 ret = PTR_ERR(mmc->supply.vqmmc); 440 if ((ret != -ENODEV) && host->dev->of_node) 441 return ret; 442 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 443 PTR_ERR(mmc->supply.vqmmc)); 444 } 445 } 446 447 host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 448 if (IS_ERR(host->pbias)) { 449 ret = PTR_ERR(host->pbias); 450 if ((ret != -ENODEV) && host->dev->of_node) { 451 dev_err(host->dev, 452 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 453 return ret; 454 } 455 dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 456 PTR_ERR(host->pbias)); 457 } 458 459 /* For eMMC do not power off when not in sleep state */ 460 if (mmc_pdata(host)->no_regulator_off_init) 461 return 0; 462 463 ret = omap_hsmmc_disable_boot_regulators(host); 464 if (ret) 465 return ret; 466 467 return 0; 468 } 469 470 static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 471 struct omap_hsmmc_host *host, 472 struct omap_hsmmc_platform_data *pdata) 473 { 474 int ret; 475 476 if (gpio_is_valid(pdata->gpio_cd)) { 477 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 478 if (ret) 479 return ret; 480 481 host->card_detect = omap_hsmmc_card_detect; 482 } 483 484 if (gpio_is_valid(pdata->gpio_wp)) { 485 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 486 if (ret) 487 return ret; 488 } 489 490 return 0; 491 } 492 493 /* 494 * Start clock to the card 495 */ 496 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 497 { 498 OMAP_HSMMC_WRITE(host->base, SYSCTL, 499 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 500 } 501 502 /* 503 * Stop clock to the card 504 */ 505 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 506 { 507 OMAP_HSMMC_WRITE(host->base, SYSCTL, 508 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 509 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 510 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 511 } 512 513 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 514 struct mmc_command *cmd) 515 { 516 u32 irq_mask = INT_EN_MASK; 517 unsigned long flags; 518 519 if (host->use_dma) 520 irq_mask &= ~(BRR_EN | BWR_EN); 521 522 /* Disable timeout for erases */ 523 if (cmd->opcode == MMC_ERASE) 524 irq_mask &= ~DTO_EN; 525 526 spin_lock_irqsave(&host->irq_lock, flags); 527 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 528 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 529 530 /* latch pending CIRQ, but don't signal MMC core */ 531 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 532 irq_mask |= CIRQ_EN; 533 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 534 spin_unlock_irqrestore(&host->irq_lock, flags); 535 } 536 537 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 538 { 539 u32 irq_mask = 0; 540 unsigned long flags; 541 542 spin_lock_irqsave(&host->irq_lock, flags); 543 /* no transfer running but need to keep cirq if enabled */ 544 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 545 irq_mask |= CIRQ_EN; 546 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 547 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 548 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 549 spin_unlock_irqrestore(&host->irq_lock, flags); 550 } 551 552 /* Calculate divisor for the given clock frequency */ 553 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 554 { 555 u16 dsor = 0; 556 557 if (ios->clock) { 558 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 559 if (dsor > CLKD_MAX) 560 dsor = CLKD_MAX; 561 } 562 563 return dsor; 564 } 565 566 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 567 { 568 struct mmc_ios *ios = &host->mmc->ios; 569 unsigned long regval; 570 unsigned long timeout; 571 unsigned long clkdiv; 572 573 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 574 575 omap_hsmmc_stop_clock(host); 576 577 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 578 regval = regval & ~(CLKD_MASK | DTO_MASK); 579 clkdiv = calc_divisor(host, ios); 580 regval = regval | (clkdiv << 6) | (DTO << 16); 581 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 582 OMAP_HSMMC_WRITE(host->base, SYSCTL, 583 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 584 585 /* Wait till the ICS bit is set */ 586 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 587 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 588 && time_before(jiffies, timeout)) 589 cpu_relax(); 590 591 /* 592 * Enable High-Speed Support 593 * Pre-Requisites 594 * - Controller should support High-Speed-Enable Bit 595 * - Controller should not be using DDR Mode 596 * - Controller should advertise that it supports High Speed 597 * in capabilities register 598 * - MMC/SD clock coming out of controller > 25MHz 599 */ 600 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 601 (ios->timing != MMC_TIMING_MMC_DDR52) && 602 (ios->timing != MMC_TIMING_UHS_DDR50) && 603 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 604 regval = OMAP_HSMMC_READ(host->base, HCTL); 605 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 606 regval |= HSPE; 607 else 608 regval &= ~HSPE; 609 610 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 611 } 612 613 omap_hsmmc_start_clock(host); 614 } 615 616 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 617 { 618 struct mmc_ios *ios = &host->mmc->ios; 619 u32 con; 620 621 con = OMAP_HSMMC_READ(host->base, CON); 622 if (ios->timing == MMC_TIMING_MMC_DDR52 || 623 ios->timing == MMC_TIMING_UHS_DDR50) 624 con |= DDR; /* configure in DDR mode */ 625 else 626 con &= ~DDR; 627 switch (ios->bus_width) { 628 case MMC_BUS_WIDTH_8: 629 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 630 break; 631 case MMC_BUS_WIDTH_4: 632 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 633 OMAP_HSMMC_WRITE(host->base, HCTL, 634 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 635 break; 636 case MMC_BUS_WIDTH_1: 637 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 638 OMAP_HSMMC_WRITE(host->base, HCTL, 639 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 640 break; 641 } 642 } 643 644 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 645 { 646 struct mmc_ios *ios = &host->mmc->ios; 647 u32 con; 648 649 con = OMAP_HSMMC_READ(host->base, CON); 650 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 651 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 652 else 653 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 654 } 655 656 #ifdef CONFIG_PM 657 658 /* 659 * Restore the MMC host context, if it was lost as result of a 660 * power state change. 661 */ 662 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 663 { 664 struct mmc_ios *ios = &host->mmc->ios; 665 u32 hctl, capa; 666 unsigned long timeout; 667 668 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 669 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 670 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 671 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 672 return 0; 673 674 host->context_loss++; 675 676 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 677 if (host->power_mode != MMC_POWER_OFF && 678 (1 << ios->vdd) <= MMC_VDD_23_24) 679 hctl = SDVS18; 680 else 681 hctl = SDVS30; 682 capa = VS30 | VS18; 683 } else { 684 hctl = SDVS18; 685 capa = VS18; 686 } 687 688 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 689 hctl |= IWE; 690 691 OMAP_HSMMC_WRITE(host->base, HCTL, 692 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 693 694 OMAP_HSMMC_WRITE(host->base, CAPA, 695 OMAP_HSMMC_READ(host->base, CAPA) | capa); 696 697 OMAP_HSMMC_WRITE(host->base, HCTL, 698 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 699 700 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 701 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 702 && time_before(jiffies, timeout)) 703 ; 704 705 OMAP_HSMMC_WRITE(host->base, ISE, 0); 706 OMAP_HSMMC_WRITE(host->base, IE, 0); 707 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 708 709 /* Do not initialize card-specific things if the power is off */ 710 if (host->power_mode == MMC_POWER_OFF) 711 goto out; 712 713 omap_hsmmc_set_bus_width(host); 714 715 omap_hsmmc_set_clock(host); 716 717 omap_hsmmc_set_bus_mode(host); 718 719 out: 720 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 721 host->context_loss); 722 return 0; 723 } 724 725 /* 726 * Save the MMC host context (store the number of power state changes so far). 727 */ 728 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 729 { 730 host->con = OMAP_HSMMC_READ(host->base, CON); 731 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 732 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 733 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 734 } 735 736 #else 737 738 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 739 { 740 return 0; 741 } 742 743 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 744 { 745 } 746 747 #endif 748 749 /* 750 * Send init stream sequence to card 751 * before sending IDLE command 752 */ 753 static void send_init_stream(struct omap_hsmmc_host *host) 754 { 755 int reg = 0; 756 unsigned long timeout; 757 758 disable_irq(host->irq); 759 760 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 761 OMAP_HSMMC_WRITE(host->base, CON, 762 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 763 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 764 765 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 766 while ((reg != CC_EN) && time_before(jiffies, timeout)) 767 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 768 769 OMAP_HSMMC_WRITE(host->base, CON, 770 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 771 772 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 773 OMAP_HSMMC_READ(host->base, STAT); 774 775 enable_irq(host->irq); 776 } 777 778 static ssize_t 779 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 780 char *buf) 781 { 782 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 783 struct omap_hsmmc_host *host = mmc_priv(mmc); 784 785 return sprintf(buf, "%s\n", mmc_pdata(host)->name); 786 } 787 788 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 789 790 /* 791 * Configure the response type and send the cmd. 792 */ 793 static void 794 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 795 struct mmc_data *data) 796 { 797 int cmdreg = 0, resptype = 0, cmdtype = 0; 798 799 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 800 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 801 host->cmd = cmd; 802 803 omap_hsmmc_enable_irq(host, cmd); 804 805 host->response_busy = 0; 806 if (cmd->flags & MMC_RSP_PRESENT) { 807 if (cmd->flags & MMC_RSP_136) 808 resptype = 1; 809 else if (cmd->flags & MMC_RSP_BUSY) { 810 resptype = 3; 811 host->response_busy = 1; 812 } else 813 resptype = 2; 814 } 815 816 /* 817 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 818 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 819 * a val of 0x3, rest 0x0. 820 */ 821 if (cmd == host->mrq->stop) 822 cmdtype = 0x3; 823 824 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 825 826 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 827 host->mrq->sbc) { 828 cmdreg |= ACEN_ACMD23; 829 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 830 } 831 if (data) { 832 cmdreg |= DP_SELECT | MSBS | BCE; 833 if (data->flags & MMC_DATA_READ) 834 cmdreg |= DDIR; 835 else 836 cmdreg &= ~(DDIR); 837 } 838 839 if (host->use_dma) 840 cmdreg |= DMAE; 841 842 host->req_in_progress = 1; 843 844 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 845 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 846 } 847 848 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 849 struct mmc_data *data) 850 { 851 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 852 } 853 854 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 855 { 856 int dma_ch; 857 unsigned long flags; 858 859 spin_lock_irqsave(&host->irq_lock, flags); 860 host->req_in_progress = 0; 861 dma_ch = host->dma_ch; 862 spin_unlock_irqrestore(&host->irq_lock, flags); 863 864 omap_hsmmc_disable_irq(host); 865 /* Do not complete the request if DMA is still in progress */ 866 if (mrq->data && host->use_dma && dma_ch != -1) 867 return; 868 host->mrq = NULL; 869 mmc_request_done(host->mmc, mrq); 870 } 871 872 /* 873 * Notify the transfer complete to MMC core 874 */ 875 static void 876 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 877 { 878 if (!data) { 879 struct mmc_request *mrq = host->mrq; 880 881 /* TC before CC from CMD6 - don't know why, but it happens */ 882 if (host->cmd && host->cmd->opcode == 6 && 883 host->response_busy) { 884 host->response_busy = 0; 885 return; 886 } 887 888 omap_hsmmc_request_done(host, mrq); 889 return; 890 } 891 892 host->data = NULL; 893 894 if (!data->error) 895 data->bytes_xfered += data->blocks * (data->blksz); 896 else 897 data->bytes_xfered = 0; 898 899 if (data->stop && (data->error || !host->mrq->sbc)) 900 omap_hsmmc_start_command(host, data->stop, NULL); 901 else 902 omap_hsmmc_request_done(host, data->mrq); 903 } 904 905 /* 906 * Notify the core about command completion 907 */ 908 static void 909 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 910 { 911 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 912 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 913 host->cmd = NULL; 914 omap_hsmmc_start_dma_transfer(host); 915 omap_hsmmc_start_command(host, host->mrq->cmd, 916 host->mrq->data); 917 return; 918 } 919 920 host->cmd = NULL; 921 922 if (cmd->flags & MMC_RSP_PRESENT) { 923 if (cmd->flags & MMC_RSP_136) { 924 /* response type 2 */ 925 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 926 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 927 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 928 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 929 } else { 930 /* response types 1, 1b, 3, 4, 5, 6 */ 931 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 932 } 933 } 934 if ((host->data == NULL && !host->response_busy) || cmd->error) 935 omap_hsmmc_request_done(host, host->mrq); 936 } 937 938 /* 939 * DMA clean up for command errors 940 */ 941 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 942 { 943 int dma_ch; 944 unsigned long flags; 945 946 host->data->error = errno; 947 948 spin_lock_irqsave(&host->irq_lock, flags); 949 dma_ch = host->dma_ch; 950 host->dma_ch = -1; 951 spin_unlock_irqrestore(&host->irq_lock, flags); 952 953 if (host->use_dma && dma_ch != -1) { 954 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 955 956 dmaengine_terminate_all(chan); 957 dma_unmap_sg(chan->device->dev, 958 host->data->sg, host->data->sg_len, 959 mmc_get_dma_dir(host->data)); 960 961 host->data->host_cookie = 0; 962 } 963 host->data = NULL; 964 } 965 966 /* 967 * Readable error output 968 */ 969 #ifdef CONFIG_MMC_DEBUG 970 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 971 { 972 /* --- means reserved bit without definition at documentation */ 973 static const char *omap_hsmmc_status_bits[] = { 974 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 975 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 976 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 977 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 978 }; 979 char res[256]; 980 char *buf = res; 981 int len, i; 982 983 len = sprintf(buf, "MMC IRQ 0x%x :", status); 984 buf += len; 985 986 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 987 if (status & (1 << i)) { 988 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 989 buf += len; 990 } 991 992 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 993 } 994 #else 995 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 996 u32 status) 997 { 998 } 999 #endif /* CONFIG_MMC_DEBUG */ 1000 1001 /* 1002 * MMC controller internal state machines reset 1003 * 1004 * Used to reset command or data internal state machines, using respectively 1005 * SRC or SRD bit of SYSCTL register 1006 * Can be called from interrupt context 1007 */ 1008 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 1009 unsigned long bit) 1010 { 1011 unsigned long i = 0; 1012 unsigned long limit = MMC_TIMEOUT_US; 1013 1014 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1015 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 1016 1017 /* 1018 * OMAP4 ES2 and greater has an updated reset logic. 1019 * Monitor a 0->1 transition first 1020 */ 1021 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1022 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 1023 && (i++ < limit)) 1024 udelay(1); 1025 } 1026 i = 0; 1027 1028 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 1029 (i++ < limit)) 1030 udelay(1); 1031 1032 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1033 dev_err(mmc_dev(host->mmc), 1034 "Timeout waiting on controller reset in %s\n", 1035 __func__); 1036 } 1037 1038 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1039 int err, int end_cmd) 1040 { 1041 if (end_cmd) { 1042 omap_hsmmc_reset_controller_fsm(host, SRC); 1043 if (host->cmd) 1044 host->cmd->error = err; 1045 } 1046 1047 if (host->data) { 1048 omap_hsmmc_reset_controller_fsm(host, SRD); 1049 omap_hsmmc_dma_cleanup(host, err); 1050 } else if (host->mrq && host->mrq->cmd) 1051 host->mrq->cmd->error = err; 1052 } 1053 1054 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1055 { 1056 struct mmc_data *data; 1057 int end_cmd = 0, end_trans = 0; 1058 int error = 0; 1059 1060 data = host->data; 1061 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1062 1063 if (status & ERR_EN) { 1064 omap_hsmmc_dbg_report_irq(host, status); 1065 1066 if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1067 end_cmd = 1; 1068 if (host->data || host->response_busy) { 1069 end_trans = !end_cmd; 1070 host->response_busy = 0; 1071 } 1072 if (status & (CTO_EN | DTO_EN)) 1073 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1074 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 1075 BADA_EN)) 1076 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1077 1078 if (status & ACE_EN) { 1079 u32 ac12; 1080 ac12 = OMAP_HSMMC_READ(host->base, AC12); 1081 if (!(ac12 & ACNE) && host->mrq->sbc) { 1082 end_cmd = 1; 1083 if (ac12 & ACTO) 1084 error = -ETIMEDOUT; 1085 else if (ac12 & (ACCE | ACEB | ACIE)) 1086 error = -EILSEQ; 1087 host->mrq->sbc->error = error; 1088 hsmmc_command_incomplete(host, error, end_cmd); 1089 } 1090 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1091 } 1092 } 1093 1094 OMAP_HSMMC_WRITE(host->base, STAT, status); 1095 if (end_cmd || ((status & CC_EN) && host->cmd)) 1096 omap_hsmmc_cmd_done(host, host->cmd); 1097 if ((end_trans || (status & TC_EN)) && host->mrq) 1098 omap_hsmmc_xfer_done(host, data); 1099 } 1100 1101 /* 1102 * MMC controller IRQ handler 1103 */ 1104 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1105 { 1106 struct omap_hsmmc_host *host = dev_id; 1107 int status; 1108 1109 status = OMAP_HSMMC_READ(host->base, STAT); 1110 while (status & (INT_EN_MASK | CIRQ_EN)) { 1111 if (host->req_in_progress) 1112 omap_hsmmc_do_irq(host, status); 1113 1114 if (status & CIRQ_EN) 1115 mmc_signal_sdio_irq(host->mmc); 1116 1117 /* Flush posted write */ 1118 status = OMAP_HSMMC_READ(host->base, STAT); 1119 } 1120 1121 return IRQ_HANDLED; 1122 } 1123 1124 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1125 { 1126 unsigned long i; 1127 1128 OMAP_HSMMC_WRITE(host->base, HCTL, 1129 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1130 for (i = 0; i < loops_per_jiffy; i++) { 1131 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1132 break; 1133 cpu_relax(); 1134 } 1135 } 1136 1137 /* 1138 * Switch MMC interface voltage ... only relevant for MMC1. 1139 * 1140 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1141 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1142 * Some chips, like eMMC ones, use internal transceivers. 1143 */ 1144 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1145 { 1146 u32 reg_val = 0; 1147 int ret; 1148 1149 /* Disable the clocks */ 1150 if (host->dbclk) 1151 clk_disable_unprepare(host->dbclk); 1152 1153 /* Turn the power off */ 1154 ret = omap_hsmmc_set_power(host, 0); 1155 1156 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1157 if (!ret) 1158 ret = omap_hsmmc_set_power(host, 1); 1159 if (host->dbclk) 1160 clk_prepare_enable(host->dbclk); 1161 1162 if (ret != 0) 1163 goto err; 1164 1165 OMAP_HSMMC_WRITE(host->base, HCTL, 1166 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1167 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1168 1169 /* 1170 * If a MMC dual voltage card is detected, the set_ios fn calls 1171 * this fn with VDD bit set for 1.8V. Upon card removal from the 1172 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1173 * 1174 * Cope with a bit of slop in the range ... per data sheets: 1175 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1176 * but recommended values are 1.71V to 1.89V 1177 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1178 * but recommended values are 2.7V to 3.3V 1179 * 1180 * Board setup code shouldn't permit anything very out-of-range. 1181 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1182 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1183 */ 1184 if ((1 << vdd) <= MMC_VDD_23_24) 1185 reg_val |= SDVS18; 1186 else 1187 reg_val |= SDVS30; 1188 1189 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1190 set_sd_bus_power(host); 1191 1192 return 0; 1193 err: 1194 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1195 return ret; 1196 } 1197 1198 static void omap_hsmmc_dma_callback(void *param) 1199 { 1200 struct omap_hsmmc_host *host = param; 1201 struct dma_chan *chan; 1202 struct mmc_data *data; 1203 int req_in_progress; 1204 1205 spin_lock_irq(&host->irq_lock); 1206 if (host->dma_ch < 0) { 1207 spin_unlock_irq(&host->irq_lock); 1208 return; 1209 } 1210 1211 data = host->mrq->data; 1212 chan = omap_hsmmc_get_dma_chan(host, data); 1213 if (!data->host_cookie) 1214 dma_unmap_sg(chan->device->dev, 1215 data->sg, data->sg_len, 1216 mmc_get_dma_dir(data)); 1217 1218 req_in_progress = host->req_in_progress; 1219 host->dma_ch = -1; 1220 spin_unlock_irq(&host->irq_lock); 1221 1222 /* If DMA has finished after TC, complete the request */ 1223 if (!req_in_progress) { 1224 struct mmc_request *mrq = host->mrq; 1225 1226 host->mrq = NULL; 1227 mmc_request_done(host->mmc, mrq); 1228 } 1229 } 1230 1231 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1232 struct mmc_data *data, 1233 struct omap_hsmmc_next *next, 1234 struct dma_chan *chan) 1235 { 1236 int dma_len; 1237 1238 if (!next && data->host_cookie && 1239 data->host_cookie != host->next_data.cookie) { 1240 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1241 " host->next_data.cookie %d\n", 1242 __func__, data->host_cookie, host->next_data.cookie); 1243 data->host_cookie = 0; 1244 } 1245 1246 /* Check if next job is already prepared */ 1247 if (next || data->host_cookie != host->next_data.cookie) { 1248 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1249 mmc_get_dma_dir(data)); 1250 1251 } else { 1252 dma_len = host->next_data.dma_len; 1253 host->next_data.dma_len = 0; 1254 } 1255 1256 1257 if (dma_len == 0) 1258 return -EINVAL; 1259 1260 if (next) { 1261 next->dma_len = dma_len; 1262 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1263 } else 1264 host->dma_len = dma_len; 1265 1266 return 0; 1267 } 1268 1269 /* 1270 * Routine to configure and start DMA for the MMC card 1271 */ 1272 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 1273 struct mmc_request *req) 1274 { 1275 struct dma_async_tx_descriptor *tx; 1276 int ret = 0, i; 1277 struct mmc_data *data = req->data; 1278 struct dma_chan *chan; 1279 struct dma_slave_config cfg = { 1280 .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1281 .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1282 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1283 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1284 .src_maxburst = data->blksz / 4, 1285 .dst_maxburst = data->blksz / 4, 1286 }; 1287 1288 /* Sanity check: all the SG entries must be aligned by block size. */ 1289 for (i = 0; i < data->sg_len; i++) { 1290 struct scatterlist *sgl; 1291 1292 sgl = data->sg + i; 1293 if (sgl->length % data->blksz) 1294 return -EINVAL; 1295 } 1296 if ((data->blksz % 4) != 0) 1297 /* REVISIT: The MMC buffer increments only when MSB is written. 1298 * Return error for blksz which is non multiple of four. 1299 */ 1300 return -EINVAL; 1301 1302 BUG_ON(host->dma_ch != -1); 1303 1304 chan = omap_hsmmc_get_dma_chan(host, data); 1305 1306 ret = dmaengine_slave_config(chan, &cfg); 1307 if (ret) 1308 return ret; 1309 1310 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1311 if (ret) 1312 return ret; 1313 1314 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1315 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1317 if (!tx) { 1318 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1319 /* FIXME: cleanup */ 1320 return -1; 1321 } 1322 1323 tx->callback = omap_hsmmc_dma_callback; 1324 tx->callback_param = host; 1325 1326 /* Does not fail */ 1327 dmaengine_submit(tx); 1328 1329 host->dma_ch = 1; 1330 1331 return 0; 1332 } 1333 1334 static void set_data_timeout(struct omap_hsmmc_host *host, 1335 unsigned long long timeout_ns, 1336 unsigned int timeout_clks) 1337 { 1338 unsigned long long timeout = timeout_ns; 1339 unsigned int cycle_ns; 1340 uint32_t reg, clkd, dto = 0; 1341 1342 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1343 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1344 if (clkd == 0) 1345 clkd = 1; 1346 1347 cycle_ns = 1000000000 / (host->clk_rate / clkd); 1348 do_div(timeout, cycle_ns); 1349 timeout += timeout_clks; 1350 if (timeout) { 1351 while ((timeout & 0x80000000) == 0) { 1352 dto += 1; 1353 timeout <<= 1; 1354 } 1355 dto = 31 - dto; 1356 timeout <<= 1; 1357 if (timeout && dto) 1358 dto += 1; 1359 if (dto >= 13) 1360 dto -= 13; 1361 else 1362 dto = 0; 1363 if (dto > 14) 1364 dto = 14; 1365 } 1366 1367 reg &= ~DTO_MASK; 1368 reg |= dto << DTO_SHIFT; 1369 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1370 } 1371 1372 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 1373 { 1374 struct mmc_request *req = host->mrq; 1375 struct dma_chan *chan; 1376 1377 if (!req->data) 1378 return; 1379 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1380 | (req->data->blocks << 16)); 1381 set_data_timeout(host, req->data->timeout_ns, 1382 req->data->timeout_clks); 1383 chan = omap_hsmmc_get_dma_chan(host, req->data); 1384 dma_async_issue_pending(chan); 1385 } 1386 1387 /* 1388 * Configure block length for MMC/SD cards and initiate the transfer. 1389 */ 1390 static int 1391 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1392 { 1393 int ret; 1394 unsigned long long timeout; 1395 1396 host->data = req->data; 1397 1398 if (req->data == NULL) { 1399 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1400 if (req->cmd->flags & MMC_RSP_BUSY) { 1401 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 1402 1403 /* 1404 * Set an arbitrary 100ms data timeout for commands with 1405 * busy signal and no indication of busy_timeout. 1406 */ 1407 if (!timeout) 1408 timeout = 100000000U; 1409 1410 set_data_timeout(host, timeout, 0); 1411 } 1412 return 0; 1413 } 1414 1415 if (host->use_dma) { 1416 ret = omap_hsmmc_setup_dma_transfer(host, req); 1417 if (ret != 0) { 1418 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1419 return ret; 1420 } 1421 } 1422 return 0; 1423 } 1424 1425 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1426 int err) 1427 { 1428 struct omap_hsmmc_host *host = mmc_priv(mmc); 1429 struct mmc_data *data = mrq->data; 1430 1431 if (host->use_dma && data->host_cookie) { 1432 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1433 1434 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1435 mmc_get_dma_dir(data)); 1436 data->host_cookie = 0; 1437 } 1438 } 1439 1440 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1441 { 1442 struct omap_hsmmc_host *host = mmc_priv(mmc); 1443 1444 if (mrq->data->host_cookie) { 1445 mrq->data->host_cookie = 0; 1446 return ; 1447 } 1448 1449 if (host->use_dma) { 1450 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1451 1452 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1453 &host->next_data, c)) 1454 mrq->data->host_cookie = 0; 1455 } 1456 } 1457 1458 /* 1459 * Request function. for read/write operation 1460 */ 1461 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1462 { 1463 struct omap_hsmmc_host *host = mmc_priv(mmc); 1464 int err; 1465 1466 BUG_ON(host->req_in_progress); 1467 BUG_ON(host->dma_ch != -1); 1468 if (host->reqs_blocked) 1469 host->reqs_blocked = 0; 1470 WARN_ON(host->mrq != NULL); 1471 host->mrq = req; 1472 host->clk_rate = clk_get_rate(host->fclk); 1473 err = omap_hsmmc_prepare_data(host, req); 1474 if (err) { 1475 req->cmd->error = err; 1476 if (req->data) 1477 req->data->error = err; 1478 host->mrq = NULL; 1479 mmc_request_done(mmc, req); 1480 return; 1481 } 1482 if (req->sbc && !(host->flags & AUTO_CMD23)) { 1483 omap_hsmmc_start_command(host, req->sbc, NULL); 1484 return; 1485 } 1486 1487 omap_hsmmc_start_dma_transfer(host); 1488 omap_hsmmc_start_command(host, req->cmd, req->data); 1489 } 1490 1491 /* Routine to configure clock values. Exposed API to core */ 1492 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1493 { 1494 struct omap_hsmmc_host *host = mmc_priv(mmc); 1495 int do_send_init_stream = 0; 1496 1497 if (ios->power_mode != host->power_mode) { 1498 switch (ios->power_mode) { 1499 case MMC_POWER_OFF: 1500 omap_hsmmc_set_power(host, 0); 1501 break; 1502 case MMC_POWER_UP: 1503 omap_hsmmc_set_power(host, 1); 1504 break; 1505 case MMC_POWER_ON: 1506 do_send_init_stream = 1; 1507 break; 1508 } 1509 host->power_mode = ios->power_mode; 1510 } 1511 1512 /* FIXME: set registers based only on changes to ios */ 1513 1514 omap_hsmmc_set_bus_width(host); 1515 1516 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1517 /* Only MMC1 can interface at 3V without some flavor 1518 * of external transceiver; but they all handle 1.8V. 1519 */ 1520 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1521 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1522 /* 1523 * The mmc_select_voltage fn of the core does 1524 * not seem to set the power_mode to 1525 * MMC_POWER_UP upon recalculating the voltage. 1526 * vdd 1.8v. 1527 */ 1528 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1529 dev_dbg(mmc_dev(host->mmc), 1530 "Switch operation failed\n"); 1531 } 1532 } 1533 1534 omap_hsmmc_set_clock(host); 1535 1536 if (do_send_init_stream) 1537 send_init_stream(host); 1538 1539 omap_hsmmc_set_bus_mode(host); 1540 } 1541 1542 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1543 { 1544 struct omap_hsmmc_host *host = mmc_priv(mmc); 1545 1546 if (!host->card_detect) 1547 return -ENOSYS; 1548 return host->card_detect(host->dev); 1549 } 1550 1551 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1552 { 1553 struct omap_hsmmc_host *host = mmc_priv(mmc); 1554 1555 if (mmc_pdata(host)->init_card) 1556 mmc_pdata(host)->init_card(card); 1557 } 1558 1559 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1560 { 1561 struct omap_hsmmc_host *host = mmc_priv(mmc); 1562 u32 irq_mask, con; 1563 unsigned long flags; 1564 1565 spin_lock_irqsave(&host->irq_lock, flags); 1566 1567 con = OMAP_HSMMC_READ(host->base, CON); 1568 irq_mask = OMAP_HSMMC_READ(host->base, ISE); 1569 if (enable) { 1570 host->flags |= HSMMC_SDIO_IRQ_ENABLED; 1571 irq_mask |= CIRQ_EN; 1572 con |= CTPL | CLKEXTFREE; 1573 } else { 1574 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 1575 irq_mask &= ~CIRQ_EN; 1576 con &= ~(CTPL | CLKEXTFREE); 1577 } 1578 OMAP_HSMMC_WRITE(host->base, CON, con); 1579 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 1580 1581 /* 1582 * if enable, piggy back detection on current request 1583 * but always disable immediately 1584 */ 1585 if (!host->req_in_progress || !enable) 1586 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 1587 1588 /* flush posted write */ 1589 OMAP_HSMMC_READ(host->base, IE); 1590 1591 spin_unlock_irqrestore(&host->irq_lock, flags); 1592 } 1593 1594 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 1595 { 1596 int ret; 1597 1598 /* 1599 * For omaps with wake-up path, wakeirq will be irq from pinctrl and 1600 * for other omaps, wakeirq will be from GPIO (dat line remuxed to 1601 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 1602 * with functional clock disabled. 1603 */ 1604 if (!host->dev->of_node || !host->wake_irq) 1605 return -ENODEV; 1606 1607 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 1608 if (ret) { 1609 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 1610 goto err; 1611 } 1612 1613 /* 1614 * Some omaps don't have wake-up path from deeper idle states 1615 * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 1616 */ 1617 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1618 struct pinctrl *p = devm_pinctrl_get(host->dev); 1619 if (IS_ERR(p)) { 1620 ret = PTR_ERR(p); 1621 goto err_free_irq; 1622 } 1623 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1624 dev_info(host->dev, "missing default pinctrl state\n"); 1625 devm_pinctrl_put(p); 1626 ret = -EINVAL; 1627 goto err_free_irq; 1628 } 1629 1630 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1631 dev_info(host->dev, "missing idle pinctrl state\n"); 1632 devm_pinctrl_put(p); 1633 ret = -EINVAL; 1634 goto err_free_irq; 1635 } 1636 devm_pinctrl_put(p); 1637 } 1638 1639 OMAP_HSMMC_WRITE(host->base, HCTL, 1640 OMAP_HSMMC_READ(host->base, HCTL) | IWE); 1641 return 0; 1642 1643 err_free_irq: 1644 dev_pm_clear_wake_irq(host->dev); 1645 err: 1646 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 1647 host->wake_irq = 0; 1648 return ret; 1649 } 1650 1651 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1652 { 1653 u32 hctl, capa, value; 1654 1655 /* Only MMC1 supports 3.0V */ 1656 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1657 hctl = SDVS30; 1658 capa = VS30 | VS18; 1659 } else { 1660 hctl = SDVS18; 1661 capa = VS18; 1662 } 1663 1664 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1665 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1666 1667 value = OMAP_HSMMC_READ(host->base, CAPA); 1668 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1669 1670 /* Set SD bus power bit */ 1671 set_sd_bus_power(host); 1672 } 1673 1674 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1675 unsigned int direction, int blk_size) 1676 { 1677 /* This controller can't do multiblock reads due to hw bugs */ 1678 if (direction == MMC_DATA_READ) 1679 return 1; 1680 1681 return blk_size; 1682 } 1683 1684 static struct mmc_host_ops omap_hsmmc_ops = { 1685 .post_req = omap_hsmmc_post_req, 1686 .pre_req = omap_hsmmc_pre_req, 1687 .request = omap_hsmmc_request, 1688 .set_ios = omap_hsmmc_set_ios, 1689 .get_cd = omap_hsmmc_get_cd, 1690 .get_ro = mmc_gpio_get_ro, 1691 .init_card = omap_hsmmc_init_card, 1692 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1693 }; 1694 1695 #ifdef CONFIG_DEBUG_FS 1696 1697 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1698 { 1699 struct mmc_host *mmc = s->private; 1700 struct omap_hsmmc_host *host = mmc_priv(mmc); 1701 1702 seq_printf(s, "mmc%d:\n", mmc->index); 1703 seq_printf(s, "sdio irq mode\t%s\n", 1704 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1705 1706 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1707 seq_printf(s, "sdio irq \t%s\n", 1708 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1709 : "disabled"); 1710 } 1711 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 1712 1713 pm_runtime_get_sync(host->dev); 1714 seq_puts(s, "\nregs:\n"); 1715 seq_printf(s, "CON:\t\t0x%08x\n", 1716 OMAP_HSMMC_READ(host->base, CON)); 1717 seq_printf(s, "PSTATE:\t\t0x%08x\n", 1718 OMAP_HSMMC_READ(host->base, PSTATE)); 1719 seq_printf(s, "HCTL:\t\t0x%08x\n", 1720 OMAP_HSMMC_READ(host->base, HCTL)); 1721 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1722 OMAP_HSMMC_READ(host->base, SYSCTL)); 1723 seq_printf(s, "IE:\t\t0x%08x\n", 1724 OMAP_HSMMC_READ(host->base, IE)); 1725 seq_printf(s, "ISE:\t\t0x%08x\n", 1726 OMAP_HSMMC_READ(host->base, ISE)); 1727 seq_printf(s, "CAPA:\t\t0x%08x\n", 1728 OMAP_HSMMC_READ(host->base, CAPA)); 1729 1730 pm_runtime_mark_last_busy(host->dev); 1731 pm_runtime_put_autosuspend(host->dev); 1732 1733 return 0; 1734 } 1735 1736 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1737 { 1738 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1739 } 1740 1741 static const struct file_operations mmc_regs_fops = { 1742 .open = omap_hsmmc_regs_open, 1743 .read = seq_read, 1744 .llseek = seq_lseek, 1745 .release = single_release, 1746 }; 1747 1748 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1749 { 1750 if (mmc->debugfs_root) 1751 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1752 mmc, &mmc_regs_fops); 1753 } 1754 1755 #else 1756 1757 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1758 { 1759 } 1760 1761 #endif 1762 1763 #ifdef CONFIG_OF 1764 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 1765 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1766 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1767 }; 1768 1769 static const struct omap_mmc_of_data omap4_mmc_of_data = { 1770 .reg_offset = 0x100, 1771 }; 1772 static const struct omap_mmc_of_data am33xx_mmc_of_data = { 1773 .reg_offset = 0x100, 1774 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 1775 }; 1776 1777 static const struct of_device_id omap_mmc_of_match[] = { 1778 { 1779 .compatible = "ti,omap2-hsmmc", 1780 }, 1781 { 1782 .compatible = "ti,omap3-pre-es3-hsmmc", 1783 .data = &omap3_pre_es3_mmc_of_data, 1784 }, 1785 { 1786 .compatible = "ti,omap3-hsmmc", 1787 }, 1788 { 1789 .compatible = "ti,omap4-hsmmc", 1790 .data = &omap4_mmc_of_data, 1791 }, 1792 { 1793 .compatible = "ti,am33xx-hsmmc", 1794 .data = &am33xx_mmc_of_data, 1795 }, 1796 {}, 1797 }; 1798 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1799 1800 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1801 { 1802 struct omap_hsmmc_platform_data *pdata, *legacy; 1803 struct device_node *np = dev->of_node; 1804 1805 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1806 if (!pdata) 1807 return ERR_PTR(-ENOMEM); /* out of memory */ 1808 1809 legacy = dev_get_platdata(dev); 1810 if (legacy && legacy->name) 1811 pdata->name = legacy->name; 1812 1813 if (of_find_property(np, "ti,dual-volt", NULL)) 1814 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1815 1816 pdata->gpio_cd = -EINVAL; 1817 pdata->gpio_wp = -EINVAL; 1818 1819 if (of_find_property(np, "ti,non-removable", NULL)) { 1820 pdata->nonremovable = true; 1821 pdata->no_regulator_off_init = true; 1822 } 1823 1824 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1825 pdata->features |= HSMMC_HAS_UPDATED_RESET; 1826 1827 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1828 pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1829 1830 return pdata; 1831 } 1832 #else 1833 static inline struct omap_hsmmc_platform_data 1834 *of_get_hsmmc_pdata(struct device *dev) 1835 { 1836 return ERR_PTR(-EINVAL); 1837 } 1838 #endif 1839 1840 static int omap_hsmmc_probe(struct platform_device *pdev) 1841 { 1842 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1843 struct mmc_host *mmc; 1844 struct omap_hsmmc_host *host = NULL; 1845 struct resource *res; 1846 int ret, irq; 1847 const struct of_device_id *match; 1848 const struct omap_mmc_of_data *data; 1849 void __iomem *base; 1850 1851 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1852 if (match) { 1853 pdata = of_get_hsmmc_pdata(&pdev->dev); 1854 1855 if (IS_ERR(pdata)) 1856 return PTR_ERR(pdata); 1857 1858 if (match->data) { 1859 data = match->data; 1860 pdata->reg_offset = data->reg_offset; 1861 pdata->controller_flags |= data->controller_flags; 1862 } 1863 } 1864 1865 if (pdata == NULL) { 1866 dev_err(&pdev->dev, "Platform Data is missing\n"); 1867 return -ENXIO; 1868 } 1869 1870 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1871 irq = platform_get_irq(pdev, 0); 1872 if (res == NULL || irq < 0) 1873 return -ENXIO; 1874 1875 base = devm_ioremap_resource(&pdev->dev, res); 1876 if (IS_ERR(base)) 1877 return PTR_ERR(base); 1878 1879 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1880 if (!mmc) { 1881 ret = -ENOMEM; 1882 goto err; 1883 } 1884 1885 ret = mmc_of_parse(mmc); 1886 if (ret) 1887 goto err1; 1888 1889 host = mmc_priv(mmc); 1890 host->mmc = mmc; 1891 host->pdata = pdata; 1892 host->dev = &pdev->dev; 1893 host->use_dma = 1; 1894 host->dma_ch = -1; 1895 host->irq = irq; 1896 host->mapbase = res->start + pdata->reg_offset; 1897 host->base = base + pdata->reg_offset; 1898 host->power_mode = MMC_POWER_OFF; 1899 host->next_data.cookie = 1; 1900 host->pbias_enabled = 0; 1901 host->vqmmc_enabled = 0; 1902 1903 ret = omap_hsmmc_gpio_init(mmc, host, pdata); 1904 if (ret) 1905 goto err_gpio; 1906 1907 platform_set_drvdata(pdev, host); 1908 1909 if (pdev->dev.of_node) 1910 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1911 1912 mmc->ops = &omap_hsmmc_ops; 1913 1914 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1915 1916 if (pdata->max_freq > 0) 1917 mmc->f_max = pdata->max_freq; 1918 else if (mmc->f_max == 0) 1919 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1920 1921 spin_lock_init(&host->irq_lock); 1922 1923 host->fclk = devm_clk_get(&pdev->dev, "fck"); 1924 if (IS_ERR(host->fclk)) { 1925 ret = PTR_ERR(host->fclk); 1926 host->fclk = NULL; 1927 goto err1; 1928 } 1929 1930 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1931 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1932 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 1933 } 1934 1935 device_init_wakeup(&pdev->dev, true); 1936 pm_runtime_enable(host->dev); 1937 pm_runtime_get_sync(host->dev); 1938 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1939 pm_runtime_use_autosuspend(host->dev); 1940 1941 omap_hsmmc_context_save(host); 1942 1943 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 1944 /* 1945 * MMC can still work without debounce clock. 1946 */ 1947 if (IS_ERR(host->dbclk)) { 1948 host->dbclk = NULL; 1949 } else if (clk_prepare_enable(host->dbclk) != 0) { 1950 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1951 host->dbclk = NULL; 1952 } 1953 1954 /* Set this to a value that allows allocating an entire descriptor 1955 * list within a page (zero order allocation). */ 1956 mmc->max_segs = 64; 1957 1958 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1959 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1960 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1961 mmc->max_seg_size = mmc->max_req_size; 1962 1963 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1964 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; 1965 1966 mmc->caps |= mmc_pdata(host)->caps; 1967 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1968 mmc->caps |= MMC_CAP_4_BIT_DATA; 1969 1970 if (mmc_pdata(host)->nonremovable) 1971 mmc->caps |= MMC_CAP_NONREMOVABLE; 1972 1973 mmc->pm_caps |= mmc_pdata(host)->pm_caps; 1974 1975 omap_hsmmc_conf_bus_power(host); 1976 1977 host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 1978 if (IS_ERR(host->rx_chan)) { 1979 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 1980 ret = PTR_ERR(host->rx_chan); 1981 goto err_irq; 1982 } 1983 1984 host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 1985 if (IS_ERR(host->tx_chan)) { 1986 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 1987 ret = PTR_ERR(host->tx_chan); 1988 goto err_irq; 1989 } 1990 1991 /* Request IRQ for MMC operations */ 1992 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 1993 mmc_hostname(mmc), host); 1994 if (ret) { 1995 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1996 goto err_irq; 1997 } 1998 1999 ret = omap_hsmmc_reg_get(host); 2000 if (ret) 2001 goto err_irq; 2002 2003 if (!mmc->ocr_avail) 2004 mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2005 2006 omap_hsmmc_disable_irq(host); 2007 2008 /* 2009 * For now, only support SDIO interrupt if we have a separate 2010 * wake-up interrupt configured from device tree. This is because 2011 * the wake-up interrupt is needed for idle state and some 2012 * platforms need special quirks. And we don't want to add new 2013 * legacy mux platform init code callbacks any longer as we 2014 * are moving to DT based booting anyways. 2015 */ 2016 ret = omap_hsmmc_configure_wake_irq(host); 2017 if (!ret) 2018 mmc->caps |= MMC_CAP_SDIO_IRQ; 2019 2020 mmc_add_host(mmc); 2021 2022 if (mmc_pdata(host)->name != NULL) { 2023 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2024 if (ret < 0) 2025 goto err_slot_name; 2026 } 2027 2028 omap_hsmmc_debugfs(mmc); 2029 pm_runtime_mark_last_busy(host->dev); 2030 pm_runtime_put_autosuspend(host->dev); 2031 2032 return 0; 2033 2034 err_slot_name: 2035 mmc_remove_host(mmc); 2036 err_irq: 2037 device_init_wakeup(&pdev->dev, false); 2038 if (!IS_ERR_OR_NULL(host->tx_chan)) 2039 dma_release_channel(host->tx_chan); 2040 if (!IS_ERR_OR_NULL(host->rx_chan)) 2041 dma_release_channel(host->rx_chan); 2042 pm_runtime_dont_use_autosuspend(host->dev); 2043 pm_runtime_put_sync(host->dev); 2044 pm_runtime_disable(host->dev); 2045 if (host->dbclk) 2046 clk_disable_unprepare(host->dbclk); 2047 err1: 2048 err_gpio: 2049 mmc_free_host(mmc); 2050 err: 2051 return ret; 2052 } 2053 2054 static int omap_hsmmc_remove(struct platform_device *pdev) 2055 { 2056 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2057 2058 pm_runtime_get_sync(host->dev); 2059 mmc_remove_host(host->mmc); 2060 2061 dma_release_channel(host->tx_chan); 2062 dma_release_channel(host->rx_chan); 2063 2064 dev_pm_clear_wake_irq(host->dev); 2065 pm_runtime_dont_use_autosuspend(host->dev); 2066 pm_runtime_put_sync(host->dev); 2067 pm_runtime_disable(host->dev); 2068 device_init_wakeup(&pdev->dev, false); 2069 if (host->dbclk) 2070 clk_disable_unprepare(host->dbclk); 2071 2072 mmc_free_host(host->mmc); 2073 2074 return 0; 2075 } 2076 2077 #ifdef CONFIG_PM_SLEEP 2078 static int omap_hsmmc_suspend(struct device *dev) 2079 { 2080 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2081 2082 if (!host) 2083 return 0; 2084 2085 pm_runtime_get_sync(host->dev); 2086 2087 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2088 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2089 OMAP_HSMMC_WRITE(host->base, IE, 0); 2090 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2091 OMAP_HSMMC_WRITE(host->base, HCTL, 2092 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2093 } 2094 2095 if (host->dbclk) 2096 clk_disable_unprepare(host->dbclk); 2097 2098 pm_runtime_put_sync(host->dev); 2099 return 0; 2100 } 2101 2102 /* Routine to resume the MMC device */ 2103 static int omap_hsmmc_resume(struct device *dev) 2104 { 2105 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2106 2107 if (!host) 2108 return 0; 2109 2110 pm_runtime_get_sync(host->dev); 2111 2112 if (host->dbclk) 2113 clk_prepare_enable(host->dbclk); 2114 2115 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2116 omap_hsmmc_conf_bus_power(host); 2117 2118 pm_runtime_mark_last_busy(host->dev); 2119 pm_runtime_put_autosuspend(host->dev); 2120 return 0; 2121 } 2122 #endif 2123 2124 static int omap_hsmmc_runtime_suspend(struct device *dev) 2125 { 2126 struct omap_hsmmc_host *host; 2127 unsigned long flags; 2128 int ret = 0; 2129 2130 host = platform_get_drvdata(to_platform_device(dev)); 2131 omap_hsmmc_context_save(host); 2132 dev_dbg(dev, "disabled\n"); 2133 2134 spin_lock_irqsave(&host->irq_lock, flags); 2135 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2136 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2137 /* disable sdio irq handling to prevent race */ 2138 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2139 OMAP_HSMMC_WRITE(host->base, IE, 0); 2140 2141 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2142 /* 2143 * dat1 line low, pending sdio irq 2144 * race condition: possible irq handler running on 2145 * multi-core, abort 2146 */ 2147 dev_dbg(dev, "pending sdio irq, abort suspend\n"); 2148 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2149 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2150 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2151 pm_runtime_mark_last_busy(dev); 2152 ret = -EBUSY; 2153 goto abort; 2154 } 2155 2156 pinctrl_pm_select_idle_state(dev); 2157 } else { 2158 pinctrl_pm_select_idle_state(dev); 2159 } 2160 2161 abort: 2162 spin_unlock_irqrestore(&host->irq_lock, flags); 2163 return ret; 2164 } 2165 2166 static int omap_hsmmc_runtime_resume(struct device *dev) 2167 { 2168 struct omap_hsmmc_host *host; 2169 unsigned long flags; 2170 2171 host = platform_get_drvdata(to_platform_device(dev)); 2172 omap_hsmmc_context_restore(host); 2173 dev_dbg(dev, "enabled\n"); 2174 2175 spin_lock_irqsave(&host->irq_lock, flags); 2176 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2177 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2178 2179 pinctrl_pm_select_default_state(host->dev); 2180 2181 /* irq lost, if pinmux incorrect */ 2182 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2183 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2184 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2185 } else { 2186 pinctrl_pm_select_default_state(host->dev); 2187 } 2188 spin_unlock_irqrestore(&host->irq_lock, flags); 2189 return 0; 2190 } 2191 2192 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2193 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2194 .runtime_suspend = omap_hsmmc_runtime_suspend, 2195 .runtime_resume = omap_hsmmc_runtime_resume, 2196 }; 2197 2198 static struct platform_driver omap_hsmmc_driver = { 2199 .probe = omap_hsmmc_probe, 2200 .remove = omap_hsmmc_remove, 2201 .driver = { 2202 .name = DRIVER_NAME, 2203 .pm = &omap_hsmmc_dev_pm_ops, 2204 .of_match_table = of_match_ptr(omap_mmc_of_match), 2205 }, 2206 }; 2207 2208 module_platform_driver(omap_hsmmc_driver); 2209 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2210 MODULE_LICENSE("GPL"); 2211 MODULE_ALIAS("platform:" DRIVER_NAME); 2212 MODULE_AUTHOR("Texas Instruments Inc"); 2213