1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/sizes.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/timer.h> 30 #include <linux/clk.h> 31 #include <linux/of.h> 32 #include <linux/of_gpio.h> 33 #include <linux/of_device.h> 34 #include <linux/omap-dma.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/core.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/io.h> 39 #include <linux/gpio.h> 40 #include <linux/regulator/consumer.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/platform_data/mmc-omap.h> 44 45 /* OMAP HSMMC Host Controller Registers */ 46 #define OMAP_HSMMC_SYSSTATUS 0x0014 47 #define OMAP_HSMMC_CON 0x002C 48 #define OMAP_HSMMC_BLK 0x0104 49 #define OMAP_HSMMC_ARG 0x0108 50 #define OMAP_HSMMC_CMD 0x010C 51 #define OMAP_HSMMC_RSP10 0x0110 52 #define OMAP_HSMMC_RSP32 0x0114 53 #define OMAP_HSMMC_RSP54 0x0118 54 #define OMAP_HSMMC_RSP76 0x011C 55 #define OMAP_HSMMC_DATA 0x0120 56 #define OMAP_HSMMC_HCTL 0x0128 57 #define OMAP_HSMMC_SYSCTL 0x012C 58 #define OMAP_HSMMC_STAT 0x0130 59 #define OMAP_HSMMC_IE 0x0134 60 #define OMAP_HSMMC_ISE 0x0138 61 #define OMAP_HSMMC_CAPA 0x0140 62 63 #define VS18 (1 << 26) 64 #define VS30 (1 << 25) 65 #define HSS (1 << 21) 66 #define SDVS18 (0x5 << 9) 67 #define SDVS30 (0x6 << 9) 68 #define SDVS33 (0x7 << 9) 69 #define SDVS_MASK 0x00000E00 70 #define SDVSCLR 0xFFFFF1FF 71 #define SDVSDET 0x00000400 72 #define AUTOIDLE 0x1 73 #define SDBP (1 << 8) 74 #define DTO 0xe 75 #define ICE 0x1 76 #define ICS 0x2 77 #define CEN (1 << 2) 78 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 79 #define CLKD_MASK 0x0000FFC0 80 #define CLKD_SHIFT 6 81 #define DTO_MASK 0x000F0000 82 #define DTO_SHIFT 16 83 #define INIT_STREAM (1 << 1) 84 #define DP_SELECT (1 << 21) 85 #define DDIR (1 << 4) 86 #define DMAE 0x1 87 #define MSBS (1 << 5) 88 #define BCE (1 << 1) 89 #define FOUR_BIT (1 << 1) 90 #define HSPE (1 << 2) 91 #define DDR (1 << 19) 92 #define DW8 (1 << 5) 93 #define OD 0x1 94 #define STAT_CLEAR 0xFFFFFFFF 95 #define INIT_STREAM_CMD 0x00000000 96 #define DUAL_VOLT_OCR_BIT 7 97 #define SRC (1 << 25) 98 #define SRD (1 << 26) 99 #define SOFTRESET (1 << 1) 100 #define RESETDONE (1 << 0) 101 102 /* Interrupt masks for IE and ISE register */ 103 #define CC_EN (1 << 0) 104 #define TC_EN (1 << 1) 105 #define BWR_EN (1 << 4) 106 #define BRR_EN (1 << 5) 107 #define ERR_EN (1 << 15) 108 #define CTO_EN (1 << 16) 109 #define CCRC_EN (1 << 17) 110 #define CEB_EN (1 << 18) 111 #define CIE_EN (1 << 19) 112 #define DTO_EN (1 << 20) 113 #define DCRC_EN (1 << 21) 114 #define DEB_EN (1 << 22) 115 #define CERR_EN (1 << 28) 116 #define BADA_EN (1 << 29) 117 118 #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 119 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 120 BRR_EN | BWR_EN | TC_EN | CC_EN) 121 122 #define MMC_AUTOSUSPEND_DELAY 100 123 #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 124 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 125 #define OMAP_MMC_MIN_CLOCK 400000 126 #define OMAP_MMC_MAX_CLOCK 52000000 127 #define DRIVER_NAME "omap_hsmmc" 128 129 /* 130 * One controller can have multiple slots, like on some omap boards using 131 * omap.c controller driver. Luckily this is not currently done on any known 132 * omap_hsmmc.c device. 133 */ 134 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 135 136 /* 137 * MMC Host controller read/write API's 138 */ 139 #define OMAP_HSMMC_READ(base, reg) \ 140 __raw_readl((base) + OMAP_HSMMC_##reg) 141 142 #define OMAP_HSMMC_WRITE(base, reg, val) \ 143 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 144 145 struct omap_hsmmc_next { 146 unsigned int dma_len; 147 s32 cookie; 148 }; 149 150 struct omap_hsmmc_host { 151 struct device *dev; 152 struct mmc_host *mmc; 153 struct mmc_request *mrq; 154 struct mmc_command *cmd; 155 struct mmc_data *data; 156 struct clk *fclk; 157 struct clk *dbclk; 158 /* 159 * vcc == configured supply 160 * vcc_aux == optional 161 * - MMC1, supply for DAT4..DAT7 162 * - MMC2/MMC2, external level shifter voltage supply, for 163 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 164 */ 165 struct regulator *vcc; 166 struct regulator *vcc_aux; 167 int pbias_disable; 168 void __iomem *base; 169 resource_size_t mapbase; 170 spinlock_t irq_lock; /* Prevent races with irq handler */ 171 unsigned int dma_len; 172 unsigned int dma_sg_idx; 173 unsigned char bus_mode; 174 unsigned char power_mode; 175 int suspended; 176 u32 con; 177 u32 hctl; 178 u32 sysctl; 179 u32 capa; 180 int irq; 181 int use_dma, dma_ch; 182 struct dma_chan *tx_chan; 183 struct dma_chan *rx_chan; 184 int slot_id; 185 int response_busy; 186 int context_loss; 187 int protect_card; 188 int reqs_blocked; 189 int use_reg; 190 int req_in_progress; 191 struct omap_hsmmc_next next_data; 192 struct omap_mmc_platform_data *pdata; 193 }; 194 195 static int omap_hsmmc_card_detect(struct device *dev, int slot) 196 { 197 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 198 struct omap_mmc_platform_data *mmc = host->pdata; 199 200 /* NOTE: assumes card detect signal is active-low */ 201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 202 } 203 204 static int omap_hsmmc_get_wp(struct device *dev, int slot) 205 { 206 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 207 struct omap_mmc_platform_data *mmc = host->pdata; 208 209 /* NOTE: assumes write protect signal is active-high */ 210 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 211 } 212 213 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 214 { 215 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 216 struct omap_mmc_platform_data *mmc = host->pdata; 217 218 /* NOTE: assumes card detect signal is active-low */ 219 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 220 } 221 222 #ifdef CONFIG_PM 223 224 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 225 { 226 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 227 struct omap_mmc_platform_data *mmc = host->pdata; 228 229 disable_irq(mmc->slots[0].card_detect_irq); 230 return 0; 231 } 232 233 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 234 { 235 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236 struct omap_mmc_platform_data *mmc = host->pdata; 237 238 enable_irq(mmc->slots[0].card_detect_irq); 239 return 0; 240 } 241 242 #else 243 244 #define omap_hsmmc_suspend_cdirq NULL 245 #define omap_hsmmc_resume_cdirq NULL 246 247 #endif 248 249 #ifdef CONFIG_REGULATOR 250 251 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 252 int vdd) 253 { 254 struct omap_hsmmc_host *host = 255 platform_get_drvdata(to_platform_device(dev)); 256 int ret = 0; 257 258 /* 259 * If we don't see a Vcc regulator, assume it's a fixed 260 * voltage always-on regulator. 261 */ 262 if (!host->vcc) 263 return 0; 264 /* 265 * With DT, never turn OFF the regulator for MMC1. This is because 266 * the pbias cell programming support is still missing when 267 * booting with Device tree 268 */ 269 if (host->pbias_disable && !vdd) 270 return 0; 271 272 if (mmc_slot(host).before_set_reg) 273 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 274 275 /* 276 * Assume Vcc regulator is used only to power the card ... OMAP 277 * VDDS is used to power the pins, optionally with a transceiver to 278 * support cards using voltages other than VDDS (1.8V nominal). When a 279 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 280 * 281 * In some cases this regulator won't support enable/disable; 282 * e.g. it's a fixed rail for a WLAN chip. 283 * 284 * In other cases vcc_aux switches interface power. Example, for 285 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 286 * chips/cards need an interface voltage rail too. 287 */ 288 if (power_on) { 289 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 290 /* Enable interface voltage rail, if needed */ 291 if (ret == 0 && host->vcc_aux) { 292 ret = regulator_enable(host->vcc_aux); 293 if (ret < 0) 294 ret = mmc_regulator_set_ocr(host->mmc, 295 host->vcc, 0); 296 } 297 } else { 298 /* Shut down the rail */ 299 if (host->vcc_aux) 300 ret = regulator_disable(host->vcc_aux); 301 if (!ret) { 302 /* Then proceed to shut down the local regulator */ 303 ret = mmc_regulator_set_ocr(host->mmc, 304 host->vcc, 0); 305 } 306 } 307 308 if (mmc_slot(host).after_set_reg) 309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 310 311 return ret; 312 } 313 314 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 315 { 316 struct regulator *reg; 317 int ocr_value = 0; 318 319 reg = regulator_get(host->dev, "vmmc"); 320 if (IS_ERR(reg)) { 321 dev_err(host->dev, "vmmc regulator missing\n"); 322 return PTR_ERR(reg); 323 } else { 324 mmc_slot(host).set_power = omap_hsmmc_set_power; 325 host->vcc = reg; 326 ocr_value = mmc_regulator_get_ocrmask(reg); 327 if (!mmc_slot(host).ocr_mask) { 328 mmc_slot(host).ocr_mask = ocr_value; 329 } else { 330 if (!(mmc_slot(host).ocr_mask & ocr_value)) { 331 dev_err(host->dev, "ocrmask %x is not supported\n", 332 mmc_slot(host).ocr_mask); 333 mmc_slot(host).ocr_mask = 0; 334 return -EINVAL; 335 } 336 } 337 338 /* Allow an aux regulator */ 339 reg = regulator_get(host->dev, "vmmc_aux"); 340 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 341 342 /* For eMMC do not power off when not in sleep state */ 343 if (mmc_slot(host).no_regulator_off_init) 344 return 0; 345 /* 346 * UGLY HACK: workaround regulator framework bugs. 347 * When the bootloader leaves a supply active, it's 348 * initialized with zero usecount ... and we can't 349 * disable it without first enabling it. Until the 350 * framework is fixed, we need a workaround like this 351 * (which is safe for MMC, but not in general). 352 */ 353 if (regulator_is_enabled(host->vcc) > 0 || 354 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 355 int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 356 357 mmc_slot(host).set_power(host->dev, host->slot_id, 358 1, vdd); 359 mmc_slot(host).set_power(host->dev, host->slot_id, 360 0, 0); 361 } 362 } 363 364 return 0; 365 } 366 367 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 368 { 369 regulator_put(host->vcc); 370 regulator_put(host->vcc_aux); 371 mmc_slot(host).set_power = NULL; 372 } 373 374 static inline int omap_hsmmc_have_reg(void) 375 { 376 return 1; 377 } 378 379 #else 380 381 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 382 { 383 return -EINVAL; 384 } 385 386 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 387 { 388 } 389 390 static inline int omap_hsmmc_have_reg(void) 391 { 392 return 0; 393 } 394 395 #endif 396 397 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 398 { 399 int ret; 400 401 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 402 if (pdata->slots[0].cover) 403 pdata->slots[0].get_cover_state = 404 omap_hsmmc_get_cover_state; 405 else 406 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 407 pdata->slots[0].card_detect_irq = 408 gpio_to_irq(pdata->slots[0].switch_pin); 409 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 410 if (ret) 411 return ret; 412 ret = gpio_direction_input(pdata->slots[0].switch_pin); 413 if (ret) 414 goto err_free_sp; 415 } else 416 pdata->slots[0].switch_pin = -EINVAL; 417 418 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 419 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 420 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 421 if (ret) 422 goto err_free_cd; 423 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 424 if (ret) 425 goto err_free_wp; 426 } else 427 pdata->slots[0].gpio_wp = -EINVAL; 428 429 return 0; 430 431 err_free_wp: 432 gpio_free(pdata->slots[0].gpio_wp); 433 err_free_cd: 434 if (gpio_is_valid(pdata->slots[0].switch_pin)) 435 err_free_sp: 436 gpio_free(pdata->slots[0].switch_pin); 437 return ret; 438 } 439 440 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 441 { 442 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 443 gpio_free(pdata->slots[0].gpio_wp); 444 if (gpio_is_valid(pdata->slots[0].switch_pin)) 445 gpio_free(pdata->slots[0].switch_pin); 446 } 447 448 /* 449 * Start clock to the card 450 */ 451 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 452 { 453 OMAP_HSMMC_WRITE(host->base, SYSCTL, 454 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 455 } 456 457 /* 458 * Stop clock to the card 459 */ 460 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 461 { 462 OMAP_HSMMC_WRITE(host->base, SYSCTL, 463 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 464 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 465 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 466 } 467 468 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 469 struct mmc_command *cmd) 470 { 471 unsigned int irq_mask; 472 473 if (host->use_dma) 474 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 475 else 476 irq_mask = INT_EN_MASK; 477 478 /* Disable timeout for erases */ 479 if (cmd->opcode == MMC_ERASE) 480 irq_mask &= ~DTO_EN; 481 482 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 483 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 484 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 485 } 486 487 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 488 { 489 OMAP_HSMMC_WRITE(host->base, ISE, 0); 490 OMAP_HSMMC_WRITE(host->base, IE, 0); 491 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 492 } 493 494 /* Calculate divisor for the given clock frequency */ 495 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 496 { 497 u16 dsor = 0; 498 499 if (ios->clock) { 500 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 501 if (dsor > CLKD_MAX) 502 dsor = CLKD_MAX; 503 } 504 505 return dsor; 506 } 507 508 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 509 { 510 struct mmc_ios *ios = &host->mmc->ios; 511 unsigned long regval; 512 unsigned long timeout; 513 unsigned long clkdiv; 514 515 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 516 517 omap_hsmmc_stop_clock(host); 518 519 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 520 regval = regval & ~(CLKD_MASK | DTO_MASK); 521 clkdiv = calc_divisor(host, ios); 522 regval = regval | (clkdiv << 6) | (DTO << 16); 523 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 524 OMAP_HSMMC_WRITE(host->base, SYSCTL, 525 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 526 527 /* Wait till the ICS bit is set */ 528 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 529 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 530 && time_before(jiffies, timeout)) 531 cpu_relax(); 532 533 /* 534 * Enable High-Speed Support 535 * Pre-Requisites 536 * - Controller should support High-Speed-Enable Bit 537 * - Controller should not be using DDR Mode 538 * - Controller should advertise that it supports High Speed 539 * in capabilities register 540 * - MMC/SD clock coming out of controller > 25MHz 541 */ 542 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 543 (ios->timing != MMC_TIMING_UHS_DDR50) && 544 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 545 regval = OMAP_HSMMC_READ(host->base, HCTL); 546 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 547 regval |= HSPE; 548 else 549 regval &= ~HSPE; 550 551 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 552 } 553 554 omap_hsmmc_start_clock(host); 555 } 556 557 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 558 { 559 struct mmc_ios *ios = &host->mmc->ios; 560 u32 con; 561 562 con = OMAP_HSMMC_READ(host->base, CON); 563 if (ios->timing == MMC_TIMING_UHS_DDR50) 564 con |= DDR; /* configure in DDR mode */ 565 else 566 con &= ~DDR; 567 switch (ios->bus_width) { 568 case MMC_BUS_WIDTH_8: 569 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 570 break; 571 case MMC_BUS_WIDTH_4: 572 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 573 OMAP_HSMMC_WRITE(host->base, HCTL, 574 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 575 break; 576 case MMC_BUS_WIDTH_1: 577 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 578 OMAP_HSMMC_WRITE(host->base, HCTL, 579 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 580 break; 581 } 582 } 583 584 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 585 { 586 struct mmc_ios *ios = &host->mmc->ios; 587 u32 con; 588 589 con = OMAP_HSMMC_READ(host->base, CON); 590 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 591 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 592 else 593 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 594 } 595 596 #ifdef CONFIG_PM 597 598 /* 599 * Restore the MMC host context, if it was lost as result of a 600 * power state change. 601 */ 602 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 603 { 604 struct mmc_ios *ios = &host->mmc->ios; 605 u32 hctl, capa; 606 unsigned long timeout; 607 608 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 609 return 1; 610 611 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 612 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 613 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 614 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 615 return 0; 616 617 host->context_loss++; 618 619 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 620 if (host->power_mode != MMC_POWER_OFF && 621 (1 << ios->vdd) <= MMC_VDD_23_24) 622 hctl = SDVS18; 623 else 624 hctl = SDVS30; 625 capa = VS30 | VS18; 626 } else { 627 hctl = SDVS18; 628 capa = VS18; 629 } 630 631 OMAP_HSMMC_WRITE(host->base, HCTL, 632 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 633 634 OMAP_HSMMC_WRITE(host->base, CAPA, 635 OMAP_HSMMC_READ(host->base, CAPA) | capa); 636 637 OMAP_HSMMC_WRITE(host->base, HCTL, 638 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 639 640 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 641 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 642 && time_before(jiffies, timeout)) 643 ; 644 645 omap_hsmmc_disable_irq(host); 646 647 /* Do not initialize card-specific things if the power is off */ 648 if (host->power_mode == MMC_POWER_OFF) 649 goto out; 650 651 omap_hsmmc_set_bus_width(host); 652 653 omap_hsmmc_set_clock(host); 654 655 omap_hsmmc_set_bus_mode(host); 656 657 out: 658 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 659 host->context_loss); 660 return 0; 661 } 662 663 /* 664 * Save the MMC host context (store the number of power state changes so far). 665 */ 666 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 667 { 668 host->con = OMAP_HSMMC_READ(host->base, CON); 669 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 670 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 671 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 672 } 673 674 #else 675 676 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 677 { 678 return 0; 679 } 680 681 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 682 { 683 } 684 685 #endif 686 687 /* 688 * Send init stream sequence to card 689 * before sending IDLE command 690 */ 691 static void send_init_stream(struct omap_hsmmc_host *host) 692 { 693 int reg = 0; 694 unsigned long timeout; 695 696 if (host->protect_card) 697 return; 698 699 disable_irq(host->irq); 700 701 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 702 OMAP_HSMMC_WRITE(host->base, CON, 703 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 704 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 705 706 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 707 while ((reg != CC_EN) && time_before(jiffies, timeout)) 708 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 709 710 OMAP_HSMMC_WRITE(host->base, CON, 711 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 712 713 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 714 OMAP_HSMMC_READ(host->base, STAT); 715 716 enable_irq(host->irq); 717 } 718 719 static inline 720 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 721 { 722 int r = 1; 723 724 if (mmc_slot(host).get_cover_state) 725 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 726 return r; 727 } 728 729 static ssize_t 730 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 731 char *buf) 732 { 733 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 734 struct omap_hsmmc_host *host = mmc_priv(mmc); 735 736 return sprintf(buf, "%s\n", 737 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 738 } 739 740 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 741 742 static ssize_t 743 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 744 char *buf) 745 { 746 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 747 struct omap_hsmmc_host *host = mmc_priv(mmc); 748 749 return sprintf(buf, "%s\n", mmc_slot(host).name); 750 } 751 752 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 753 754 /* 755 * Configure the response type and send the cmd. 756 */ 757 static void 758 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 759 struct mmc_data *data) 760 { 761 int cmdreg = 0, resptype = 0, cmdtype = 0; 762 763 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 764 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 765 host->cmd = cmd; 766 767 omap_hsmmc_enable_irq(host, cmd); 768 769 host->response_busy = 0; 770 if (cmd->flags & MMC_RSP_PRESENT) { 771 if (cmd->flags & MMC_RSP_136) 772 resptype = 1; 773 else if (cmd->flags & MMC_RSP_BUSY) { 774 resptype = 3; 775 host->response_busy = 1; 776 } else 777 resptype = 2; 778 } 779 780 /* 781 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 782 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 783 * a val of 0x3, rest 0x0. 784 */ 785 if (cmd == host->mrq->stop) 786 cmdtype = 0x3; 787 788 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 789 790 if (data) { 791 cmdreg |= DP_SELECT | MSBS | BCE; 792 if (data->flags & MMC_DATA_READ) 793 cmdreg |= DDIR; 794 else 795 cmdreg &= ~(DDIR); 796 } 797 798 if (host->use_dma) 799 cmdreg |= DMAE; 800 801 host->req_in_progress = 1; 802 803 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 804 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 805 } 806 807 static int 808 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 809 { 810 if (data->flags & MMC_DATA_WRITE) 811 return DMA_TO_DEVICE; 812 else 813 return DMA_FROM_DEVICE; 814 } 815 816 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 817 struct mmc_data *data) 818 { 819 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 820 } 821 822 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 823 { 824 int dma_ch; 825 unsigned long flags; 826 827 spin_lock_irqsave(&host->irq_lock, flags); 828 host->req_in_progress = 0; 829 dma_ch = host->dma_ch; 830 spin_unlock_irqrestore(&host->irq_lock, flags); 831 832 omap_hsmmc_disable_irq(host); 833 /* Do not complete the request if DMA is still in progress */ 834 if (mrq->data && host->use_dma && dma_ch != -1) 835 return; 836 host->mrq = NULL; 837 mmc_request_done(host->mmc, mrq); 838 } 839 840 /* 841 * Notify the transfer complete to MMC core 842 */ 843 static void 844 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 845 { 846 if (!data) { 847 struct mmc_request *mrq = host->mrq; 848 849 /* TC before CC from CMD6 - don't know why, but it happens */ 850 if (host->cmd && host->cmd->opcode == 6 && 851 host->response_busy) { 852 host->response_busy = 0; 853 return; 854 } 855 856 omap_hsmmc_request_done(host, mrq); 857 return; 858 } 859 860 host->data = NULL; 861 862 if (!data->error) 863 data->bytes_xfered += data->blocks * (data->blksz); 864 else 865 data->bytes_xfered = 0; 866 867 if (!data->stop) { 868 omap_hsmmc_request_done(host, data->mrq); 869 return; 870 } 871 omap_hsmmc_start_command(host, data->stop, NULL); 872 } 873 874 /* 875 * Notify the core about command completion 876 */ 877 static void 878 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 879 { 880 host->cmd = NULL; 881 882 if (cmd->flags & MMC_RSP_PRESENT) { 883 if (cmd->flags & MMC_RSP_136) { 884 /* response type 2 */ 885 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 886 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 887 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 888 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 889 } else { 890 /* response types 1, 1b, 3, 4, 5, 6 */ 891 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 892 } 893 } 894 if ((host->data == NULL && !host->response_busy) || cmd->error) 895 omap_hsmmc_request_done(host, cmd->mrq); 896 } 897 898 /* 899 * DMA clean up for command errors 900 */ 901 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 902 { 903 int dma_ch; 904 unsigned long flags; 905 906 host->data->error = errno; 907 908 spin_lock_irqsave(&host->irq_lock, flags); 909 dma_ch = host->dma_ch; 910 host->dma_ch = -1; 911 spin_unlock_irqrestore(&host->irq_lock, flags); 912 913 if (host->use_dma && dma_ch != -1) { 914 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 915 916 dmaengine_terminate_all(chan); 917 dma_unmap_sg(chan->device->dev, 918 host->data->sg, host->data->sg_len, 919 omap_hsmmc_get_dma_dir(host, host->data)); 920 921 host->data->host_cookie = 0; 922 } 923 host->data = NULL; 924 } 925 926 /* 927 * Readable error output 928 */ 929 #ifdef CONFIG_MMC_DEBUG 930 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 931 { 932 /* --- means reserved bit without definition at documentation */ 933 static const char *omap_hsmmc_status_bits[] = { 934 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 935 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 936 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 937 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 938 }; 939 char res[256]; 940 char *buf = res; 941 int len, i; 942 943 len = sprintf(buf, "MMC IRQ 0x%x :", status); 944 buf += len; 945 946 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 947 if (status & (1 << i)) { 948 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 949 buf += len; 950 } 951 952 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 953 } 954 #else 955 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 956 u32 status) 957 { 958 } 959 #endif /* CONFIG_MMC_DEBUG */ 960 961 /* 962 * MMC controller internal state machines reset 963 * 964 * Used to reset command or data internal state machines, using respectively 965 * SRC or SRD bit of SYSCTL register 966 * Can be called from interrupt context 967 */ 968 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 969 unsigned long bit) 970 { 971 unsigned long i = 0; 972 unsigned long limit = MMC_TIMEOUT_US; 973 974 OMAP_HSMMC_WRITE(host->base, SYSCTL, 975 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 976 977 /* 978 * OMAP4 ES2 and greater has an updated reset logic. 979 * Monitor a 0->1 transition first 980 */ 981 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 982 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 983 && (i++ < limit)) 984 udelay(1); 985 } 986 i = 0; 987 988 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 989 (i++ < limit)) 990 udelay(1); 991 992 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 993 dev_err(mmc_dev(host->mmc), 994 "Timeout waiting on controller reset in %s\n", 995 __func__); 996 } 997 998 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 999 int err, int end_cmd) 1000 { 1001 if (end_cmd) { 1002 omap_hsmmc_reset_controller_fsm(host, SRC); 1003 if (host->cmd) 1004 host->cmd->error = err; 1005 } 1006 1007 if (host->data) { 1008 omap_hsmmc_reset_controller_fsm(host, SRD); 1009 omap_hsmmc_dma_cleanup(host, err); 1010 } else if (host->mrq && host->mrq->cmd) 1011 host->mrq->cmd->error = err; 1012 } 1013 1014 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1015 { 1016 struct mmc_data *data; 1017 int end_cmd = 0, end_trans = 0; 1018 1019 data = host->data; 1020 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1021 1022 if (status & ERR_EN) { 1023 omap_hsmmc_dbg_report_irq(host, status); 1024 1025 if (status & (CTO_EN | CCRC_EN)) 1026 end_cmd = 1; 1027 if (status & (CTO_EN | DTO_EN)) 1028 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1029 else if (status & (CCRC_EN | DCRC_EN)) 1030 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1031 1032 if (host->data || host->response_busy) { 1033 end_trans = !end_cmd; 1034 host->response_busy = 0; 1035 } 1036 } 1037 1038 OMAP_HSMMC_WRITE(host->base, STAT, status); 1039 if (end_cmd || ((status & CC_EN) && host->cmd)) 1040 omap_hsmmc_cmd_done(host, host->cmd); 1041 if ((end_trans || (status & TC_EN)) && host->mrq) 1042 omap_hsmmc_xfer_done(host, data); 1043 } 1044 1045 /* 1046 * MMC controller IRQ handler 1047 */ 1048 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1049 { 1050 struct omap_hsmmc_host *host = dev_id; 1051 int status; 1052 1053 status = OMAP_HSMMC_READ(host->base, STAT); 1054 while (status & INT_EN_MASK && host->req_in_progress) { 1055 omap_hsmmc_do_irq(host, status); 1056 1057 /* Flush posted write */ 1058 status = OMAP_HSMMC_READ(host->base, STAT); 1059 } 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1065 { 1066 unsigned long i; 1067 1068 OMAP_HSMMC_WRITE(host->base, HCTL, 1069 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1070 for (i = 0; i < loops_per_jiffy; i++) { 1071 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1072 break; 1073 cpu_relax(); 1074 } 1075 } 1076 1077 /* 1078 * Switch MMC interface voltage ... only relevant for MMC1. 1079 * 1080 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1081 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1082 * Some chips, like eMMC ones, use internal transceivers. 1083 */ 1084 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1085 { 1086 u32 reg_val = 0; 1087 int ret; 1088 1089 /* Disable the clocks */ 1090 pm_runtime_put_sync(host->dev); 1091 if (host->dbclk) 1092 clk_disable_unprepare(host->dbclk); 1093 1094 /* Turn the power off */ 1095 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1096 1097 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1098 if (!ret) 1099 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1100 vdd); 1101 pm_runtime_get_sync(host->dev); 1102 if (host->dbclk) 1103 clk_prepare_enable(host->dbclk); 1104 1105 if (ret != 0) 1106 goto err; 1107 1108 OMAP_HSMMC_WRITE(host->base, HCTL, 1109 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1110 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1111 1112 /* 1113 * If a MMC dual voltage card is detected, the set_ios fn calls 1114 * this fn with VDD bit set for 1.8V. Upon card removal from the 1115 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1116 * 1117 * Cope with a bit of slop in the range ... per data sheets: 1118 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1119 * but recommended values are 1.71V to 1.89V 1120 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1121 * but recommended values are 2.7V to 3.3V 1122 * 1123 * Board setup code shouldn't permit anything very out-of-range. 1124 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1125 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1126 */ 1127 if ((1 << vdd) <= MMC_VDD_23_24) 1128 reg_val |= SDVS18; 1129 else 1130 reg_val |= SDVS30; 1131 1132 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1133 set_sd_bus_power(host); 1134 1135 return 0; 1136 err: 1137 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1138 return ret; 1139 } 1140 1141 /* Protect the card while the cover is open */ 1142 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1143 { 1144 if (!mmc_slot(host).get_cover_state) 1145 return; 1146 1147 host->reqs_blocked = 0; 1148 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1149 if (host->protect_card) { 1150 dev_info(host->dev, "%s: cover is closed, " 1151 "card is now accessible\n", 1152 mmc_hostname(host->mmc)); 1153 host->protect_card = 0; 1154 } 1155 } else { 1156 if (!host->protect_card) { 1157 dev_info(host->dev, "%s: cover is open, " 1158 "card is now inaccessible\n", 1159 mmc_hostname(host->mmc)); 1160 host->protect_card = 1; 1161 } 1162 } 1163 } 1164 1165 /* 1166 * irq handler to notify the core about card insertion/removal 1167 */ 1168 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1169 { 1170 struct omap_hsmmc_host *host = dev_id; 1171 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1172 int carddetect; 1173 1174 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1175 1176 if (slot->card_detect) 1177 carddetect = slot->card_detect(host->dev, host->slot_id); 1178 else { 1179 omap_hsmmc_protect_card(host); 1180 carddetect = -ENOSYS; 1181 } 1182 1183 if (carddetect) 1184 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1185 else 1186 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1187 return IRQ_HANDLED; 1188 } 1189 1190 static void omap_hsmmc_dma_callback(void *param) 1191 { 1192 struct omap_hsmmc_host *host = param; 1193 struct dma_chan *chan; 1194 struct mmc_data *data; 1195 int req_in_progress; 1196 1197 spin_lock_irq(&host->irq_lock); 1198 if (host->dma_ch < 0) { 1199 spin_unlock_irq(&host->irq_lock); 1200 return; 1201 } 1202 1203 data = host->mrq->data; 1204 chan = omap_hsmmc_get_dma_chan(host, data); 1205 if (!data->host_cookie) 1206 dma_unmap_sg(chan->device->dev, 1207 data->sg, data->sg_len, 1208 omap_hsmmc_get_dma_dir(host, data)); 1209 1210 req_in_progress = host->req_in_progress; 1211 host->dma_ch = -1; 1212 spin_unlock_irq(&host->irq_lock); 1213 1214 /* If DMA has finished after TC, complete the request */ 1215 if (!req_in_progress) { 1216 struct mmc_request *mrq = host->mrq; 1217 1218 host->mrq = NULL; 1219 mmc_request_done(host->mmc, mrq); 1220 } 1221 } 1222 1223 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1224 struct mmc_data *data, 1225 struct omap_hsmmc_next *next, 1226 struct dma_chan *chan) 1227 { 1228 int dma_len; 1229 1230 if (!next && data->host_cookie && 1231 data->host_cookie != host->next_data.cookie) { 1232 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1233 " host->next_data.cookie %d\n", 1234 __func__, data->host_cookie, host->next_data.cookie); 1235 data->host_cookie = 0; 1236 } 1237 1238 /* Check if next job is already prepared */ 1239 if (next || 1240 (!next && data->host_cookie != host->next_data.cookie)) { 1241 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1242 omap_hsmmc_get_dma_dir(host, data)); 1243 1244 } else { 1245 dma_len = host->next_data.dma_len; 1246 host->next_data.dma_len = 0; 1247 } 1248 1249 1250 if (dma_len == 0) 1251 return -EINVAL; 1252 1253 if (next) { 1254 next->dma_len = dma_len; 1255 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1256 } else 1257 host->dma_len = dma_len; 1258 1259 return 0; 1260 } 1261 1262 /* 1263 * Routine to configure and start DMA for the MMC card 1264 */ 1265 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1266 struct mmc_request *req) 1267 { 1268 struct dma_slave_config cfg; 1269 struct dma_async_tx_descriptor *tx; 1270 int ret = 0, i; 1271 struct mmc_data *data = req->data; 1272 struct dma_chan *chan; 1273 1274 /* Sanity check: all the SG entries must be aligned by block size. */ 1275 for (i = 0; i < data->sg_len; i++) { 1276 struct scatterlist *sgl; 1277 1278 sgl = data->sg + i; 1279 if (sgl->length % data->blksz) 1280 return -EINVAL; 1281 } 1282 if ((data->blksz % 4) != 0) 1283 /* REVISIT: The MMC buffer increments only when MSB is written. 1284 * Return error for blksz which is non multiple of four. 1285 */ 1286 return -EINVAL; 1287 1288 BUG_ON(host->dma_ch != -1); 1289 1290 chan = omap_hsmmc_get_dma_chan(host, data); 1291 1292 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1293 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1294 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1295 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1296 cfg.src_maxburst = data->blksz / 4; 1297 cfg.dst_maxburst = data->blksz / 4; 1298 1299 ret = dmaengine_slave_config(chan, &cfg); 1300 if (ret) 1301 return ret; 1302 1303 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1304 if (ret) 1305 return ret; 1306 1307 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1308 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1309 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1310 if (!tx) { 1311 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1312 /* FIXME: cleanup */ 1313 return -1; 1314 } 1315 1316 tx->callback = omap_hsmmc_dma_callback; 1317 tx->callback_param = host; 1318 1319 /* Does not fail */ 1320 dmaengine_submit(tx); 1321 1322 host->dma_ch = 1; 1323 1324 dma_async_issue_pending(chan); 1325 1326 return 0; 1327 } 1328 1329 static void set_data_timeout(struct omap_hsmmc_host *host, 1330 unsigned int timeout_ns, 1331 unsigned int timeout_clks) 1332 { 1333 unsigned int timeout, cycle_ns; 1334 uint32_t reg, clkd, dto = 0; 1335 1336 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1337 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1338 if (clkd == 0) 1339 clkd = 1; 1340 1341 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1342 timeout = timeout_ns / cycle_ns; 1343 timeout += timeout_clks; 1344 if (timeout) { 1345 while ((timeout & 0x80000000) == 0) { 1346 dto += 1; 1347 timeout <<= 1; 1348 } 1349 dto = 31 - dto; 1350 timeout <<= 1; 1351 if (timeout && dto) 1352 dto += 1; 1353 if (dto >= 13) 1354 dto -= 13; 1355 else 1356 dto = 0; 1357 if (dto > 14) 1358 dto = 14; 1359 } 1360 1361 reg &= ~DTO_MASK; 1362 reg |= dto << DTO_SHIFT; 1363 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1364 } 1365 1366 /* 1367 * Configure block length for MMC/SD cards and initiate the transfer. 1368 */ 1369 static int 1370 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1371 { 1372 int ret; 1373 host->data = req->data; 1374 1375 if (req->data == NULL) { 1376 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1377 /* 1378 * Set an arbitrary 100ms data timeout for commands with 1379 * busy signal. 1380 */ 1381 if (req->cmd->flags & MMC_RSP_BUSY) 1382 set_data_timeout(host, 100000000U, 0); 1383 return 0; 1384 } 1385 1386 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1387 | (req->data->blocks << 16)); 1388 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1389 1390 if (host->use_dma) { 1391 ret = omap_hsmmc_start_dma_transfer(host, req); 1392 if (ret != 0) { 1393 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1394 return ret; 1395 } 1396 } 1397 return 0; 1398 } 1399 1400 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1401 int err) 1402 { 1403 struct omap_hsmmc_host *host = mmc_priv(mmc); 1404 struct mmc_data *data = mrq->data; 1405 1406 if (host->use_dma && data->host_cookie) { 1407 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1408 1409 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1410 omap_hsmmc_get_dma_dir(host, data)); 1411 data->host_cookie = 0; 1412 } 1413 } 1414 1415 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1416 bool is_first_req) 1417 { 1418 struct omap_hsmmc_host *host = mmc_priv(mmc); 1419 1420 if (mrq->data->host_cookie) { 1421 mrq->data->host_cookie = 0; 1422 return ; 1423 } 1424 1425 if (host->use_dma) { 1426 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1427 1428 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1429 &host->next_data, c)) 1430 mrq->data->host_cookie = 0; 1431 } 1432 } 1433 1434 /* 1435 * Request function. for read/write operation 1436 */ 1437 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1438 { 1439 struct omap_hsmmc_host *host = mmc_priv(mmc); 1440 int err; 1441 1442 BUG_ON(host->req_in_progress); 1443 BUG_ON(host->dma_ch != -1); 1444 if (host->protect_card) { 1445 if (host->reqs_blocked < 3) { 1446 /* 1447 * Ensure the controller is left in a consistent 1448 * state by resetting the command and data state 1449 * machines. 1450 */ 1451 omap_hsmmc_reset_controller_fsm(host, SRD); 1452 omap_hsmmc_reset_controller_fsm(host, SRC); 1453 host->reqs_blocked += 1; 1454 } 1455 req->cmd->error = -EBADF; 1456 if (req->data) 1457 req->data->error = -EBADF; 1458 req->cmd->retries = 0; 1459 mmc_request_done(mmc, req); 1460 return; 1461 } else if (host->reqs_blocked) 1462 host->reqs_blocked = 0; 1463 WARN_ON(host->mrq != NULL); 1464 host->mrq = req; 1465 err = omap_hsmmc_prepare_data(host, req); 1466 if (err) { 1467 req->cmd->error = err; 1468 if (req->data) 1469 req->data->error = err; 1470 host->mrq = NULL; 1471 mmc_request_done(mmc, req); 1472 return; 1473 } 1474 1475 omap_hsmmc_start_command(host, req->cmd, req->data); 1476 } 1477 1478 /* Routine to configure clock values. Exposed API to core */ 1479 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1480 { 1481 struct omap_hsmmc_host *host = mmc_priv(mmc); 1482 int do_send_init_stream = 0; 1483 1484 pm_runtime_get_sync(host->dev); 1485 1486 if (ios->power_mode != host->power_mode) { 1487 switch (ios->power_mode) { 1488 case MMC_POWER_OFF: 1489 mmc_slot(host).set_power(host->dev, host->slot_id, 1490 0, 0); 1491 break; 1492 case MMC_POWER_UP: 1493 mmc_slot(host).set_power(host->dev, host->slot_id, 1494 1, ios->vdd); 1495 break; 1496 case MMC_POWER_ON: 1497 do_send_init_stream = 1; 1498 break; 1499 } 1500 host->power_mode = ios->power_mode; 1501 } 1502 1503 /* FIXME: set registers based only on changes to ios */ 1504 1505 omap_hsmmc_set_bus_width(host); 1506 1507 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1508 /* Only MMC1 can interface at 3V without some flavor 1509 * of external transceiver; but they all handle 1.8V. 1510 */ 1511 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1512 (ios->vdd == DUAL_VOLT_OCR_BIT) && 1513 /* 1514 * With pbias cell programming missing, this 1515 * can't be allowed on MMC1 when booting with device 1516 * tree. 1517 */ 1518 !host->pbias_disable) { 1519 /* 1520 * The mmc_select_voltage fn of the core does 1521 * not seem to set the power_mode to 1522 * MMC_POWER_UP upon recalculating the voltage. 1523 * vdd 1.8v. 1524 */ 1525 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1526 dev_dbg(mmc_dev(host->mmc), 1527 "Switch operation failed\n"); 1528 } 1529 } 1530 1531 omap_hsmmc_set_clock(host); 1532 1533 if (do_send_init_stream) 1534 send_init_stream(host); 1535 1536 omap_hsmmc_set_bus_mode(host); 1537 1538 pm_runtime_put_autosuspend(host->dev); 1539 } 1540 1541 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1542 { 1543 struct omap_hsmmc_host *host = mmc_priv(mmc); 1544 1545 if (!mmc_slot(host).card_detect) 1546 return -ENOSYS; 1547 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1548 } 1549 1550 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1551 { 1552 struct omap_hsmmc_host *host = mmc_priv(mmc); 1553 1554 if (!mmc_slot(host).get_ro) 1555 return -ENOSYS; 1556 return mmc_slot(host).get_ro(host->dev, 0); 1557 } 1558 1559 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1560 { 1561 struct omap_hsmmc_host *host = mmc_priv(mmc); 1562 1563 if (mmc_slot(host).init_card) 1564 mmc_slot(host).init_card(card); 1565 } 1566 1567 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1568 { 1569 u32 hctl, capa, value; 1570 1571 /* Only MMC1 supports 3.0V */ 1572 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1573 hctl = SDVS30; 1574 capa = VS30 | VS18; 1575 } else { 1576 hctl = SDVS18; 1577 capa = VS18; 1578 } 1579 1580 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1581 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1582 1583 value = OMAP_HSMMC_READ(host->base, CAPA); 1584 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1585 1586 /* Set SD bus power bit */ 1587 set_sd_bus_power(host); 1588 } 1589 1590 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1591 { 1592 struct omap_hsmmc_host *host = mmc_priv(mmc); 1593 1594 pm_runtime_get_sync(host->dev); 1595 1596 return 0; 1597 } 1598 1599 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1600 { 1601 struct omap_hsmmc_host *host = mmc_priv(mmc); 1602 1603 pm_runtime_mark_last_busy(host->dev); 1604 pm_runtime_put_autosuspend(host->dev); 1605 1606 return 0; 1607 } 1608 1609 static const struct mmc_host_ops omap_hsmmc_ops = { 1610 .enable = omap_hsmmc_enable_fclk, 1611 .disable = omap_hsmmc_disable_fclk, 1612 .post_req = omap_hsmmc_post_req, 1613 .pre_req = omap_hsmmc_pre_req, 1614 .request = omap_hsmmc_request, 1615 .set_ios = omap_hsmmc_set_ios, 1616 .get_cd = omap_hsmmc_get_cd, 1617 .get_ro = omap_hsmmc_get_ro, 1618 .init_card = omap_hsmmc_init_card, 1619 /* NYET -- enable_sdio_irq */ 1620 }; 1621 1622 #ifdef CONFIG_DEBUG_FS 1623 1624 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1625 { 1626 struct mmc_host *mmc = s->private; 1627 struct omap_hsmmc_host *host = mmc_priv(mmc); 1628 1629 seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 1630 mmc->index, host->context_loss); 1631 1632 pm_runtime_get_sync(host->dev); 1633 1634 seq_printf(s, "CON:\t\t0x%08x\n", 1635 OMAP_HSMMC_READ(host->base, CON)); 1636 seq_printf(s, "HCTL:\t\t0x%08x\n", 1637 OMAP_HSMMC_READ(host->base, HCTL)); 1638 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1639 OMAP_HSMMC_READ(host->base, SYSCTL)); 1640 seq_printf(s, "IE:\t\t0x%08x\n", 1641 OMAP_HSMMC_READ(host->base, IE)); 1642 seq_printf(s, "ISE:\t\t0x%08x\n", 1643 OMAP_HSMMC_READ(host->base, ISE)); 1644 seq_printf(s, "CAPA:\t\t0x%08x\n", 1645 OMAP_HSMMC_READ(host->base, CAPA)); 1646 1647 pm_runtime_mark_last_busy(host->dev); 1648 pm_runtime_put_autosuspend(host->dev); 1649 1650 return 0; 1651 } 1652 1653 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1654 { 1655 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1656 } 1657 1658 static const struct file_operations mmc_regs_fops = { 1659 .open = omap_hsmmc_regs_open, 1660 .read = seq_read, 1661 .llseek = seq_lseek, 1662 .release = single_release, 1663 }; 1664 1665 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1666 { 1667 if (mmc->debugfs_root) 1668 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1669 mmc, &mmc_regs_fops); 1670 } 1671 1672 #else 1673 1674 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1675 { 1676 } 1677 1678 #endif 1679 1680 #ifdef CONFIG_OF 1681 static u16 omap4_reg_offset = 0x100; 1682 1683 static const struct of_device_id omap_mmc_of_match[] = { 1684 { 1685 .compatible = "ti,omap2-hsmmc", 1686 }, 1687 { 1688 .compatible = "ti,omap3-hsmmc", 1689 }, 1690 { 1691 .compatible = "ti,omap4-hsmmc", 1692 .data = &omap4_reg_offset, 1693 }, 1694 {}, 1695 }; 1696 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1697 1698 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1699 { 1700 struct omap_mmc_platform_data *pdata; 1701 struct device_node *np = dev->of_node; 1702 u32 bus_width, max_freq; 1703 int cd_gpio, wp_gpio; 1704 1705 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1706 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1707 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1708 return ERR_PTR(-EPROBE_DEFER); 1709 1710 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1711 if (!pdata) 1712 return NULL; /* out of memory */ 1713 1714 if (of_find_property(np, "ti,dual-volt", NULL)) 1715 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1716 1717 /* This driver only supports 1 slot */ 1718 pdata->nr_slots = 1; 1719 pdata->slots[0].switch_pin = cd_gpio; 1720 pdata->slots[0].gpio_wp = wp_gpio; 1721 1722 if (of_find_property(np, "ti,non-removable", NULL)) { 1723 pdata->slots[0].nonremovable = true; 1724 pdata->slots[0].no_regulator_off_init = true; 1725 } 1726 of_property_read_u32(np, "bus-width", &bus_width); 1727 if (bus_width == 4) 1728 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 1729 else if (bus_width == 8) 1730 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 1731 1732 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1733 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 1734 1735 if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1736 pdata->max_freq = max_freq; 1737 1738 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1739 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1740 1741 return pdata; 1742 } 1743 #else 1744 static inline struct omap_mmc_platform_data 1745 *of_get_hsmmc_pdata(struct device *dev) 1746 { 1747 return NULL; 1748 } 1749 #endif 1750 1751 static int omap_hsmmc_probe(struct platform_device *pdev) 1752 { 1753 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1754 struct mmc_host *mmc; 1755 struct omap_hsmmc_host *host = NULL; 1756 struct resource *res; 1757 int ret, irq; 1758 const struct of_device_id *match; 1759 dma_cap_mask_t mask; 1760 unsigned tx_req, rx_req; 1761 struct pinctrl *pinctrl; 1762 1763 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1764 if (match) { 1765 pdata = of_get_hsmmc_pdata(&pdev->dev); 1766 1767 if (IS_ERR(pdata)) 1768 return PTR_ERR(pdata); 1769 1770 if (match->data) { 1771 const u16 *offsetp = match->data; 1772 pdata->reg_offset = *offsetp; 1773 } 1774 } 1775 1776 if (pdata == NULL) { 1777 dev_err(&pdev->dev, "Platform Data is missing\n"); 1778 return -ENXIO; 1779 } 1780 1781 if (pdata->nr_slots == 0) { 1782 dev_err(&pdev->dev, "No Slots\n"); 1783 return -ENXIO; 1784 } 1785 1786 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1787 irq = platform_get_irq(pdev, 0); 1788 if (res == NULL || irq < 0) 1789 return -ENXIO; 1790 1791 res = request_mem_region(res->start, resource_size(res), pdev->name); 1792 if (res == NULL) 1793 return -EBUSY; 1794 1795 ret = omap_hsmmc_gpio_init(pdata); 1796 if (ret) 1797 goto err; 1798 1799 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1800 if (!mmc) { 1801 ret = -ENOMEM; 1802 goto err_alloc; 1803 } 1804 1805 host = mmc_priv(mmc); 1806 host->mmc = mmc; 1807 host->pdata = pdata; 1808 host->dev = &pdev->dev; 1809 host->use_dma = 1; 1810 host->dma_ch = -1; 1811 host->irq = irq; 1812 host->slot_id = 0; 1813 host->mapbase = res->start + pdata->reg_offset; 1814 host->base = ioremap(host->mapbase, SZ_4K); 1815 host->power_mode = MMC_POWER_OFF; 1816 host->next_data.cookie = 1; 1817 1818 platform_set_drvdata(pdev, host); 1819 1820 mmc->ops = &omap_hsmmc_ops; 1821 1822 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1823 1824 if (pdata->max_freq > 0) 1825 mmc->f_max = pdata->max_freq; 1826 else 1827 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1828 1829 spin_lock_init(&host->irq_lock); 1830 1831 host->fclk = clk_get(&pdev->dev, "fck"); 1832 if (IS_ERR(host->fclk)) { 1833 ret = PTR_ERR(host->fclk); 1834 host->fclk = NULL; 1835 goto err1; 1836 } 1837 1838 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1839 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1840 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 1841 } 1842 1843 pm_runtime_enable(host->dev); 1844 pm_runtime_get_sync(host->dev); 1845 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1846 pm_runtime_use_autosuspend(host->dev); 1847 1848 omap_hsmmc_context_save(host); 1849 1850 /* This can be removed once we support PBIAS with DT */ 1851 if (host->dev->of_node && res->start == 0x4809c000) 1852 host->pbias_disable = 1; 1853 1854 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1855 /* 1856 * MMC can still work without debounce clock. 1857 */ 1858 if (IS_ERR(host->dbclk)) { 1859 host->dbclk = NULL; 1860 } else if (clk_prepare_enable(host->dbclk) != 0) { 1861 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1862 clk_put(host->dbclk); 1863 host->dbclk = NULL; 1864 } 1865 1866 /* Since we do only SG emulation, we can have as many segs 1867 * as we want. */ 1868 mmc->max_segs = 1024; 1869 1870 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1871 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1872 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1873 mmc->max_seg_size = mmc->max_req_size; 1874 1875 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1876 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1877 1878 mmc->caps |= mmc_slot(host).caps; 1879 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1880 mmc->caps |= MMC_CAP_4_BIT_DATA; 1881 1882 if (mmc_slot(host).nonremovable) 1883 mmc->caps |= MMC_CAP_NONREMOVABLE; 1884 1885 mmc->pm_caps = mmc_slot(host).pm_caps; 1886 1887 omap_hsmmc_conf_bus_power(host); 1888 1889 if (!pdev->dev.of_node) { 1890 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1891 if (!res) { 1892 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 1893 ret = -ENXIO; 1894 goto err_irq; 1895 } 1896 tx_req = res->start; 1897 1898 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1899 if (!res) { 1900 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 1901 ret = -ENXIO; 1902 goto err_irq; 1903 } 1904 rx_req = res->start; 1905 } 1906 1907 dma_cap_zero(mask); 1908 dma_cap_set(DMA_SLAVE, mask); 1909 1910 host->rx_chan = 1911 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1912 &rx_req, &pdev->dev, "rx"); 1913 1914 if (!host->rx_chan) { 1915 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 1916 ret = -ENXIO; 1917 goto err_irq; 1918 } 1919 1920 host->tx_chan = 1921 dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1922 &tx_req, &pdev->dev, "tx"); 1923 1924 if (!host->tx_chan) { 1925 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 1926 ret = -ENXIO; 1927 goto err_irq; 1928 } 1929 1930 /* Request IRQ for MMC operations */ 1931 ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1932 mmc_hostname(mmc), host); 1933 if (ret) { 1934 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1935 goto err_irq; 1936 } 1937 1938 if (pdata->init != NULL) { 1939 if (pdata->init(&pdev->dev) != 0) { 1940 dev_err(mmc_dev(host->mmc), 1941 "Unable to configure MMC IRQs\n"); 1942 goto err_irq_cd_init; 1943 } 1944 } 1945 1946 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1947 ret = omap_hsmmc_reg_get(host); 1948 if (ret) 1949 goto err_reg; 1950 host->use_reg = 1; 1951 } 1952 1953 mmc->ocr_avail = mmc_slot(host).ocr_mask; 1954 1955 /* Request IRQ for card detect */ 1956 if ((mmc_slot(host).card_detect_irq)) { 1957 ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 1958 NULL, 1959 omap_hsmmc_detect, 1960 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1961 mmc_hostname(mmc), host); 1962 if (ret) { 1963 dev_err(mmc_dev(host->mmc), 1964 "Unable to grab MMC CD IRQ\n"); 1965 goto err_irq_cd; 1966 } 1967 pdata->suspend = omap_hsmmc_suspend_cdirq; 1968 pdata->resume = omap_hsmmc_resume_cdirq; 1969 } 1970 1971 omap_hsmmc_disable_irq(host); 1972 1973 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1974 if (IS_ERR(pinctrl)) 1975 dev_warn(&pdev->dev, 1976 "pins are not configured from the driver\n"); 1977 1978 omap_hsmmc_protect_card(host); 1979 1980 mmc_add_host(mmc); 1981 1982 if (mmc_slot(host).name != NULL) { 1983 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1984 if (ret < 0) 1985 goto err_slot_name; 1986 } 1987 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1988 ret = device_create_file(&mmc->class_dev, 1989 &dev_attr_cover_switch); 1990 if (ret < 0) 1991 goto err_slot_name; 1992 } 1993 1994 omap_hsmmc_debugfs(mmc); 1995 pm_runtime_mark_last_busy(host->dev); 1996 pm_runtime_put_autosuspend(host->dev); 1997 1998 return 0; 1999 2000 err_slot_name: 2001 mmc_remove_host(mmc); 2002 free_irq(mmc_slot(host).card_detect_irq, host); 2003 err_irq_cd: 2004 if (host->use_reg) 2005 omap_hsmmc_reg_put(host); 2006 err_reg: 2007 if (host->pdata->cleanup) 2008 host->pdata->cleanup(&pdev->dev); 2009 err_irq_cd_init: 2010 free_irq(host->irq, host); 2011 err_irq: 2012 if (host->tx_chan) 2013 dma_release_channel(host->tx_chan); 2014 if (host->rx_chan) 2015 dma_release_channel(host->rx_chan); 2016 pm_runtime_put_sync(host->dev); 2017 pm_runtime_disable(host->dev); 2018 clk_put(host->fclk); 2019 if (host->dbclk) { 2020 clk_disable_unprepare(host->dbclk); 2021 clk_put(host->dbclk); 2022 } 2023 err1: 2024 iounmap(host->base); 2025 mmc_free_host(mmc); 2026 err_alloc: 2027 omap_hsmmc_gpio_free(pdata); 2028 err: 2029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2030 if (res) 2031 release_mem_region(res->start, resource_size(res)); 2032 return ret; 2033 } 2034 2035 static int omap_hsmmc_remove(struct platform_device *pdev) 2036 { 2037 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2038 struct resource *res; 2039 2040 pm_runtime_get_sync(host->dev); 2041 mmc_remove_host(host->mmc); 2042 if (host->use_reg) 2043 omap_hsmmc_reg_put(host); 2044 if (host->pdata->cleanup) 2045 host->pdata->cleanup(&pdev->dev); 2046 free_irq(host->irq, host); 2047 if (mmc_slot(host).card_detect_irq) 2048 free_irq(mmc_slot(host).card_detect_irq, host); 2049 2050 if (host->tx_chan) 2051 dma_release_channel(host->tx_chan); 2052 if (host->rx_chan) 2053 dma_release_channel(host->rx_chan); 2054 2055 pm_runtime_put_sync(host->dev); 2056 pm_runtime_disable(host->dev); 2057 clk_put(host->fclk); 2058 if (host->dbclk) { 2059 clk_disable_unprepare(host->dbclk); 2060 clk_put(host->dbclk); 2061 } 2062 2063 omap_hsmmc_gpio_free(host->pdata); 2064 iounmap(host->base); 2065 mmc_free_host(host->mmc); 2066 2067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2068 if (res) 2069 release_mem_region(res->start, resource_size(res)); 2070 2071 return 0; 2072 } 2073 2074 #ifdef CONFIG_PM 2075 static int omap_hsmmc_prepare(struct device *dev) 2076 { 2077 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2078 2079 if (host->pdata->suspend) 2080 return host->pdata->suspend(dev, host->slot_id); 2081 2082 return 0; 2083 } 2084 2085 static void omap_hsmmc_complete(struct device *dev) 2086 { 2087 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2088 2089 if (host->pdata->resume) 2090 host->pdata->resume(dev, host->slot_id); 2091 2092 } 2093 2094 static int omap_hsmmc_suspend(struct device *dev) 2095 { 2096 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2097 2098 if (!host) 2099 return 0; 2100 2101 pm_runtime_get_sync(host->dev); 2102 2103 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2104 omap_hsmmc_disable_irq(host); 2105 OMAP_HSMMC_WRITE(host->base, HCTL, 2106 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2107 } 2108 2109 if (host->dbclk) 2110 clk_disable_unprepare(host->dbclk); 2111 2112 pm_runtime_put_sync(host->dev); 2113 return 0; 2114 } 2115 2116 /* Routine to resume the MMC device */ 2117 static int omap_hsmmc_resume(struct device *dev) 2118 { 2119 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2120 2121 if (!host) 2122 return 0; 2123 2124 pm_runtime_get_sync(host->dev); 2125 2126 if (host->dbclk) 2127 clk_prepare_enable(host->dbclk); 2128 2129 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2130 omap_hsmmc_conf_bus_power(host); 2131 2132 omap_hsmmc_protect_card(host); 2133 2134 pm_runtime_mark_last_busy(host->dev); 2135 pm_runtime_put_autosuspend(host->dev); 2136 return 0; 2137 } 2138 2139 #else 2140 #define omap_hsmmc_prepare NULL 2141 #define omap_hsmmc_complete NULL 2142 #define omap_hsmmc_suspend NULL 2143 #define omap_hsmmc_resume NULL 2144 #endif 2145 2146 static int omap_hsmmc_runtime_suspend(struct device *dev) 2147 { 2148 struct omap_hsmmc_host *host; 2149 2150 host = platform_get_drvdata(to_platform_device(dev)); 2151 omap_hsmmc_context_save(host); 2152 dev_dbg(dev, "disabled\n"); 2153 2154 return 0; 2155 } 2156 2157 static int omap_hsmmc_runtime_resume(struct device *dev) 2158 { 2159 struct omap_hsmmc_host *host; 2160 2161 host = platform_get_drvdata(to_platform_device(dev)); 2162 omap_hsmmc_context_restore(host); 2163 dev_dbg(dev, "enabled\n"); 2164 2165 return 0; 2166 } 2167 2168 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2169 .suspend = omap_hsmmc_suspend, 2170 .resume = omap_hsmmc_resume, 2171 .prepare = omap_hsmmc_prepare, 2172 .complete = omap_hsmmc_complete, 2173 .runtime_suspend = omap_hsmmc_runtime_suspend, 2174 .runtime_resume = omap_hsmmc_runtime_resume, 2175 }; 2176 2177 static struct platform_driver omap_hsmmc_driver = { 2178 .probe = omap_hsmmc_probe, 2179 .remove = omap_hsmmc_remove, 2180 .driver = { 2181 .name = DRIVER_NAME, 2182 .owner = THIS_MODULE, 2183 .pm = &omap_hsmmc_dev_pm_ops, 2184 .of_match_table = of_match_ptr(omap_mmc_of_match), 2185 }, 2186 }; 2187 2188 module_platform_driver(omap_hsmmc_driver); 2189 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2190 MODULE_LICENSE("GPL"); 2191 MODULE_ALIAS("platform:" DRIVER_NAME); 2192 MODULE_AUTHOR("Texas Instruments Inc"); 2193