1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/sizes.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/timer.h> 30 #include <linux/clk.h> 31 #include <linux/of.h> 32 #include <linux/of_irq.h> 33 #include <linux/of_gpio.h> 34 #include <linux/of_device.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/core.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/mmc/slot-gpio.h> 39 #include <linux/io.h> 40 #include <linux/irq.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/pm_wakeirq.h> 46 #include <linux/platform_data/hsmmc-omap.h> 47 48 /* OMAP HSMMC Host Controller Registers */ 49 #define OMAP_HSMMC_SYSSTATUS 0x0014 50 #define OMAP_HSMMC_CON 0x002C 51 #define OMAP_HSMMC_SDMASA 0x0100 52 #define OMAP_HSMMC_BLK 0x0104 53 #define OMAP_HSMMC_ARG 0x0108 54 #define OMAP_HSMMC_CMD 0x010C 55 #define OMAP_HSMMC_RSP10 0x0110 56 #define OMAP_HSMMC_RSP32 0x0114 57 #define OMAP_HSMMC_RSP54 0x0118 58 #define OMAP_HSMMC_RSP76 0x011C 59 #define OMAP_HSMMC_DATA 0x0120 60 #define OMAP_HSMMC_PSTATE 0x0124 61 #define OMAP_HSMMC_HCTL 0x0128 62 #define OMAP_HSMMC_SYSCTL 0x012C 63 #define OMAP_HSMMC_STAT 0x0130 64 #define OMAP_HSMMC_IE 0x0134 65 #define OMAP_HSMMC_ISE 0x0138 66 #define OMAP_HSMMC_AC12 0x013C 67 #define OMAP_HSMMC_CAPA 0x0140 68 69 #define VS18 (1 << 26) 70 #define VS30 (1 << 25) 71 #define HSS (1 << 21) 72 #define SDVS18 (0x5 << 9) 73 #define SDVS30 (0x6 << 9) 74 #define SDVS33 (0x7 << 9) 75 #define SDVS_MASK 0x00000E00 76 #define SDVSCLR 0xFFFFF1FF 77 #define SDVSDET 0x00000400 78 #define AUTOIDLE 0x1 79 #define SDBP (1 << 8) 80 #define DTO 0xe 81 #define ICE 0x1 82 #define ICS 0x2 83 #define CEN (1 << 2) 84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85 #define CLKD_MASK 0x0000FFC0 86 #define CLKD_SHIFT 6 87 #define DTO_MASK 0x000F0000 88 #define DTO_SHIFT 16 89 #define INIT_STREAM (1 << 1) 90 #define ACEN_ACMD23 (2 << 2) 91 #define DP_SELECT (1 << 21) 92 #define DDIR (1 << 4) 93 #define DMAE 0x1 94 #define MSBS (1 << 5) 95 #define BCE (1 << 1) 96 #define FOUR_BIT (1 << 1) 97 #define HSPE (1 << 2) 98 #define IWE (1 << 24) 99 #define DDR (1 << 19) 100 #define CLKEXTFREE (1 << 16) 101 #define CTPL (1 << 11) 102 #define DW8 (1 << 5) 103 #define OD 0x1 104 #define STAT_CLEAR 0xFFFFFFFF 105 #define INIT_STREAM_CMD 0x00000000 106 #define DUAL_VOLT_OCR_BIT 7 107 #define SRC (1 << 25) 108 #define SRD (1 << 26) 109 #define SOFTRESET (1 << 1) 110 111 /* PSTATE */ 112 #define DLEV_DAT(x) (1 << (20 + (x))) 113 114 /* Interrupt masks for IE and ISE register */ 115 #define CC_EN (1 << 0) 116 #define TC_EN (1 << 1) 117 #define BWR_EN (1 << 4) 118 #define BRR_EN (1 << 5) 119 #define CIRQ_EN (1 << 8) 120 #define ERR_EN (1 << 15) 121 #define CTO_EN (1 << 16) 122 #define CCRC_EN (1 << 17) 123 #define CEB_EN (1 << 18) 124 #define CIE_EN (1 << 19) 125 #define DTO_EN (1 << 20) 126 #define DCRC_EN (1 << 21) 127 #define DEB_EN (1 << 22) 128 #define ACE_EN (1 << 24) 129 #define CERR_EN (1 << 28) 130 #define BADA_EN (1 << 29) 131 132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134 BRR_EN | BWR_EN | TC_EN | CC_EN) 135 136 #define CNI (1 << 7) 137 #define ACIE (1 << 4) 138 #define ACEB (1 << 3) 139 #define ACCE (1 << 2) 140 #define ACTO (1 << 1) 141 #define ACNE (1 << 0) 142 143 #define MMC_AUTOSUSPEND_DELAY 100 144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 146 #define OMAP_MMC_MIN_CLOCK 400000 147 #define OMAP_MMC_MAX_CLOCK 52000000 148 #define DRIVER_NAME "omap_hsmmc" 149 150 #define VDD_1V8 1800000 /* 180000 uV */ 151 #define VDD_3V0 3000000 /* 300000 uV */ 152 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 153 154 /* 155 * One controller can have multiple slots, like on some omap boards using 156 * omap.c controller driver. Luckily this is not currently done on any known 157 * omap_hsmmc.c device. 158 */ 159 #define mmc_pdata(host) host->pdata 160 161 /* 162 * MMC Host controller read/write API's 163 */ 164 #define OMAP_HSMMC_READ(base, reg) \ 165 __raw_readl((base) + OMAP_HSMMC_##reg) 166 167 #define OMAP_HSMMC_WRITE(base, reg, val) \ 168 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 169 170 struct omap_hsmmc_next { 171 unsigned int dma_len; 172 s32 cookie; 173 }; 174 175 struct omap_hsmmc_host { 176 struct device *dev; 177 struct mmc_host *mmc; 178 struct mmc_request *mrq; 179 struct mmc_command *cmd; 180 struct mmc_data *data; 181 struct clk *fclk; 182 struct clk *dbclk; 183 struct regulator *pbias; 184 bool pbias_enabled; 185 void __iomem *base; 186 int vqmmc_enabled; 187 resource_size_t mapbase; 188 spinlock_t irq_lock; /* Prevent races with irq handler */ 189 unsigned int dma_len; 190 unsigned int dma_sg_idx; 191 unsigned char bus_mode; 192 unsigned char power_mode; 193 int suspended; 194 u32 con; 195 u32 hctl; 196 u32 sysctl; 197 u32 capa; 198 int irq; 199 int wake_irq; 200 int use_dma, dma_ch; 201 struct dma_chan *tx_chan; 202 struct dma_chan *rx_chan; 203 int response_busy; 204 int context_loss; 205 int protect_card; 206 int reqs_blocked; 207 int req_in_progress; 208 unsigned long clk_rate; 209 unsigned int flags; 210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 212 struct omap_hsmmc_next next_data; 213 struct omap_hsmmc_platform_data *pdata; 214 215 /* return MMC cover switch state, can be NULL if not supported. 216 * 217 * possible return values: 218 * 0 - closed 219 * 1 - open 220 */ 221 int (*get_cover_state)(struct device *dev); 222 223 int (*card_detect)(struct device *dev); 224 }; 225 226 struct omap_mmc_of_data { 227 u32 reg_offset; 228 u8 controller_flags; 229 }; 230 231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232 233 static int omap_hsmmc_card_detect(struct device *dev) 234 { 235 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236 237 return mmc_gpio_get_cd(host->mmc); 238 } 239 240 static int omap_hsmmc_get_cover_state(struct device *dev) 241 { 242 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243 244 return mmc_gpio_get_cd(host->mmc); 245 } 246 247 static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 248 { 249 int ret; 250 struct omap_hsmmc_host *host = mmc_priv(mmc); 251 struct mmc_ios *ios = &mmc->ios; 252 253 if (!IS_ERR(mmc->supply.vmmc)) { 254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 255 if (ret) 256 return ret; 257 } 258 259 /* Enable interface voltage rail, if needed */ 260 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 261 ret = regulator_enable(mmc->supply.vqmmc); 262 if (ret) { 263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 264 goto err_vqmmc; 265 } 266 host->vqmmc_enabled = 1; 267 } 268 269 return 0; 270 271 err_vqmmc: 272 if (!IS_ERR(mmc->supply.vmmc)) 273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 274 275 return ret; 276 } 277 278 static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 279 { 280 int ret; 281 int status; 282 struct omap_hsmmc_host *host = mmc_priv(mmc); 283 284 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 285 ret = regulator_disable(mmc->supply.vqmmc); 286 if (ret) { 287 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 288 return ret; 289 } 290 host->vqmmc_enabled = 0; 291 } 292 293 if (!IS_ERR(mmc->supply.vmmc)) { 294 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 295 if (ret) 296 goto err_set_ocr; 297 } 298 299 return 0; 300 301 err_set_ocr: 302 if (!IS_ERR(mmc->supply.vqmmc)) { 303 status = regulator_enable(mmc->supply.vqmmc); 304 if (status) 305 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 306 } 307 308 return ret; 309 } 310 311 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 312 int vdd) 313 { 314 int ret; 315 316 if (IS_ERR(host->pbias)) 317 return 0; 318 319 if (power_on) { 320 if (vdd <= VDD_165_195) 321 ret = regulator_set_voltage(host->pbias, VDD_1V8, 322 VDD_1V8); 323 else 324 ret = regulator_set_voltage(host->pbias, VDD_3V0, 325 VDD_3V0); 326 if (ret < 0) { 327 dev_err(host->dev, "pbias set voltage fail\n"); 328 return ret; 329 } 330 331 if (host->pbias_enabled == 0) { 332 ret = regulator_enable(host->pbias); 333 if (ret) { 334 dev_err(host->dev, "pbias reg enable fail\n"); 335 return ret; 336 } 337 host->pbias_enabled = 1; 338 } 339 } else { 340 if (host->pbias_enabled == 1) { 341 ret = regulator_disable(host->pbias); 342 if (ret) { 343 dev_err(host->dev, "pbias reg disable fail\n"); 344 return ret; 345 } 346 host->pbias_enabled = 0; 347 } 348 } 349 350 return 0; 351 } 352 353 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, 354 int vdd) 355 { 356 struct mmc_host *mmc = host->mmc; 357 int ret = 0; 358 359 if (mmc_pdata(host)->set_power) 360 return mmc_pdata(host)->set_power(host->dev, power_on, vdd); 361 362 /* 363 * If we don't see a Vcc regulator, assume it's a fixed 364 * voltage always-on regulator. 365 */ 366 if (IS_ERR(mmc->supply.vmmc)) 367 return 0; 368 369 if (mmc_pdata(host)->before_set_reg) 370 mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd); 371 372 ret = omap_hsmmc_set_pbias(host, false, 0); 373 if (ret) 374 return ret; 375 376 /* 377 * Assume Vcc regulator is used only to power the card ... OMAP 378 * VDDS is used to power the pins, optionally with a transceiver to 379 * support cards using voltages other than VDDS (1.8V nominal). When a 380 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 381 * 382 * In some cases this regulator won't support enable/disable; 383 * e.g. it's a fixed rail for a WLAN chip. 384 * 385 * In other cases vcc_aux switches interface power. Example, for 386 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 387 * chips/cards need an interface voltage rail too. 388 */ 389 if (power_on) { 390 ret = omap_hsmmc_enable_supply(mmc); 391 if (ret) 392 return ret; 393 394 ret = omap_hsmmc_set_pbias(host, true, vdd); 395 if (ret) 396 goto err_set_voltage; 397 } else { 398 ret = omap_hsmmc_disable_supply(mmc); 399 if (ret) 400 return ret; 401 } 402 403 if (mmc_pdata(host)->after_set_reg) 404 mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd); 405 406 return 0; 407 408 err_set_voltage: 409 omap_hsmmc_disable_supply(mmc); 410 411 return ret; 412 } 413 414 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 415 { 416 int ret; 417 418 if (IS_ERR(reg)) 419 return 0; 420 421 if (regulator_is_enabled(reg)) { 422 ret = regulator_enable(reg); 423 if (ret) 424 return ret; 425 426 ret = regulator_disable(reg); 427 if (ret) 428 return ret; 429 } 430 431 return 0; 432 } 433 434 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 435 { 436 struct mmc_host *mmc = host->mmc; 437 int ret; 438 439 /* 440 * disable regulators enabled during boot and get the usecount 441 * right so that regulators can be enabled/disabled by checking 442 * the return value of regulator_is_enabled 443 */ 444 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 445 if (ret) { 446 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 447 return ret; 448 } 449 450 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 451 if (ret) { 452 dev_err(host->dev, 453 "fail to disable boot enabled vmmc_aux reg\n"); 454 return ret; 455 } 456 457 ret = omap_hsmmc_disable_boot_regulator(host->pbias); 458 if (ret) { 459 dev_err(host->dev, 460 "failed to disable boot enabled pbias reg\n"); 461 return ret; 462 } 463 464 return 0; 465 } 466 467 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 468 { 469 int ret; 470 struct mmc_host *mmc = host->mmc; 471 472 if (mmc_pdata(host)->set_power) 473 return 0; 474 475 ret = mmc_regulator_get_supply(mmc); 476 if (ret == -EPROBE_DEFER) 477 return ret; 478 479 /* Allow an aux regulator */ 480 if (IS_ERR(mmc->supply.vqmmc)) { 481 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 482 "vmmc_aux"); 483 if (IS_ERR(mmc->supply.vqmmc)) { 484 ret = PTR_ERR(mmc->supply.vqmmc); 485 if ((ret != -ENODEV) && host->dev->of_node) 486 return ret; 487 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 488 PTR_ERR(mmc->supply.vqmmc)); 489 } 490 } 491 492 host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 493 if (IS_ERR(host->pbias)) { 494 ret = PTR_ERR(host->pbias); 495 if ((ret != -ENODEV) && host->dev->of_node) { 496 dev_err(host->dev, 497 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 498 return ret; 499 } 500 dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 501 PTR_ERR(host->pbias)); 502 } 503 504 /* For eMMC do not power off when not in sleep state */ 505 if (mmc_pdata(host)->no_regulator_off_init) 506 return 0; 507 508 ret = omap_hsmmc_disable_boot_regulators(host); 509 if (ret) 510 return ret; 511 512 return 0; 513 } 514 515 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 516 517 static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 518 struct omap_hsmmc_host *host, 519 struct omap_hsmmc_platform_data *pdata) 520 { 521 int ret; 522 523 if (gpio_is_valid(pdata->gpio_cod)) { 524 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 525 if (ret) 526 return ret; 527 528 host->get_cover_state = omap_hsmmc_get_cover_state; 529 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 530 } else if (gpio_is_valid(pdata->gpio_cd)) { 531 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 532 if (ret) 533 return ret; 534 535 host->card_detect = omap_hsmmc_card_detect; 536 } 537 538 if (gpio_is_valid(pdata->gpio_wp)) { 539 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 540 if (ret) 541 return ret; 542 } 543 544 return 0; 545 } 546 547 /* 548 * Start clock to the card 549 */ 550 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 551 { 552 OMAP_HSMMC_WRITE(host->base, SYSCTL, 553 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 554 } 555 556 /* 557 * Stop clock to the card 558 */ 559 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 560 { 561 OMAP_HSMMC_WRITE(host->base, SYSCTL, 562 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 563 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 564 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 565 } 566 567 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 568 struct mmc_command *cmd) 569 { 570 u32 irq_mask = INT_EN_MASK; 571 unsigned long flags; 572 573 if (host->use_dma) 574 irq_mask &= ~(BRR_EN | BWR_EN); 575 576 /* Disable timeout for erases */ 577 if (cmd->opcode == MMC_ERASE) 578 irq_mask &= ~DTO_EN; 579 580 spin_lock_irqsave(&host->irq_lock, flags); 581 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 582 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 583 584 /* latch pending CIRQ, but don't signal MMC core */ 585 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 586 irq_mask |= CIRQ_EN; 587 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 588 spin_unlock_irqrestore(&host->irq_lock, flags); 589 } 590 591 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 592 { 593 u32 irq_mask = 0; 594 unsigned long flags; 595 596 spin_lock_irqsave(&host->irq_lock, flags); 597 /* no transfer running but need to keep cirq if enabled */ 598 if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 599 irq_mask |= CIRQ_EN; 600 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 601 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 602 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 603 spin_unlock_irqrestore(&host->irq_lock, flags); 604 } 605 606 /* Calculate divisor for the given clock frequency */ 607 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 608 { 609 u16 dsor = 0; 610 611 if (ios->clock) { 612 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 613 if (dsor > CLKD_MAX) 614 dsor = CLKD_MAX; 615 } 616 617 return dsor; 618 } 619 620 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 621 { 622 struct mmc_ios *ios = &host->mmc->ios; 623 unsigned long regval; 624 unsigned long timeout; 625 unsigned long clkdiv; 626 627 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 628 629 omap_hsmmc_stop_clock(host); 630 631 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 632 regval = regval & ~(CLKD_MASK | DTO_MASK); 633 clkdiv = calc_divisor(host, ios); 634 regval = regval | (clkdiv << 6) | (DTO << 16); 635 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 636 OMAP_HSMMC_WRITE(host->base, SYSCTL, 637 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 638 639 /* Wait till the ICS bit is set */ 640 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 641 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 642 && time_before(jiffies, timeout)) 643 cpu_relax(); 644 645 /* 646 * Enable High-Speed Support 647 * Pre-Requisites 648 * - Controller should support High-Speed-Enable Bit 649 * - Controller should not be using DDR Mode 650 * - Controller should advertise that it supports High Speed 651 * in capabilities register 652 * - MMC/SD clock coming out of controller > 25MHz 653 */ 654 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 655 (ios->timing != MMC_TIMING_MMC_DDR52) && 656 (ios->timing != MMC_TIMING_UHS_DDR50) && 657 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 658 regval = OMAP_HSMMC_READ(host->base, HCTL); 659 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 660 regval |= HSPE; 661 else 662 regval &= ~HSPE; 663 664 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 665 } 666 667 omap_hsmmc_start_clock(host); 668 } 669 670 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 671 { 672 struct mmc_ios *ios = &host->mmc->ios; 673 u32 con; 674 675 con = OMAP_HSMMC_READ(host->base, CON); 676 if (ios->timing == MMC_TIMING_MMC_DDR52 || 677 ios->timing == MMC_TIMING_UHS_DDR50) 678 con |= DDR; /* configure in DDR mode */ 679 else 680 con &= ~DDR; 681 switch (ios->bus_width) { 682 case MMC_BUS_WIDTH_8: 683 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 684 break; 685 case MMC_BUS_WIDTH_4: 686 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 687 OMAP_HSMMC_WRITE(host->base, HCTL, 688 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 689 break; 690 case MMC_BUS_WIDTH_1: 691 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 692 OMAP_HSMMC_WRITE(host->base, HCTL, 693 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 694 break; 695 } 696 } 697 698 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 699 { 700 struct mmc_ios *ios = &host->mmc->ios; 701 u32 con; 702 703 con = OMAP_HSMMC_READ(host->base, CON); 704 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 705 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 706 else 707 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 708 } 709 710 #ifdef CONFIG_PM 711 712 /* 713 * Restore the MMC host context, if it was lost as result of a 714 * power state change. 715 */ 716 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 717 { 718 struct mmc_ios *ios = &host->mmc->ios; 719 u32 hctl, capa; 720 unsigned long timeout; 721 722 if (host->con == OMAP_HSMMC_READ(host->base, CON) && 723 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 724 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 725 host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 726 return 0; 727 728 host->context_loss++; 729 730 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 731 if (host->power_mode != MMC_POWER_OFF && 732 (1 << ios->vdd) <= MMC_VDD_23_24) 733 hctl = SDVS18; 734 else 735 hctl = SDVS30; 736 capa = VS30 | VS18; 737 } else { 738 hctl = SDVS18; 739 capa = VS18; 740 } 741 742 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 743 hctl |= IWE; 744 745 OMAP_HSMMC_WRITE(host->base, HCTL, 746 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 747 748 OMAP_HSMMC_WRITE(host->base, CAPA, 749 OMAP_HSMMC_READ(host->base, CAPA) | capa); 750 751 OMAP_HSMMC_WRITE(host->base, HCTL, 752 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 753 754 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 755 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 756 && time_before(jiffies, timeout)) 757 ; 758 759 OMAP_HSMMC_WRITE(host->base, ISE, 0); 760 OMAP_HSMMC_WRITE(host->base, IE, 0); 761 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 762 763 /* Do not initialize card-specific things if the power is off */ 764 if (host->power_mode == MMC_POWER_OFF) 765 goto out; 766 767 omap_hsmmc_set_bus_width(host); 768 769 omap_hsmmc_set_clock(host); 770 771 omap_hsmmc_set_bus_mode(host); 772 773 out: 774 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 775 host->context_loss); 776 return 0; 777 } 778 779 /* 780 * Save the MMC host context (store the number of power state changes so far). 781 */ 782 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 783 { 784 host->con = OMAP_HSMMC_READ(host->base, CON); 785 host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 786 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 787 host->capa = OMAP_HSMMC_READ(host->base, CAPA); 788 } 789 790 #else 791 792 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 793 { 794 return 0; 795 } 796 797 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 798 { 799 } 800 801 #endif 802 803 /* 804 * Send init stream sequence to card 805 * before sending IDLE command 806 */ 807 static void send_init_stream(struct omap_hsmmc_host *host) 808 { 809 int reg = 0; 810 unsigned long timeout; 811 812 if (host->protect_card) 813 return; 814 815 disable_irq(host->irq); 816 817 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 818 OMAP_HSMMC_WRITE(host->base, CON, 819 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 820 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 821 822 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 823 while ((reg != CC_EN) && time_before(jiffies, timeout)) 824 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 825 826 OMAP_HSMMC_WRITE(host->base, CON, 827 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 828 829 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 830 OMAP_HSMMC_READ(host->base, STAT); 831 832 enable_irq(host->irq); 833 } 834 835 static inline 836 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 837 { 838 int r = 1; 839 840 if (host->get_cover_state) 841 r = host->get_cover_state(host->dev); 842 return r; 843 } 844 845 static ssize_t 846 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 847 char *buf) 848 { 849 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 850 struct omap_hsmmc_host *host = mmc_priv(mmc); 851 852 return sprintf(buf, "%s\n", 853 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 854 } 855 856 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 857 858 static ssize_t 859 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 860 char *buf) 861 { 862 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 863 struct omap_hsmmc_host *host = mmc_priv(mmc); 864 865 return sprintf(buf, "%s\n", mmc_pdata(host)->name); 866 } 867 868 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 869 870 /* 871 * Configure the response type and send the cmd. 872 */ 873 static void 874 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 875 struct mmc_data *data) 876 { 877 int cmdreg = 0, resptype = 0, cmdtype = 0; 878 879 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 880 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 881 host->cmd = cmd; 882 883 omap_hsmmc_enable_irq(host, cmd); 884 885 host->response_busy = 0; 886 if (cmd->flags & MMC_RSP_PRESENT) { 887 if (cmd->flags & MMC_RSP_136) 888 resptype = 1; 889 else if (cmd->flags & MMC_RSP_BUSY) { 890 resptype = 3; 891 host->response_busy = 1; 892 } else 893 resptype = 2; 894 } 895 896 /* 897 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 898 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 899 * a val of 0x3, rest 0x0. 900 */ 901 if (cmd == host->mrq->stop) 902 cmdtype = 0x3; 903 904 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 905 906 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 907 host->mrq->sbc) { 908 cmdreg |= ACEN_ACMD23; 909 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 910 } 911 if (data) { 912 cmdreg |= DP_SELECT | MSBS | BCE; 913 if (data->flags & MMC_DATA_READ) 914 cmdreg |= DDIR; 915 else 916 cmdreg &= ~(DDIR); 917 } 918 919 if (host->use_dma) 920 cmdreg |= DMAE; 921 922 host->req_in_progress = 1; 923 924 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 925 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 926 } 927 928 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 929 struct mmc_data *data) 930 { 931 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 932 } 933 934 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 935 { 936 int dma_ch; 937 unsigned long flags; 938 939 spin_lock_irqsave(&host->irq_lock, flags); 940 host->req_in_progress = 0; 941 dma_ch = host->dma_ch; 942 spin_unlock_irqrestore(&host->irq_lock, flags); 943 944 omap_hsmmc_disable_irq(host); 945 /* Do not complete the request if DMA is still in progress */ 946 if (mrq->data && host->use_dma && dma_ch != -1) 947 return; 948 host->mrq = NULL; 949 mmc_request_done(host->mmc, mrq); 950 } 951 952 /* 953 * Notify the transfer complete to MMC core 954 */ 955 static void 956 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 957 { 958 if (!data) { 959 struct mmc_request *mrq = host->mrq; 960 961 /* TC before CC from CMD6 - don't know why, but it happens */ 962 if (host->cmd && host->cmd->opcode == 6 && 963 host->response_busy) { 964 host->response_busy = 0; 965 return; 966 } 967 968 omap_hsmmc_request_done(host, mrq); 969 return; 970 } 971 972 host->data = NULL; 973 974 if (!data->error) 975 data->bytes_xfered += data->blocks * (data->blksz); 976 else 977 data->bytes_xfered = 0; 978 979 if (data->stop && (data->error || !host->mrq->sbc)) 980 omap_hsmmc_start_command(host, data->stop, NULL); 981 else 982 omap_hsmmc_request_done(host, data->mrq); 983 } 984 985 /* 986 * Notify the core about command completion 987 */ 988 static void 989 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 990 { 991 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 992 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 993 host->cmd = NULL; 994 omap_hsmmc_start_dma_transfer(host); 995 omap_hsmmc_start_command(host, host->mrq->cmd, 996 host->mrq->data); 997 return; 998 } 999 1000 host->cmd = NULL; 1001 1002 if (cmd->flags & MMC_RSP_PRESENT) { 1003 if (cmd->flags & MMC_RSP_136) { 1004 /* response type 2 */ 1005 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1006 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1007 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1008 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1009 } else { 1010 /* response types 1, 1b, 3, 4, 5, 6 */ 1011 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1012 } 1013 } 1014 if ((host->data == NULL && !host->response_busy) || cmd->error) 1015 omap_hsmmc_request_done(host, host->mrq); 1016 } 1017 1018 /* 1019 * DMA clean up for command errors 1020 */ 1021 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1022 { 1023 int dma_ch; 1024 unsigned long flags; 1025 1026 host->data->error = errno; 1027 1028 spin_lock_irqsave(&host->irq_lock, flags); 1029 dma_ch = host->dma_ch; 1030 host->dma_ch = -1; 1031 spin_unlock_irqrestore(&host->irq_lock, flags); 1032 1033 if (host->use_dma && dma_ch != -1) { 1034 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1035 1036 dmaengine_terminate_all(chan); 1037 dma_unmap_sg(chan->device->dev, 1038 host->data->sg, host->data->sg_len, 1039 mmc_get_dma_dir(host->data)); 1040 1041 host->data->host_cookie = 0; 1042 } 1043 host->data = NULL; 1044 } 1045 1046 /* 1047 * Readable error output 1048 */ 1049 #ifdef CONFIG_MMC_DEBUG 1050 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1051 { 1052 /* --- means reserved bit without definition at documentation */ 1053 static const char *omap_hsmmc_status_bits[] = { 1054 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1055 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1056 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1057 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1058 }; 1059 char res[256]; 1060 char *buf = res; 1061 int len, i; 1062 1063 len = sprintf(buf, "MMC IRQ 0x%x :", status); 1064 buf += len; 1065 1066 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1067 if (status & (1 << i)) { 1068 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1069 buf += len; 1070 } 1071 1072 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1073 } 1074 #else 1075 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1076 u32 status) 1077 { 1078 } 1079 #endif /* CONFIG_MMC_DEBUG */ 1080 1081 /* 1082 * MMC controller internal state machines reset 1083 * 1084 * Used to reset command or data internal state machines, using respectively 1085 * SRC or SRD bit of SYSCTL register 1086 * Can be called from interrupt context 1087 */ 1088 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 1089 unsigned long bit) 1090 { 1091 unsigned long i = 0; 1092 unsigned long limit = MMC_TIMEOUT_US; 1093 1094 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1095 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 1096 1097 /* 1098 * OMAP4 ES2 and greater has an updated reset logic. 1099 * Monitor a 0->1 transition first 1100 */ 1101 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1102 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 1103 && (i++ < limit)) 1104 udelay(1); 1105 } 1106 i = 0; 1107 1108 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 1109 (i++ < limit)) 1110 udelay(1); 1111 1112 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 1113 dev_err(mmc_dev(host->mmc), 1114 "Timeout waiting on controller reset in %s\n", 1115 __func__); 1116 } 1117 1118 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1119 int err, int end_cmd) 1120 { 1121 if (end_cmd) { 1122 omap_hsmmc_reset_controller_fsm(host, SRC); 1123 if (host->cmd) 1124 host->cmd->error = err; 1125 } 1126 1127 if (host->data) { 1128 omap_hsmmc_reset_controller_fsm(host, SRD); 1129 omap_hsmmc_dma_cleanup(host, err); 1130 } else if (host->mrq && host->mrq->cmd) 1131 host->mrq->cmd->error = err; 1132 } 1133 1134 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1135 { 1136 struct mmc_data *data; 1137 int end_cmd = 0, end_trans = 0; 1138 int error = 0; 1139 1140 data = host->data; 1141 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1142 1143 if (status & ERR_EN) { 1144 omap_hsmmc_dbg_report_irq(host, status); 1145 1146 if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1147 end_cmd = 1; 1148 if (host->data || host->response_busy) { 1149 end_trans = !end_cmd; 1150 host->response_busy = 0; 1151 } 1152 if (status & (CTO_EN | DTO_EN)) 1153 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1154 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 1155 BADA_EN)) 1156 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1157 1158 if (status & ACE_EN) { 1159 u32 ac12; 1160 ac12 = OMAP_HSMMC_READ(host->base, AC12); 1161 if (!(ac12 & ACNE) && host->mrq->sbc) { 1162 end_cmd = 1; 1163 if (ac12 & ACTO) 1164 error = -ETIMEDOUT; 1165 else if (ac12 & (ACCE | ACEB | ACIE)) 1166 error = -EILSEQ; 1167 host->mrq->sbc->error = error; 1168 hsmmc_command_incomplete(host, error, end_cmd); 1169 } 1170 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1171 } 1172 } 1173 1174 OMAP_HSMMC_WRITE(host->base, STAT, status); 1175 if (end_cmd || ((status & CC_EN) && host->cmd)) 1176 omap_hsmmc_cmd_done(host, host->cmd); 1177 if ((end_trans || (status & TC_EN)) && host->mrq) 1178 omap_hsmmc_xfer_done(host, data); 1179 } 1180 1181 /* 1182 * MMC controller IRQ handler 1183 */ 1184 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1185 { 1186 struct omap_hsmmc_host *host = dev_id; 1187 int status; 1188 1189 status = OMAP_HSMMC_READ(host->base, STAT); 1190 while (status & (INT_EN_MASK | CIRQ_EN)) { 1191 if (host->req_in_progress) 1192 omap_hsmmc_do_irq(host, status); 1193 1194 if (status & CIRQ_EN) 1195 mmc_signal_sdio_irq(host->mmc); 1196 1197 /* Flush posted write */ 1198 status = OMAP_HSMMC_READ(host->base, STAT); 1199 } 1200 1201 return IRQ_HANDLED; 1202 } 1203 1204 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1205 { 1206 unsigned long i; 1207 1208 OMAP_HSMMC_WRITE(host->base, HCTL, 1209 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1210 for (i = 0; i < loops_per_jiffy; i++) { 1211 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1212 break; 1213 cpu_relax(); 1214 } 1215 } 1216 1217 /* 1218 * Switch MMC interface voltage ... only relevant for MMC1. 1219 * 1220 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1221 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1222 * Some chips, like eMMC ones, use internal transceivers. 1223 */ 1224 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1225 { 1226 u32 reg_val = 0; 1227 int ret; 1228 1229 /* Disable the clocks */ 1230 if (host->dbclk) 1231 clk_disable_unprepare(host->dbclk); 1232 1233 /* Turn the power off */ 1234 ret = omap_hsmmc_set_power(host, 0, 0); 1235 1236 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1237 if (!ret) 1238 ret = omap_hsmmc_set_power(host, 1, vdd); 1239 if (host->dbclk) 1240 clk_prepare_enable(host->dbclk); 1241 1242 if (ret != 0) 1243 goto err; 1244 1245 OMAP_HSMMC_WRITE(host->base, HCTL, 1246 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1247 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1248 1249 /* 1250 * If a MMC dual voltage card is detected, the set_ios fn calls 1251 * this fn with VDD bit set for 1.8V. Upon card removal from the 1252 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1253 * 1254 * Cope with a bit of slop in the range ... per data sheets: 1255 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1256 * but recommended values are 1.71V to 1.89V 1257 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1258 * but recommended values are 2.7V to 3.3V 1259 * 1260 * Board setup code shouldn't permit anything very out-of-range. 1261 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1262 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1263 */ 1264 if ((1 << vdd) <= MMC_VDD_23_24) 1265 reg_val |= SDVS18; 1266 else 1267 reg_val |= SDVS30; 1268 1269 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1270 set_sd_bus_power(host); 1271 1272 return 0; 1273 err: 1274 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1275 return ret; 1276 } 1277 1278 /* Protect the card while the cover is open */ 1279 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1280 { 1281 if (!host->get_cover_state) 1282 return; 1283 1284 host->reqs_blocked = 0; 1285 if (host->get_cover_state(host->dev)) { 1286 if (host->protect_card) { 1287 dev_info(host->dev, "%s: cover is closed, " 1288 "card is now accessible\n", 1289 mmc_hostname(host->mmc)); 1290 host->protect_card = 0; 1291 } 1292 } else { 1293 if (!host->protect_card) { 1294 dev_info(host->dev, "%s: cover is open, " 1295 "card is now inaccessible\n", 1296 mmc_hostname(host->mmc)); 1297 host->protect_card = 1; 1298 } 1299 } 1300 } 1301 1302 /* 1303 * irq handler when (cell-phone) cover is mounted/removed 1304 */ 1305 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1306 { 1307 struct omap_hsmmc_host *host = dev_id; 1308 1309 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1310 1311 omap_hsmmc_protect_card(host); 1312 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1313 return IRQ_HANDLED; 1314 } 1315 1316 static void omap_hsmmc_dma_callback(void *param) 1317 { 1318 struct omap_hsmmc_host *host = param; 1319 struct dma_chan *chan; 1320 struct mmc_data *data; 1321 int req_in_progress; 1322 1323 spin_lock_irq(&host->irq_lock); 1324 if (host->dma_ch < 0) { 1325 spin_unlock_irq(&host->irq_lock); 1326 return; 1327 } 1328 1329 data = host->mrq->data; 1330 chan = omap_hsmmc_get_dma_chan(host, data); 1331 if (!data->host_cookie) 1332 dma_unmap_sg(chan->device->dev, 1333 data->sg, data->sg_len, 1334 mmc_get_dma_dir(data)); 1335 1336 req_in_progress = host->req_in_progress; 1337 host->dma_ch = -1; 1338 spin_unlock_irq(&host->irq_lock); 1339 1340 /* If DMA has finished after TC, complete the request */ 1341 if (!req_in_progress) { 1342 struct mmc_request *mrq = host->mrq; 1343 1344 host->mrq = NULL; 1345 mmc_request_done(host->mmc, mrq); 1346 } 1347 } 1348 1349 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1350 struct mmc_data *data, 1351 struct omap_hsmmc_next *next, 1352 struct dma_chan *chan) 1353 { 1354 int dma_len; 1355 1356 if (!next && data->host_cookie && 1357 data->host_cookie != host->next_data.cookie) { 1358 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1359 " host->next_data.cookie %d\n", 1360 __func__, data->host_cookie, host->next_data.cookie); 1361 data->host_cookie = 0; 1362 } 1363 1364 /* Check if next job is already prepared */ 1365 if (next || data->host_cookie != host->next_data.cookie) { 1366 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1367 mmc_get_dma_dir(data)); 1368 1369 } else { 1370 dma_len = host->next_data.dma_len; 1371 host->next_data.dma_len = 0; 1372 } 1373 1374 1375 if (dma_len == 0) 1376 return -EINVAL; 1377 1378 if (next) { 1379 next->dma_len = dma_len; 1380 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1381 } else 1382 host->dma_len = dma_len; 1383 1384 return 0; 1385 } 1386 1387 /* 1388 * Routine to configure and start DMA for the MMC card 1389 */ 1390 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 1391 struct mmc_request *req) 1392 { 1393 struct dma_async_tx_descriptor *tx; 1394 int ret = 0, i; 1395 struct mmc_data *data = req->data; 1396 struct dma_chan *chan; 1397 struct dma_slave_config cfg = { 1398 .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1399 .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1400 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1401 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1402 .src_maxburst = data->blksz / 4, 1403 .dst_maxburst = data->blksz / 4, 1404 }; 1405 1406 /* Sanity check: all the SG entries must be aligned by block size. */ 1407 for (i = 0; i < data->sg_len; i++) { 1408 struct scatterlist *sgl; 1409 1410 sgl = data->sg + i; 1411 if (sgl->length % data->blksz) 1412 return -EINVAL; 1413 } 1414 if ((data->blksz % 4) != 0) 1415 /* REVISIT: The MMC buffer increments only when MSB is written. 1416 * Return error for blksz which is non multiple of four. 1417 */ 1418 return -EINVAL; 1419 1420 BUG_ON(host->dma_ch != -1); 1421 1422 chan = omap_hsmmc_get_dma_chan(host, data); 1423 1424 ret = dmaengine_slave_config(chan, &cfg); 1425 if (ret) 1426 return ret; 1427 1428 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1429 if (ret) 1430 return ret; 1431 1432 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1433 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1434 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1435 if (!tx) { 1436 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1437 /* FIXME: cleanup */ 1438 return -1; 1439 } 1440 1441 tx->callback = omap_hsmmc_dma_callback; 1442 tx->callback_param = host; 1443 1444 /* Does not fail */ 1445 dmaengine_submit(tx); 1446 1447 host->dma_ch = 1; 1448 1449 return 0; 1450 } 1451 1452 static void set_data_timeout(struct omap_hsmmc_host *host, 1453 unsigned long long timeout_ns, 1454 unsigned int timeout_clks) 1455 { 1456 unsigned long long timeout = timeout_ns; 1457 unsigned int cycle_ns; 1458 uint32_t reg, clkd, dto = 0; 1459 1460 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1461 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1462 if (clkd == 0) 1463 clkd = 1; 1464 1465 cycle_ns = 1000000000 / (host->clk_rate / clkd); 1466 do_div(timeout, cycle_ns); 1467 timeout += timeout_clks; 1468 if (timeout) { 1469 while ((timeout & 0x80000000) == 0) { 1470 dto += 1; 1471 timeout <<= 1; 1472 } 1473 dto = 31 - dto; 1474 timeout <<= 1; 1475 if (timeout && dto) 1476 dto += 1; 1477 if (dto >= 13) 1478 dto -= 13; 1479 else 1480 dto = 0; 1481 if (dto > 14) 1482 dto = 14; 1483 } 1484 1485 reg &= ~DTO_MASK; 1486 reg |= dto << DTO_SHIFT; 1487 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1488 } 1489 1490 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 1491 { 1492 struct mmc_request *req = host->mrq; 1493 struct dma_chan *chan; 1494 1495 if (!req->data) 1496 return; 1497 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1498 | (req->data->blocks << 16)); 1499 set_data_timeout(host, req->data->timeout_ns, 1500 req->data->timeout_clks); 1501 chan = omap_hsmmc_get_dma_chan(host, req->data); 1502 dma_async_issue_pending(chan); 1503 } 1504 1505 /* 1506 * Configure block length for MMC/SD cards and initiate the transfer. 1507 */ 1508 static int 1509 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1510 { 1511 int ret; 1512 unsigned long long timeout; 1513 1514 host->data = req->data; 1515 1516 if (req->data == NULL) { 1517 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1518 if (req->cmd->flags & MMC_RSP_BUSY) { 1519 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 1520 1521 /* 1522 * Set an arbitrary 100ms data timeout for commands with 1523 * busy signal and no indication of busy_timeout. 1524 */ 1525 if (!timeout) 1526 timeout = 100000000U; 1527 1528 set_data_timeout(host, timeout, 0); 1529 } 1530 return 0; 1531 } 1532 1533 if (host->use_dma) { 1534 ret = omap_hsmmc_setup_dma_transfer(host, req); 1535 if (ret != 0) { 1536 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1537 return ret; 1538 } 1539 } 1540 return 0; 1541 } 1542 1543 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1544 int err) 1545 { 1546 struct omap_hsmmc_host *host = mmc_priv(mmc); 1547 struct mmc_data *data = mrq->data; 1548 1549 if (host->use_dma && data->host_cookie) { 1550 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1551 1552 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1553 mmc_get_dma_dir(data)); 1554 data->host_cookie = 0; 1555 } 1556 } 1557 1558 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1559 { 1560 struct omap_hsmmc_host *host = mmc_priv(mmc); 1561 1562 if (mrq->data->host_cookie) { 1563 mrq->data->host_cookie = 0; 1564 return ; 1565 } 1566 1567 if (host->use_dma) { 1568 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1569 1570 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1571 &host->next_data, c)) 1572 mrq->data->host_cookie = 0; 1573 } 1574 } 1575 1576 /* 1577 * Request function. for read/write operation 1578 */ 1579 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1580 { 1581 struct omap_hsmmc_host *host = mmc_priv(mmc); 1582 int err; 1583 1584 BUG_ON(host->req_in_progress); 1585 BUG_ON(host->dma_ch != -1); 1586 if (host->protect_card) { 1587 if (host->reqs_blocked < 3) { 1588 /* 1589 * Ensure the controller is left in a consistent 1590 * state by resetting the command and data state 1591 * machines. 1592 */ 1593 omap_hsmmc_reset_controller_fsm(host, SRD); 1594 omap_hsmmc_reset_controller_fsm(host, SRC); 1595 host->reqs_blocked += 1; 1596 } 1597 req->cmd->error = -EBADF; 1598 if (req->data) 1599 req->data->error = -EBADF; 1600 req->cmd->retries = 0; 1601 mmc_request_done(mmc, req); 1602 return; 1603 } else if (host->reqs_blocked) 1604 host->reqs_blocked = 0; 1605 WARN_ON(host->mrq != NULL); 1606 host->mrq = req; 1607 host->clk_rate = clk_get_rate(host->fclk); 1608 err = omap_hsmmc_prepare_data(host, req); 1609 if (err) { 1610 req->cmd->error = err; 1611 if (req->data) 1612 req->data->error = err; 1613 host->mrq = NULL; 1614 mmc_request_done(mmc, req); 1615 return; 1616 } 1617 if (req->sbc && !(host->flags & AUTO_CMD23)) { 1618 omap_hsmmc_start_command(host, req->sbc, NULL); 1619 return; 1620 } 1621 1622 omap_hsmmc_start_dma_transfer(host); 1623 omap_hsmmc_start_command(host, req->cmd, req->data); 1624 } 1625 1626 /* Routine to configure clock values. Exposed API to core */ 1627 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1628 { 1629 struct omap_hsmmc_host *host = mmc_priv(mmc); 1630 int do_send_init_stream = 0; 1631 1632 if (ios->power_mode != host->power_mode) { 1633 switch (ios->power_mode) { 1634 case MMC_POWER_OFF: 1635 omap_hsmmc_set_power(host, 0, 0); 1636 break; 1637 case MMC_POWER_UP: 1638 omap_hsmmc_set_power(host, 1, ios->vdd); 1639 break; 1640 case MMC_POWER_ON: 1641 do_send_init_stream = 1; 1642 break; 1643 } 1644 host->power_mode = ios->power_mode; 1645 } 1646 1647 /* FIXME: set registers based only on changes to ios */ 1648 1649 omap_hsmmc_set_bus_width(host); 1650 1651 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1652 /* Only MMC1 can interface at 3V without some flavor 1653 * of external transceiver; but they all handle 1.8V. 1654 */ 1655 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1656 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1657 /* 1658 * The mmc_select_voltage fn of the core does 1659 * not seem to set the power_mode to 1660 * MMC_POWER_UP upon recalculating the voltage. 1661 * vdd 1.8v. 1662 */ 1663 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1664 dev_dbg(mmc_dev(host->mmc), 1665 "Switch operation failed\n"); 1666 } 1667 } 1668 1669 omap_hsmmc_set_clock(host); 1670 1671 if (do_send_init_stream) 1672 send_init_stream(host); 1673 1674 omap_hsmmc_set_bus_mode(host); 1675 } 1676 1677 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1678 { 1679 struct omap_hsmmc_host *host = mmc_priv(mmc); 1680 1681 if (!host->card_detect) 1682 return -ENOSYS; 1683 return host->card_detect(host->dev); 1684 } 1685 1686 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1687 { 1688 struct omap_hsmmc_host *host = mmc_priv(mmc); 1689 1690 if (mmc_pdata(host)->init_card) 1691 mmc_pdata(host)->init_card(card); 1692 } 1693 1694 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1695 { 1696 struct omap_hsmmc_host *host = mmc_priv(mmc); 1697 u32 irq_mask, con; 1698 unsigned long flags; 1699 1700 spin_lock_irqsave(&host->irq_lock, flags); 1701 1702 con = OMAP_HSMMC_READ(host->base, CON); 1703 irq_mask = OMAP_HSMMC_READ(host->base, ISE); 1704 if (enable) { 1705 host->flags |= HSMMC_SDIO_IRQ_ENABLED; 1706 irq_mask |= CIRQ_EN; 1707 con |= CTPL | CLKEXTFREE; 1708 } else { 1709 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 1710 irq_mask &= ~CIRQ_EN; 1711 con &= ~(CTPL | CLKEXTFREE); 1712 } 1713 OMAP_HSMMC_WRITE(host->base, CON, con); 1714 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 1715 1716 /* 1717 * if enable, piggy back detection on current request 1718 * but always disable immediately 1719 */ 1720 if (!host->req_in_progress || !enable) 1721 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 1722 1723 /* flush posted write */ 1724 OMAP_HSMMC_READ(host->base, IE); 1725 1726 spin_unlock_irqrestore(&host->irq_lock, flags); 1727 } 1728 1729 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 1730 { 1731 int ret; 1732 1733 /* 1734 * For omaps with wake-up path, wakeirq will be irq from pinctrl and 1735 * for other omaps, wakeirq will be from GPIO (dat line remuxed to 1736 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 1737 * with functional clock disabled. 1738 */ 1739 if (!host->dev->of_node || !host->wake_irq) 1740 return -ENODEV; 1741 1742 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 1743 if (ret) { 1744 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 1745 goto err; 1746 } 1747 1748 /* 1749 * Some omaps don't have wake-up path from deeper idle states 1750 * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 1751 */ 1752 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1753 struct pinctrl *p = devm_pinctrl_get(host->dev); 1754 if (IS_ERR(p)) { 1755 ret = PTR_ERR(p); 1756 goto err_free_irq; 1757 } 1758 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1759 dev_info(host->dev, "missing default pinctrl state\n"); 1760 devm_pinctrl_put(p); 1761 ret = -EINVAL; 1762 goto err_free_irq; 1763 } 1764 1765 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1766 dev_info(host->dev, "missing idle pinctrl state\n"); 1767 devm_pinctrl_put(p); 1768 ret = -EINVAL; 1769 goto err_free_irq; 1770 } 1771 devm_pinctrl_put(p); 1772 } 1773 1774 OMAP_HSMMC_WRITE(host->base, HCTL, 1775 OMAP_HSMMC_READ(host->base, HCTL) | IWE); 1776 return 0; 1777 1778 err_free_irq: 1779 dev_pm_clear_wake_irq(host->dev); 1780 err: 1781 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 1782 host->wake_irq = 0; 1783 return ret; 1784 } 1785 1786 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1787 { 1788 u32 hctl, capa, value; 1789 1790 /* Only MMC1 supports 3.0V */ 1791 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1792 hctl = SDVS30; 1793 capa = VS30 | VS18; 1794 } else { 1795 hctl = SDVS18; 1796 capa = VS18; 1797 } 1798 1799 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1800 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1801 1802 value = OMAP_HSMMC_READ(host->base, CAPA); 1803 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1804 1805 /* Set SD bus power bit */ 1806 set_sd_bus_power(host); 1807 } 1808 1809 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1810 unsigned int direction, int blk_size) 1811 { 1812 /* This controller can't do multiblock reads due to hw bugs */ 1813 if (direction == MMC_DATA_READ) 1814 return 1; 1815 1816 return blk_size; 1817 } 1818 1819 static struct mmc_host_ops omap_hsmmc_ops = { 1820 .post_req = omap_hsmmc_post_req, 1821 .pre_req = omap_hsmmc_pre_req, 1822 .request = omap_hsmmc_request, 1823 .set_ios = omap_hsmmc_set_ios, 1824 .get_cd = omap_hsmmc_get_cd, 1825 .get_ro = mmc_gpio_get_ro, 1826 .init_card = omap_hsmmc_init_card, 1827 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1828 }; 1829 1830 #ifdef CONFIG_DEBUG_FS 1831 1832 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1833 { 1834 struct mmc_host *mmc = s->private; 1835 struct omap_hsmmc_host *host = mmc_priv(mmc); 1836 1837 seq_printf(s, "mmc%d:\n", mmc->index); 1838 seq_printf(s, "sdio irq mode\t%s\n", 1839 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1840 1841 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1842 seq_printf(s, "sdio irq \t%s\n", 1843 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1844 : "disabled"); 1845 } 1846 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 1847 1848 pm_runtime_get_sync(host->dev); 1849 seq_puts(s, "\nregs:\n"); 1850 seq_printf(s, "CON:\t\t0x%08x\n", 1851 OMAP_HSMMC_READ(host->base, CON)); 1852 seq_printf(s, "PSTATE:\t\t0x%08x\n", 1853 OMAP_HSMMC_READ(host->base, PSTATE)); 1854 seq_printf(s, "HCTL:\t\t0x%08x\n", 1855 OMAP_HSMMC_READ(host->base, HCTL)); 1856 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1857 OMAP_HSMMC_READ(host->base, SYSCTL)); 1858 seq_printf(s, "IE:\t\t0x%08x\n", 1859 OMAP_HSMMC_READ(host->base, IE)); 1860 seq_printf(s, "ISE:\t\t0x%08x\n", 1861 OMAP_HSMMC_READ(host->base, ISE)); 1862 seq_printf(s, "CAPA:\t\t0x%08x\n", 1863 OMAP_HSMMC_READ(host->base, CAPA)); 1864 1865 pm_runtime_mark_last_busy(host->dev); 1866 pm_runtime_put_autosuspend(host->dev); 1867 1868 return 0; 1869 } 1870 1871 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1872 { 1873 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1874 } 1875 1876 static const struct file_operations mmc_regs_fops = { 1877 .open = omap_hsmmc_regs_open, 1878 .read = seq_read, 1879 .llseek = seq_lseek, 1880 .release = single_release, 1881 }; 1882 1883 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1884 { 1885 if (mmc->debugfs_root) 1886 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1887 mmc, &mmc_regs_fops); 1888 } 1889 1890 #else 1891 1892 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1893 { 1894 } 1895 1896 #endif 1897 1898 #ifdef CONFIG_OF 1899 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 1900 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1901 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1902 }; 1903 1904 static const struct omap_mmc_of_data omap4_mmc_of_data = { 1905 .reg_offset = 0x100, 1906 }; 1907 static const struct omap_mmc_of_data am33xx_mmc_of_data = { 1908 .reg_offset = 0x100, 1909 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 1910 }; 1911 1912 static const struct of_device_id omap_mmc_of_match[] = { 1913 { 1914 .compatible = "ti,omap2-hsmmc", 1915 }, 1916 { 1917 .compatible = "ti,omap3-pre-es3-hsmmc", 1918 .data = &omap3_pre_es3_mmc_of_data, 1919 }, 1920 { 1921 .compatible = "ti,omap3-hsmmc", 1922 }, 1923 { 1924 .compatible = "ti,omap4-hsmmc", 1925 .data = &omap4_mmc_of_data, 1926 }, 1927 { 1928 .compatible = "ti,am33xx-hsmmc", 1929 .data = &am33xx_mmc_of_data, 1930 }, 1931 {}, 1932 }; 1933 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1934 1935 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1936 { 1937 struct omap_hsmmc_platform_data *pdata, *legacy; 1938 struct device_node *np = dev->of_node; 1939 1940 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1941 if (!pdata) 1942 return ERR_PTR(-ENOMEM); /* out of memory */ 1943 1944 legacy = dev_get_platdata(dev); 1945 if (legacy && legacy->name) 1946 pdata->name = legacy->name; 1947 1948 if (of_find_property(np, "ti,dual-volt", NULL)) 1949 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1950 1951 pdata->gpio_cd = -EINVAL; 1952 pdata->gpio_cod = -EINVAL; 1953 pdata->gpio_wp = -EINVAL; 1954 1955 if (of_find_property(np, "ti,non-removable", NULL)) { 1956 pdata->nonremovable = true; 1957 pdata->no_regulator_off_init = true; 1958 } 1959 1960 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1961 pdata->features |= HSMMC_HAS_UPDATED_RESET; 1962 1963 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1964 pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1965 1966 return pdata; 1967 } 1968 #else 1969 static inline struct omap_hsmmc_platform_data 1970 *of_get_hsmmc_pdata(struct device *dev) 1971 { 1972 return ERR_PTR(-EINVAL); 1973 } 1974 #endif 1975 1976 static int omap_hsmmc_probe(struct platform_device *pdev) 1977 { 1978 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1979 struct mmc_host *mmc; 1980 struct omap_hsmmc_host *host = NULL; 1981 struct resource *res; 1982 int ret, irq; 1983 const struct of_device_id *match; 1984 const struct omap_mmc_of_data *data; 1985 void __iomem *base; 1986 1987 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1988 if (match) { 1989 pdata = of_get_hsmmc_pdata(&pdev->dev); 1990 1991 if (IS_ERR(pdata)) 1992 return PTR_ERR(pdata); 1993 1994 if (match->data) { 1995 data = match->data; 1996 pdata->reg_offset = data->reg_offset; 1997 pdata->controller_flags |= data->controller_flags; 1998 } 1999 } 2000 2001 if (pdata == NULL) { 2002 dev_err(&pdev->dev, "Platform Data is missing\n"); 2003 return -ENXIO; 2004 } 2005 2006 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2007 irq = platform_get_irq(pdev, 0); 2008 if (res == NULL || irq < 0) 2009 return -ENXIO; 2010 2011 base = devm_ioremap_resource(&pdev->dev, res); 2012 if (IS_ERR(base)) 2013 return PTR_ERR(base); 2014 2015 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2016 if (!mmc) { 2017 ret = -ENOMEM; 2018 goto err; 2019 } 2020 2021 ret = mmc_of_parse(mmc); 2022 if (ret) 2023 goto err1; 2024 2025 host = mmc_priv(mmc); 2026 host->mmc = mmc; 2027 host->pdata = pdata; 2028 host->dev = &pdev->dev; 2029 host->use_dma = 1; 2030 host->dma_ch = -1; 2031 host->irq = irq; 2032 host->mapbase = res->start + pdata->reg_offset; 2033 host->base = base + pdata->reg_offset; 2034 host->power_mode = MMC_POWER_OFF; 2035 host->next_data.cookie = 1; 2036 host->pbias_enabled = 0; 2037 host->vqmmc_enabled = 0; 2038 2039 ret = omap_hsmmc_gpio_init(mmc, host, pdata); 2040 if (ret) 2041 goto err_gpio; 2042 2043 platform_set_drvdata(pdev, host); 2044 2045 if (pdev->dev.of_node) 2046 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 2047 2048 mmc->ops = &omap_hsmmc_ops; 2049 2050 mmc->f_min = OMAP_MMC_MIN_CLOCK; 2051 2052 if (pdata->max_freq > 0) 2053 mmc->f_max = pdata->max_freq; 2054 else if (mmc->f_max == 0) 2055 mmc->f_max = OMAP_MMC_MAX_CLOCK; 2056 2057 spin_lock_init(&host->irq_lock); 2058 2059 host->fclk = devm_clk_get(&pdev->dev, "fck"); 2060 if (IS_ERR(host->fclk)) { 2061 ret = PTR_ERR(host->fclk); 2062 host->fclk = NULL; 2063 goto err1; 2064 } 2065 2066 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 2067 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2068 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 2069 } 2070 2071 device_init_wakeup(&pdev->dev, true); 2072 pm_runtime_enable(host->dev); 2073 pm_runtime_get_sync(host->dev); 2074 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2075 pm_runtime_use_autosuspend(host->dev); 2076 2077 omap_hsmmc_context_save(host); 2078 2079 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2080 /* 2081 * MMC can still work without debounce clock. 2082 */ 2083 if (IS_ERR(host->dbclk)) { 2084 host->dbclk = NULL; 2085 } else if (clk_prepare_enable(host->dbclk) != 0) { 2086 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2087 host->dbclk = NULL; 2088 } 2089 2090 /* Since we do only SG emulation, we can have as many segs 2091 * as we want. */ 2092 mmc->max_segs = 1024; 2093 2094 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2095 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2096 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2097 mmc->max_seg_size = mmc->max_req_size; 2098 2099 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2100 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2101 2102 mmc->caps |= mmc_pdata(host)->caps; 2103 if (mmc->caps & MMC_CAP_8_BIT_DATA) 2104 mmc->caps |= MMC_CAP_4_BIT_DATA; 2105 2106 if (mmc_pdata(host)->nonremovable) 2107 mmc->caps |= MMC_CAP_NONREMOVABLE; 2108 2109 mmc->pm_caps |= mmc_pdata(host)->pm_caps; 2110 2111 omap_hsmmc_conf_bus_power(host); 2112 2113 host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 2114 if (IS_ERR(host->rx_chan)) { 2115 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 2116 ret = PTR_ERR(host->rx_chan); 2117 goto err_irq; 2118 } 2119 2120 host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 2121 if (IS_ERR(host->tx_chan)) { 2122 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 2123 ret = PTR_ERR(host->tx_chan); 2124 goto err_irq; 2125 } 2126 2127 /* Request IRQ for MMC operations */ 2128 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2129 mmc_hostname(mmc), host); 2130 if (ret) { 2131 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2132 goto err_irq; 2133 } 2134 2135 ret = omap_hsmmc_reg_get(host); 2136 if (ret) 2137 goto err_irq; 2138 2139 if (!mmc->ocr_avail) 2140 mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2141 2142 omap_hsmmc_disable_irq(host); 2143 2144 /* 2145 * For now, only support SDIO interrupt if we have a separate 2146 * wake-up interrupt configured from device tree. This is because 2147 * the wake-up interrupt is needed for idle state and some 2148 * platforms need special quirks. And we don't want to add new 2149 * legacy mux platform init code callbacks any longer as we 2150 * are moving to DT based booting anyways. 2151 */ 2152 ret = omap_hsmmc_configure_wake_irq(host); 2153 if (!ret) 2154 mmc->caps |= MMC_CAP_SDIO_IRQ; 2155 2156 omap_hsmmc_protect_card(host); 2157 2158 mmc_add_host(mmc); 2159 2160 if (mmc_pdata(host)->name != NULL) { 2161 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2162 if (ret < 0) 2163 goto err_slot_name; 2164 } 2165 if (host->get_cover_state) { 2166 ret = device_create_file(&mmc->class_dev, 2167 &dev_attr_cover_switch); 2168 if (ret < 0) 2169 goto err_slot_name; 2170 } 2171 2172 omap_hsmmc_debugfs(mmc); 2173 pm_runtime_mark_last_busy(host->dev); 2174 pm_runtime_put_autosuspend(host->dev); 2175 2176 return 0; 2177 2178 err_slot_name: 2179 mmc_remove_host(mmc); 2180 err_irq: 2181 device_init_wakeup(&pdev->dev, false); 2182 if (!IS_ERR_OR_NULL(host->tx_chan)) 2183 dma_release_channel(host->tx_chan); 2184 if (!IS_ERR_OR_NULL(host->rx_chan)) 2185 dma_release_channel(host->rx_chan); 2186 pm_runtime_dont_use_autosuspend(host->dev); 2187 pm_runtime_put_sync(host->dev); 2188 pm_runtime_disable(host->dev); 2189 if (host->dbclk) 2190 clk_disable_unprepare(host->dbclk); 2191 err1: 2192 err_gpio: 2193 mmc_free_host(mmc); 2194 err: 2195 return ret; 2196 } 2197 2198 static int omap_hsmmc_remove(struct platform_device *pdev) 2199 { 2200 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2201 2202 pm_runtime_get_sync(host->dev); 2203 mmc_remove_host(host->mmc); 2204 2205 dma_release_channel(host->tx_chan); 2206 dma_release_channel(host->rx_chan); 2207 2208 pm_runtime_dont_use_autosuspend(host->dev); 2209 pm_runtime_put_sync(host->dev); 2210 pm_runtime_disable(host->dev); 2211 device_init_wakeup(&pdev->dev, false); 2212 if (host->dbclk) 2213 clk_disable_unprepare(host->dbclk); 2214 2215 mmc_free_host(host->mmc); 2216 2217 return 0; 2218 } 2219 2220 #ifdef CONFIG_PM_SLEEP 2221 static int omap_hsmmc_suspend(struct device *dev) 2222 { 2223 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2224 2225 if (!host) 2226 return 0; 2227 2228 pm_runtime_get_sync(host->dev); 2229 2230 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2231 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2232 OMAP_HSMMC_WRITE(host->base, IE, 0); 2233 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2234 OMAP_HSMMC_WRITE(host->base, HCTL, 2235 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2236 } 2237 2238 if (host->dbclk) 2239 clk_disable_unprepare(host->dbclk); 2240 2241 pm_runtime_put_sync(host->dev); 2242 return 0; 2243 } 2244 2245 /* Routine to resume the MMC device */ 2246 static int omap_hsmmc_resume(struct device *dev) 2247 { 2248 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2249 2250 if (!host) 2251 return 0; 2252 2253 pm_runtime_get_sync(host->dev); 2254 2255 if (host->dbclk) 2256 clk_prepare_enable(host->dbclk); 2257 2258 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2259 omap_hsmmc_conf_bus_power(host); 2260 2261 omap_hsmmc_protect_card(host); 2262 pm_runtime_mark_last_busy(host->dev); 2263 pm_runtime_put_autosuspend(host->dev); 2264 return 0; 2265 } 2266 #endif 2267 2268 static int omap_hsmmc_runtime_suspend(struct device *dev) 2269 { 2270 struct omap_hsmmc_host *host; 2271 unsigned long flags; 2272 int ret = 0; 2273 2274 host = platform_get_drvdata(to_platform_device(dev)); 2275 omap_hsmmc_context_save(host); 2276 dev_dbg(dev, "disabled\n"); 2277 2278 spin_lock_irqsave(&host->irq_lock, flags); 2279 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2280 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2281 /* disable sdio irq handling to prevent race */ 2282 OMAP_HSMMC_WRITE(host->base, ISE, 0); 2283 OMAP_HSMMC_WRITE(host->base, IE, 0); 2284 2285 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2286 /* 2287 * dat1 line low, pending sdio irq 2288 * race condition: possible irq handler running on 2289 * multi-core, abort 2290 */ 2291 dev_dbg(dev, "pending sdio irq, abort suspend\n"); 2292 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2293 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2294 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2295 pm_runtime_mark_last_busy(dev); 2296 ret = -EBUSY; 2297 goto abort; 2298 } 2299 2300 pinctrl_pm_select_idle_state(dev); 2301 } else { 2302 pinctrl_pm_select_idle_state(dev); 2303 } 2304 2305 abort: 2306 spin_unlock_irqrestore(&host->irq_lock, flags); 2307 return ret; 2308 } 2309 2310 static int omap_hsmmc_runtime_resume(struct device *dev) 2311 { 2312 struct omap_hsmmc_host *host; 2313 unsigned long flags; 2314 2315 host = platform_get_drvdata(to_platform_device(dev)); 2316 omap_hsmmc_context_restore(host); 2317 dev_dbg(dev, "enabled\n"); 2318 2319 spin_lock_irqsave(&host->irq_lock, flags); 2320 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 2321 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 2322 2323 pinctrl_pm_select_default_state(host->dev); 2324 2325 /* irq lost, if pinmux incorrect */ 2326 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2327 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2328 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2329 } else { 2330 pinctrl_pm_select_default_state(host->dev); 2331 } 2332 spin_unlock_irqrestore(&host->irq_lock, flags); 2333 return 0; 2334 } 2335 2336 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2337 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2338 .runtime_suspend = omap_hsmmc_runtime_suspend, 2339 .runtime_resume = omap_hsmmc_runtime_resume, 2340 }; 2341 2342 static struct platform_driver omap_hsmmc_driver = { 2343 .probe = omap_hsmmc_probe, 2344 .remove = omap_hsmmc_remove, 2345 .driver = { 2346 .name = DRIVER_NAME, 2347 .pm = &omap_hsmmc_dev_pm_ops, 2348 .of_match_table = of_match_ptr(omap_mmc_of_match), 2349 }, 2350 }; 2351 2352 module_platform_driver(omap_hsmmc_driver); 2353 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2354 MODULE_LICENSE("GPL"); 2355 MODULE_ALIAS("platform:" DRIVER_NAME); 2356 MODULE_AUTHOR("Texas Instruments Inc"); 2357