1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 3246856a68SRajendra Nayak #include <linux/of_gpio.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 343451c067SRussell King #include <linux/omap-dma.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 39db0fefc5SAdrian Hunter #include <linux/gpio.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4368f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 44a45c6cb8SMadhusudhan Chikkature 45a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65cd587096SHebbar, Gururaja #define HSS (1 << 21) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 79a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 80a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 81a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 82a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 83a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 84a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 85a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 86a7e96879SVenkatraman S #define DMAE 0x1 87a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 88a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 89a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 90cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9103b5d924SBalaji T K #define DDR (1 << 19) 9273153010SJarkko Lavinen #define DW8 (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define OD 0x1 94a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 95a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 96a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 97a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 98a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10011dd62a7SDenis Karpov #define RESETDONE (1 << 0) 101a45c6cb8SMadhusudhan Chikkature 102a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 103a7e96879SVenkatraman S #define CC_EN (1 << 0) 104a7e96879SVenkatraman S #define TC_EN (1 << 1) 105a7e96879SVenkatraman S #define BWR_EN (1 << 4) 106a7e96879SVenkatraman S #define BRR_EN (1 << 5) 107a7e96879SVenkatraman S #define ERR_EN (1 << 15) 108a7e96879SVenkatraman S #define CTO_EN (1 << 16) 109a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 110a7e96879SVenkatraman S #define CEB_EN (1 << 18) 111a7e96879SVenkatraman S #define CIE_EN (1 << 19) 112a7e96879SVenkatraman S #define DTO_EN (1 << 20) 113a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 114a7e96879SVenkatraman S #define DEB_EN (1 << 22) 115a7e96879SVenkatraman S #define CERR_EN (1 << 28) 116a7e96879SVenkatraman S #define BADA_EN (1 << 29) 117a7e96879SVenkatraman S 118a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 119a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 120a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 121a7e96879SVenkatraman S 122fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1231e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1241e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1256b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1266b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1270005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 128a45c6cb8SMadhusudhan Chikkature 129a45c6cb8SMadhusudhan Chikkature /* 130a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 131a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 132a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 133a45c6cb8SMadhusudhan Chikkature */ 134a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 135a45c6cb8SMadhusudhan Chikkature 136a45c6cb8SMadhusudhan Chikkature /* 137a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 138a45c6cb8SMadhusudhan Chikkature */ 139a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 140a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 141a45c6cb8SMadhusudhan Chikkature 142a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 143a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 144a45c6cb8SMadhusudhan Chikkature 1459782aff8SPer Forlin struct omap_hsmmc_next { 1469782aff8SPer Forlin unsigned int dma_len; 1479782aff8SPer Forlin s32 cookie; 1489782aff8SPer Forlin }; 1499782aff8SPer Forlin 15070a3341aSDenis Karpov struct omap_hsmmc_host { 151a45c6cb8SMadhusudhan Chikkature struct device *dev; 152a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 153a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 154a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 155a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 156a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 157a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 158db0fefc5SAdrian Hunter /* 159db0fefc5SAdrian Hunter * vcc == configured supply 160db0fefc5SAdrian Hunter * vcc_aux == optional 161db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 162db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 163db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 164db0fefc5SAdrian Hunter */ 165db0fefc5SAdrian Hunter struct regulator *vcc; 166db0fefc5SAdrian Hunter struct regulator *vcc_aux; 167cf5ae40bSTony Lindgren int pbias_disable; 168a45c6cb8SMadhusudhan Chikkature void __iomem *base; 169a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1704dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 171a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1720ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 173a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 174a3621465SAdrian Hunter unsigned char power_mode; 175a45c6cb8SMadhusudhan Chikkature int suspended; 1760a82e06eSTony Lindgren u32 con; 1770a82e06eSTony Lindgren u32 hctl; 1780a82e06eSTony Lindgren u32 sysctl; 1790a82e06eSTony Lindgren u32 capa; 180a45c6cb8SMadhusudhan Chikkature int irq; 181a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 182c5c98927SRussell King struct dma_chan *tx_chan; 183c5c98927SRussell King struct dma_chan *rx_chan; 184a45c6cb8SMadhusudhan Chikkature int slot_id; 1854a694dc9SAdrian Hunter int response_busy; 18611dd62a7SDenis Karpov int context_loss; 187b62f6228SAdrian Hunter int protect_card; 188b62f6228SAdrian Hunter int reqs_blocked; 189db0fefc5SAdrian Hunter int use_reg; 190b417577dSAdrian Hunter int req_in_progress; 1919782aff8SPer Forlin struct omap_hsmmc_next next_data; 192a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 193a45c6cb8SMadhusudhan Chikkature }; 194a45c6cb8SMadhusudhan Chikkature 195db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 196db0fefc5SAdrian Hunter { 1979ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 1989ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 199db0fefc5SAdrian Hunter 200db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 201db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 202db0fefc5SAdrian Hunter } 203db0fefc5SAdrian Hunter 204db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 205db0fefc5SAdrian Hunter { 2069ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2079ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 208db0fefc5SAdrian Hunter 209db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 210db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 211db0fefc5SAdrian Hunter } 212db0fefc5SAdrian Hunter 213db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 214db0fefc5SAdrian Hunter { 2159ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2169ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 217db0fefc5SAdrian Hunter 218db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 219db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 220db0fefc5SAdrian Hunter } 221db0fefc5SAdrian Hunter 222db0fefc5SAdrian Hunter #ifdef CONFIG_PM 223db0fefc5SAdrian Hunter 224db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 225db0fefc5SAdrian Hunter { 2269ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2279ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 228db0fefc5SAdrian Hunter 229db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 230db0fefc5SAdrian Hunter return 0; 231db0fefc5SAdrian Hunter } 232db0fefc5SAdrian Hunter 233db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2369ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 237db0fefc5SAdrian Hunter 238db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 239db0fefc5SAdrian Hunter return 0; 240db0fefc5SAdrian Hunter } 241db0fefc5SAdrian Hunter 242db0fefc5SAdrian Hunter #else 243db0fefc5SAdrian Hunter 244db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 245db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 246db0fefc5SAdrian Hunter 247db0fefc5SAdrian Hunter #endif 248db0fefc5SAdrian Hunter 249b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 250b702b106SAdrian Hunter 25169b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 252db0fefc5SAdrian Hunter int vdd) 253db0fefc5SAdrian Hunter { 254db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 255db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 256db0fefc5SAdrian Hunter int ret = 0; 257db0fefc5SAdrian Hunter 258db0fefc5SAdrian Hunter /* 259db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 260db0fefc5SAdrian Hunter * voltage always-on regulator. 261db0fefc5SAdrian Hunter */ 262db0fefc5SAdrian Hunter if (!host->vcc) 263db0fefc5SAdrian Hunter return 0; 2641f84b71bSRajendra Nayak /* 265cf5ae40bSTony Lindgren * With DT, never turn OFF the regulator for MMC1. This is because 2661f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2671f84b71bSRajendra Nayak * booting with Device tree 2681f84b71bSRajendra Nayak */ 269cf5ae40bSTony Lindgren if (host->pbias_disable && !vdd) 2701f84b71bSRajendra Nayak return 0; 271db0fefc5SAdrian Hunter 272db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 273db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 274db0fefc5SAdrian Hunter 275db0fefc5SAdrian Hunter /* 276db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 277db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 278db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 279db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 280db0fefc5SAdrian Hunter * 281db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 282db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 283db0fefc5SAdrian Hunter * 284db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 285db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 286db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 287db0fefc5SAdrian Hunter */ 288db0fefc5SAdrian Hunter if (power_on) { 28999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 290db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 291db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 292db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 293db0fefc5SAdrian Hunter if (ret < 0) 29499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 29599fc5131SLinus Walleij host->vcc, 0); 296db0fefc5SAdrian Hunter } 297db0fefc5SAdrian Hunter } else { 29899fc5131SLinus Walleij /* Shut down the rail */ 2996da20c89SAdrian Hunter if (host->vcc_aux) 300db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 30199fc5131SLinus Walleij if (!ret) { 30299fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 30399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30499fc5131SLinus Walleij host->vcc, 0); 30599fc5131SLinus Walleij } 306db0fefc5SAdrian Hunter } 307db0fefc5SAdrian Hunter 308db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 309db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 310db0fefc5SAdrian Hunter 311db0fefc5SAdrian Hunter return ret; 312db0fefc5SAdrian Hunter } 313db0fefc5SAdrian Hunter 314db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 315db0fefc5SAdrian Hunter { 316db0fefc5SAdrian Hunter struct regulator *reg; 31764be9782Skishore kadiyala int ocr_value = 0; 318db0fefc5SAdrian Hunter 319db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 320db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 321b1e056aeSVenkatraman S dev_err(host->dev, "vmmc regulator missing\n"); 3221fdc90fbSNeilBrown return PTR_ERR(reg); 323db0fefc5SAdrian Hunter } else { 3241fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 325db0fefc5SAdrian Hunter host->vcc = reg; 32664be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 32764be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 32864be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 32964be9782Skishore kadiyala } else { 33064be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3312cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 332e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 33364be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 33464be9782Skishore kadiyala return -EINVAL; 33564be9782Skishore kadiyala } 33664be9782Skishore kadiyala } 337db0fefc5SAdrian Hunter 338db0fefc5SAdrian Hunter /* Allow an aux regulator */ 339db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 340db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 341db0fefc5SAdrian Hunter 342b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 343b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 344b1c1df7aSBalaji T K return 0; 345db0fefc5SAdrian Hunter /* 346db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 347db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 348db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 349db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 350db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 351db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 352db0fefc5SAdrian Hunter */ 353e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 354e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 355e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 356e840ce13SAdrian Hunter 357e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 358e840ce13SAdrian Hunter 1, vdd); 359e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 360e840ce13SAdrian Hunter 0, 0); 361db0fefc5SAdrian Hunter } 362db0fefc5SAdrian Hunter } 363db0fefc5SAdrian Hunter 364db0fefc5SAdrian Hunter return 0; 365db0fefc5SAdrian Hunter } 366db0fefc5SAdrian Hunter 367db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 368db0fefc5SAdrian Hunter { 369db0fefc5SAdrian Hunter regulator_put(host->vcc); 370db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 371db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 372db0fefc5SAdrian Hunter } 373db0fefc5SAdrian Hunter 374b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 375b702b106SAdrian Hunter { 376b702b106SAdrian Hunter return 1; 377b702b106SAdrian Hunter } 378b702b106SAdrian Hunter 379b702b106SAdrian Hunter #else 380b702b106SAdrian Hunter 381b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 382b702b106SAdrian Hunter { 383b702b106SAdrian Hunter return -EINVAL; 384b702b106SAdrian Hunter } 385b702b106SAdrian Hunter 386b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 387b702b106SAdrian Hunter { 388b702b106SAdrian Hunter } 389b702b106SAdrian Hunter 390b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 391b702b106SAdrian Hunter { 392b702b106SAdrian Hunter return 0; 393b702b106SAdrian Hunter } 394b702b106SAdrian Hunter 395b702b106SAdrian Hunter #endif 396b702b106SAdrian Hunter 397b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 398b702b106SAdrian Hunter { 399b702b106SAdrian Hunter int ret; 400b702b106SAdrian Hunter 401b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 402b702b106SAdrian Hunter if (pdata->slots[0].cover) 403b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 404b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 405b702b106SAdrian Hunter else 406b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 407b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 408b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 409b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 410b702b106SAdrian Hunter if (ret) 411b702b106SAdrian Hunter return ret; 412b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 413b702b106SAdrian Hunter if (ret) 414b702b106SAdrian Hunter goto err_free_sp; 415b702b106SAdrian Hunter } else 416b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 417b702b106SAdrian Hunter 418b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 419b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 420b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 421b702b106SAdrian Hunter if (ret) 422b702b106SAdrian Hunter goto err_free_cd; 423b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 424b702b106SAdrian Hunter if (ret) 425b702b106SAdrian Hunter goto err_free_wp; 426b702b106SAdrian Hunter } else 427b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 428b702b106SAdrian Hunter 429b702b106SAdrian Hunter return 0; 430b702b106SAdrian Hunter 431b702b106SAdrian Hunter err_free_wp: 432b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 433b702b106SAdrian Hunter err_free_cd: 434b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 435b702b106SAdrian Hunter err_free_sp: 436b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 437b702b106SAdrian Hunter return ret; 438b702b106SAdrian Hunter } 439b702b106SAdrian Hunter 440b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 441b702b106SAdrian Hunter { 442b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 443b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 444b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 445b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 446b702b106SAdrian Hunter } 447b702b106SAdrian Hunter 448a45c6cb8SMadhusudhan Chikkature /* 449e0c7f99bSAndy Shevchenko * Start clock to the card 450e0c7f99bSAndy Shevchenko */ 451e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 452e0c7f99bSAndy Shevchenko { 453e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 454e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 455e0c7f99bSAndy Shevchenko } 456e0c7f99bSAndy Shevchenko 457e0c7f99bSAndy Shevchenko /* 458a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 459a45c6cb8SMadhusudhan Chikkature */ 46070a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 461a45c6cb8SMadhusudhan Chikkature { 462a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 463a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 464a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4657122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 466a45c6cb8SMadhusudhan Chikkature } 467a45c6cb8SMadhusudhan Chikkature 46893caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 46993caf8e6SAdrian Hunter struct mmc_command *cmd) 470b417577dSAdrian Hunter { 471b417577dSAdrian Hunter unsigned int irq_mask; 472b417577dSAdrian Hunter 473b417577dSAdrian Hunter if (host->use_dma) 474a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 475b417577dSAdrian Hunter else 476b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 477b417577dSAdrian Hunter 47893caf8e6SAdrian Hunter /* Disable timeout for erases */ 47993caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 480a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 48193caf8e6SAdrian Hunter 482b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 483b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 484b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 485b417577dSAdrian Hunter } 486b417577dSAdrian Hunter 487b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 488b417577dSAdrian Hunter { 489b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 490b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 491b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 492b417577dSAdrian Hunter } 493b417577dSAdrian Hunter 494ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 495d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 496ac330f44SAndy Shevchenko { 497ac330f44SAndy Shevchenko u16 dsor = 0; 498ac330f44SAndy Shevchenko 499ac330f44SAndy Shevchenko if (ios->clock) { 500d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 501ed164182SBalaji T K if (dsor > CLKD_MAX) 502ed164182SBalaji T K dsor = CLKD_MAX; 503ac330f44SAndy Shevchenko } 504ac330f44SAndy Shevchenko 505ac330f44SAndy Shevchenko return dsor; 506ac330f44SAndy Shevchenko } 507ac330f44SAndy Shevchenko 5085934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5095934df2fSAndy Shevchenko { 5105934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5115934df2fSAndy Shevchenko unsigned long regval; 5125934df2fSAndy Shevchenko unsigned long timeout; 513cd587096SHebbar, Gururaja unsigned long clkdiv; 5145934df2fSAndy Shevchenko 5158986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5165934df2fSAndy Shevchenko 5175934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5185934df2fSAndy Shevchenko 5195934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5205934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 521cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 522cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5235934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5245934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5255934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5265934df2fSAndy Shevchenko 5275934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5285934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5295934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5305934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5315934df2fSAndy Shevchenko cpu_relax(); 5325934df2fSAndy Shevchenko 533cd587096SHebbar, Gururaja /* 534cd587096SHebbar, Gururaja * Enable High-Speed Support 535cd587096SHebbar, Gururaja * Pre-Requisites 536cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 537cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 538cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 539cd587096SHebbar, Gururaja * in capabilities register 540cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 541cd587096SHebbar, Gururaja */ 542cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 543cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 544cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 545cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 546cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 547cd587096SHebbar, Gururaja regval |= HSPE; 548cd587096SHebbar, Gururaja else 549cd587096SHebbar, Gururaja regval &= ~HSPE; 550cd587096SHebbar, Gururaja 551cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 552cd587096SHebbar, Gururaja } 553cd587096SHebbar, Gururaja 5545934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5555934df2fSAndy Shevchenko } 5565934df2fSAndy Shevchenko 5573796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5583796fb8aSAndy Shevchenko { 5593796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5603796fb8aSAndy Shevchenko u32 con; 5613796fb8aSAndy Shevchenko 5623796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 56303b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 56403b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 56503b5d924SBalaji T K else 56603b5d924SBalaji T K con &= ~DDR; 5673796fb8aSAndy Shevchenko switch (ios->bus_width) { 5683796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5693796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5703796fb8aSAndy Shevchenko break; 5713796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5723796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5733796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5743796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5753796fb8aSAndy Shevchenko break; 5763796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5773796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5783796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5793796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5803796fb8aSAndy Shevchenko break; 5813796fb8aSAndy Shevchenko } 5823796fb8aSAndy Shevchenko } 5833796fb8aSAndy Shevchenko 5843796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5853796fb8aSAndy Shevchenko { 5863796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5873796fb8aSAndy Shevchenko u32 con; 5883796fb8aSAndy Shevchenko 5893796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5903796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5913796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5923796fb8aSAndy Shevchenko else 5933796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5943796fb8aSAndy Shevchenko } 5953796fb8aSAndy Shevchenko 59611dd62a7SDenis Karpov #ifdef CONFIG_PM 59711dd62a7SDenis Karpov 59811dd62a7SDenis Karpov /* 59911dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 60011dd62a7SDenis Karpov * power state change. 60111dd62a7SDenis Karpov */ 60270a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 60311dd62a7SDenis Karpov { 60411dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6053796fb8aSAndy Shevchenko u32 hctl, capa; 60611dd62a7SDenis Karpov unsigned long timeout; 60711dd62a7SDenis Karpov 6086c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 6096c31b215SVenkatraman S return 1; 61011dd62a7SDenis Karpov 6110a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6120a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6130a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6140a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6150a82e06eSTony Lindgren return 0; 6160a82e06eSTony Lindgren 6170a82e06eSTony Lindgren host->context_loss++; 6180a82e06eSTony Lindgren 619c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 62011dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 62111dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 62211dd62a7SDenis Karpov hctl = SDVS18; 62311dd62a7SDenis Karpov else 62411dd62a7SDenis Karpov hctl = SDVS30; 62511dd62a7SDenis Karpov capa = VS30 | VS18; 62611dd62a7SDenis Karpov } else { 62711dd62a7SDenis Karpov hctl = SDVS18; 62811dd62a7SDenis Karpov capa = VS18; 62911dd62a7SDenis Karpov } 63011dd62a7SDenis Karpov 63111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 63311dd62a7SDenis Karpov 63411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 63511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 63611dd62a7SDenis Karpov 63711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 63911dd62a7SDenis Karpov 64011dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 64111dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 64211dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64311dd62a7SDenis Karpov ; 64411dd62a7SDenis Karpov 645b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 64611dd62a7SDenis Karpov 64711dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 64811dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 64911dd62a7SDenis Karpov goto out; 65011dd62a7SDenis Karpov 6513796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 65211dd62a7SDenis Karpov 6535934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 65411dd62a7SDenis Karpov 6553796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6563796fb8aSAndy Shevchenko 65711dd62a7SDenis Karpov out: 6580a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6590a82e06eSTony Lindgren host->context_loss); 66011dd62a7SDenis Karpov return 0; 66111dd62a7SDenis Karpov } 66211dd62a7SDenis Karpov 66311dd62a7SDenis Karpov /* 66411dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 66511dd62a7SDenis Karpov */ 66670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 66711dd62a7SDenis Karpov { 6680a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6690a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6700a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6710a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 67211dd62a7SDenis Karpov } 67311dd62a7SDenis Karpov 67411dd62a7SDenis Karpov #else 67511dd62a7SDenis Karpov 67670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 67711dd62a7SDenis Karpov { 67811dd62a7SDenis Karpov return 0; 67911dd62a7SDenis Karpov } 68011dd62a7SDenis Karpov 68170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 68211dd62a7SDenis Karpov { 68311dd62a7SDenis Karpov } 68411dd62a7SDenis Karpov 68511dd62a7SDenis Karpov #endif 68611dd62a7SDenis Karpov 687a45c6cb8SMadhusudhan Chikkature /* 688a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 689a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 690a45c6cb8SMadhusudhan Chikkature */ 69170a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 692a45c6cb8SMadhusudhan Chikkature { 693a45c6cb8SMadhusudhan Chikkature int reg = 0; 694a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 695a45c6cb8SMadhusudhan Chikkature 696b62f6228SAdrian Hunter if (host->protect_card) 697b62f6228SAdrian Hunter return; 698b62f6228SAdrian Hunter 699a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 700b417577dSAdrian Hunter 701b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 702a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 703a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 704a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 705a45c6cb8SMadhusudhan Chikkature 706a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 707a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 708a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 709a45c6cb8SMadhusudhan Chikkature 710a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 711a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 712c653a6d4SAdrian Hunter 713c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 714c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 715c653a6d4SAdrian Hunter 716a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 717a45c6cb8SMadhusudhan Chikkature } 718a45c6cb8SMadhusudhan Chikkature 719a45c6cb8SMadhusudhan Chikkature static inline 72070a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 721a45c6cb8SMadhusudhan Chikkature { 722a45c6cb8SMadhusudhan Chikkature int r = 1; 723a45c6cb8SMadhusudhan Chikkature 724191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 725191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 726a45c6cb8SMadhusudhan Chikkature return r; 727a45c6cb8SMadhusudhan Chikkature } 728a45c6cb8SMadhusudhan Chikkature 729a45c6cb8SMadhusudhan Chikkature static ssize_t 73070a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 731a45c6cb8SMadhusudhan Chikkature char *buf) 732a45c6cb8SMadhusudhan Chikkature { 733a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 73470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 735a45c6cb8SMadhusudhan Chikkature 73670a3341aSDenis Karpov return sprintf(buf, "%s\n", 73770a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 738a45c6cb8SMadhusudhan Chikkature } 739a45c6cb8SMadhusudhan Chikkature 74070a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 741a45c6cb8SMadhusudhan Chikkature 742a45c6cb8SMadhusudhan Chikkature static ssize_t 74370a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 744a45c6cb8SMadhusudhan Chikkature char *buf) 745a45c6cb8SMadhusudhan Chikkature { 746a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 74770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 748a45c6cb8SMadhusudhan Chikkature 749191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 750a45c6cb8SMadhusudhan Chikkature } 751a45c6cb8SMadhusudhan Chikkature 75270a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 753a45c6cb8SMadhusudhan Chikkature 754a45c6cb8SMadhusudhan Chikkature /* 755a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 756a45c6cb8SMadhusudhan Chikkature */ 757a45c6cb8SMadhusudhan Chikkature static void 75870a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 759a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 760a45c6cb8SMadhusudhan Chikkature { 761a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 762a45c6cb8SMadhusudhan Chikkature 7638986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 764a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 765a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 766a45c6cb8SMadhusudhan Chikkature 76793caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 768a45c6cb8SMadhusudhan Chikkature 7694a694dc9SAdrian Hunter host->response_busy = 0; 770a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 771a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 772a45c6cb8SMadhusudhan Chikkature resptype = 1; 7734a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7744a694dc9SAdrian Hunter resptype = 3; 7754a694dc9SAdrian Hunter host->response_busy = 1; 7764a694dc9SAdrian Hunter } else 777a45c6cb8SMadhusudhan Chikkature resptype = 2; 778a45c6cb8SMadhusudhan Chikkature } 779a45c6cb8SMadhusudhan Chikkature 780a45c6cb8SMadhusudhan Chikkature /* 781a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 782a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 783a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 784a45c6cb8SMadhusudhan Chikkature */ 785a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 786a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 787a45c6cb8SMadhusudhan Chikkature 788a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 789a45c6cb8SMadhusudhan Chikkature 790a45c6cb8SMadhusudhan Chikkature if (data) { 791a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 792a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 793a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 794a45c6cb8SMadhusudhan Chikkature else 795a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 796a45c6cb8SMadhusudhan Chikkature } 797a45c6cb8SMadhusudhan Chikkature 798a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 799a7e96879SVenkatraman S cmdreg |= DMAE; 800a45c6cb8SMadhusudhan Chikkature 801b417577dSAdrian Hunter host->req_in_progress = 1; 8024dffd7a2SAdrian Hunter 803a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 804a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 805a45c6cb8SMadhusudhan Chikkature } 806a45c6cb8SMadhusudhan Chikkature 8070ccd76d4SJuha Yrjola static int 80870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8090ccd76d4SJuha Yrjola { 8100ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8110ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8120ccd76d4SJuha Yrjola else 8130ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8140ccd76d4SJuha Yrjola } 8150ccd76d4SJuha Yrjola 816c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 817c5c98927SRussell King struct mmc_data *data) 818c5c98927SRussell King { 819c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 820c5c98927SRussell King } 821c5c98927SRussell King 822b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 823b417577dSAdrian Hunter { 824b417577dSAdrian Hunter int dma_ch; 82531463b14SVenkatraman S unsigned long flags; 826b417577dSAdrian Hunter 82731463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 828b417577dSAdrian Hunter host->req_in_progress = 0; 829b417577dSAdrian Hunter dma_ch = host->dma_ch; 83031463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 831b417577dSAdrian Hunter 832b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 833b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 834b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 835b417577dSAdrian Hunter return; 836b417577dSAdrian Hunter host->mrq = NULL; 837b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 838b417577dSAdrian Hunter } 839b417577dSAdrian Hunter 840a45c6cb8SMadhusudhan Chikkature /* 841a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 842a45c6cb8SMadhusudhan Chikkature */ 843a45c6cb8SMadhusudhan Chikkature static void 84470a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 845a45c6cb8SMadhusudhan Chikkature { 8464a694dc9SAdrian Hunter if (!data) { 8474a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8484a694dc9SAdrian Hunter 84923050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 85023050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 85123050103SAdrian Hunter host->response_busy) { 85223050103SAdrian Hunter host->response_busy = 0; 85323050103SAdrian Hunter return; 85423050103SAdrian Hunter } 85523050103SAdrian Hunter 856b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8574a694dc9SAdrian Hunter return; 8584a694dc9SAdrian Hunter } 8594a694dc9SAdrian Hunter 860a45c6cb8SMadhusudhan Chikkature host->data = NULL; 861a45c6cb8SMadhusudhan Chikkature 862a45c6cb8SMadhusudhan Chikkature if (!data->error) 863a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 864a45c6cb8SMadhusudhan Chikkature else 865a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 866a45c6cb8SMadhusudhan Chikkature 867fe852273SMing Lei if (!data->stop) { 868dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 869fe852273SMing Lei return; 870dba3c29eSBalaji T K } 871fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 872a45c6cb8SMadhusudhan Chikkature } 873a45c6cb8SMadhusudhan Chikkature 874a45c6cb8SMadhusudhan Chikkature /* 875a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 876a45c6cb8SMadhusudhan Chikkature */ 877a45c6cb8SMadhusudhan Chikkature static void 87870a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 879a45c6cb8SMadhusudhan Chikkature { 880a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 881a45c6cb8SMadhusudhan Chikkature 882a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 883a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 884a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 885a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 886a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 887a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 888a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 889a45c6cb8SMadhusudhan Chikkature } else { 890a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 891a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 892a45c6cb8SMadhusudhan Chikkature } 893a45c6cb8SMadhusudhan Chikkature } 894b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 895b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 896a45c6cb8SMadhusudhan Chikkature } 897a45c6cb8SMadhusudhan Chikkature 898a45c6cb8SMadhusudhan Chikkature /* 899a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 900a45c6cb8SMadhusudhan Chikkature */ 90170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 902a45c6cb8SMadhusudhan Chikkature { 903b417577dSAdrian Hunter int dma_ch; 90431463b14SVenkatraman S unsigned long flags; 905b417577dSAdrian Hunter 90682788ff5SJarkko Lavinen host->data->error = errno; 907a45c6cb8SMadhusudhan Chikkature 90831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 909b417577dSAdrian Hunter dma_ch = host->dma_ch; 910b417577dSAdrian Hunter host->dma_ch = -1; 91131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 912b417577dSAdrian Hunter 913b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 914c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 915c5c98927SRussell King 916c5c98927SRussell King dmaengine_terminate_all(chan); 917c5c98927SRussell King dma_unmap_sg(chan->device->dev, 918c5c98927SRussell King host->data->sg, host->data->sg_len, 91970a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 920c5c98927SRussell King 921053bf34fSPer Forlin host->data->host_cookie = 0; 922a45c6cb8SMadhusudhan Chikkature } 923a45c6cb8SMadhusudhan Chikkature host->data = NULL; 924a45c6cb8SMadhusudhan Chikkature } 925a45c6cb8SMadhusudhan Chikkature 926a45c6cb8SMadhusudhan Chikkature /* 927a45c6cb8SMadhusudhan Chikkature * Readable error output 928a45c6cb8SMadhusudhan Chikkature */ 929a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 930699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 931a45c6cb8SMadhusudhan Chikkature { 932a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 93370a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 934699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 935699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 936699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 937699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 938a45c6cb8SMadhusudhan Chikkature }; 939a45c6cb8SMadhusudhan Chikkature char res[256]; 940a45c6cb8SMadhusudhan Chikkature char *buf = res; 941a45c6cb8SMadhusudhan Chikkature int len, i; 942a45c6cb8SMadhusudhan Chikkature 943a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 944a45c6cb8SMadhusudhan Chikkature buf += len; 945a45c6cb8SMadhusudhan Chikkature 94670a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 947a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 94870a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 949a45c6cb8SMadhusudhan Chikkature buf += len; 950a45c6cb8SMadhusudhan Chikkature } 951a45c6cb8SMadhusudhan Chikkature 9528986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 953a45c6cb8SMadhusudhan Chikkature } 954699b958bSAdrian Hunter #else 955699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 956699b958bSAdrian Hunter u32 status) 957699b958bSAdrian Hunter { 958699b958bSAdrian Hunter } 959a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 960a45c6cb8SMadhusudhan Chikkature 9613ebf74b1SJean Pihet /* 9623ebf74b1SJean Pihet * MMC controller internal state machines reset 9633ebf74b1SJean Pihet * 9643ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9653ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9663ebf74b1SJean Pihet * Can be called from interrupt context 9673ebf74b1SJean Pihet */ 96870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9693ebf74b1SJean Pihet unsigned long bit) 9703ebf74b1SJean Pihet { 9713ebf74b1SJean Pihet unsigned long i = 0; 9721e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 9733ebf74b1SJean Pihet 9743ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9753ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9763ebf74b1SJean Pihet 97707ad64b6SMadhusudhan Chikkature /* 97807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 97907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 98007ad64b6SMadhusudhan Chikkature */ 98107ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 982b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 98307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 9841e881786SJianpeng Ma udelay(1); 98507ad64b6SMadhusudhan Chikkature } 98607ad64b6SMadhusudhan Chikkature i = 0; 98707ad64b6SMadhusudhan Chikkature 9883ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9893ebf74b1SJean Pihet (i++ < limit)) 9901e881786SJianpeng Ma udelay(1); 9913ebf74b1SJean Pihet 9923ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9933ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9943ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 9953ebf74b1SJean Pihet __func__); 9963ebf74b1SJean Pihet } 997a45c6cb8SMadhusudhan Chikkature 99825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 99925e1897bSBalaji T K int err, int end_cmd) 1000ae4bf788SVenkatraman S { 100125e1897bSBalaji T K if (end_cmd) { 100294d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 100325e1897bSBalaji T K if (host->cmd) 1004ae4bf788SVenkatraman S host->cmd->error = err; 100525e1897bSBalaji T K } 1006ae4bf788SVenkatraman S 1007ae4bf788SVenkatraman S if (host->data) { 1008ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1009ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1010dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1011dc7745bdSBalaji T K host->mrq->cmd->error = err; 1012ae4bf788SVenkatraman S } 1013ae4bf788SVenkatraman S 1014b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1015a45c6cb8SMadhusudhan Chikkature { 1016a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1017b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1018a45c6cb8SMadhusudhan Chikkature 1019a45c6cb8SMadhusudhan Chikkature data = host->data; 10208986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1021a45c6cb8SMadhusudhan Chikkature 1022a7e96879SVenkatraman S if (status & ERR_EN) { 1023699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10244a694dc9SAdrian Hunter 1025a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1026a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1027a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 102825e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1029a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 103025e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 103125e1897bSBalaji T K 1032ae4bf788SVenkatraman S if (host->data || host->response_busy) { 103325e1897bSBalaji T K end_trans = !end_cmd; 1034ae4bf788SVenkatraman S host->response_busy = 0; 1035a45c6cb8SMadhusudhan Chikkature } 1036a45c6cb8SMadhusudhan Chikkature } 1037a45c6cb8SMadhusudhan Chikkature 10387472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1039a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 104070a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1041a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 104270a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1043b417577dSAdrian Hunter } 1044a45c6cb8SMadhusudhan Chikkature 1045b417577dSAdrian Hunter /* 1046b417577dSAdrian Hunter * MMC controller IRQ handler 1047b417577dSAdrian Hunter */ 1048b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1049b417577dSAdrian Hunter { 1050b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1051b417577dSAdrian Hunter int status; 1052b417577dSAdrian Hunter 1053b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10541f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1055b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10561f6b9fa4SVenkatraman S 1057b417577dSAdrian Hunter /* Flush posted write */ 1058b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10591f6b9fa4SVenkatraman S } 10604dffd7a2SAdrian Hunter 1061a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1062a45c6cb8SMadhusudhan Chikkature } 1063a45c6cb8SMadhusudhan Chikkature 106470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1065e13bb300SAdrian Hunter { 1066e13bb300SAdrian Hunter unsigned long i; 1067e13bb300SAdrian Hunter 1068e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1069e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1070e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1071e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1072e13bb300SAdrian Hunter break; 1073e13bb300SAdrian Hunter cpu_relax(); 1074e13bb300SAdrian Hunter } 1075e13bb300SAdrian Hunter } 1076e13bb300SAdrian Hunter 1077a45c6cb8SMadhusudhan Chikkature /* 1078eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1079eb250826SDavid Brownell * 1080eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1081eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1082eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1083a45c6cb8SMadhusudhan Chikkature */ 108470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1085a45c6cb8SMadhusudhan Chikkature { 1086a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1087a45c6cb8SMadhusudhan Chikkature int ret; 1088a45c6cb8SMadhusudhan Chikkature 1089a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1090fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1091cd03d9a8SRajendra Nayak if (host->dbclk) 109294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1093a45c6cb8SMadhusudhan Chikkature 1094a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1095a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1096a45c6cb8SMadhusudhan Chikkature 1097a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 10982bec0893SAdrian Hunter if (!ret) 10992bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11002bec0893SAdrian Hunter vdd); 1101fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1102cd03d9a8SRajendra Nayak if (host->dbclk) 110394c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11042bec0893SAdrian Hunter 1105a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1106a45c6cb8SMadhusudhan Chikkature goto err; 1107a45c6cb8SMadhusudhan Chikkature 1108a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1109a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1110a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1111eb250826SDavid Brownell 1112a45c6cb8SMadhusudhan Chikkature /* 1113a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1114a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 111570a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1116a45c6cb8SMadhusudhan Chikkature * 1117eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1118eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1119eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1120eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1121eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1122eb250826SDavid Brownell * 1123eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1124eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1125eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1126a45c6cb8SMadhusudhan Chikkature */ 1127eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1128a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1129eb250826SDavid Brownell else 1130eb250826SDavid Brownell reg_val |= SDVS30; 1131a45c6cb8SMadhusudhan Chikkature 1132a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1133e13bb300SAdrian Hunter set_sd_bus_power(host); 1134a45c6cb8SMadhusudhan Chikkature 1135a45c6cb8SMadhusudhan Chikkature return 0; 1136a45c6cb8SMadhusudhan Chikkature err: 1137b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1138a45c6cb8SMadhusudhan Chikkature return ret; 1139a45c6cb8SMadhusudhan Chikkature } 1140a45c6cb8SMadhusudhan Chikkature 1141b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1142b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1143b62f6228SAdrian Hunter { 1144b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1145b62f6228SAdrian Hunter return; 1146b62f6228SAdrian Hunter 1147b62f6228SAdrian Hunter host->reqs_blocked = 0; 1148b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1149b62f6228SAdrian Hunter if (host->protect_card) { 11502cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1151b62f6228SAdrian Hunter "card is now accessible\n", 1152b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1153b62f6228SAdrian Hunter host->protect_card = 0; 1154b62f6228SAdrian Hunter } 1155b62f6228SAdrian Hunter } else { 1156b62f6228SAdrian Hunter if (!host->protect_card) { 11572cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1158b62f6228SAdrian Hunter "card is now inaccessible\n", 1159b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1160b62f6228SAdrian Hunter host->protect_card = 1; 1161b62f6228SAdrian Hunter } 1162b62f6228SAdrian Hunter } 1163b62f6228SAdrian Hunter } 1164b62f6228SAdrian Hunter 1165a45c6cb8SMadhusudhan Chikkature /* 11667efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1167a45c6cb8SMadhusudhan Chikkature */ 11687efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1169a45c6cb8SMadhusudhan Chikkature { 11707efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1171249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1172a6b2240dSAdrian Hunter int carddetect; 1173249d0fa9SDavid Brownell 1174a6b2240dSAdrian Hunter if (host->suspended) 11757efab4f3SNeilBrown return IRQ_HANDLED; 1176a45c6cb8SMadhusudhan Chikkature 1177a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1178a6b2240dSAdrian Hunter 1179191d1f1dSDenis Karpov if (slot->card_detect) 1180db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1181b62f6228SAdrian Hunter else { 1182b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1183a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1184b62f6228SAdrian Hunter } 1185a6b2240dSAdrian Hunter 1186cdeebaddSMadhusudhan Chikkature if (carddetect) 1187a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1188cdeebaddSMadhusudhan Chikkature else 1189a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1190a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1191a45c6cb8SMadhusudhan Chikkature } 1192a45c6cb8SMadhusudhan Chikkature 1193c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11940ccd76d4SJuha Yrjola { 1195c5c98927SRussell King struct omap_hsmmc_host *host = param; 1196c5c98927SRussell King struct dma_chan *chan; 1197770d7432SAdrian Hunter struct mmc_data *data; 1198c5c98927SRussell King int req_in_progress; 1199a45c6cb8SMadhusudhan Chikkature 1200c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1201b417577dSAdrian Hunter if (host->dma_ch < 0) { 1202c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1203a45c6cb8SMadhusudhan Chikkature return; 1204b417577dSAdrian Hunter } 1205a45c6cb8SMadhusudhan Chikkature 1206770d7432SAdrian Hunter data = host->mrq->data; 1207c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12089782aff8SPer Forlin if (!data->host_cookie) 1209c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1210c5c98927SRussell King data->sg, data->sg_len, 1211b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1212b417577dSAdrian Hunter 1213b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1214a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1215c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1216b417577dSAdrian Hunter 1217b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1218b417577dSAdrian Hunter if (!req_in_progress) { 1219b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1220b417577dSAdrian Hunter 1221b417577dSAdrian Hunter host->mrq = NULL; 1222b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1223b417577dSAdrian Hunter } 1224a45c6cb8SMadhusudhan Chikkature } 1225a45c6cb8SMadhusudhan Chikkature 12269782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12279782aff8SPer Forlin struct mmc_data *data, 1228c5c98927SRussell King struct omap_hsmmc_next *next, 122926b88520SRussell King struct dma_chan *chan) 12309782aff8SPer Forlin { 12319782aff8SPer Forlin int dma_len; 12329782aff8SPer Forlin 12339782aff8SPer Forlin if (!next && data->host_cookie && 12349782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12352cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12369782aff8SPer Forlin " host->next_data.cookie %d\n", 12379782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12389782aff8SPer Forlin data->host_cookie = 0; 12399782aff8SPer Forlin } 12409782aff8SPer Forlin 12419782aff8SPer Forlin /* Check if next job is already prepared */ 12429782aff8SPer Forlin if (next || 12439782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 124426b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12459782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12469782aff8SPer Forlin 12479782aff8SPer Forlin } else { 12489782aff8SPer Forlin dma_len = host->next_data.dma_len; 12499782aff8SPer Forlin host->next_data.dma_len = 0; 12509782aff8SPer Forlin } 12519782aff8SPer Forlin 12529782aff8SPer Forlin 12539782aff8SPer Forlin if (dma_len == 0) 12549782aff8SPer Forlin return -EINVAL; 12559782aff8SPer Forlin 12569782aff8SPer Forlin if (next) { 12579782aff8SPer Forlin next->dma_len = dma_len; 12589782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12599782aff8SPer Forlin } else 12609782aff8SPer Forlin host->dma_len = dma_len; 12619782aff8SPer Forlin 12629782aff8SPer Forlin return 0; 12639782aff8SPer Forlin } 12649782aff8SPer Forlin 1265a45c6cb8SMadhusudhan Chikkature /* 1266a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1267a45c6cb8SMadhusudhan Chikkature */ 126870a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 126970a3341aSDenis Karpov struct mmc_request *req) 1270a45c6cb8SMadhusudhan Chikkature { 127126b88520SRussell King struct dma_slave_config cfg; 127226b88520SRussell King struct dma_async_tx_descriptor *tx; 127326b88520SRussell King int ret = 0, i; 1274a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1275c5c98927SRussell King struct dma_chan *chan; 1276a45c6cb8SMadhusudhan Chikkature 12770ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1278a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12790ccd76d4SJuha Yrjola struct scatterlist *sgl; 12800ccd76d4SJuha Yrjola 12810ccd76d4SJuha Yrjola sgl = data->sg + i; 12820ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12830ccd76d4SJuha Yrjola return -EINVAL; 12840ccd76d4SJuha Yrjola } 12850ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12860ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12870ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12880ccd76d4SJuha Yrjola */ 12890ccd76d4SJuha Yrjola return -EINVAL; 12900ccd76d4SJuha Yrjola 1291b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1292a45c6cb8SMadhusudhan Chikkature 1293c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1294c5c98927SRussell King 1295c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1296c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1297c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1298c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1299c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1300c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1301c5c98927SRussell King 1302c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13039782aff8SPer Forlin if (ret) 13049782aff8SPer Forlin return ret; 1305a45c6cb8SMadhusudhan Chikkature 130626b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1307c5c98927SRussell King if (ret) 1308c5c98927SRussell King return ret; 1309a45c6cb8SMadhusudhan Chikkature 1310c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1311c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1312c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1313c5c98927SRussell King if (!tx) { 1314c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1315c5c98927SRussell King /* FIXME: cleanup */ 1316c5c98927SRussell King return -1; 1317c5c98927SRussell King } 1318c5c98927SRussell King 1319c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1320c5c98927SRussell King tx->callback_param = host; 1321c5c98927SRussell King 1322c5c98927SRussell King /* Does not fail */ 1323c5c98927SRussell King dmaengine_submit(tx); 1324c5c98927SRussell King 132526b88520SRussell King host->dma_ch = 1; 1326c5c98927SRussell King 1327c5c98927SRussell King dma_async_issue_pending(chan); 1328a45c6cb8SMadhusudhan Chikkature 1329a45c6cb8SMadhusudhan Chikkature return 0; 1330a45c6cb8SMadhusudhan Chikkature } 1331a45c6cb8SMadhusudhan Chikkature 133270a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1333e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1334e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1335a45c6cb8SMadhusudhan Chikkature { 1336a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1337a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1338a45c6cb8SMadhusudhan Chikkature 1339a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1340a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1341a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1342a45c6cb8SMadhusudhan Chikkature clkd = 1; 1343a45c6cb8SMadhusudhan Chikkature 1344a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1345e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1346e2bf08d6SAdrian Hunter timeout += timeout_clks; 1347a45c6cb8SMadhusudhan Chikkature if (timeout) { 1348a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1349a45c6cb8SMadhusudhan Chikkature dto += 1; 1350a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1351a45c6cb8SMadhusudhan Chikkature } 1352a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1353a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1354a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1355a45c6cb8SMadhusudhan Chikkature dto += 1; 1356a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1357a45c6cb8SMadhusudhan Chikkature dto -= 13; 1358a45c6cb8SMadhusudhan Chikkature else 1359a45c6cb8SMadhusudhan Chikkature dto = 0; 1360a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1361a45c6cb8SMadhusudhan Chikkature dto = 14; 1362a45c6cb8SMadhusudhan Chikkature } 1363a45c6cb8SMadhusudhan Chikkature 1364a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1365a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1366a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1367a45c6cb8SMadhusudhan Chikkature } 1368a45c6cb8SMadhusudhan Chikkature 1369a45c6cb8SMadhusudhan Chikkature /* 1370a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1371a45c6cb8SMadhusudhan Chikkature */ 1372a45c6cb8SMadhusudhan Chikkature static int 137370a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1374a45c6cb8SMadhusudhan Chikkature { 1375a45c6cb8SMadhusudhan Chikkature int ret; 1376a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1377a45c6cb8SMadhusudhan Chikkature 1378a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1379a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1380e2bf08d6SAdrian Hunter /* 1381e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1382e2bf08d6SAdrian Hunter * busy signal. 1383e2bf08d6SAdrian Hunter */ 1384e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1385e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1386a45c6cb8SMadhusudhan Chikkature return 0; 1387a45c6cb8SMadhusudhan Chikkature } 1388a45c6cb8SMadhusudhan Chikkature 1389a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1390a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1391e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1392a45c6cb8SMadhusudhan Chikkature 1393a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 139470a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1395a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1396b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1397a45c6cb8SMadhusudhan Chikkature return ret; 1398a45c6cb8SMadhusudhan Chikkature } 1399a45c6cb8SMadhusudhan Chikkature } 1400a45c6cb8SMadhusudhan Chikkature return 0; 1401a45c6cb8SMadhusudhan Chikkature } 1402a45c6cb8SMadhusudhan Chikkature 14039782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14049782aff8SPer Forlin int err) 14059782aff8SPer Forlin { 14069782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14079782aff8SPer Forlin struct mmc_data *data = mrq->data; 14089782aff8SPer Forlin 140926b88520SRussell King if (host->use_dma && data->host_cookie) { 1410c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1411c5c98927SRussell King 141226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14139782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14149782aff8SPer Forlin data->host_cookie = 0; 14159782aff8SPer Forlin } 14169782aff8SPer Forlin } 14179782aff8SPer Forlin 14189782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14199782aff8SPer Forlin bool is_first_req) 14209782aff8SPer Forlin { 14219782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14229782aff8SPer Forlin 14239782aff8SPer Forlin if (mrq->data->host_cookie) { 14249782aff8SPer Forlin mrq->data->host_cookie = 0; 14259782aff8SPer Forlin return ; 14269782aff8SPer Forlin } 14279782aff8SPer Forlin 1428c5c98927SRussell King if (host->use_dma) { 1429c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1430c5c98927SRussell King 14319782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 143226b88520SRussell King &host->next_data, c)) 14339782aff8SPer Forlin mrq->data->host_cookie = 0; 14349782aff8SPer Forlin } 1435c5c98927SRussell King } 14369782aff8SPer Forlin 1437a45c6cb8SMadhusudhan Chikkature /* 1438a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1439a45c6cb8SMadhusudhan Chikkature */ 144070a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1441a45c6cb8SMadhusudhan Chikkature { 144270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1443a3f406f8SJarkko Lavinen int err; 1444a45c6cb8SMadhusudhan Chikkature 1445b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1446b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1447b62f6228SAdrian Hunter if (host->protect_card) { 1448b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1449b62f6228SAdrian Hunter /* 1450b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1451b62f6228SAdrian Hunter * state by resetting the command and data state 1452b62f6228SAdrian Hunter * machines. 1453b62f6228SAdrian Hunter */ 1454b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1455b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1456b62f6228SAdrian Hunter host->reqs_blocked += 1; 1457b62f6228SAdrian Hunter } 1458b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1459b62f6228SAdrian Hunter if (req->data) 1460b62f6228SAdrian Hunter req->data->error = -EBADF; 1461b417577dSAdrian Hunter req->cmd->retries = 0; 1462b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1463b62f6228SAdrian Hunter return; 1464b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1465b62f6228SAdrian Hunter host->reqs_blocked = 0; 1466a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1467a45c6cb8SMadhusudhan Chikkature host->mrq = req; 146870a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1469a3f406f8SJarkko Lavinen if (err) { 1470a3f406f8SJarkko Lavinen req->cmd->error = err; 1471a3f406f8SJarkko Lavinen if (req->data) 1472a3f406f8SJarkko Lavinen req->data->error = err; 1473a3f406f8SJarkko Lavinen host->mrq = NULL; 1474a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1475a3f406f8SJarkko Lavinen return; 1476a3f406f8SJarkko Lavinen } 1477a3f406f8SJarkko Lavinen 147870a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1479a45c6cb8SMadhusudhan Chikkature } 1480a45c6cb8SMadhusudhan Chikkature 1481a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 148270a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1483a45c6cb8SMadhusudhan Chikkature { 148470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1485a3621465SAdrian Hunter int do_send_init_stream = 0; 1486a45c6cb8SMadhusudhan Chikkature 1487fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14885e2ea617SAdrian Hunter 1489a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1490a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1491a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1492a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1493a3621465SAdrian Hunter 0, 0); 1494a45c6cb8SMadhusudhan Chikkature break; 1495a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1496a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1497a3621465SAdrian Hunter 1, ios->vdd); 1498a45c6cb8SMadhusudhan Chikkature break; 1499a3621465SAdrian Hunter case MMC_POWER_ON: 1500a3621465SAdrian Hunter do_send_init_stream = 1; 1501a3621465SAdrian Hunter break; 1502a3621465SAdrian Hunter } 1503a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1504a45c6cb8SMadhusudhan Chikkature } 1505a45c6cb8SMadhusudhan Chikkature 1506dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1507dd498effSDenis Karpov 15083796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1509a45c6cb8SMadhusudhan Chikkature 15104621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1511eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1512eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1513eb250826SDavid Brownell */ 1514a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15151f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15161f84b71bSRajendra Nayak /* 15171f84b71bSRajendra Nayak * With pbias cell programming missing, this 1518cf5ae40bSTony Lindgren * can't be allowed on MMC1 when booting with device 15191f84b71bSRajendra Nayak * tree. 15201f84b71bSRajendra Nayak */ 1521cf5ae40bSTony Lindgren !host->pbias_disable) { 1522a45c6cb8SMadhusudhan Chikkature /* 1523a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1524a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1525a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1526a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1527a45c6cb8SMadhusudhan Chikkature */ 152870a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1529a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1530a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1531a45c6cb8SMadhusudhan Chikkature } 1532a45c6cb8SMadhusudhan Chikkature } 1533a45c6cb8SMadhusudhan Chikkature 15345934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1535a45c6cb8SMadhusudhan Chikkature 1536a3621465SAdrian Hunter if (do_send_init_stream) 1537a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1538a45c6cb8SMadhusudhan Chikkature 15393796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15405e2ea617SAdrian Hunter 1541fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1542a45c6cb8SMadhusudhan Chikkature } 1543a45c6cb8SMadhusudhan Chikkature 1544a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1545a45c6cb8SMadhusudhan Chikkature { 154670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1547a45c6cb8SMadhusudhan Chikkature 1548191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1549a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1550db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1551a45c6cb8SMadhusudhan Chikkature } 1552a45c6cb8SMadhusudhan Chikkature 1553a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1554a45c6cb8SMadhusudhan Chikkature { 155570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1556a45c6cb8SMadhusudhan Chikkature 1557191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1558a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1559191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1560a45c6cb8SMadhusudhan Chikkature } 1561a45c6cb8SMadhusudhan Chikkature 15624816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15634816858cSGrazvydas Ignotas { 15644816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15654816858cSGrazvydas Ignotas 15664816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15674816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15684816858cSGrazvydas Ignotas } 15694816858cSGrazvydas Ignotas 157070a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15711b331e69SKim Kyuwon { 15721b331e69SKim Kyuwon u32 hctl, capa, value; 15731b331e69SKim Kyuwon 15741b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15754621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15761b331e69SKim Kyuwon hctl = SDVS30; 15771b331e69SKim Kyuwon capa = VS30 | VS18; 15781b331e69SKim Kyuwon } else { 15791b331e69SKim Kyuwon hctl = SDVS18; 15801b331e69SKim Kyuwon capa = VS18; 15811b331e69SKim Kyuwon } 15821b331e69SKim Kyuwon 15831b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15841b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15851b331e69SKim Kyuwon 15861b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15871b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15881b331e69SKim Kyuwon 15891b331e69SKim Kyuwon /* Set SD bus power bit */ 1590e13bb300SAdrian Hunter set_sd_bus_power(host); 15911b331e69SKim Kyuwon } 15921b331e69SKim Kyuwon 159370a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1594dd498effSDenis Karpov { 159570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1596dd498effSDenis Karpov 1597fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1598fa4aa2d4SBalaji T K 1599dd498effSDenis Karpov return 0; 1600dd498effSDenis Karpov } 1601dd498effSDenis Karpov 1602907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1603dd498effSDenis Karpov { 160470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1605dd498effSDenis Karpov 1606fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1607fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1608fa4aa2d4SBalaji T K 1609dd498effSDenis Karpov return 0; 1610dd498effSDenis Karpov } 1611dd498effSDenis Karpov 161270a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 161370a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 161470a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16159782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16169782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 161770a3341aSDenis Karpov .request = omap_hsmmc_request, 161870a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1619dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1620dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16214816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1622dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1623dd498effSDenis Karpov }; 1624dd498effSDenis Karpov 1625d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1626d900f712SDenis Karpov 162770a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1628d900f712SDenis Karpov { 1629d900f712SDenis Karpov struct mmc_host *mmc = s->private; 163070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 163111dd62a7SDenis Karpov 16320a82e06eSTony Lindgren seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 16330a82e06eSTony Lindgren mmc->index, host->context_loss); 16345e2ea617SAdrian Hunter 16357a8c2cefSBalaji T K if (host->suspended) { 1636dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1637dd498effSDenis Karpov return 0; 1638dd498effSDenis Karpov } 1639dd498effSDenis Karpov 1640fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1641d900f712SDenis Karpov 1642d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1643d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1644d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1645d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1646d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1647d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1648d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1649d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1650d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1651d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1652d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1653d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16545e2ea617SAdrian Hunter 1655fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1656fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1657dd498effSDenis Karpov 1658d900f712SDenis Karpov return 0; 1659d900f712SDenis Karpov } 1660d900f712SDenis Karpov 166170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1662d900f712SDenis Karpov { 166370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1664d900f712SDenis Karpov } 1665d900f712SDenis Karpov 1666d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 166770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1668d900f712SDenis Karpov .read = seq_read, 1669d900f712SDenis Karpov .llseek = seq_lseek, 1670d900f712SDenis Karpov .release = single_release, 1671d900f712SDenis Karpov }; 1672d900f712SDenis Karpov 167370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1674d900f712SDenis Karpov { 1675d900f712SDenis Karpov if (mmc->debugfs_root) 1676d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1677d900f712SDenis Karpov mmc, &mmc_regs_fops); 1678d900f712SDenis Karpov } 1679d900f712SDenis Karpov 1680d900f712SDenis Karpov #else 1681d900f712SDenis Karpov 168270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1683d900f712SDenis Karpov { 1684d900f712SDenis Karpov } 1685d900f712SDenis Karpov 1686d900f712SDenis Karpov #endif 1687d900f712SDenis Karpov 168846856a68SRajendra Nayak #ifdef CONFIG_OF 168946856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 169046856a68SRajendra Nayak 169146856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 169246856a68SRajendra Nayak { 169346856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 169446856a68SRajendra Nayak }, 169546856a68SRajendra Nayak { 169646856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 169746856a68SRajendra Nayak }, 169846856a68SRajendra Nayak { 169946856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 170046856a68SRajendra Nayak .data = &omap4_reg_offset, 170146856a68SRajendra Nayak }, 170246856a68SRajendra Nayak {}, 1703b6d085f6SChris Ball }; 170446856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 170546856a68SRajendra Nayak 170646856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 170746856a68SRajendra Nayak { 170846856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 170946856a68SRajendra Nayak struct device_node *np = dev->of_node; 1710d8714e87SDaniel Mack u32 bus_width, max_freq; 1711dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1712dc642c28SJan Luebbe 1713dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1714dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1715dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1716dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 171746856a68SRajendra Nayak 171846856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 171946856a68SRajendra Nayak if (!pdata) 172046856a68SRajendra Nayak return NULL; /* out of memory */ 172146856a68SRajendra Nayak 172246856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 172346856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 172446856a68SRajendra Nayak 172546856a68SRajendra Nayak /* This driver only supports 1 slot */ 172646856a68SRajendra Nayak pdata->nr_slots = 1; 1727dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1728dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 172946856a68SRajendra Nayak 173046856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 173146856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 173246856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 173346856a68SRajendra Nayak } 17347f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 173546856a68SRajendra Nayak if (bus_width == 4) 173646856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 173746856a68SRajendra Nayak else if (bus_width == 8) 173846856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 173946856a68SRajendra Nayak 174046856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 174146856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 174246856a68SRajendra Nayak 1743d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1744d8714e87SDaniel Mack pdata->max_freq = max_freq; 1745d8714e87SDaniel Mack 1746cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1747cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1748cd587096SHebbar, Gururaja 174946856a68SRajendra Nayak return pdata; 175046856a68SRajendra Nayak } 175146856a68SRajendra Nayak #else 175246856a68SRajendra Nayak static inline struct omap_mmc_platform_data 175346856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 175446856a68SRajendra Nayak { 175546856a68SRajendra Nayak return NULL; 175646856a68SRajendra Nayak } 175746856a68SRajendra Nayak #endif 175846856a68SRajendra Nayak 1759c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1760a45c6cb8SMadhusudhan Chikkature { 1761a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1762a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 176370a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1764a45c6cb8SMadhusudhan Chikkature struct resource *res; 1765db0fefc5SAdrian Hunter int ret, irq; 176646856a68SRajendra Nayak const struct of_device_id *match; 176726b88520SRussell King dma_cap_mask_t mask; 176826b88520SRussell King unsigned tx_req, rx_req; 176946b76035SDaniel Mack struct pinctrl *pinctrl; 177046856a68SRajendra Nayak 177146856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 177246856a68SRajendra Nayak if (match) { 177346856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1774dc642c28SJan Luebbe 1775dc642c28SJan Luebbe if (IS_ERR(pdata)) 1776dc642c28SJan Luebbe return PTR_ERR(pdata); 1777dc642c28SJan Luebbe 177846856a68SRajendra Nayak if (match->data) { 1779efc9b736SUwe Kleine-König const u16 *offsetp = match->data; 178046856a68SRajendra Nayak pdata->reg_offset = *offsetp; 178146856a68SRajendra Nayak } 178246856a68SRajendra Nayak } 1783a45c6cb8SMadhusudhan Chikkature 1784a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1785a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1786a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1787a45c6cb8SMadhusudhan Chikkature } 1788a45c6cb8SMadhusudhan Chikkature 1789a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1790a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1791a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1792a45c6cb8SMadhusudhan Chikkature } 1793a45c6cb8SMadhusudhan Chikkature 1794a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1795a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1796a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1797a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1798a45c6cb8SMadhusudhan Chikkature 1799984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1800a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1801a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1802a45c6cb8SMadhusudhan Chikkature 1803db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1804db0fefc5SAdrian Hunter if (ret) 1805db0fefc5SAdrian Hunter goto err; 1806db0fefc5SAdrian Hunter 180770a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1808a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1809a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1810db0fefc5SAdrian Hunter goto err_alloc; 1811a45c6cb8SMadhusudhan Chikkature } 1812a45c6cb8SMadhusudhan Chikkature 1813a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1814a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1815a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1816a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1817a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1818a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1819a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1820a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1821fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1822a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18236da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18249782aff8SPer Forlin host->next_data.cookie = 1; 1825a45c6cb8SMadhusudhan Chikkature 1826a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1827a45c6cb8SMadhusudhan Chikkature 182870a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1829dd498effSDenis Karpov 1830e0eb2424SAdrian Hunter /* 1831e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1832e0eb2424SAdrian Hunter * no off state. 1833e0eb2424SAdrian Hunter */ 1834e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1835e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1836e0eb2424SAdrian Hunter 18376b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1838d418ed87SDaniel Mack 1839d418ed87SDaniel Mack if (pdata->max_freq > 0) 1840d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1841d418ed87SDaniel Mack else 18426b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1843a45c6cb8SMadhusudhan Chikkature 18444dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1845a45c6cb8SMadhusudhan Chikkature 18466f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1847a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1848a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1849a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1850a45c6cb8SMadhusudhan Chikkature goto err1; 1851a45c6cb8SMadhusudhan Chikkature } 1852a45c6cb8SMadhusudhan Chikkature 18539b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18549b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18559b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18569b68256cSPaul Walmsley } 1857dd498effSDenis Karpov 1858fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1859fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1860fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1861fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1862a45c6cb8SMadhusudhan Chikkature 186392a3aebfSBalaji T K omap_hsmmc_context_save(host); 186492a3aebfSBalaji T K 1865cf5ae40bSTony Lindgren /* This can be removed once we support PBIAS with DT */ 1866e002264fSBalaji T K if (host->dev->of_node && res->start == 0x4809c000) 1867cf5ae40bSTony Lindgren host->pbias_disable = 1; 1868cf5ae40bSTony Lindgren 1869a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1870a45c6cb8SMadhusudhan Chikkature /* 1871a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1872a45c6cb8SMadhusudhan Chikkature */ 1873cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1874cd03d9a8SRajendra Nayak host->dbclk = NULL; 187594c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1876cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1877cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1878cd03d9a8SRajendra Nayak host->dbclk = NULL; 18792bec0893SAdrian Hunter } 1880a45c6cb8SMadhusudhan Chikkature 18810ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18820ccd76d4SJuha Yrjola * as we want. */ 1883a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18840ccd76d4SJuha Yrjola 1885a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1886a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1887a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1888a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1889a45c6cb8SMadhusudhan Chikkature 189013189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 189193caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1892a45c6cb8SMadhusudhan Chikkature 18933a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 18943a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1895a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1896a45c6cb8SMadhusudhan Chikkature 1897191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 189823d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 189923d99bb9SAdrian Hunter 19006fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19016fdc75deSEliad Peller 190270a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1903a45c6cb8SMadhusudhan Chikkature 19044a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 1905b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1906b7bf773bSBalaji T K if (!res) { 1907b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19089c17d08cSKevin Hilman ret = -ENXIO; 1909f3e2f1ddSGrazvydas Ignotas goto err_irq; 1910a45c6cb8SMadhusudhan Chikkature } 191126b88520SRussell King tx_req = res->start; 1912b7bf773bSBalaji T K 1913b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1914b7bf773bSBalaji T K if (!res) { 1915b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19169c17d08cSKevin Hilman ret = -ENXIO; 1917b7bf773bSBalaji T K goto err_irq; 1918b7bf773bSBalaji T K } 191926b88520SRussell King rx_req = res->start; 19204a29b559SSantosh Shilimkar } 1921c5c98927SRussell King 1922c5c98927SRussell King dma_cap_zero(mask); 1923c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 192426b88520SRussell King 1925d272fbf0SMatt Porter host->rx_chan = 1926d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1927d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1928d272fbf0SMatt Porter 1929c5c98927SRussell King if (!host->rx_chan) { 193026b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 193104e8c7bcSKevin Hilman ret = -ENXIO; 193226b88520SRussell King goto err_irq; 1933c5c98927SRussell King } 193426b88520SRussell King 1935d272fbf0SMatt Porter host->tx_chan = 1936d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1937d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1938d272fbf0SMatt Porter 1939c5c98927SRussell King if (!host->tx_chan) { 194026b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 194104e8c7bcSKevin Hilman ret = -ENXIO; 194226b88520SRussell King goto err_irq; 1943c5c98927SRussell King } 1944a45c6cb8SMadhusudhan Chikkature 1945a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1946d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1947a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1948a45c6cb8SMadhusudhan Chikkature if (ret) { 1949b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1950a45c6cb8SMadhusudhan Chikkature goto err_irq; 1951a45c6cb8SMadhusudhan Chikkature } 1952a45c6cb8SMadhusudhan Chikkature 1953a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1954a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1955b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 195670a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1957a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1958a45c6cb8SMadhusudhan Chikkature } 1959a45c6cb8SMadhusudhan Chikkature } 1960db0fefc5SAdrian Hunter 1961b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1962db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1963db0fefc5SAdrian Hunter if (ret) 1964db0fefc5SAdrian Hunter goto err_reg; 1965db0fefc5SAdrian Hunter host->use_reg = 1; 1966db0fefc5SAdrian Hunter } 1967db0fefc5SAdrian Hunter 1968b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1969a45c6cb8SMadhusudhan Chikkature 1970a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1971e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19727efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19737efab4f3SNeilBrown NULL, 19747efab4f3SNeilBrown omap_hsmmc_detect, 1975db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1976a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1977a45c6cb8SMadhusudhan Chikkature if (ret) { 1978b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 1979a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1980a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1981a45c6cb8SMadhusudhan Chikkature } 198272f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 198372f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1984a45c6cb8SMadhusudhan Chikkature } 1985a45c6cb8SMadhusudhan Chikkature 1986b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1987a45c6cb8SMadhusudhan Chikkature 198846b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 198946b76035SDaniel Mack if (IS_ERR(pinctrl)) 199046b76035SDaniel Mack dev_warn(&pdev->dev, 199146b76035SDaniel Mack "pins are not configured from the driver\n"); 199246b76035SDaniel Mack 1993b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1994b62f6228SAdrian Hunter 1995a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1996a45c6cb8SMadhusudhan Chikkature 1997191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1998a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1999a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2000a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2001a45c6cb8SMadhusudhan Chikkature } 2002191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2003a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2004a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2005a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2006db0fefc5SAdrian Hunter goto err_slot_name; 2007a45c6cb8SMadhusudhan Chikkature } 2008a45c6cb8SMadhusudhan Chikkature 200970a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2010fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2011fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2012d900f712SDenis Karpov 2013a45c6cb8SMadhusudhan Chikkature return 0; 2014a45c6cb8SMadhusudhan Chikkature 2015a45c6cb8SMadhusudhan Chikkature err_slot_name: 2016a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2017a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2018db0fefc5SAdrian Hunter err_irq_cd: 2019db0fefc5SAdrian Hunter if (host->use_reg) 2020db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2021db0fefc5SAdrian Hunter err_reg: 2022db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2023db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2024a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2025a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2026a45c6cb8SMadhusudhan Chikkature err_irq: 2027c5c98927SRussell King if (host->tx_chan) 2028c5c98927SRussell King dma_release_channel(host->tx_chan); 2029c5c98927SRussell King if (host->rx_chan) 2030c5c98927SRussell King dma_release_channel(host->rx_chan); 2031d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 203237f6190dSTony Lindgren pm_runtime_disable(host->dev); 2033a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2034cd03d9a8SRajendra Nayak if (host->dbclk) { 203594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2036a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2037a45c6cb8SMadhusudhan Chikkature } 2038a45c6cb8SMadhusudhan Chikkature err1: 2039a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2040a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2041db0fefc5SAdrian Hunter err_alloc: 2042db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2043db0fefc5SAdrian Hunter err: 204448b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204548b332f9SRussell King if (res) 2046984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2047a45c6cb8SMadhusudhan Chikkature return ret; 2048a45c6cb8SMadhusudhan Chikkature } 2049a45c6cb8SMadhusudhan Chikkature 20506e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2051a45c6cb8SMadhusudhan Chikkature { 205270a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2053a45c6cb8SMadhusudhan Chikkature struct resource *res; 2054a45c6cb8SMadhusudhan Chikkature 2055fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2056a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2057db0fefc5SAdrian Hunter if (host->use_reg) 2058db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2059a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2060a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2061a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2062a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2063a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2064a45c6cb8SMadhusudhan Chikkature 2065c5c98927SRussell King if (host->tx_chan) 2066c5c98927SRussell King dma_release_channel(host->tx_chan); 2067c5c98927SRussell King if (host->rx_chan) 2068c5c98927SRussell King dma_release_channel(host->rx_chan); 2069c5c98927SRussell King 2070fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2071fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2072a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2073cd03d9a8SRajendra Nayak if (host->dbclk) { 207494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2075a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2076a45c6cb8SMadhusudhan Chikkature } 2077a45c6cb8SMadhusudhan Chikkature 20789ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2079a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 20809d1f0286SBalaji T K mmc_free_host(host->mmc); 2081a45c6cb8SMadhusudhan Chikkature 2082a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2083a45c6cb8SMadhusudhan Chikkature if (res) 2084984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2085a45c6cb8SMadhusudhan Chikkature 2086a45c6cb8SMadhusudhan Chikkature return 0; 2087a45c6cb8SMadhusudhan Chikkature } 2088a45c6cb8SMadhusudhan Chikkature 2089a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2090a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2091a48ce884SFelipe Balbi { 2092a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2093a48ce884SFelipe Balbi 2094a48ce884SFelipe Balbi if (host->pdata->suspend) 2095a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2096a48ce884SFelipe Balbi 2097a48ce884SFelipe Balbi return 0; 2098a48ce884SFelipe Balbi } 2099a48ce884SFelipe Balbi 2100a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2101a48ce884SFelipe Balbi { 2102a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2103a48ce884SFelipe Balbi 2104a48ce884SFelipe Balbi if (host->pdata->resume) 2105a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2106a48ce884SFelipe Balbi 2107a48ce884SFelipe Balbi } 2108a48ce884SFelipe Balbi 2109a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2110a45c6cb8SMadhusudhan Chikkature { 2111a45c6cb8SMadhusudhan Chikkature int ret = 0; 2112927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2113927ce944SFelipe Balbi 2114927ce944SFelipe Balbi if (!host) 2115927ce944SFelipe Balbi return 0; 2116a45c6cb8SMadhusudhan Chikkature 2117a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2118a45c6cb8SMadhusudhan Chikkature return 0; 2119a45c6cb8SMadhusudhan Chikkature 2120fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2121a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 21221a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2123fa4aa2d4SBalaji T K 212431f9d463SEliad Peller if (ret) { 2125a6b2240dSAdrian Hunter host->suspended = 0; 212631f9d463SEliad Peller goto err; 2127a6b2240dSAdrian Hunter } 212831f9d463SEliad Peller 212931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 213031f9d463SEliad Peller omap_hsmmc_disable_irq(host); 213131f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 213231f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 213331f9d463SEliad Peller } 2134927ce944SFelipe Balbi 2135cd03d9a8SRajendra Nayak if (host->dbclk) 213694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 213731f9d463SEliad Peller err: 2138fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2139a45c6cb8SMadhusudhan Chikkature return ret; 2140a45c6cb8SMadhusudhan Chikkature } 2141a45c6cb8SMadhusudhan Chikkature 2142a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2143a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2144a45c6cb8SMadhusudhan Chikkature { 2145a45c6cb8SMadhusudhan Chikkature int ret = 0; 2146927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2147927ce944SFelipe Balbi 2148927ce944SFelipe Balbi if (!host) 2149927ce944SFelipe Balbi return 0; 2150a45c6cb8SMadhusudhan Chikkature 2151a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2152a45c6cb8SMadhusudhan Chikkature return 0; 2153a45c6cb8SMadhusudhan Chikkature 2154fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 215511dd62a7SDenis Karpov 2156cd03d9a8SRajendra Nayak if (host->dbclk) 215794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21582bec0893SAdrian Hunter 215931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 216070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21611b331e69SKim Kyuwon 2162b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2163b62f6228SAdrian Hunter 2164a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2165a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2166a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2167a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2168fa4aa2d4SBalaji T K 2169fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2170fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2171a45c6cb8SMadhusudhan Chikkature 2172a45c6cb8SMadhusudhan Chikkature return ret; 2173a45c6cb8SMadhusudhan Chikkature 2174a45c6cb8SMadhusudhan Chikkature } 2175a45c6cb8SMadhusudhan Chikkature 2176a45c6cb8SMadhusudhan Chikkature #else 2177a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2178a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 217970a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 218070a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2181a45c6cb8SMadhusudhan Chikkature #endif 2182a45c6cb8SMadhusudhan Chikkature 2183fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2184fa4aa2d4SBalaji T K { 2185fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2186fa4aa2d4SBalaji T K 2187fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2188fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2189927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2190fa4aa2d4SBalaji T K 2191fa4aa2d4SBalaji T K return 0; 2192fa4aa2d4SBalaji T K } 2193fa4aa2d4SBalaji T K 2194fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2195fa4aa2d4SBalaji T K { 2196fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2197fa4aa2d4SBalaji T K 2198fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2199fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2200927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2201fa4aa2d4SBalaji T K 2202fa4aa2d4SBalaji T K return 0; 2203fa4aa2d4SBalaji T K } 2204fa4aa2d4SBalaji T K 2205a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 220670a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 220770a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2208a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2209a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2210fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2211fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2212a791daa1SKevin Hilman }; 2213a791daa1SKevin Hilman 2214a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2215efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22160433c143SBill Pemberton .remove = omap_hsmmc_remove, 2217a45c6cb8SMadhusudhan Chikkature .driver = { 2218a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2219a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2220a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 222146856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2222a45c6cb8SMadhusudhan Chikkature }, 2223a45c6cb8SMadhusudhan Chikkature }; 2224a45c6cb8SMadhusudhan Chikkature 2225b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2226a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2227a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2228a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2229a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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