1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184e99448ffSBalaji T K struct regulator *pbias; 185e99448ffSBalaji T K bool pbias_enabled; 186a45c6cb8SMadhusudhan Chikkature void __iomem *base; 187a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1884dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 189a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1900ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 191a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 192a3621465SAdrian Hunter unsigned char power_mode; 193a45c6cb8SMadhusudhan Chikkature int suspended; 1940a82e06eSTony Lindgren u32 con; 1950a82e06eSTony Lindgren u32 hctl; 1960a82e06eSTony Lindgren u32 sysctl; 1970a82e06eSTony Lindgren u32 capa; 198a45c6cb8SMadhusudhan Chikkature int irq; 1992cd3a2a5SAndreas Fenkart int wake_irq; 200a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 201c5c98927SRussell King struct dma_chan *tx_chan; 202c5c98927SRussell King struct dma_chan *rx_chan; 2034a694dc9SAdrian Hunter int response_busy; 20411dd62a7SDenis Karpov int context_loss; 205b62f6228SAdrian Hunter int protect_card; 206b62f6228SAdrian Hunter int reqs_blocked; 207b417577dSAdrian Hunter int req_in_progress; 2086e3076c2SBalaji T K unsigned long clk_rate; 209a2e77152SBalaji T K unsigned int flags; 2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2129782aff8SPer Forlin struct omap_hsmmc_next next_data; 21355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 214b5cd43f0SAndreas Fenkart 215b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 216b5cd43f0SAndreas Fenkart * 217b5cd43f0SAndreas Fenkart * possible return values: 218b5cd43f0SAndreas Fenkart * 0 - closed 219b5cd43f0SAndreas Fenkart * 1 - open 220b5cd43f0SAndreas Fenkart */ 22180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 222b5cd43f0SAndreas Fenkart 22380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 224a45c6cb8SMadhusudhan Chikkature }; 225a45c6cb8SMadhusudhan Chikkature 22659445b10SNishanth Menon struct omap_mmc_of_data { 22759445b10SNishanth Menon u32 reg_offset; 22859445b10SNishanth Menon u8 controller_flags; 22959445b10SNishanth Menon }; 23059445b10SNishanth Menon 231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232bf129e1cSBalaji T K 23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236db0fefc5SAdrian Hunter 23741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 241db0fefc5SAdrian Hunter { 2429ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243db0fefc5SAdrian Hunter 24441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 247b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 248b702b106SAdrian Hunter 2492a17f844SKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc, int vdd) 2502a17f844SKishon Vijay Abraham I { 2512a17f844SKishon Vijay Abraham I int ret; 2522a17f844SKishon Vijay Abraham I 2532a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2542a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 2552a17f844SKishon Vijay Abraham I if (ret) 2562a17f844SKishon Vijay Abraham I return ret; 2572a17f844SKishon Vijay Abraham I } 2582a17f844SKishon Vijay Abraham I 2592a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 2602a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 2612a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2622a17f844SKishon Vijay Abraham I if (ret) { 2632a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2642a17f844SKishon Vijay Abraham I goto err_vqmmc; 2652a17f844SKishon Vijay Abraham I } 2662a17f844SKishon Vijay Abraham I } 2672a17f844SKishon Vijay Abraham I 2682a17f844SKishon Vijay Abraham I return 0; 2692a17f844SKishon Vijay Abraham I 2702a17f844SKishon Vijay Abraham I err_vqmmc: 2712a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) 2722a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2732a17f844SKishon Vijay Abraham I 2742a17f844SKishon Vijay Abraham I return ret; 2752a17f844SKishon Vijay Abraham I } 2762a17f844SKishon Vijay Abraham I 2772a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2782a17f844SKishon Vijay Abraham I { 2792a17f844SKishon Vijay Abraham I int ret; 2802a17f844SKishon Vijay Abraham I int status; 2812a17f844SKishon Vijay Abraham I 2822a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 2832a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2842a17f844SKishon Vijay Abraham I if (ret) { 2852a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2862a17f844SKishon Vijay Abraham I return ret; 2872a17f844SKishon Vijay Abraham I } 2882a17f844SKishon Vijay Abraham I } 2892a17f844SKishon Vijay Abraham I 2902a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2912a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2922a17f844SKishon Vijay Abraham I if (ret) 2932a17f844SKishon Vijay Abraham I goto err_set_ocr; 2942a17f844SKishon Vijay Abraham I } 2952a17f844SKishon Vijay Abraham I 2962a17f844SKishon Vijay Abraham I return 0; 2972a17f844SKishon Vijay Abraham I 2982a17f844SKishon Vijay Abraham I err_set_ocr: 2992a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 3002a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3012a17f844SKishon Vijay Abraham I if (status) 3022a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3032a17f844SKishon Vijay Abraham I } 3042a17f844SKishon Vijay Abraham I 3052a17f844SKishon Vijay Abraham I return ret; 3062a17f844SKishon Vijay Abraham I } 3072a17f844SKishon Vijay Abraham I 308ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 309ec85c95eSKishon Vijay Abraham I int vdd) 310ec85c95eSKishon Vijay Abraham I { 311ec85c95eSKishon Vijay Abraham I int ret; 312ec85c95eSKishon Vijay Abraham I 313ec85c95eSKishon Vijay Abraham I if (!host->pbias) 314ec85c95eSKishon Vijay Abraham I return 0; 315ec85c95eSKishon Vijay Abraham I 316ec85c95eSKishon Vijay Abraham I if (power_on) { 317ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 318ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 319ec85c95eSKishon Vijay Abraham I VDD_1V8); 320ec85c95eSKishon Vijay Abraham I else 321ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 322ec85c95eSKishon Vijay Abraham I VDD_3V0); 323ec85c95eSKishon Vijay Abraham I if (ret < 0) { 324ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 325ec85c95eSKishon Vijay Abraham I return ret; 326ec85c95eSKishon Vijay Abraham I } 327ec85c95eSKishon Vijay Abraham I 328ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 0) { 329ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 330ec85c95eSKishon Vijay Abraham I if (ret) { 331ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 332ec85c95eSKishon Vijay Abraham I return ret; 333ec85c95eSKishon Vijay Abraham I } 334ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 1; 335ec85c95eSKishon Vijay Abraham I } 336ec85c95eSKishon Vijay Abraham I } else { 337ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 1) { 338ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 339ec85c95eSKishon Vijay Abraham I if (ret) { 340ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 341ec85c95eSKishon Vijay Abraham I return ret; 342ec85c95eSKishon Vijay Abraham I } 343ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 0; 344ec85c95eSKishon Vijay Abraham I } 345ec85c95eSKishon Vijay Abraham I } 346ec85c95eSKishon Vijay Abraham I 347ec85c95eSKishon Vijay Abraham I return 0; 348ec85c95eSKishon Vijay Abraham I } 349ec85c95eSKishon Vijay Abraham I 35080412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 351db0fefc5SAdrian Hunter { 352db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 353db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 354aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 355db0fefc5SAdrian Hunter int ret = 0; 356db0fefc5SAdrian Hunter 357f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 358f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 359f7f0f035SAndreas Fenkart 360db0fefc5SAdrian Hunter /* 361db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 362db0fefc5SAdrian Hunter * voltage always-on regulator. 363db0fefc5SAdrian Hunter */ 364aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 365db0fefc5SAdrian Hunter return 0; 366db0fefc5SAdrian Hunter 367326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 36880412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 369db0fefc5SAdrian Hunter 370ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 371ec85c95eSKishon Vijay Abraham I if (ret) 372229f3292SKishon Vijay Abraham I return ret; 373e99448ffSBalaji T K 374db0fefc5SAdrian Hunter /* 375db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 376db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 377db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 378db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 379db0fefc5SAdrian Hunter * 380db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 381db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 382db0fefc5SAdrian Hunter * 383db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 384db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 385db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 386db0fefc5SAdrian Hunter */ 387db0fefc5SAdrian Hunter if (power_on) { 3882a17f844SKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc, vdd); 389229f3292SKishon Vijay Abraham I if (ret) 390229f3292SKishon Vijay Abraham I return ret; 391db0fefc5SAdrian Hunter } else { 3922a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 393229f3292SKishon Vijay Abraham I if (ret) 394229f3292SKishon Vijay Abraham I return ret; 39599fc5131SLinus Walleij } 396db0fefc5SAdrian Hunter 397ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 398ec85c95eSKishon Vijay Abraham I if (ret) 399229f3292SKishon Vijay Abraham I goto err_set_voltage; 400e99448ffSBalaji T K 401326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 40280412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 403db0fefc5SAdrian Hunter 404229f3292SKishon Vijay Abraham I return 0; 405229f3292SKishon Vijay Abraham I 406229f3292SKishon Vijay Abraham I err_set_voltage: 4072a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 408229f3292SKishon Vijay Abraham I 409db0fefc5SAdrian Hunter return ret; 410db0fefc5SAdrian Hunter } 411db0fefc5SAdrian Hunter 412db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 413db0fefc5SAdrian Hunter { 41464be9782Skishore kadiyala int ocr_value = 0; 4157d607f91SKishon Vijay Abraham I int ret; 416aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 417db0fefc5SAdrian Hunter 418f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 419f7f0f035SAndreas Fenkart return 0; 420f7f0f035SAndreas Fenkart 421aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 422aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 423aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 4247d607f91SKishon Vijay Abraham I if (ret != -ENODEV) 4257d607f91SKishon Vijay Abraham I return ret; 4267d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 427aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 428aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 429db0fefc5SAdrian Hunter } else { 430aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 431b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 432326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 433987fd49bSBalaji T K } 434db0fefc5SAdrian Hunter 435db0fefc5SAdrian Hunter /* Allow an aux regulator */ 436aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 437aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 438aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 4396a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 4406a9b2ff0SKishon Vijay Abraham I return ret; 4416a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 442aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 443aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 4446a9b2ff0SKishon Vijay Abraham I } 445db0fefc5SAdrian Hunter 446c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 447c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 448c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 4496a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 4506a9b2ff0SKishon Vijay Abraham I return ret; 4516a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 452c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 453c299dc39SKishon Vijay Abraham I host->pbias = NULL; 4546a9b2ff0SKishon Vijay Abraham I } 455e99448ffSBalaji T K 456b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 457326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 458b1c1df7aSBalaji T K return 0; 459db0fefc5SAdrian Hunter /* 460987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 461987fd49bSBalaji T K * to increase usecount and then disable it. 462db0fefc5SAdrian Hunter */ 463aa9a6801SKishon Vijay Abraham I if ((mmc->supply.vmmc && regulator_is_enabled(mmc->supply.vmmc) > 0) || 464aa9a6801SKishon Vijay Abraham I (mmc->supply.vqmmc && regulator_is_enabled(mmc->supply.vqmmc))) { 465326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 466e840ce13SAdrian Hunter 467f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, vdd); 468f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 469db0fefc5SAdrian Hunter } 470db0fefc5SAdrian Hunter 471db0fefc5SAdrian Hunter return 0; 472db0fefc5SAdrian Hunter } 473db0fefc5SAdrian Hunter 474b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 475b702b106SAdrian Hunter { 476b702b106SAdrian Hunter return 1; 477b702b106SAdrian Hunter } 478b702b106SAdrian Hunter 479b702b106SAdrian Hunter #else 480b702b106SAdrian Hunter 481f7f0f035SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 482f7f0f035SAndreas Fenkart { 483f7f0f035SAndreas Fenkart return 0; 484f7f0f035SAndreas Fenkart } 485f7f0f035SAndreas Fenkart 486b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 487b702b106SAdrian Hunter { 488b702b106SAdrian Hunter return -EINVAL; 489b702b106SAdrian Hunter } 490b702b106SAdrian Hunter 491b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 492b702b106SAdrian Hunter { 493b702b106SAdrian Hunter return 0; 494b702b106SAdrian Hunter } 495b702b106SAdrian Hunter 496b702b106SAdrian Hunter #endif 497b702b106SAdrian Hunter 498cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 49941afa314SNeilBrown 50041afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 50141afa314SNeilBrown struct omap_hsmmc_host *host, 5021e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 503b702b106SAdrian Hunter { 504b702b106SAdrian Hunter int ret; 505b702b106SAdrian Hunter 506b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 507b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 508b702b106SAdrian Hunter if (ret) 509b702b106SAdrian Hunter return ret; 510cde592cbSAndreas Fenkart 511cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 512cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 513b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 514b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 515cde592cbSAndreas Fenkart if (ret) 516cde592cbSAndreas Fenkart return ret; 517cde592cbSAndreas Fenkart 518cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 519326119c9SAndreas Fenkart } 520b702b106SAdrian Hunter 521326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 52241afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 523b702b106SAdrian Hunter if (ret) 52441afa314SNeilBrown return ret; 525326119c9SAndreas Fenkart } 526b702b106SAdrian Hunter 527b702b106SAdrian Hunter return 0; 528b702b106SAdrian Hunter } 529b702b106SAdrian Hunter 530a45c6cb8SMadhusudhan Chikkature /* 531e0c7f99bSAndy Shevchenko * Start clock to the card 532e0c7f99bSAndy Shevchenko */ 533e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 534e0c7f99bSAndy Shevchenko { 535e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 536e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 537e0c7f99bSAndy Shevchenko } 538e0c7f99bSAndy Shevchenko 539e0c7f99bSAndy Shevchenko /* 540a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 541a45c6cb8SMadhusudhan Chikkature */ 54270a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 543a45c6cb8SMadhusudhan Chikkature { 544a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 545a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 546a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5477122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 548a45c6cb8SMadhusudhan Chikkature } 549a45c6cb8SMadhusudhan Chikkature 55093caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 55193caf8e6SAdrian Hunter struct mmc_command *cmd) 552b417577dSAdrian Hunter { 5532cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5542cd3a2a5SAndreas Fenkart unsigned long flags; 555b417577dSAdrian Hunter 556b417577dSAdrian Hunter if (host->use_dma) 5572cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 558b417577dSAdrian Hunter 55993caf8e6SAdrian Hunter /* Disable timeout for erases */ 56093caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 561a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 56293caf8e6SAdrian Hunter 5632cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 564b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 565b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5662cd3a2a5SAndreas Fenkart 5672cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5682cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5692cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 570b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5712cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 572b417577dSAdrian Hunter } 573b417577dSAdrian Hunter 574b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 575b417577dSAdrian Hunter { 5762cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5772cd3a2a5SAndreas Fenkart unsigned long flags; 5782cd3a2a5SAndreas Fenkart 5792cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5802cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5812cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5822cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5832cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5842cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 585b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5862cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 587b417577dSAdrian Hunter } 588b417577dSAdrian Hunter 589ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 590d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 591ac330f44SAndy Shevchenko { 592ac330f44SAndy Shevchenko u16 dsor = 0; 593ac330f44SAndy Shevchenko 594ac330f44SAndy Shevchenko if (ios->clock) { 595d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 596ed164182SBalaji T K if (dsor > CLKD_MAX) 597ed164182SBalaji T K dsor = CLKD_MAX; 598ac330f44SAndy Shevchenko } 599ac330f44SAndy Shevchenko 600ac330f44SAndy Shevchenko return dsor; 601ac330f44SAndy Shevchenko } 602ac330f44SAndy Shevchenko 6035934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6045934df2fSAndy Shevchenko { 6055934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6065934df2fSAndy Shevchenko unsigned long regval; 6075934df2fSAndy Shevchenko unsigned long timeout; 608cd587096SHebbar, Gururaja unsigned long clkdiv; 6095934df2fSAndy Shevchenko 6108986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6115934df2fSAndy Shevchenko 6125934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6135934df2fSAndy Shevchenko 6145934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6155934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 616cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 617cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6185934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6195934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6205934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6215934df2fSAndy Shevchenko 6225934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6235934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6245934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6255934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6265934df2fSAndy Shevchenko cpu_relax(); 6275934df2fSAndy Shevchenko 628cd587096SHebbar, Gururaja /* 629cd587096SHebbar, Gururaja * Enable High-Speed Support 630cd587096SHebbar, Gururaja * Pre-Requisites 631cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 632cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 633cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 634cd587096SHebbar, Gururaja * in capabilities register 635cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 636cd587096SHebbar, Gururaja */ 637326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6385438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 639903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 640cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 641cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 642cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 643cd587096SHebbar, Gururaja regval |= HSPE; 644cd587096SHebbar, Gururaja else 645cd587096SHebbar, Gururaja regval &= ~HSPE; 646cd587096SHebbar, Gururaja 647cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 648cd587096SHebbar, Gururaja } 649cd587096SHebbar, Gururaja 6505934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6515934df2fSAndy Shevchenko } 6525934df2fSAndy Shevchenko 6533796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6543796fb8aSAndy Shevchenko { 6553796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6563796fb8aSAndy Shevchenko u32 con; 6573796fb8aSAndy Shevchenko 6583796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 659903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 660903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 66103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 66203b5d924SBalaji T K else 66303b5d924SBalaji T K con &= ~DDR; 6643796fb8aSAndy Shevchenko switch (ios->bus_width) { 6653796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6663796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6673796fb8aSAndy Shevchenko break; 6683796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6693796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6703796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6713796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6723796fb8aSAndy Shevchenko break; 6733796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6743796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6753796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6763796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6773796fb8aSAndy Shevchenko break; 6783796fb8aSAndy Shevchenko } 6793796fb8aSAndy Shevchenko } 6803796fb8aSAndy Shevchenko 6813796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6823796fb8aSAndy Shevchenko { 6833796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6843796fb8aSAndy Shevchenko u32 con; 6853796fb8aSAndy Shevchenko 6863796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6873796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6883796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6893796fb8aSAndy Shevchenko else 6903796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6913796fb8aSAndy Shevchenko } 6923796fb8aSAndy Shevchenko 69311dd62a7SDenis Karpov #ifdef CONFIG_PM 69411dd62a7SDenis Karpov 69511dd62a7SDenis Karpov /* 69611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 69711dd62a7SDenis Karpov * power state change. 69811dd62a7SDenis Karpov */ 69970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70011dd62a7SDenis Karpov { 70111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7023796fb8aSAndy Shevchenko u32 hctl, capa; 70311dd62a7SDenis Karpov unsigned long timeout; 70411dd62a7SDenis Karpov 7050a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7060a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7070a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7080a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7090a82e06eSTony Lindgren return 0; 7100a82e06eSTony Lindgren 7110a82e06eSTony Lindgren host->context_loss++; 7120a82e06eSTony Lindgren 713c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 71411dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 71511dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 71611dd62a7SDenis Karpov hctl = SDVS18; 71711dd62a7SDenis Karpov else 71811dd62a7SDenis Karpov hctl = SDVS30; 71911dd62a7SDenis Karpov capa = VS30 | VS18; 72011dd62a7SDenis Karpov } else { 72111dd62a7SDenis Karpov hctl = SDVS18; 72211dd62a7SDenis Karpov capa = VS18; 72311dd62a7SDenis Karpov } 72411dd62a7SDenis Karpov 7255a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7265a52b08bSBalaji T K hctl |= IWE; 7275a52b08bSBalaji T K 72811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 72911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 73011dd62a7SDenis Karpov 73111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 73211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 73311dd62a7SDenis Karpov 73411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 73511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 73611dd62a7SDenis Karpov 73711dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 73811dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 73911dd62a7SDenis Karpov && time_before(jiffies, timeout)) 74011dd62a7SDenis Karpov ; 74111dd62a7SDenis Karpov 7422cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7432cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7442cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 74511dd62a7SDenis Karpov 74611dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 74711dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 74811dd62a7SDenis Karpov goto out; 74911dd62a7SDenis Karpov 7503796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 75111dd62a7SDenis Karpov 7525934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 75311dd62a7SDenis Karpov 7543796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7553796fb8aSAndy Shevchenko 75611dd62a7SDenis Karpov out: 7570a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7580a82e06eSTony Lindgren host->context_loss); 75911dd62a7SDenis Karpov return 0; 76011dd62a7SDenis Karpov } 76111dd62a7SDenis Karpov 76211dd62a7SDenis Karpov /* 76311dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 76411dd62a7SDenis Karpov */ 76570a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 76611dd62a7SDenis Karpov { 7670a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7680a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7690a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7700a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 77111dd62a7SDenis Karpov } 77211dd62a7SDenis Karpov 77311dd62a7SDenis Karpov #else 77411dd62a7SDenis Karpov 77570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 77611dd62a7SDenis Karpov { 77711dd62a7SDenis Karpov return 0; 77811dd62a7SDenis Karpov } 77911dd62a7SDenis Karpov 78070a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 78111dd62a7SDenis Karpov { 78211dd62a7SDenis Karpov } 78311dd62a7SDenis Karpov 78411dd62a7SDenis Karpov #endif 78511dd62a7SDenis Karpov 786a45c6cb8SMadhusudhan Chikkature /* 787a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 788a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 789a45c6cb8SMadhusudhan Chikkature */ 79070a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 791a45c6cb8SMadhusudhan Chikkature { 792a45c6cb8SMadhusudhan Chikkature int reg = 0; 793a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 794a45c6cb8SMadhusudhan Chikkature 795b62f6228SAdrian Hunter if (host->protect_card) 796b62f6228SAdrian Hunter return; 797b62f6228SAdrian Hunter 798a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 799b417577dSAdrian Hunter 800b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 801a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 802a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 803a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 804a45c6cb8SMadhusudhan Chikkature 805a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 806a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 807a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 808a45c6cb8SMadhusudhan Chikkature 809a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 810a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 811c653a6d4SAdrian Hunter 812c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 813c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 814c653a6d4SAdrian Hunter 815a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 816a45c6cb8SMadhusudhan Chikkature } 817a45c6cb8SMadhusudhan Chikkature 818a45c6cb8SMadhusudhan Chikkature static inline 81970a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 820a45c6cb8SMadhusudhan Chikkature { 821a45c6cb8SMadhusudhan Chikkature int r = 1; 822a45c6cb8SMadhusudhan Chikkature 823b5cd43f0SAndreas Fenkart if (host->get_cover_state) 82480412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 825a45c6cb8SMadhusudhan Chikkature return r; 826a45c6cb8SMadhusudhan Chikkature } 827a45c6cb8SMadhusudhan Chikkature 828a45c6cb8SMadhusudhan Chikkature static ssize_t 82970a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 830a45c6cb8SMadhusudhan Chikkature char *buf) 831a45c6cb8SMadhusudhan Chikkature { 832a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 83370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 834a45c6cb8SMadhusudhan Chikkature 83570a3341aSDenis Karpov return sprintf(buf, "%s\n", 83670a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 837a45c6cb8SMadhusudhan Chikkature } 838a45c6cb8SMadhusudhan Chikkature 83970a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 840a45c6cb8SMadhusudhan Chikkature 841a45c6cb8SMadhusudhan Chikkature static ssize_t 84270a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 843a45c6cb8SMadhusudhan Chikkature char *buf) 844a45c6cb8SMadhusudhan Chikkature { 845a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 84670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 847a45c6cb8SMadhusudhan Chikkature 848326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 849a45c6cb8SMadhusudhan Chikkature } 850a45c6cb8SMadhusudhan Chikkature 85170a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 852a45c6cb8SMadhusudhan Chikkature 853a45c6cb8SMadhusudhan Chikkature /* 854a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 855a45c6cb8SMadhusudhan Chikkature */ 856a45c6cb8SMadhusudhan Chikkature static void 85770a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 858a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 859a45c6cb8SMadhusudhan Chikkature { 860a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 861a45c6cb8SMadhusudhan Chikkature 8628986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 863a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 864a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 865a45c6cb8SMadhusudhan Chikkature 86693caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 867a45c6cb8SMadhusudhan Chikkature 8684a694dc9SAdrian Hunter host->response_busy = 0; 869a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 870a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 871a45c6cb8SMadhusudhan Chikkature resptype = 1; 8724a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8734a694dc9SAdrian Hunter resptype = 3; 8744a694dc9SAdrian Hunter host->response_busy = 1; 8754a694dc9SAdrian Hunter } else 876a45c6cb8SMadhusudhan Chikkature resptype = 2; 877a45c6cb8SMadhusudhan Chikkature } 878a45c6cb8SMadhusudhan Chikkature 879a45c6cb8SMadhusudhan Chikkature /* 880a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 881a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 882a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 883a45c6cb8SMadhusudhan Chikkature */ 884a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 885a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 886a45c6cb8SMadhusudhan Chikkature 887a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 888a45c6cb8SMadhusudhan Chikkature 889a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 890a2e77152SBalaji T K host->mrq->sbc) { 891a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 892a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 893a2e77152SBalaji T K } 894a45c6cb8SMadhusudhan Chikkature if (data) { 895a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 896a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 897a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 898a45c6cb8SMadhusudhan Chikkature else 899a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 900a45c6cb8SMadhusudhan Chikkature } 901a45c6cb8SMadhusudhan Chikkature 902a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 903a7e96879SVenkatraman S cmdreg |= DMAE; 904a45c6cb8SMadhusudhan Chikkature 905b417577dSAdrian Hunter host->req_in_progress = 1; 9064dffd7a2SAdrian Hunter 907a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 908a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 909a45c6cb8SMadhusudhan Chikkature } 910a45c6cb8SMadhusudhan Chikkature 9110ccd76d4SJuha Yrjola static int 91270a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9130ccd76d4SJuha Yrjola { 9140ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9150ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9160ccd76d4SJuha Yrjola else 9170ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9180ccd76d4SJuha Yrjola } 9190ccd76d4SJuha Yrjola 920c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 921c5c98927SRussell King struct mmc_data *data) 922c5c98927SRussell King { 923c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 924c5c98927SRussell King } 925c5c98927SRussell King 926b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 927b417577dSAdrian Hunter { 928b417577dSAdrian Hunter int dma_ch; 92931463b14SVenkatraman S unsigned long flags; 930b417577dSAdrian Hunter 93131463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 932b417577dSAdrian Hunter host->req_in_progress = 0; 933b417577dSAdrian Hunter dma_ch = host->dma_ch; 93431463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 935b417577dSAdrian Hunter 936b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 937b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 938b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 939b417577dSAdrian Hunter return; 940b417577dSAdrian Hunter host->mrq = NULL; 941b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 942f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 943f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 944b417577dSAdrian Hunter } 945b417577dSAdrian Hunter 946a45c6cb8SMadhusudhan Chikkature /* 947a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 948a45c6cb8SMadhusudhan Chikkature */ 949a45c6cb8SMadhusudhan Chikkature static void 95070a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 951a45c6cb8SMadhusudhan Chikkature { 9524a694dc9SAdrian Hunter if (!data) { 9534a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9544a694dc9SAdrian Hunter 95523050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 95623050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 95723050103SAdrian Hunter host->response_busy) { 95823050103SAdrian Hunter host->response_busy = 0; 95923050103SAdrian Hunter return; 96023050103SAdrian Hunter } 96123050103SAdrian Hunter 962b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9634a694dc9SAdrian Hunter return; 9644a694dc9SAdrian Hunter } 9654a694dc9SAdrian Hunter 966a45c6cb8SMadhusudhan Chikkature host->data = NULL; 967a45c6cb8SMadhusudhan Chikkature 968a45c6cb8SMadhusudhan Chikkature if (!data->error) 969a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 970a45c6cb8SMadhusudhan Chikkature else 971a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 972a45c6cb8SMadhusudhan Chikkature 973bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 974fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 975bf129e1cSBalaji T K else 976bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 977a45c6cb8SMadhusudhan Chikkature } 978a45c6cb8SMadhusudhan Chikkature 979a45c6cb8SMadhusudhan Chikkature /* 980a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 981a45c6cb8SMadhusudhan Chikkature */ 982a45c6cb8SMadhusudhan Chikkature static void 98370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 984a45c6cb8SMadhusudhan Chikkature { 985bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 986a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9872177fa94SBalaji T K host->cmd = NULL; 988bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 989bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 990bf129e1cSBalaji T K host->mrq->data); 991bf129e1cSBalaji T K return; 992bf129e1cSBalaji T K } 993bf129e1cSBalaji T K 9942177fa94SBalaji T K host->cmd = NULL; 9952177fa94SBalaji T K 996a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 997a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 998a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 999a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1000a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1001a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1002a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1003a45c6cb8SMadhusudhan Chikkature } else { 1004a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1005a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1006a45c6cb8SMadhusudhan Chikkature } 1007a45c6cb8SMadhusudhan Chikkature } 1008b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1009d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1010a45c6cb8SMadhusudhan Chikkature } 1011a45c6cb8SMadhusudhan Chikkature 1012a45c6cb8SMadhusudhan Chikkature /* 1013a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1014a45c6cb8SMadhusudhan Chikkature */ 101570a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1016a45c6cb8SMadhusudhan Chikkature { 1017b417577dSAdrian Hunter int dma_ch; 101831463b14SVenkatraman S unsigned long flags; 1019b417577dSAdrian Hunter 102082788ff5SJarkko Lavinen host->data->error = errno; 1021a45c6cb8SMadhusudhan Chikkature 102231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1023b417577dSAdrian Hunter dma_ch = host->dma_ch; 1024b417577dSAdrian Hunter host->dma_ch = -1; 102531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1026b417577dSAdrian Hunter 1027b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1028c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1029c5c98927SRussell King 1030c5c98927SRussell King dmaengine_terminate_all(chan); 1031c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1032c5c98927SRussell King host->data->sg, host->data->sg_len, 103370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1034c5c98927SRussell King 1035053bf34fSPer Forlin host->data->host_cookie = 0; 1036a45c6cb8SMadhusudhan Chikkature } 1037a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1038a45c6cb8SMadhusudhan Chikkature } 1039a45c6cb8SMadhusudhan Chikkature 1040a45c6cb8SMadhusudhan Chikkature /* 1041a45c6cb8SMadhusudhan Chikkature * Readable error output 1042a45c6cb8SMadhusudhan Chikkature */ 1043a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1044699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1045a45c6cb8SMadhusudhan Chikkature { 1046a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 104770a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1048699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1049699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1050699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1051699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1052a45c6cb8SMadhusudhan Chikkature }; 1053a45c6cb8SMadhusudhan Chikkature char res[256]; 1054a45c6cb8SMadhusudhan Chikkature char *buf = res; 1055a45c6cb8SMadhusudhan Chikkature int len, i; 1056a45c6cb8SMadhusudhan Chikkature 1057a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1058a45c6cb8SMadhusudhan Chikkature buf += len; 1059a45c6cb8SMadhusudhan Chikkature 106070a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1061a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 106270a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1063a45c6cb8SMadhusudhan Chikkature buf += len; 1064a45c6cb8SMadhusudhan Chikkature } 1065a45c6cb8SMadhusudhan Chikkature 10668986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1067a45c6cb8SMadhusudhan Chikkature } 1068699b958bSAdrian Hunter #else 1069699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1070699b958bSAdrian Hunter u32 status) 1071699b958bSAdrian Hunter { 1072699b958bSAdrian Hunter } 1073a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1074a45c6cb8SMadhusudhan Chikkature 10753ebf74b1SJean Pihet /* 10763ebf74b1SJean Pihet * MMC controller internal state machines reset 10773ebf74b1SJean Pihet * 10783ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10793ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10803ebf74b1SJean Pihet * Can be called from interrupt context 10813ebf74b1SJean Pihet */ 108270a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10833ebf74b1SJean Pihet unsigned long bit) 10843ebf74b1SJean Pihet { 10853ebf74b1SJean Pihet unsigned long i = 0; 10861e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10873ebf74b1SJean Pihet 10883ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10893ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10903ebf74b1SJean Pihet 109107ad64b6SMadhusudhan Chikkature /* 109207ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 109307ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 109407ad64b6SMadhusudhan Chikkature */ 1095326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1096b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 109707ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10981e881786SJianpeng Ma udelay(1); 109907ad64b6SMadhusudhan Chikkature } 110007ad64b6SMadhusudhan Chikkature i = 0; 110107ad64b6SMadhusudhan Chikkature 11023ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 11033ebf74b1SJean Pihet (i++ < limit)) 11041e881786SJianpeng Ma udelay(1); 11053ebf74b1SJean Pihet 11063ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11073ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11083ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11093ebf74b1SJean Pihet __func__); 11103ebf74b1SJean Pihet } 1111a45c6cb8SMadhusudhan Chikkature 111225e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 111325e1897bSBalaji T K int err, int end_cmd) 1114ae4bf788SVenkatraman S { 111525e1897bSBalaji T K if (end_cmd) { 111694d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 111725e1897bSBalaji T K if (host->cmd) 1118ae4bf788SVenkatraman S host->cmd->error = err; 111925e1897bSBalaji T K } 1120ae4bf788SVenkatraman S 1121ae4bf788SVenkatraman S if (host->data) { 1122ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1123ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1124dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1125dc7745bdSBalaji T K host->mrq->cmd->error = err; 1126ae4bf788SVenkatraman S } 1127ae4bf788SVenkatraman S 1128b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1129a45c6cb8SMadhusudhan Chikkature { 1130a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1131b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1132a2e77152SBalaji T K int error = 0; 1133a45c6cb8SMadhusudhan Chikkature 1134a45c6cb8SMadhusudhan Chikkature data = host->data; 11358986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1136a45c6cb8SMadhusudhan Chikkature 1137a7e96879SVenkatraman S if (status & ERR_EN) { 1138699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11394a694dc9SAdrian Hunter 1140a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1141a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1142408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1143408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1144408806f7SKishon Vijay Abraham I host->response_busy = 0; 1145408806f7SKishon Vijay Abraham I } 1146a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 114725e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11485027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11495027cd1eSVignesh R BADA_EN)) 115025e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 115125e1897bSBalaji T K 1152a2e77152SBalaji T K if (status & ACE_EN) { 1153a2e77152SBalaji T K u32 ac12; 1154a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1155a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1156a2e77152SBalaji T K end_cmd = 1; 1157a2e77152SBalaji T K if (ac12 & ACTO) 1158a2e77152SBalaji T K error = -ETIMEDOUT; 1159a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1160a2e77152SBalaji T K error = -EILSEQ; 1161a2e77152SBalaji T K host->mrq->sbc->error = error; 1162a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1163a2e77152SBalaji T K } 1164a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1165a2e77152SBalaji T K } 1166a45c6cb8SMadhusudhan Chikkature } 1167a45c6cb8SMadhusudhan Chikkature 11687472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1169a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 117070a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1171a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 117270a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1173b417577dSAdrian Hunter } 1174a45c6cb8SMadhusudhan Chikkature 1175b417577dSAdrian Hunter /* 1176b417577dSAdrian Hunter * MMC controller IRQ handler 1177b417577dSAdrian Hunter */ 1178b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1179b417577dSAdrian Hunter { 1180b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1181b417577dSAdrian Hunter int status; 1182b417577dSAdrian Hunter 1183b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11842cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11852cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1186b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11871f6b9fa4SVenkatraman S 11882cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11892cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11902cd3a2a5SAndreas Fenkart 1191b417577dSAdrian Hunter /* Flush posted write */ 1192b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11931f6b9fa4SVenkatraman S } 11944dffd7a2SAdrian Hunter 1195a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1196a45c6cb8SMadhusudhan Chikkature } 1197a45c6cb8SMadhusudhan Chikkature 119870a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1199e13bb300SAdrian Hunter { 1200e13bb300SAdrian Hunter unsigned long i; 1201e13bb300SAdrian Hunter 1202e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1203e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1204e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1205e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1206e13bb300SAdrian Hunter break; 1207e13bb300SAdrian Hunter cpu_relax(); 1208e13bb300SAdrian Hunter } 1209e13bb300SAdrian Hunter } 1210e13bb300SAdrian Hunter 1211a45c6cb8SMadhusudhan Chikkature /* 1212eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1213eb250826SDavid Brownell * 1214eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1215eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1216eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1217a45c6cb8SMadhusudhan Chikkature */ 121870a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1219a45c6cb8SMadhusudhan Chikkature { 1220a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1221a45c6cb8SMadhusudhan Chikkature int ret; 1222a45c6cb8SMadhusudhan Chikkature 1223a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1224fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1225cd03d9a8SRajendra Nayak if (host->dbclk) 122694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1227a45c6cb8SMadhusudhan Chikkature 1228a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1229f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1230a45c6cb8SMadhusudhan Chikkature 1231a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12322bec0893SAdrian Hunter if (!ret) 1233f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1234fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1235cd03d9a8SRajendra Nayak if (host->dbclk) 123694c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12372bec0893SAdrian Hunter 1238a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1239a45c6cb8SMadhusudhan Chikkature goto err; 1240a45c6cb8SMadhusudhan Chikkature 1241a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1242a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1243a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1244eb250826SDavid Brownell 1245a45c6cb8SMadhusudhan Chikkature /* 1246a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1247a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 124870a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1249a45c6cb8SMadhusudhan Chikkature * 1250eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1251eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1252eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1253eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1254eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1255eb250826SDavid Brownell * 1256eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1257eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1258eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1259a45c6cb8SMadhusudhan Chikkature */ 1260eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1261a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1262eb250826SDavid Brownell else 1263eb250826SDavid Brownell reg_val |= SDVS30; 1264a45c6cb8SMadhusudhan Chikkature 1265a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1266e13bb300SAdrian Hunter set_sd_bus_power(host); 1267a45c6cb8SMadhusudhan Chikkature 1268a45c6cb8SMadhusudhan Chikkature return 0; 1269a45c6cb8SMadhusudhan Chikkature err: 1270b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1271a45c6cb8SMadhusudhan Chikkature return ret; 1272a45c6cb8SMadhusudhan Chikkature } 1273a45c6cb8SMadhusudhan Chikkature 1274b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1275b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1276b62f6228SAdrian Hunter { 1277b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1278b62f6228SAdrian Hunter return; 1279b62f6228SAdrian Hunter 1280b62f6228SAdrian Hunter host->reqs_blocked = 0; 128180412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1282b62f6228SAdrian Hunter if (host->protect_card) { 12832cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1284b62f6228SAdrian Hunter "card is now accessible\n", 1285b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1286b62f6228SAdrian Hunter host->protect_card = 0; 1287b62f6228SAdrian Hunter } 1288b62f6228SAdrian Hunter } else { 1289b62f6228SAdrian Hunter if (!host->protect_card) { 12902cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1291b62f6228SAdrian Hunter "card is now inaccessible\n", 1292b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1293b62f6228SAdrian Hunter host->protect_card = 1; 1294b62f6228SAdrian Hunter } 1295b62f6228SAdrian Hunter } 1296b62f6228SAdrian Hunter } 1297b62f6228SAdrian Hunter 1298a45c6cb8SMadhusudhan Chikkature /* 1299cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1300cde592cbSAndreas Fenkart */ 1301cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1302cde592cbSAndreas Fenkart { 1303cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1304cde592cbSAndreas Fenkart 1305cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1306cde592cbSAndreas Fenkart 1307cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1308cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1309cde592cbSAndreas Fenkart return IRQ_HANDLED; 1310cde592cbSAndreas Fenkart } 1311cde592cbSAndreas Fenkart 1312c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13130ccd76d4SJuha Yrjola { 1314c5c98927SRussell King struct omap_hsmmc_host *host = param; 1315c5c98927SRussell King struct dma_chan *chan; 1316770d7432SAdrian Hunter struct mmc_data *data; 1317c5c98927SRussell King int req_in_progress; 1318a45c6cb8SMadhusudhan Chikkature 1319c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1320b417577dSAdrian Hunter if (host->dma_ch < 0) { 1321c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1322a45c6cb8SMadhusudhan Chikkature return; 1323b417577dSAdrian Hunter } 1324a45c6cb8SMadhusudhan Chikkature 1325770d7432SAdrian Hunter data = host->mrq->data; 1326c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13279782aff8SPer Forlin if (!data->host_cookie) 1328c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1329c5c98927SRussell King data->sg, data->sg_len, 1330b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1331b417577dSAdrian Hunter 1332b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1333a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1334c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1335b417577dSAdrian Hunter 1336b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1337b417577dSAdrian Hunter if (!req_in_progress) { 1338b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1339b417577dSAdrian Hunter 1340b417577dSAdrian Hunter host->mrq = NULL; 1341b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1342f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1343f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1344b417577dSAdrian Hunter } 1345a45c6cb8SMadhusudhan Chikkature } 1346a45c6cb8SMadhusudhan Chikkature 13479782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13489782aff8SPer Forlin struct mmc_data *data, 1349c5c98927SRussell King struct omap_hsmmc_next *next, 135026b88520SRussell King struct dma_chan *chan) 13519782aff8SPer Forlin { 13529782aff8SPer Forlin int dma_len; 13539782aff8SPer Forlin 13549782aff8SPer Forlin if (!next && data->host_cookie && 13559782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13562cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13579782aff8SPer Forlin " host->next_data.cookie %d\n", 13589782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13599782aff8SPer Forlin data->host_cookie = 0; 13609782aff8SPer Forlin } 13619782aff8SPer Forlin 13629782aff8SPer Forlin /* Check if next job is already prepared */ 1363b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 136426b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13659782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13669782aff8SPer Forlin 13679782aff8SPer Forlin } else { 13689782aff8SPer Forlin dma_len = host->next_data.dma_len; 13699782aff8SPer Forlin host->next_data.dma_len = 0; 13709782aff8SPer Forlin } 13719782aff8SPer Forlin 13729782aff8SPer Forlin 13739782aff8SPer Forlin if (dma_len == 0) 13749782aff8SPer Forlin return -EINVAL; 13759782aff8SPer Forlin 13769782aff8SPer Forlin if (next) { 13779782aff8SPer Forlin next->dma_len = dma_len; 13789782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13799782aff8SPer Forlin } else 13809782aff8SPer Forlin host->dma_len = dma_len; 13819782aff8SPer Forlin 13829782aff8SPer Forlin return 0; 13839782aff8SPer Forlin } 13849782aff8SPer Forlin 1385a45c6cb8SMadhusudhan Chikkature /* 1386a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1387a45c6cb8SMadhusudhan Chikkature */ 13889d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 138970a3341aSDenis Karpov struct mmc_request *req) 1390a45c6cb8SMadhusudhan Chikkature { 139126b88520SRussell King struct dma_slave_config cfg; 139226b88520SRussell King struct dma_async_tx_descriptor *tx; 139326b88520SRussell King int ret = 0, i; 1394a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1395c5c98927SRussell King struct dma_chan *chan; 1396a45c6cb8SMadhusudhan Chikkature 13970ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1398a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13990ccd76d4SJuha Yrjola struct scatterlist *sgl; 14000ccd76d4SJuha Yrjola 14010ccd76d4SJuha Yrjola sgl = data->sg + i; 14020ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14030ccd76d4SJuha Yrjola return -EINVAL; 14040ccd76d4SJuha Yrjola } 14050ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14060ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14070ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14080ccd76d4SJuha Yrjola */ 14090ccd76d4SJuha Yrjola return -EINVAL; 14100ccd76d4SJuha Yrjola 1411b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1412a45c6cb8SMadhusudhan Chikkature 1413c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1414c5c98927SRussell King 1415c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1416c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1417c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1418c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1419c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1420c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1421c5c98927SRussell King 1422c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14239782aff8SPer Forlin if (ret) 14249782aff8SPer Forlin return ret; 1425a45c6cb8SMadhusudhan Chikkature 142626b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1427c5c98927SRussell King if (ret) 1428c5c98927SRussell King return ret; 1429a45c6cb8SMadhusudhan Chikkature 1430c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1431c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1432c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1433c5c98927SRussell King if (!tx) { 1434c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1435c5c98927SRussell King /* FIXME: cleanup */ 1436c5c98927SRussell King return -1; 1437c5c98927SRussell King } 1438c5c98927SRussell King 1439c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1440c5c98927SRussell King tx->callback_param = host; 1441c5c98927SRussell King 1442c5c98927SRussell King /* Does not fail */ 1443c5c98927SRussell King dmaengine_submit(tx); 1444c5c98927SRussell King 144526b88520SRussell King host->dma_ch = 1; 1446c5c98927SRussell King 1447a45c6cb8SMadhusudhan Chikkature return 0; 1448a45c6cb8SMadhusudhan Chikkature } 1449a45c6cb8SMadhusudhan Chikkature 145070a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1451e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1452e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1453a45c6cb8SMadhusudhan Chikkature { 1454a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1455a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1456a45c6cb8SMadhusudhan Chikkature 1457a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1458a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1459a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1460a45c6cb8SMadhusudhan Chikkature clkd = 1; 1461a45c6cb8SMadhusudhan Chikkature 14626e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1463e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1464e2bf08d6SAdrian Hunter timeout += timeout_clks; 1465a45c6cb8SMadhusudhan Chikkature if (timeout) { 1466a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1467a45c6cb8SMadhusudhan Chikkature dto += 1; 1468a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1469a45c6cb8SMadhusudhan Chikkature } 1470a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1471a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1472a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1473a45c6cb8SMadhusudhan Chikkature dto += 1; 1474a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1475a45c6cb8SMadhusudhan Chikkature dto -= 13; 1476a45c6cb8SMadhusudhan Chikkature else 1477a45c6cb8SMadhusudhan Chikkature dto = 0; 1478a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1479a45c6cb8SMadhusudhan Chikkature dto = 14; 1480a45c6cb8SMadhusudhan Chikkature } 1481a45c6cb8SMadhusudhan Chikkature 1482a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1483a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1484a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1485a45c6cb8SMadhusudhan Chikkature } 1486a45c6cb8SMadhusudhan Chikkature 14879d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14889d025334SBalaji T K { 14899d025334SBalaji T K struct mmc_request *req = host->mrq; 14909d025334SBalaji T K struct dma_chan *chan; 14919d025334SBalaji T K 14929d025334SBalaji T K if (!req->data) 14939d025334SBalaji T K return; 14949d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14959d025334SBalaji T K | (req->data->blocks << 16)); 14969d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14979d025334SBalaji T K req->data->timeout_clks); 14989d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14999d025334SBalaji T K dma_async_issue_pending(chan); 15009d025334SBalaji T K } 15019d025334SBalaji T K 1502a45c6cb8SMadhusudhan Chikkature /* 1503a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1504a45c6cb8SMadhusudhan Chikkature */ 1505a45c6cb8SMadhusudhan Chikkature static int 150670a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1507a45c6cb8SMadhusudhan Chikkature { 1508a45c6cb8SMadhusudhan Chikkature int ret; 1509a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1510a45c6cb8SMadhusudhan Chikkature 1511a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1512a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1513e2bf08d6SAdrian Hunter /* 1514e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1515e2bf08d6SAdrian Hunter * busy signal. 1516e2bf08d6SAdrian Hunter */ 1517e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1518e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1519a45c6cb8SMadhusudhan Chikkature return 0; 1520a45c6cb8SMadhusudhan Chikkature } 1521a45c6cb8SMadhusudhan Chikkature 1522a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15239d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1524a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1525b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1526a45c6cb8SMadhusudhan Chikkature return ret; 1527a45c6cb8SMadhusudhan Chikkature } 1528a45c6cb8SMadhusudhan Chikkature } 1529a45c6cb8SMadhusudhan Chikkature return 0; 1530a45c6cb8SMadhusudhan Chikkature } 1531a45c6cb8SMadhusudhan Chikkature 15329782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15339782aff8SPer Forlin int err) 15349782aff8SPer Forlin { 15359782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15369782aff8SPer Forlin struct mmc_data *data = mrq->data; 15379782aff8SPer Forlin 153826b88520SRussell King if (host->use_dma && data->host_cookie) { 1539c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1540c5c98927SRussell King 154126b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15429782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15439782aff8SPer Forlin data->host_cookie = 0; 15449782aff8SPer Forlin } 15459782aff8SPer Forlin } 15469782aff8SPer Forlin 15479782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15489782aff8SPer Forlin bool is_first_req) 15499782aff8SPer Forlin { 15509782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15519782aff8SPer Forlin 15529782aff8SPer Forlin if (mrq->data->host_cookie) { 15539782aff8SPer Forlin mrq->data->host_cookie = 0; 15549782aff8SPer Forlin return ; 15559782aff8SPer Forlin } 15569782aff8SPer Forlin 1557c5c98927SRussell King if (host->use_dma) { 1558c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1559c5c98927SRussell King 15609782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 156126b88520SRussell King &host->next_data, c)) 15629782aff8SPer Forlin mrq->data->host_cookie = 0; 15639782aff8SPer Forlin } 1564c5c98927SRussell King } 15659782aff8SPer Forlin 1566a45c6cb8SMadhusudhan Chikkature /* 1567a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1568a45c6cb8SMadhusudhan Chikkature */ 156970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1570a45c6cb8SMadhusudhan Chikkature { 157170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1572a3f406f8SJarkko Lavinen int err; 1573a45c6cb8SMadhusudhan Chikkature 1574b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1575b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1576f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1577b62f6228SAdrian Hunter if (host->protect_card) { 1578b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1579b62f6228SAdrian Hunter /* 1580b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1581b62f6228SAdrian Hunter * state by resetting the command and data state 1582b62f6228SAdrian Hunter * machines. 1583b62f6228SAdrian Hunter */ 1584b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1585b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1586b62f6228SAdrian Hunter host->reqs_blocked += 1; 1587b62f6228SAdrian Hunter } 1588b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1589b62f6228SAdrian Hunter if (req->data) 1590b62f6228SAdrian Hunter req->data->error = -EBADF; 1591b417577dSAdrian Hunter req->cmd->retries = 0; 1592b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1593f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1594f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1595b62f6228SAdrian Hunter return; 1596b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1597b62f6228SAdrian Hunter host->reqs_blocked = 0; 1598a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1599a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16006e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 160170a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1602a3f406f8SJarkko Lavinen if (err) { 1603a3f406f8SJarkko Lavinen req->cmd->error = err; 1604a3f406f8SJarkko Lavinen if (req->data) 1605a3f406f8SJarkko Lavinen req->data->error = err; 1606a3f406f8SJarkko Lavinen host->mrq = NULL; 1607a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1608f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1609f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1610a3f406f8SJarkko Lavinen return; 1611a3f406f8SJarkko Lavinen } 1612a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1613bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1614bf129e1cSBalaji T K return; 1615bf129e1cSBalaji T K } 1616a3f406f8SJarkko Lavinen 16179d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 161870a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1619a45c6cb8SMadhusudhan Chikkature } 1620a45c6cb8SMadhusudhan Chikkature 1621a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 162270a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1623a45c6cb8SMadhusudhan Chikkature { 162470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1625a3621465SAdrian Hunter int do_send_init_stream = 0; 1626a45c6cb8SMadhusudhan Chikkature 1627fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16285e2ea617SAdrian Hunter 1629a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1630a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1631a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1632f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1633a45c6cb8SMadhusudhan Chikkature break; 1634a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1635f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1636a45c6cb8SMadhusudhan Chikkature break; 1637a3621465SAdrian Hunter case MMC_POWER_ON: 1638a3621465SAdrian Hunter do_send_init_stream = 1; 1639a3621465SAdrian Hunter break; 1640a3621465SAdrian Hunter } 1641a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1642a45c6cb8SMadhusudhan Chikkature } 1643a45c6cb8SMadhusudhan Chikkature 1644dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1645dd498effSDenis Karpov 16463796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1647a45c6cb8SMadhusudhan Chikkature 16484621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1649eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1650eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1651eb250826SDavid Brownell */ 1652a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16532cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1654a45c6cb8SMadhusudhan Chikkature /* 1655a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1656a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1657a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1658a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1659a45c6cb8SMadhusudhan Chikkature */ 166070a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1661a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1662a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1663a45c6cb8SMadhusudhan Chikkature } 1664a45c6cb8SMadhusudhan Chikkature } 1665a45c6cb8SMadhusudhan Chikkature 16665934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1667a45c6cb8SMadhusudhan Chikkature 1668a3621465SAdrian Hunter if (do_send_init_stream) 1669a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1670a45c6cb8SMadhusudhan Chikkature 16713796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16725e2ea617SAdrian Hunter 1673fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1674a45c6cb8SMadhusudhan Chikkature } 1675a45c6cb8SMadhusudhan Chikkature 1676a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1677a45c6cb8SMadhusudhan Chikkature { 167870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1679a45c6cb8SMadhusudhan Chikkature 1680b5cd43f0SAndreas Fenkart if (!host->card_detect) 1681a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 168280412ca8SAndreas Fenkart return host->card_detect(host->dev); 1683a45c6cb8SMadhusudhan Chikkature } 1684a45c6cb8SMadhusudhan Chikkature 16854816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16864816858cSGrazvydas Ignotas { 16874816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16884816858cSGrazvydas Ignotas 1689326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1690326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16914816858cSGrazvydas Ignotas } 16924816858cSGrazvydas Ignotas 16932cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16942cd3a2a5SAndreas Fenkart { 16952cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16965a52b08bSBalaji T K u32 irq_mask, con; 16972cd3a2a5SAndreas Fenkart unsigned long flags; 16982cd3a2a5SAndreas Fenkart 16992cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17002cd3a2a5SAndreas Fenkart 17015a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17022cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17032cd3a2a5SAndreas Fenkart if (enable) { 17042cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17052cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17065a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17072cd3a2a5SAndreas Fenkart } else { 17082cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17092cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17105a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17112cd3a2a5SAndreas Fenkart } 17125a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17132cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17142cd3a2a5SAndreas Fenkart 17152cd3a2a5SAndreas Fenkart /* 17162cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17172cd3a2a5SAndreas Fenkart * but always disable immediately 17182cd3a2a5SAndreas Fenkart */ 17192cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17202cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17212cd3a2a5SAndreas Fenkart 17222cd3a2a5SAndreas Fenkart /* flush posted write */ 17232cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17242cd3a2a5SAndreas Fenkart 17252cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17262cd3a2a5SAndreas Fenkart } 17272cd3a2a5SAndreas Fenkart 17282cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17292cd3a2a5SAndreas Fenkart { 17302cd3a2a5SAndreas Fenkart int ret; 17312cd3a2a5SAndreas Fenkart 17322cd3a2a5SAndreas Fenkart /* 17332cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17342cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17352cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17362cd3a2a5SAndreas Fenkart * with functional clock disabled. 17372cd3a2a5SAndreas Fenkart */ 17382cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17392cd3a2a5SAndreas Fenkart return -ENODEV; 17402cd3a2a5SAndreas Fenkart 17415b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17422cd3a2a5SAndreas Fenkart if (ret) { 17432cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17442cd3a2a5SAndreas Fenkart goto err; 17452cd3a2a5SAndreas Fenkart } 17462cd3a2a5SAndreas Fenkart 17472cd3a2a5SAndreas Fenkart /* 17482cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17492cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17502cd3a2a5SAndreas Fenkart */ 17512cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1752455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1753455e5cd6SAndreas Fenkart if (!p) { 17542cd3a2a5SAndreas Fenkart ret = -ENODEV; 1755455e5cd6SAndreas Fenkart goto err_free_irq; 1756455e5cd6SAndreas Fenkart } 1757455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1758455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1759455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1760455e5cd6SAndreas Fenkart ret = -EINVAL; 1761455e5cd6SAndreas Fenkart goto err_free_irq; 1762455e5cd6SAndreas Fenkart } 1763455e5cd6SAndreas Fenkart 1764455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1765455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1766455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1767455e5cd6SAndreas Fenkart ret = -EINVAL; 1768455e5cd6SAndreas Fenkart goto err_free_irq; 1769455e5cd6SAndreas Fenkart } 1770455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17712cd3a2a5SAndreas Fenkart } 17722cd3a2a5SAndreas Fenkart 17735a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17745a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17752cd3a2a5SAndreas Fenkart return 0; 17762cd3a2a5SAndreas Fenkart 1777455e5cd6SAndreas Fenkart err_free_irq: 17785b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17792cd3a2a5SAndreas Fenkart err: 17802cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17812cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17822cd3a2a5SAndreas Fenkart return ret; 17832cd3a2a5SAndreas Fenkart } 17842cd3a2a5SAndreas Fenkart 178570a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17861b331e69SKim Kyuwon { 17871b331e69SKim Kyuwon u32 hctl, capa, value; 17881b331e69SKim Kyuwon 17891b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17904621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17911b331e69SKim Kyuwon hctl = SDVS30; 17921b331e69SKim Kyuwon capa = VS30 | VS18; 17931b331e69SKim Kyuwon } else { 17941b331e69SKim Kyuwon hctl = SDVS18; 17951b331e69SKim Kyuwon capa = VS18; 17961b331e69SKim Kyuwon } 17971b331e69SKim Kyuwon 17981b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17991b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18001b331e69SKim Kyuwon 18011b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18021b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18031b331e69SKim Kyuwon 18041b331e69SKim Kyuwon /* Set SD bus power bit */ 1805e13bb300SAdrian Hunter set_sd_bus_power(host); 18061b331e69SKim Kyuwon } 18071b331e69SKim Kyuwon 1808afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1809afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1810afd8c29dSKuninori Morimoto { 1811afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1812afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1813afd8c29dSKuninori Morimoto return 1; 1814afd8c29dSKuninori Morimoto 1815afd8c29dSKuninori Morimoto return blk_size; 1816afd8c29dSKuninori Morimoto } 1817afd8c29dSKuninori Morimoto 1818afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18199782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18209782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 182170a3341aSDenis Karpov .request = omap_hsmmc_request, 182270a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1823dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1824a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18254816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18262cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1827dd498effSDenis Karpov }; 1828dd498effSDenis Karpov 1829d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1830d900f712SDenis Karpov 183170a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1832d900f712SDenis Karpov { 1833d900f712SDenis Karpov struct mmc_host *mmc = s->private; 183470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 183511dd62a7SDenis Karpov 1836bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1837bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1838bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1839bb0635f0SAndreas Fenkart 1840bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1841bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1842bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1843bb0635f0SAndreas Fenkart : "disabled"); 1844bb0635f0SAndreas Fenkart } 1845bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18465e2ea617SAdrian Hunter 1847fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1848bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1849d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1850d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1851bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1852bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1853d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1854d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1855d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1856d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1857d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1858d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1859d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1860d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1861d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1862d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18635e2ea617SAdrian Hunter 1864fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1865fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1866dd498effSDenis Karpov 1867d900f712SDenis Karpov return 0; 1868d900f712SDenis Karpov } 1869d900f712SDenis Karpov 187070a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1871d900f712SDenis Karpov { 187270a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1873d900f712SDenis Karpov } 1874d900f712SDenis Karpov 1875d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 187670a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1877d900f712SDenis Karpov .read = seq_read, 1878d900f712SDenis Karpov .llseek = seq_lseek, 1879d900f712SDenis Karpov .release = single_release, 1880d900f712SDenis Karpov }; 1881d900f712SDenis Karpov 188270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1883d900f712SDenis Karpov { 1884d900f712SDenis Karpov if (mmc->debugfs_root) 1885d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1886d900f712SDenis Karpov mmc, &mmc_regs_fops); 1887d900f712SDenis Karpov } 1888d900f712SDenis Karpov 1889d900f712SDenis Karpov #else 1890d900f712SDenis Karpov 189170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1892d900f712SDenis Karpov { 1893d900f712SDenis Karpov } 1894d900f712SDenis Karpov 1895d900f712SDenis Karpov #endif 1896d900f712SDenis Karpov 189746856a68SRajendra Nayak #ifdef CONFIG_OF 189859445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 189959445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 190059445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 190159445b10SNishanth Menon }; 190259445b10SNishanth Menon 190359445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 190459445b10SNishanth Menon .reg_offset = 0x100, 190559445b10SNishanth Menon }; 19062cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19072cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19082cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19092cd3a2a5SAndreas Fenkart }; 191046856a68SRajendra Nayak 191146856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 191246856a68SRajendra Nayak { 191346856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 191446856a68SRajendra Nayak }, 191546856a68SRajendra Nayak { 191659445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 191759445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 191859445b10SNishanth Menon }, 191959445b10SNishanth Menon { 192046856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 192146856a68SRajendra Nayak }, 192246856a68SRajendra Nayak { 192346856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 192459445b10SNishanth Menon .data = &omap4_mmc_of_data, 192546856a68SRajendra Nayak }, 19262cd3a2a5SAndreas Fenkart { 19272cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19282cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19292cd3a2a5SAndreas Fenkart }, 193046856a68SRajendra Nayak {}, 1931b6d085f6SChris Ball }; 193246856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 193346856a68SRajendra Nayak 193455143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 193546856a68SRajendra Nayak { 193655143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 193746856a68SRajendra Nayak struct device_node *np = dev->of_node; 193846856a68SRajendra Nayak 193946856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 194046856a68SRajendra Nayak if (!pdata) 194119df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 194246856a68SRajendra Nayak 194346856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 194446856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 194546856a68SRajendra Nayak 1946b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1947b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1948fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 194946856a68SRajendra Nayak 195046856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1951326119c9SAndreas Fenkart pdata->nonremovable = true; 1952326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 195346856a68SRajendra Nayak } 195446856a68SRajendra Nayak 195546856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1956326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 195746856a68SRajendra Nayak 1958cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1959326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1960cd587096SHebbar, Gururaja 196146856a68SRajendra Nayak return pdata; 196246856a68SRajendra Nayak } 196346856a68SRajendra Nayak #else 196455143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 196546856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 196646856a68SRajendra Nayak { 196719df45bcSBalaji T K return ERR_PTR(-EINVAL); 196846856a68SRajendra Nayak } 196946856a68SRajendra Nayak #endif 197046856a68SRajendra Nayak 1971c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1972a45c6cb8SMadhusudhan Chikkature { 197355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1974a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 197570a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1976a45c6cb8SMadhusudhan Chikkature struct resource *res; 1977db0fefc5SAdrian Hunter int ret, irq; 197846856a68SRajendra Nayak const struct of_device_id *match; 197926b88520SRussell King dma_cap_mask_t mask; 198026b88520SRussell King unsigned tx_req, rx_req; 198159445b10SNishanth Menon const struct omap_mmc_of_data *data; 198277fae219SBalaji T K void __iomem *base; 198346856a68SRajendra Nayak 198446856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 198546856a68SRajendra Nayak if (match) { 198646856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1987dc642c28SJan Luebbe 1988dc642c28SJan Luebbe if (IS_ERR(pdata)) 1989dc642c28SJan Luebbe return PTR_ERR(pdata); 1990dc642c28SJan Luebbe 199146856a68SRajendra Nayak if (match->data) { 199259445b10SNishanth Menon data = match->data; 199359445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 199459445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 199546856a68SRajendra Nayak } 199646856a68SRajendra Nayak } 1997a45c6cb8SMadhusudhan Chikkature 1998a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1999a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2000a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2001a45c6cb8SMadhusudhan Chikkature } 2002a45c6cb8SMadhusudhan Chikkature 2003a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2004a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2005a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2006a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2007a45c6cb8SMadhusudhan Chikkature 200877fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 200977fae219SBalaji T K if (IS_ERR(base)) 201077fae219SBalaji T K return PTR_ERR(base); 2011a45c6cb8SMadhusudhan Chikkature 201270a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2013a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2014a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20151e363e3bSAndreas Fenkart goto err; 2016a45c6cb8SMadhusudhan Chikkature } 2017a45c6cb8SMadhusudhan Chikkature 2018fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2019fdb9de12SNeilBrown if (ret) 2020fdb9de12SNeilBrown goto err1; 2021fdb9de12SNeilBrown 2022a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2023a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2024a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2025a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2026a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2027a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2028a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2029fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 203077fae219SBalaji T K host->base = base + pdata->reg_offset; 20316da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20329782aff8SPer Forlin host->next_data.cookie = 1; 2033e99448ffSBalaji T K host->pbias_enabled = 0; 2034a45c6cb8SMadhusudhan Chikkature 203541afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20361e363e3bSAndreas Fenkart if (ret) 20371e363e3bSAndreas Fenkart goto err_gpio; 20381e363e3bSAndreas Fenkart 2039a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2040a45c6cb8SMadhusudhan Chikkature 20412cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20422cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20432cd3a2a5SAndreas Fenkart 204470a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2045dd498effSDenis Karpov 20466b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2047d418ed87SDaniel Mack 2048d418ed87SDaniel Mack if (pdata->max_freq > 0) 2049d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2050fdb9de12SNeilBrown else if (mmc->f_max == 0) 20516b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2052a45c6cb8SMadhusudhan Chikkature 20534dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2054a45c6cb8SMadhusudhan Chikkature 20559618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2056a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2057a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2058a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2059a45c6cb8SMadhusudhan Chikkature goto err1; 2060a45c6cb8SMadhusudhan Chikkature } 2061a45c6cb8SMadhusudhan Chikkature 20629b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20639b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2064afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20659b68256cSPaul Walmsley } 2066dd498effSDenis Karpov 20675b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2068fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2069fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2070fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2071fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2072a45c6cb8SMadhusudhan Chikkature 207392a3aebfSBalaji T K omap_hsmmc_context_save(host); 207492a3aebfSBalaji T K 20759618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2076a45c6cb8SMadhusudhan Chikkature /* 2077a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2078a45c6cb8SMadhusudhan Chikkature */ 2079cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2080cd03d9a8SRajendra Nayak host->dbclk = NULL; 208194c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2082cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2083cd03d9a8SRajendra Nayak host->dbclk = NULL; 20842bec0893SAdrian Hunter } 2085a45c6cb8SMadhusudhan Chikkature 20860ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20870ccd76d4SJuha Yrjola * as we want. */ 2088a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20890ccd76d4SJuha Yrjola 2090a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2091a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2092a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2093a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2094a45c6cb8SMadhusudhan Chikkature 209513189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 209693caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2097a45c6cb8SMadhusudhan Chikkature 2098326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20993a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2100a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2101a45c6cb8SMadhusudhan Chikkature 2102326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 210323d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 210423d99bb9SAdrian Hunter 2105fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 21066fdc75deSEliad Peller 210770a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2108a45c6cb8SMadhusudhan Chikkature 21094a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2110b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2111b7bf773bSBalaji T K if (!res) { 2112b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21139c17d08cSKevin Hilman ret = -ENXIO; 2114f3e2f1ddSGrazvydas Ignotas goto err_irq; 2115a45c6cb8SMadhusudhan Chikkature } 211626b88520SRussell King tx_req = res->start; 2117b7bf773bSBalaji T K 2118b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2119b7bf773bSBalaji T K if (!res) { 2120b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21219c17d08cSKevin Hilman ret = -ENXIO; 2122b7bf773bSBalaji T K goto err_irq; 2123b7bf773bSBalaji T K } 212426b88520SRussell King rx_req = res->start; 21254a29b559SSantosh Shilimkar } 2126c5c98927SRussell King 2127c5c98927SRussell King dma_cap_zero(mask); 2128c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 212926b88520SRussell King 2130d272fbf0SMatt Porter host->rx_chan = 2131d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2132d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2133d272fbf0SMatt Porter 2134c5c98927SRussell King if (!host->rx_chan) { 213526b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 213604e8c7bcSKevin Hilman ret = -ENXIO; 213726b88520SRussell King goto err_irq; 2138c5c98927SRussell King } 213926b88520SRussell King 2140d272fbf0SMatt Porter host->tx_chan = 2141d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2142d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2143d272fbf0SMatt Porter 2144c5c98927SRussell King if (!host->tx_chan) { 214526b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 214604e8c7bcSKevin Hilman ret = -ENXIO; 214726b88520SRussell King goto err_irq; 2148c5c98927SRussell King } 2149a45c6cb8SMadhusudhan Chikkature 2150a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2151e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2152a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2153a45c6cb8SMadhusudhan Chikkature if (ret) { 2154b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2155a45c6cb8SMadhusudhan Chikkature goto err_irq; 2156a45c6cb8SMadhusudhan Chikkature } 2157a45c6cb8SMadhusudhan Chikkature 2158f7f0f035SAndreas Fenkart if (omap_hsmmc_have_reg()) { 2159db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2160db0fefc5SAdrian Hunter if (ret) 2161bb09d151SAndreas Fenkart goto err_irq; 2162db0fefc5SAdrian Hunter } 2163db0fefc5SAdrian Hunter 2164326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2165a45c6cb8SMadhusudhan Chikkature 2166b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2167a45c6cb8SMadhusudhan Chikkature 21682cd3a2a5SAndreas Fenkart /* 21692cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21702cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21712cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21722cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21732cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21742cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21752cd3a2a5SAndreas Fenkart */ 21762cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21772cd3a2a5SAndreas Fenkart if (!ret) 21782cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21792cd3a2a5SAndreas Fenkart 2180b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2181b62f6228SAdrian Hunter 2182a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2183a45c6cb8SMadhusudhan Chikkature 2184326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2185a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2186a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2187a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2188a45c6cb8SMadhusudhan Chikkature } 2189cde592cbSAndreas Fenkart if (host->get_cover_state) { 2190a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2191a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2192a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2193db0fefc5SAdrian Hunter goto err_slot_name; 2194a45c6cb8SMadhusudhan Chikkature } 2195a45c6cb8SMadhusudhan Chikkature 219670a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2197fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2198fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2199d900f712SDenis Karpov 2200a45c6cb8SMadhusudhan Chikkature return 0; 2201a45c6cb8SMadhusudhan Chikkature 2202a45c6cb8SMadhusudhan Chikkature err_slot_name: 2203a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2204a45c6cb8SMadhusudhan Chikkature err_irq: 22055b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2206c5c98927SRussell King if (host->tx_chan) 2207c5c98927SRussell King dma_release_channel(host->tx_chan); 2208c5c98927SRussell King if (host->rx_chan) 2209c5c98927SRussell King dma_release_channel(host->rx_chan); 2210d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 221137f6190dSTony Lindgren pm_runtime_disable(host->dev); 22129618195eSBalaji T K if (host->dbclk) 221394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2214a45c6cb8SMadhusudhan Chikkature err1: 22151e363e3bSAndreas Fenkart err_gpio: 2216a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2217db0fefc5SAdrian Hunter err: 2218a45c6cb8SMadhusudhan Chikkature return ret; 2219a45c6cb8SMadhusudhan Chikkature } 2220a45c6cb8SMadhusudhan Chikkature 22216e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2222a45c6cb8SMadhusudhan Chikkature { 222370a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2224a45c6cb8SMadhusudhan Chikkature 2225fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2226a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2227a45c6cb8SMadhusudhan Chikkature 2228c5c98927SRussell King if (host->tx_chan) 2229c5c98927SRussell King dma_release_channel(host->tx_chan); 2230c5c98927SRussell King if (host->rx_chan) 2231c5c98927SRussell King dma_release_channel(host->rx_chan); 2232c5c98927SRussell King 2233fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2234fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22355b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22369618195eSBalaji T K if (host->dbclk) 223794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2238a45c6cb8SMadhusudhan Chikkature 22399d1f0286SBalaji T K mmc_free_host(host->mmc); 2240a45c6cb8SMadhusudhan Chikkature 2241a45c6cb8SMadhusudhan Chikkature return 0; 2242a45c6cb8SMadhusudhan Chikkature } 2243a45c6cb8SMadhusudhan Chikkature 22443d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2245a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2246a45c6cb8SMadhusudhan Chikkature { 2247927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2248927ce944SFelipe Balbi 2249927ce944SFelipe Balbi if (!host) 2250927ce944SFelipe Balbi return 0; 2251a45c6cb8SMadhusudhan Chikkature 2252fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 225331f9d463SEliad Peller 225431f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22552cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22562cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22572cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 225831f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 225931f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 226031f9d463SEliad Peller } 2261927ce944SFelipe Balbi 2262cd03d9a8SRajendra Nayak if (host->dbclk) 226394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22643932afd5SUlf Hansson 2265fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22663932afd5SUlf Hansson return 0; 2267a45c6cb8SMadhusudhan Chikkature } 2268a45c6cb8SMadhusudhan Chikkature 2269a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2270a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2271a45c6cb8SMadhusudhan Chikkature { 2272927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2273927ce944SFelipe Balbi 2274927ce944SFelipe Balbi if (!host) 2275927ce944SFelipe Balbi return 0; 2276a45c6cb8SMadhusudhan Chikkature 2277fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 227811dd62a7SDenis Karpov 2279cd03d9a8SRajendra Nayak if (host->dbclk) 228094c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22812bec0893SAdrian Hunter 228231f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 228370a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22841b331e69SKim Kyuwon 2285b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2286fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2287fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22883932afd5SUlf Hansson return 0; 2289a45c6cb8SMadhusudhan Chikkature } 2290a45c6cb8SMadhusudhan Chikkature #endif 2291a45c6cb8SMadhusudhan Chikkature 2292fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2293fa4aa2d4SBalaji T K { 2294fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22952cd3a2a5SAndreas Fenkart unsigned long flags; 2296f945901fSAndreas Fenkart int ret = 0; 2297fa4aa2d4SBalaji T K 2298fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2299fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2300927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2301fa4aa2d4SBalaji T K 23022cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23032cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23042cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23052cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23062cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23072cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2308f945901fSAndreas Fenkart 2309f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2310f945901fSAndreas Fenkart /* 2311f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2312f945901fSAndreas Fenkart * race condition: possible irq handler running on 2313f945901fSAndreas Fenkart * multi-core, abort 2314f945901fSAndreas Fenkart */ 2315f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23162cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2317f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2318f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2319f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2320f945901fSAndreas Fenkart ret = -EBUSY; 2321f945901fSAndreas Fenkart goto abort; 2322f945901fSAndreas Fenkart } 23232cd3a2a5SAndreas Fenkart 232497978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 232597978a44SAndreas Fenkart } else { 232697978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23272cd3a2a5SAndreas Fenkart } 232897978a44SAndreas Fenkart 2329f945901fSAndreas Fenkart abort: 23302cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2331f945901fSAndreas Fenkart return ret; 2332fa4aa2d4SBalaji T K } 2333fa4aa2d4SBalaji T K 2334fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2335fa4aa2d4SBalaji T K { 2336fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23372cd3a2a5SAndreas Fenkart unsigned long flags; 2338fa4aa2d4SBalaji T K 2339fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2340fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2341927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2342fa4aa2d4SBalaji T K 23432cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23442cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23452cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23462cd3a2a5SAndreas Fenkart 234797978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 234897978a44SAndreas Fenkart 234997978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23502cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23512cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23522cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 235397978a44SAndreas Fenkart } else { 235497978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23552cd3a2a5SAndreas Fenkart } 23562cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2357fa4aa2d4SBalaji T K return 0; 2358fa4aa2d4SBalaji T K } 2359fa4aa2d4SBalaji T K 2360a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23613d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2362fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2363fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2364a791daa1SKevin Hilman }; 2365a791daa1SKevin Hilman 2366a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2367efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23680433c143SBill Pemberton .remove = omap_hsmmc_remove, 2369a45c6cb8SMadhusudhan Chikkature .driver = { 2370a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2371a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 237246856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2373a45c6cb8SMadhusudhan Chikkature }, 2374a45c6cb8SMadhusudhan Chikkature }; 2375a45c6cb8SMadhusudhan Chikkature 2376b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2377a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2378a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2379a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2380a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2381