1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3841afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 455b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 47a45c6cb8SMadhusudhan Chikkature 48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 66a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 68a45c6cb8SMadhusudhan Chikkature 69a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 70a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 71cd587096SHebbar, Gururaja #define HSS (1 << 21) 72a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 73a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 74eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 751b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 77a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 79a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 80a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 81a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 82a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 83a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 84ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 90a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 92a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 93a7e96879SVenkatraman S #define DMAE 0x1 94a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 97cd587096SHebbar, Gururaja #define HSPE (1 << 2) 985a52b08bSBalaji T K #define IWE (1 << 24) 9903b5d924SBalaji T K #define DDR (1 << 19) 1005a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1015a52b08bSBalaji T K #define CTPL (1 << 11) 10273153010SJarkko Lavinen #define DW8 (1 << 5) 103a45c6cb8SMadhusudhan Chikkature #define OD 0x1 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 110a45c6cb8SMadhusudhan Chikkature 111f945901fSAndreas Fenkart /* PSTATE */ 112f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 113f945901fSAndreas Fenkart 114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 115a7e96879SVenkatraman S #define CC_EN (1 << 0) 116a7e96879SVenkatraman S #define TC_EN (1 << 1) 117a7e96879SVenkatraman S #define BWR_EN (1 << 4) 118a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1192cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 120a7e96879SVenkatraman S #define ERR_EN (1 << 15) 121a7e96879SVenkatraman S #define CTO_EN (1 << 16) 122a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 123a7e96879SVenkatraman S #define CEB_EN (1 << 18) 124a7e96879SVenkatraman S #define CIE_EN (1 << 19) 125a7e96879SVenkatraman S #define DTO_EN (1 << 20) 126a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 127a7e96879SVenkatraman S #define DEB_EN (1 << 22) 128a2e77152SBalaji T K #define ACE_EN (1 << 24) 129a7e96879SVenkatraman S #define CERR_EN (1 << 28) 130a7e96879SVenkatraman S #define BADA_EN (1 << 29) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 135a7e96879SVenkatraman S 136a2e77152SBalaji T K #define CNI (1 << 7) 137a2e77152SBalaji T K #define ACIE (1 << 4) 138a2e77152SBalaji T K #define ACEB (1 << 3) 139a2e77152SBalaji T K #define ACCE (1 << 2) 140a2e77152SBalaji T K #define ACTO (1 << 1) 141a2e77152SBalaji T K #define ACNE (1 << 0) 142a2e77152SBalaji T K 143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1451e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1480005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 149a45c6cb8SMadhusudhan Chikkature 150e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 151e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 152e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 153e99448ffSBalaji T K 154a45c6cb8SMadhusudhan Chikkature /* 155a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 156a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 157a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 158a45c6cb8SMadhusudhan Chikkature */ 159326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 160a45c6cb8SMadhusudhan Chikkature 161a45c6cb8SMadhusudhan Chikkature /* 162a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 163a45c6cb8SMadhusudhan Chikkature */ 164a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 165a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 166a45c6cb8SMadhusudhan Chikkature 167a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 168a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 169a45c6cb8SMadhusudhan Chikkature 1709782aff8SPer Forlin struct omap_hsmmc_next { 1719782aff8SPer Forlin unsigned int dma_len; 1729782aff8SPer Forlin s32 cookie; 1739782aff8SPer Forlin }; 1749782aff8SPer Forlin 17570a3341aSDenis Karpov struct omap_hsmmc_host { 176a45c6cb8SMadhusudhan Chikkature struct device *dev; 177a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 178a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 179a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 180a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 181a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 182a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 183e99448ffSBalaji T K struct regulator *pbias; 184bb2726b5STony Lindgren bool pbias_enabled; 185a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1863f77f702SKishon Vijay Abraham I int vqmmc_enabled; 187a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1884dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 189a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1900ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 191a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 192a3621465SAdrian Hunter unsigned char power_mode; 193a45c6cb8SMadhusudhan Chikkature int suspended; 1940a82e06eSTony Lindgren u32 con; 1950a82e06eSTony Lindgren u32 hctl; 1960a82e06eSTony Lindgren u32 sysctl; 1970a82e06eSTony Lindgren u32 capa; 198a45c6cb8SMadhusudhan Chikkature int irq; 1992cd3a2a5SAndreas Fenkart int wake_irq; 200a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 201c5c98927SRussell King struct dma_chan *tx_chan; 202c5c98927SRussell King struct dma_chan *rx_chan; 2034a694dc9SAdrian Hunter int response_busy; 20411dd62a7SDenis Karpov int context_loss; 205b62f6228SAdrian Hunter int protect_card; 206b62f6228SAdrian Hunter int reqs_blocked; 207b417577dSAdrian Hunter int req_in_progress; 2086e3076c2SBalaji T K unsigned long clk_rate; 209a2e77152SBalaji T K unsigned int flags; 2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2129782aff8SPer Forlin struct omap_hsmmc_next next_data; 21355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 214b5cd43f0SAndreas Fenkart 215b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 216b5cd43f0SAndreas Fenkart * 217b5cd43f0SAndreas Fenkart * possible return values: 218b5cd43f0SAndreas Fenkart * 0 - closed 219b5cd43f0SAndreas Fenkart * 1 - open 220b5cd43f0SAndreas Fenkart */ 22180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 222b5cd43f0SAndreas Fenkart 22380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 224a45c6cb8SMadhusudhan Chikkature }; 225a45c6cb8SMadhusudhan Chikkature 22659445b10SNishanth Menon struct omap_mmc_of_data { 22759445b10SNishanth Menon u32 reg_offset; 22859445b10SNishanth Menon u8 controller_flags; 22959445b10SNishanth Menon }; 23059445b10SNishanth Menon 231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232bf129e1cSBalaji T K 23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236db0fefc5SAdrian Hunter 23741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 241db0fefc5SAdrian Hunter { 2429ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243db0fefc5SAdrian Hunter 24441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 2471d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 2482a17f844SKishon Vijay Abraham I { 2492a17f844SKishon Vijay Abraham I int ret; 2503f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2511d17f30bSKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 2522a17f844SKishon Vijay Abraham I 2532a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2541d17f30bSKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 2552a17f844SKishon Vijay Abraham I if (ret) 2562a17f844SKishon Vijay Abraham I return ret; 2572a17f844SKishon Vijay Abraham I } 2582a17f844SKishon Vijay Abraham I 2592a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 2603f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && !host->vqmmc_enabled) { 2612a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2622a17f844SKishon Vijay Abraham I if (ret) { 2632a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2642a17f844SKishon Vijay Abraham I goto err_vqmmc; 2652a17f844SKishon Vijay Abraham I } 2663f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2672a17f844SKishon Vijay Abraham I } 2682a17f844SKishon Vijay Abraham I 2692a17f844SKishon Vijay Abraham I return 0; 2702a17f844SKishon Vijay Abraham I 2712a17f844SKishon Vijay Abraham I err_vqmmc: 2722a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) 2732a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2742a17f844SKishon Vijay Abraham I 2752a17f844SKishon Vijay Abraham I return ret; 2762a17f844SKishon Vijay Abraham I } 2772a17f844SKishon Vijay Abraham I 2782a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2792a17f844SKishon Vijay Abraham I { 2802a17f844SKishon Vijay Abraham I int ret; 2812a17f844SKishon Vijay Abraham I int status; 2823f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2832a17f844SKishon Vijay Abraham I 2843f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && host->vqmmc_enabled) { 2852a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2862a17f844SKishon Vijay Abraham I if (ret) { 2872a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2882a17f844SKishon Vijay Abraham I return ret; 2892a17f844SKishon Vijay Abraham I } 2903f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2912a17f844SKishon Vijay Abraham I } 2922a17f844SKishon Vijay Abraham I 2932a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2942a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2952a17f844SKishon Vijay Abraham I if (ret) 2962a17f844SKishon Vijay Abraham I goto err_set_ocr; 2972a17f844SKishon Vijay Abraham I } 2982a17f844SKishon Vijay Abraham I 2992a17f844SKishon Vijay Abraham I return 0; 3002a17f844SKishon Vijay Abraham I 3012a17f844SKishon Vijay Abraham I err_set_ocr: 3022a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 3032a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3042a17f844SKishon Vijay Abraham I if (status) 3052a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3062a17f844SKishon Vijay Abraham I } 3072a17f844SKishon Vijay Abraham I 3082a17f844SKishon Vijay Abraham I return ret; 3092a17f844SKishon Vijay Abraham I } 3102a17f844SKishon Vijay Abraham I 311ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 312ec85c95eSKishon Vijay Abraham I int vdd) 313ec85c95eSKishon Vijay Abraham I { 314ec85c95eSKishon Vijay Abraham I int ret; 315ec85c95eSKishon Vijay Abraham I 316ec85c95eSKishon Vijay Abraham I if (!host->pbias) 317ec85c95eSKishon Vijay Abraham I return 0; 318ec85c95eSKishon Vijay Abraham I 319ec85c95eSKishon Vijay Abraham I if (power_on) { 320ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 321ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 322ec85c95eSKishon Vijay Abraham I VDD_1V8); 323ec85c95eSKishon Vijay Abraham I else 324ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 325ec85c95eSKishon Vijay Abraham I VDD_3V0); 326ec85c95eSKishon Vijay Abraham I if (ret < 0) { 327ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 328ec85c95eSKishon Vijay Abraham I return ret; 329ec85c95eSKishon Vijay Abraham I } 330ec85c95eSKishon Vijay Abraham I 331bb2726b5STony Lindgren if (host->pbias_enabled == 0) { 332ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 333ec85c95eSKishon Vijay Abraham I if (ret) { 334ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 335ec85c95eSKishon Vijay Abraham I return ret; 336ec85c95eSKishon Vijay Abraham I } 337bb2726b5STony Lindgren host->pbias_enabled = 1; 338ec85c95eSKishon Vijay Abraham I } 339ec85c95eSKishon Vijay Abraham I } else { 340bb2726b5STony Lindgren if (host->pbias_enabled == 1) { 341ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 342ec85c95eSKishon Vijay Abraham I if (ret) { 343ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 344ec85c95eSKishon Vijay Abraham I return ret; 345ec85c95eSKishon Vijay Abraham I } 346bb2726b5STony Lindgren host->pbias_enabled = 0; 347ec85c95eSKishon Vijay Abraham I } 348ec85c95eSKishon Vijay Abraham I } 349ec85c95eSKishon Vijay Abraham I 350ec85c95eSKishon Vijay Abraham I return 0; 351ec85c95eSKishon Vijay Abraham I } 352ec85c95eSKishon Vijay Abraham I 3531ca4d359SAndreas Fenkart static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, 3541ca4d359SAndreas Fenkart int vdd) 355db0fefc5SAdrian Hunter { 356aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 357db0fefc5SAdrian Hunter int ret = 0; 358db0fefc5SAdrian Hunter 359f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 3601ca4d359SAndreas Fenkart return mmc_pdata(host)->set_power(host->dev, power_on, vdd); 361f7f0f035SAndreas Fenkart 362db0fefc5SAdrian Hunter /* 363db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 364db0fefc5SAdrian Hunter * voltage always-on regulator. 365db0fefc5SAdrian Hunter */ 366aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 367db0fefc5SAdrian Hunter return 0; 368db0fefc5SAdrian Hunter 369326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 3701ca4d359SAndreas Fenkart mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd); 371db0fefc5SAdrian Hunter 372ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 373ec85c95eSKishon Vijay Abraham I if (ret) 374229f3292SKishon Vijay Abraham I return ret; 375e99448ffSBalaji T K 376db0fefc5SAdrian Hunter /* 377db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 378db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 379db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 380db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 381db0fefc5SAdrian Hunter * 382db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 383db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 384db0fefc5SAdrian Hunter * 385db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 386db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 387db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 388db0fefc5SAdrian Hunter */ 389db0fefc5SAdrian Hunter if (power_on) { 3901d17f30bSKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc); 391229f3292SKishon Vijay Abraham I if (ret) 392229f3292SKishon Vijay Abraham I return ret; 39397fe7e5aSKishon Vijay Abraham I 39497fe7e5aSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 39597fe7e5aSKishon Vijay Abraham I if (ret) 39697fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 397db0fefc5SAdrian Hunter } else { 3982a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 399229f3292SKishon Vijay Abraham I if (ret) 400229f3292SKishon Vijay Abraham I return ret; 40199fc5131SLinus Walleij } 402db0fefc5SAdrian Hunter 403326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 4041ca4d359SAndreas Fenkart mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd); 405db0fefc5SAdrian Hunter 406229f3292SKishon Vijay Abraham I return 0; 407229f3292SKishon Vijay Abraham I 408229f3292SKishon Vijay Abraham I err_set_voltage: 4092a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 410229f3292SKishon Vijay Abraham I 411db0fefc5SAdrian Hunter return ret; 412db0fefc5SAdrian Hunter } 413db0fefc5SAdrian Hunter 414c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 415c8518efaSKishon Vijay Abraham I { 416c8518efaSKishon Vijay Abraham I int ret; 417c8518efaSKishon Vijay Abraham I 418c8518efaSKishon Vijay Abraham I if (!reg) 419c8518efaSKishon Vijay Abraham I return 0; 420c8518efaSKishon Vijay Abraham I 421c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 422c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 423c8518efaSKishon Vijay Abraham I if (ret) 424c8518efaSKishon Vijay Abraham I return ret; 425c8518efaSKishon Vijay Abraham I 426c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 427c8518efaSKishon Vijay Abraham I if (ret) 428c8518efaSKishon Vijay Abraham I return ret; 429c8518efaSKishon Vijay Abraham I } 430c8518efaSKishon Vijay Abraham I 431c8518efaSKishon Vijay Abraham I return 0; 432c8518efaSKishon Vijay Abraham I } 433c8518efaSKishon Vijay Abraham I 434c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 435c8518efaSKishon Vijay Abraham I { 436c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 437c8518efaSKishon Vijay Abraham I int ret; 438c8518efaSKishon Vijay Abraham I 439c8518efaSKishon Vijay Abraham I /* 440c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 441c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 442c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 443c8518efaSKishon Vijay Abraham I */ 444c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 445c8518efaSKishon Vijay Abraham I if (ret) { 446c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 447c8518efaSKishon Vijay Abraham I return ret; 448c8518efaSKishon Vijay Abraham I } 449c8518efaSKishon Vijay Abraham I 450c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 451c8518efaSKishon Vijay Abraham I if (ret) { 452c8518efaSKishon Vijay Abraham I dev_err(host->dev, 453c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 454c8518efaSKishon Vijay Abraham I return ret; 455c8518efaSKishon Vijay Abraham I } 456c8518efaSKishon Vijay Abraham I 457c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 458c8518efaSKishon Vijay Abraham I if (ret) { 459c8518efaSKishon Vijay Abraham I dev_err(host->dev, 460c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 461c8518efaSKishon Vijay Abraham I return ret; 462c8518efaSKishon Vijay Abraham I } 463c8518efaSKishon Vijay Abraham I 464c8518efaSKishon Vijay Abraham I return 0; 465c8518efaSKishon Vijay Abraham I } 466c8518efaSKishon Vijay Abraham I 467db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 468db0fefc5SAdrian Hunter { 46964be9782Skishore kadiyala int ocr_value = 0; 4707d607f91SKishon Vijay Abraham I int ret; 471aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 472db0fefc5SAdrian Hunter 473f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 474f7f0f035SAndreas Fenkart return 0; 475f7f0f035SAndreas Fenkart 476aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 477aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 478aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 479123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4807d607f91SKishon Vijay Abraham I return ret; 4817d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 482aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 483aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 484db0fefc5SAdrian Hunter } else { 485aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 486b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 487326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 488987fd49bSBalaji T K } 489db0fefc5SAdrian Hunter 490db0fefc5SAdrian Hunter /* Allow an aux regulator */ 491aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 492aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 493aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 494123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4956a9b2ff0SKishon Vijay Abraham I return ret; 4966a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 497aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 498aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 4996a9b2ff0SKishon Vijay Abraham I } 500db0fefc5SAdrian Hunter 501c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 502c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 503c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 5049143757bSKishon Vijay Abraham I if ((ret != -ENODEV) && host->dev->of_node) { 5059143757bSKishon Vijay Abraham I dev_err(host->dev, 5069143757bSKishon Vijay Abraham I "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 5076a9b2ff0SKishon Vijay Abraham I return ret; 5089143757bSKishon Vijay Abraham I } 5096a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 510c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 511c299dc39SKishon Vijay Abraham I host->pbias = NULL; 5126a9b2ff0SKishon Vijay Abraham I } 513e99448ffSBalaji T K 514b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 515326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 516b1c1df7aSBalaji T K return 0; 517e840ce13SAdrian Hunter 518c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 519c8518efaSKishon Vijay Abraham I if (ret) 520c8518efaSKishon Vijay Abraham I return ret; 521db0fefc5SAdrian Hunter 522db0fefc5SAdrian Hunter return 0; 523db0fefc5SAdrian Hunter } 524db0fefc5SAdrian Hunter 525cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 52641afa314SNeilBrown 52741afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 52841afa314SNeilBrown struct omap_hsmmc_host *host, 5291e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 530b702b106SAdrian Hunter { 531b702b106SAdrian Hunter int ret; 532b702b106SAdrian Hunter 533b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 534b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 535b702b106SAdrian Hunter if (ret) 536b702b106SAdrian Hunter return ret; 537cde592cbSAndreas Fenkart 538cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 539cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 540b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 541b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 542cde592cbSAndreas Fenkart if (ret) 543cde592cbSAndreas Fenkart return ret; 544cde592cbSAndreas Fenkart 545cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 546326119c9SAndreas Fenkart } 547b702b106SAdrian Hunter 548326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 54941afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 550b702b106SAdrian Hunter if (ret) 55141afa314SNeilBrown return ret; 552326119c9SAndreas Fenkart } 553b702b106SAdrian Hunter 554b702b106SAdrian Hunter return 0; 555b702b106SAdrian Hunter } 556b702b106SAdrian Hunter 557a45c6cb8SMadhusudhan Chikkature /* 558e0c7f99bSAndy Shevchenko * Start clock to the card 559e0c7f99bSAndy Shevchenko */ 560e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 561e0c7f99bSAndy Shevchenko { 562e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 563e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 564e0c7f99bSAndy Shevchenko } 565e0c7f99bSAndy Shevchenko 566e0c7f99bSAndy Shevchenko /* 567a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 568a45c6cb8SMadhusudhan Chikkature */ 56970a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 570a45c6cb8SMadhusudhan Chikkature { 571a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 572a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 573a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5747122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 575a45c6cb8SMadhusudhan Chikkature } 576a45c6cb8SMadhusudhan Chikkature 57793caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 57893caf8e6SAdrian Hunter struct mmc_command *cmd) 579b417577dSAdrian Hunter { 5802cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5812cd3a2a5SAndreas Fenkart unsigned long flags; 582b417577dSAdrian Hunter 583b417577dSAdrian Hunter if (host->use_dma) 5842cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 585b417577dSAdrian Hunter 58693caf8e6SAdrian Hunter /* Disable timeout for erases */ 58793caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 588a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 58993caf8e6SAdrian Hunter 5902cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 591b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 592b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5932cd3a2a5SAndreas Fenkart 5942cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5952cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5962cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 597b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5982cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 599b417577dSAdrian Hunter } 600b417577dSAdrian Hunter 601b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 602b417577dSAdrian Hunter { 6032cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 6042cd3a2a5SAndreas Fenkart unsigned long flags; 6052cd3a2a5SAndreas Fenkart 6062cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 6072cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 6082cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6092cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 6102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6112cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 612b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 6132cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 614b417577dSAdrian Hunter } 615b417577dSAdrian Hunter 616ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 617d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 618ac330f44SAndy Shevchenko { 619ac330f44SAndy Shevchenko u16 dsor = 0; 620ac330f44SAndy Shevchenko 621ac330f44SAndy Shevchenko if (ios->clock) { 622d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 623ed164182SBalaji T K if (dsor > CLKD_MAX) 624ed164182SBalaji T K dsor = CLKD_MAX; 625ac330f44SAndy Shevchenko } 626ac330f44SAndy Shevchenko 627ac330f44SAndy Shevchenko return dsor; 628ac330f44SAndy Shevchenko } 629ac330f44SAndy Shevchenko 6305934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6315934df2fSAndy Shevchenko { 6325934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6335934df2fSAndy Shevchenko unsigned long regval; 6345934df2fSAndy Shevchenko unsigned long timeout; 635cd587096SHebbar, Gururaja unsigned long clkdiv; 6365934df2fSAndy Shevchenko 6378986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6385934df2fSAndy Shevchenko 6395934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6405934df2fSAndy Shevchenko 6415934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6425934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 643cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 644cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6455934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6465934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6475934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6485934df2fSAndy Shevchenko 6495934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6505934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6515934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6525934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6535934df2fSAndy Shevchenko cpu_relax(); 6545934df2fSAndy Shevchenko 655cd587096SHebbar, Gururaja /* 656cd587096SHebbar, Gururaja * Enable High-Speed Support 657cd587096SHebbar, Gururaja * Pre-Requisites 658cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 659cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 660cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 661cd587096SHebbar, Gururaja * in capabilities register 662cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 663cd587096SHebbar, Gururaja */ 664326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6655438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 666903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 667cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 668cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 669cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 670cd587096SHebbar, Gururaja regval |= HSPE; 671cd587096SHebbar, Gururaja else 672cd587096SHebbar, Gururaja regval &= ~HSPE; 673cd587096SHebbar, Gururaja 674cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 675cd587096SHebbar, Gururaja } 676cd587096SHebbar, Gururaja 6775934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6785934df2fSAndy Shevchenko } 6795934df2fSAndy Shevchenko 6803796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6813796fb8aSAndy Shevchenko { 6823796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6833796fb8aSAndy Shevchenko u32 con; 6843796fb8aSAndy Shevchenko 6853796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 686903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 687903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 68803b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 68903b5d924SBalaji T K else 69003b5d924SBalaji T K con &= ~DDR; 6913796fb8aSAndy Shevchenko switch (ios->bus_width) { 6923796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6933796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6943796fb8aSAndy Shevchenko break; 6953796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6973796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6983796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6993796fb8aSAndy Shevchenko break; 7003796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 7013796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7023796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7033796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 7043796fb8aSAndy Shevchenko break; 7053796fb8aSAndy Shevchenko } 7063796fb8aSAndy Shevchenko } 7073796fb8aSAndy Shevchenko 7083796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 7093796fb8aSAndy Shevchenko { 7103796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7113796fb8aSAndy Shevchenko u32 con; 7123796fb8aSAndy Shevchenko 7133796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 7143796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 7153796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 7163796fb8aSAndy Shevchenko else 7173796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 7183796fb8aSAndy Shevchenko } 7193796fb8aSAndy Shevchenko 72011dd62a7SDenis Karpov #ifdef CONFIG_PM 72111dd62a7SDenis Karpov 72211dd62a7SDenis Karpov /* 72311dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 72411dd62a7SDenis Karpov * power state change. 72511dd62a7SDenis Karpov */ 72670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 72711dd62a7SDenis Karpov { 72811dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7293796fb8aSAndy Shevchenko u32 hctl, capa; 73011dd62a7SDenis Karpov unsigned long timeout; 73111dd62a7SDenis Karpov 7320a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7330a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7340a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7350a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7360a82e06eSTony Lindgren return 0; 7370a82e06eSTony Lindgren 7380a82e06eSTony Lindgren host->context_loss++; 7390a82e06eSTony Lindgren 740c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 74111dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 74211dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 74311dd62a7SDenis Karpov hctl = SDVS18; 74411dd62a7SDenis Karpov else 74511dd62a7SDenis Karpov hctl = SDVS30; 74611dd62a7SDenis Karpov capa = VS30 | VS18; 74711dd62a7SDenis Karpov } else { 74811dd62a7SDenis Karpov hctl = SDVS18; 74911dd62a7SDenis Karpov capa = VS18; 75011dd62a7SDenis Karpov } 75111dd62a7SDenis Karpov 7525a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7535a52b08bSBalaji T K hctl |= IWE; 7545a52b08bSBalaji T K 75511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 75611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 75711dd62a7SDenis Karpov 75811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 75911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 76011dd62a7SDenis Karpov 76111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 76211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 76311dd62a7SDenis Karpov 76411dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 76511dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 76611dd62a7SDenis Karpov && time_before(jiffies, timeout)) 76711dd62a7SDenis Karpov ; 76811dd62a7SDenis Karpov 7692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7702cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7712cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 77211dd62a7SDenis Karpov 77311dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 77411dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 77511dd62a7SDenis Karpov goto out; 77611dd62a7SDenis Karpov 7773796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 77811dd62a7SDenis Karpov 7795934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 78011dd62a7SDenis Karpov 7813796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7823796fb8aSAndy Shevchenko 78311dd62a7SDenis Karpov out: 7840a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7850a82e06eSTony Lindgren host->context_loss); 78611dd62a7SDenis Karpov return 0; 78711dd62a7SDenis Karpov } 78811dd62a7SDenis Karpov 78911dd62a7SDenis Karpov /* 79011dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 79111dd62a7SDenis Karpov */ 79270a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 79311dd62a7SDenis Karpov { 7940a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7950a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7960a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7970a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 79811dd62a7SDenis Karpov } 79911dd62a7SDenis Karpov 80011dd62a7SDenis Karpov #else 80111dd62a7SDenis Karpov 80270a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 80311dd62a7SDenis Karpov { 80411dd62a7SDenis Karpov return 0; 80511dd62a7SDenis Karpov } 80611dd62a7SDenis Karpov 80770a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 80811dd62a7SDenis Karpov { 80911dd62a7SDenis Karpov } 81011dd62a7SDenis Karpov 81111dd62a7SDenis Karpov #endif 81211dd62a7SDenis Karpov 813a45c6cb8SMadhusudhan Chikkature /* 814a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 815a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 816a45c6cb8SMadhusudhan Chikkature */ 81770a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 818a45c6cb8SMadhusudhan Chikkature { 819a45c6cb8SMadhusudhan Chikkature int reg = 0; 820a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 821a45c6cb8SMadhusudhan Chikkature 822b62f6228SAdrian Hunter if (host->protect_card) 823b62f6228SAdrian Hunter return; 824b62f6228SAdrian Hunter 825a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 826b417577dSAdrian Hunter 827b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 828a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 829a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 830a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 831a45c6cb8SMadhusudhan Chikkature 832a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 833a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 834a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 835a45c6cb8SMadhusudhan Chikkature 836a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 837a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 838c653a6d4SAdrian Hunter 839c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 840c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 841c653a6d4SAdrian Hunter 842a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 843a45c6cb8SMadhusudhan Chikkature } 844a45c6cb8SMadhusudhan Chikkature 845a45c6cb8SMadhusudhan Chikkature static inline 84670a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 847a45c6cb8SMadhusudhan Chikkature { 848a45c6cb8SMadhusudhan Chikkature int r = 1; 849a45c6cb8SMadhusudhan Chikkature 850b5cd43f0SAndreas Fenkart if (host->get_cover_state) 85180412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 852a45c6cb8SMadhusudhan Chikkature return r; 853a45c6cb8SMadhusudhan Chikkature } 854a45c6cb8SMadhusudhan Chikkature 855a45c6cb8SMadhusudhan Chikkature static ssize_t 85670a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 857a45c6cb8SMadhusudhan Chikkature char *buf) 858a45c6cb8SMadhusudhan Chikkature { 859a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 86070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 861a45c6cb8SMadhusudhan Chikkature 86270a3341aSDenis Karpov return sprintf(buf, "%s\n", 86370a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 864a45c6cb8SMadhusudhan Chikkature } 865a45c6cb8SMadhusudhan Chikkature 86670a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 867a45c6cb8SMadhusudhan Chikkature 868a45c6cb8SMadhusudhan Chikkature static ssize_t 86970a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 870a45c6cb8SMadhusudhan Chikkature char *buf) 871a45c6cb8SMadhusudhan Chikkature { 872a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 87370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 874a45c6cb8SMadhusudhan Chikkature 875326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 876a45c6cb8SMadhusudhan Chikkature } 877a45c6cb8SMadhusudhan Chikkature 87870a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 879a45c6cb8SMadhusudhan Chikkature 880a45c6cb8SMadhusudhan Chikkature /* 881a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 882a45c6cb8SMadhusudhan Chikkature */ 883a45c6cb8SMadhusudhan Chikkature static void 88470a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 885a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 886a45c6cb8SMadhusudhan Chikkature { 887a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 888a45c6cb8SMadhusudhan Chikkature 8898986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 890a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 891a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 892a45c6cb8SMadhusudhan Chikkature 89393caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 894a45c6cb8SMadhusudhan Chikkature 8954a694dc9SAdrian Hunter host->response_busy = 0; 896a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 897a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 898a45c6cb8SMadhusudhan Chikkature resptype = 1; 8994a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 9004a694dc9SAdrian Hunter resptype = 3; 9014a694dc9SAdrian Hunter host->response_busy = 1; 9024a694dc9SAdrian Hunter } else 903a45c6cb8SMadhusudhan Chikkature resptype = 2; 904a45c6cb8SMadhusudhan Chikkature } 905a45c6cb8SMadhusudhan Chikkature 906a45c6cb8SMadhusudhan Chikkature /* 907a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 908a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 909a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 910a45c6cb8SMadhusudhan Chikkature */ 911a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 912a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 913a45c6cb8SMadhusudhan Chikkature 914a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 915a45c6cb8SMadhusudhan Chikkature 916a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 917a2e77152SBalaji T K host->mrq->sbc) { 918a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 919a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 920a2e77152SBalaji T K } 921a45c6cb8SMadhusudhan Chikkature if (data) { 922a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 923a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 924a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 925a45c6cb8SMadhusudhan Chikkature else 926a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 927a45c6cb8SMadhusudhan Chikkature } 928a45c6cb8SMadhusudhan Chikkature 929a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 930a7e96879SVenkatraman S cmdreg |= DMAE; 931a45c6cb8SMadhusudhan Chikkature 932b417577dSAdrian Hunter host->req_in_progress = 1; 9334dffd7a2SAdrian Hunter 934a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 935a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 936a45c6cb8SMadhusudhan Chikkature } 937a45c6cb8SMadhusudhan Chikkature 938c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 939c5c98927SRussell King struct mmc_data *data) 940c5c98927SRussell King { 941c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 942c5c98927SRussell King } 943c5c98927SRussell King 944b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 945b417577dSAdrian Hunter { 946b417577dSAdrian Hunter int dma_ch; 94731463b14SVenkatraman S unsigned long flags; 948b417577dSAdrian Hunter 94931463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 950b417577dSAdrian Hunter host->req_in_progress = 0; 951b417577dSAdrian Hunter dma_ch = host->dma_ch; 95231463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 953b417577dSAdrian Hunter 954b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 955b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 956b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 957b417577dSAdrian Hunter return; 958b417577dSAdrian Hunter host->mrq = NULL; 959b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 960b417577dSAdrian Hunter } 961b417577dSAdrian Hunter 962a45c6cb8SMadhusudhan Chikkature /* 963a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 964a45c6cb8SMadhusudhan Chikkature */ 965a45c6cb8SMadhusudhan Chikkature static void 96670a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 967a45c6cb8SMadhusudhan Chikkature { 9684a694dc9SAdrian Hunter if (!data) { 9694a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9704a694dc9SAdrian Hunter 97123050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 97223050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 97323050103SAdrian Hunter host->response_busy) { 97423050103SAdrian Hunter host->response_busy = 0; 97523050103SAdrian Hunter return; 97623050103SAdrian Hunter } 97723050103SAdrian Hunter 978b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9794a694dc9SAdrian Hunter return; 9804a694dc9SAdrian Hunter } 9814a694dc9SAdrian Hunter 982a45c6cb8SMadhusudhan Chikkature host->data = NULL; 983a45c6cb8SMadhusudhan Chikkature 984a45c6cb8SMadhusudhan Chikkature if (!data->error) 985a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 986a45c6cb8SMadhusudhan Chikkature else 987a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 988a45c6cb8SMadhusudhan Chikkature 989bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 990fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 991bf129e1cSBalaji T K else 992bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 993a45c6cb8SMadhusudhan Chikkature } 994a45c6cb8SMadhusudhan Chikkature 995a45c6cb8SMadhusudhan Chikkature /* 996a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 997a45c6cb8SMadhusudhan Chikkature */ 998a45c6cb8SMadhusudhan Chikkature static void 99970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 1000a45c6cb8SMadhusudhan Chikkature { 1001bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 1002a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 10032177fa94SBalaji T K host->cmd = NULL; 1004bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 1005bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 1006bf129e1cSBalaji T K host->mrq->data); 1007bf129e1cSBalaji T K return; 1008bf129e1cSBalaji T K } 1009bf129e1cSBalaji T K 10102177fa94SBalaji T K host->cmd = NULL; 10112177fa94SBalaji T K 1012a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 1013a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 1014a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 1015a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1016a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1017a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1018a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1019a45c6cb8SMadhusudhan Chikkature } else { 1020a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1021a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1022a45c6cb8SMadhusudhan Chikkature } 1023a45c6cb8SMadhusudhan Chikkature } 1024b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1025d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1026a45c6cb8SMadhusudhan Chikkature } 1027a45c6cb8SMadhusudhan Chikkature 1028a45c6cb8SMadhusudhan Chikkature /* 1029a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1030a45c6cb8SMadhusudhan Chikkature */ 103170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1032a45c6cb8SMadhusudhan Chikkature { 1033b417577dSAdrian Hunter int dma_ch; 103431463b14SVenkatraman S unsigned long flags; 1035b417577dSAdrian Hunter 103682788ff5SJarkko Lavinen host->data->error = errno; 1037a45c6cb8SMadhusudhan Chikkature 103831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1039b417577dSAdrian Hunter dma_ch = host->dma_ch; 1040b417577dSAdrian Hunter host->dma_ch = -1; 104131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1042b417577dSAdrian Hunter 1043b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1044c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1045c5c98927SRussell King 1046c5c98927SRussell King dmaengine_terminate_all(chan); 1047c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1048c5c98927SRussell King host->data->sg, host->data->sg_len, 1049feeef096SHeiner Kallweit mmc_get_dma_dir(host->data)); 1050c5c98927SRussell King 1051053bf34fSPer Forlin host->data->host_cookie = 0; 1052a45c6cb8SMadhusudhan Chikkature } 1053a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1054a45c6cb8SMadhusudhan Chikkature } 1055a45c6cb8SMadhusudhan Chikkature 1056a45c6cb8SMadhusudhan Chikkature /* 1057a45c6cb8SMadhusudhan Chikkature * Readable error output 1058a45c6cb8SMadhusudhan Chikkature */ 1059a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1060699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1061a45c6cb8SMadhusudhan Chikkature { 1062a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 106370a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1064699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1065699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1066699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1067699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1068a45c6cb8SMadhusudhan Chikkature }; 1069a45c6cb8SMadhusudhan Chikkature char res[256]; 1070a45c6cb8SMadhusudhan Chikkature char *buf = res; 1071a45c6cb8SMadhusudhan Chikkature int len, i; 1072a45c6cb8SMadhusudhan Chikkature 1073a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1074a45c6cb8SMadhusudhan Chikkature buf += len; 1075a45c6cb8SMadhusudhan Chikkature 107670a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1077a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 107870a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1079a45c6cb8SMadhusudhan Chikkature buf += len; 1080a45c6cb8SMadhusudhan Chikkature } 1081a45c6cb8SMadhusudhan Chikkature 10828986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1083a45c6cb8SMadhusudhan Chikkature } 1084699b958bSAdrian Hunter #else 1085699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1086699b958bSAdrian Hunter u32 status) 1087699b958bSAdrian Hunter { 1088699b958bSAdrian Hunter } 1089a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1090a45c6cb8SMadhusudhan Chikkature 10913ebf74b1SJean Pihet /* 10923ebf74b1SJean Pihet * MMC controller internal state machines reset 10933ebf74b1SJean Pihet * 10943ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10953ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10963ebf74b1SJean Pihet * Can be called from interrupt context 10973ebf74b1SJean Pihet */ 109870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10993ebf74b1SJean Pihet unsigned long bit) 11003ebf74b1SJean Pihet { 11013ebf74b1SJean Pihet unsigned long i = 0; 11021e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 11033ebf74b1SJean Pihet 11043ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 11053ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 11063ebf74b1SJean Pihet 110707ad64b6SMadhusudhan Chikkature /* 110807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 110907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 111007ad64b6SMadhusudhan Chikkature */ 1111326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1112b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 111307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 11141e881786SJianpeng Ma udelay(1); 111507ad64b6SMadhusudhan Chikkature } 111607ad64b6SMadhusudhan Chikkature i = 0; 111707ad64b6SMadhusudhan Chikkature 11183ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 11193ebf74b1SJean Pihet (i++ < limit)) 11201e881786SJianpeng Ma udelay(1); 11213ebf74b1SJean Pihet 11223ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11233ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11243ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11253ebf74b1SJean Pihet __func__); 11263ebf74b1SJean Pihet } 1127a45c6cb8SMadhusudhan Chikkature 112825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 112925e1897bSBalaji T K int err, int end_cmd) 1130ae4bf788SVenkatraman S { 113125e1897bSBalaji T K if (end_cmd) { 113294d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 113325e1897bSBalaji T K if (host->cmd) 1134ae4bf788SVenkatraman S host->cmd->error = err; 113525e1897bSBalaji T K } 1136ae4bf788SVenkatraman S 1137ae4bf788SVenkatraman S if (host->data) { 1138ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1139ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1140dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1141dc7745bdSBalaji T K host->mrq->cmd->error = err; 1142ae4bf788SVenkatraman S } 1143ae4bf788SVenkatraman S 1144b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1145a45c6cb8SMadhusudhan Chikkature { 1146a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1147b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1148a2e77152SBalaji T K int error = 0; 1149a45c6cb8SMadhusudhan Chikkature 1150a45c6cb8SMadhusudhan Chikkature data = host->data; 11518986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1152a45c6cb8SMadhusudhan Chikkature 1153a7e96879SVenkatraman S if (status & ERR_EN) { 1154699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11554a694dc9SAdrian Hunter 115624380dd4SRavikumar Kattekola if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1157a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1158408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1159408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1160408806f7SKishon Vijay Abraham I host->response_busy = 0; 1161408806f7SKishon Vijay Abraham I } 1162a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 116325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11645027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11655027cd1eSVignesh R BADA_EN)) 116625e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 116725e1897bSBalaji T K 1168a2e77152SBalaji T K if (status & ACE_EN) { 1169a2e77152SBalaji T K u32 ac12; 1170a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1171a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1172a2e77152SBalaji T K end_cmd = 1; 1173a2e77152SBalaji T K if (ac12 & ACTO) 1174a2e77152SBalaji T K error = -ETIMEDOUT; 1175a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1176a2e77152SBalaji T K error = -EILSEQ; 1177a2e77152SBalaji T K host->mrq->sbc->error = error; 1178a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1179a2e77152SBalaji T K } 1180a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1181a2e77152SBalaji T K } 1182a45c6cb8SMadhusudhan Chikkature } 1183a45c6cb8SMadhusudhan Chikkature 11847472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1185a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 118670a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1187a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 118870a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1189b417577dSAdrian Hunter } 1190a45c6cb8SMadhusudhan Chikkature 1191b417577dSAdrian Hunter /* 1192b417577dSAdrian Hunter * MMC controller IRQ handler 1193b417577dSAdrian Hunter */ 1194b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1195b417577dSAdrian Hunter { 1196b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1197b417577dSAdrian Hunter int status; 1198b417577dSAdrian Hunter 1199b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12002cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 12012cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1202b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 12031f6b9fa4SVenkatraman S 12042cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 12052cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 12062cd3a2a5SAndreas Fenkart 1207b417577dSAdrian Hunter /* Flush posted write */ 1208b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12091f6b9fa4SVenkatraman S } 12104dffd7a2SAdrian Hunter 1211a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1212a45c6cb8SMadhusudhan Chikkature } 1213a45c6cb8SMadhusudhan Chikkature 121470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1215e13bb300SAdrian Hunter { 1216e13bb300SAdrian Hunter unsigned long i; 1217e13bb300SAdrian Hunter 1218e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1219e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1220e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1221e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1222e13bb300SAdrian Hunter break; 1223e13bb300SAdrian Hunter cpu_relax(); 1224e13bb300SAdrian Hunter } 1225e13bb300SAdrian Hunter } 1226e13bb300SAdrian Hunter 1227a45c6cb8SMadhusudhan Chikkature /* 1228eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1229eb250826SDavid Brownell * 1230eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1231eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1232eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1233a45c6cb8SMadhusudhan Chikkature */ 123470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1235a45c6cb8SMadhusudhan Chikkature { 1236a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1237a45c6cb8SMadhusudhan Chikkature int ret; 1238a45c6cb8SMadhusudhan Chikkature 1239a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1240cd03d9a8SRajendra Nayak if (host->dbclk) 124194c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1242a45c6cb8SMadhusudhan Chikkature 1243a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 12441ca4d359SAndreas Fenkart ret = omap_hsmmc_set_power(host, 0, 0); 1245a45c6cb8SMadhusudhan Chikkature 1246a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12472bec0893SAdrian Hunter if (!ret) 12481ca4d359SAndreas Fenkart ret = omap_hsmmc_set_power(host, 1, vdd); 1249cd03d9a8SRajendra Nayak if (host->dbclk) 125094c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12512bec0893SAdrian Hunter 1252a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1253a45c6cb8SMadhusudhan Chikkature goto err; 1254a45c6cb8SMadhusudhan Chikkature 1255a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1256a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1257a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1258eb250826SDavid Brownell 1259a45c6cb8SMadhusudhan Chikkature /* 1260a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1261a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 126270a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1263a45c6cb8SMadhusudhan Chikkature * 1264eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1265eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1266eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1267eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1268eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1269eb250826SDavid Brownell * 1270eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1271eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1272eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1273a45c6cb8SMadhusudhan Chikkature */ 1274eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1275a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1276eb250826SDavid Brownell else 1277eb250826SDavid Brownell reg_val |= SDVS30; 1278a45c6cb8SMadhusudhan Chikkature 1279a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1280e13bb300SAdrian Hunter set_sd_bus_power(host); 1281a45c6cb8SMadhusudhan Chikkature 1282a45c6cb8SMadhusudhan Chikkature return 0; 1283a45c6cb8SMadhusudhan Chikkature err: 1284b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1285a45c6cb8SMadhusudhan Chikkature return ret; 1286a45c6cb8SMadhusudhan Chikkature } 1287a45c6cb8SMadhusudhan Chikkature 1288b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1289b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1290b62f6228SAdrian Hunter { 1291b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1292b62f6228SAdrian Hunter return; 1293b62f6228SAdrian Hunter 1294b62f6228SAdrian Hunter host->reqs_blocked = 0; 129580412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1296b62f6228SAdrian Hunter if (host->protect_card) { 12972cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1298b62f6228SAdrian Hunter "card is now accessible\n", 1299b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1300b62f6228SAdrian Hunter host->protect_card = 0; 1301b62f6228SAdrian Hunter } 1302b62f6228SAdrian Hunter } else { 1303b62f6228SAdrian Hunter if (!host->protect_card) { 13042cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1305b62f6228SAdrian Hunter "card is now inaccessible\n", 1306b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1307b62f6228SAdrian Hunter host->protect_card = 1; 1308b62f6228SAdrian Hunter } 1309b62f6228SAdrian Hunter } 1310b62f6228SAdrian Hunter } 1311b62f6228SAdrian Hunter 1312a45c6cb8SMadhusudhan Chikkature /* 1313cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1314cde592cbSAndreas Fenkart */ 1315cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1316cde592cbSAndreas Fenkart { 1317cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1318cde592cbSAndreas Fenkart 1319cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1320cde592cbSAndreas Fenkart 1321cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1322cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1323cde592cbSAndreas Fenkart return IRQ_HANDLED; 1324cde592cbSAndreas Fenkart } 1325cde592cbSAndreas Fenkart 1326c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13270ccd76d4SJuha Yrjola { 1328c5c98927SRussell King struct omap_hsmmc_host *host = param; 1329c5c98927SRussell King struct dma_chan *chan; 1330770d7432SAdrian Hunter struct mmc_data *data; 1331c5c98927SRussell King int req_in_progress; 1332a45c6cb8SMadhusudhan Chikkature 1333c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1334b417577dSAdrian Hunter if (host->dma_ch < 0) { 1335c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1336a45c6cb8SMadhusudhan Chikkature return; 1337b417577dSAdrian Hunter } 1338a45c6cb8SMadhusudhan Chikkature 1339770d7432SAdrian Hunter data = host->mrq->data; 1340c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13419782aff8SPer Forlin if (!data->host_cookie) 1342c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1343c5c98927SRussell King data->sg, data->sg_len, 1344feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 1345b417577dSAdrian Hunter 1346b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1347a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1348c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1349b417577dSAdrian Hunter 1350b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1351b417577dSAdrian Hunter if (!req_in_progress) { 1352b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1353b417577dSAdrian Hunter 1354b417577dSAdrian Hunter host->mrq = NULL; 1355b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1356b417577dSAdrian Hunter } 1357a45c6cb8SMadhusudhan Chikkature } 1358a45c6cb8SMadhusudhan Chikkature 13599782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13609782aff8SPer Forlin struct mmc_data *data, 1361c5c98927SRussell King struct omap_hsmmc_next *next, 136226b88520SRussell King struct dma_chan *chan) 13639782aff8SPer Forlin { 13649782aff8SPer Forlin int dma_len; 13659782aff8SPer Forlin 13669782aff8SPer Forlin if (!next && data->host_cookie && 13679782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13682cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13699782aff8SPer Forlin " host->next_data.cookie %d\n", 13709782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13719782aff8SPer Forlin data->host_cookie = 0; 13729782aff8SPer Forlin } 13739782aff8SPer Forlin 13749782aff8SPer Forlin /* Check if next job is already prepared */ 1375b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 137626b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1377feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 13789782aff8SPer Forlin 13799782aff8SPer Forlin } else { 13809782aff8SPer Forlin dma_len = host->next_data.dma_len; 13819782aff8SPer Forlin host->next_data.dma_len = 0; 13829782aff8SPer Forlin } 13839782aff8SPer Forlin 13849782aff8SPer Forlin 13859782aff8SPer Forlin if (dma_len == 0) 13869782aff8SPer Forlin return -EINVAL; 13879782aff8SPer Forlin 13889782aff8SPer Forlin if (next) { 13899782aff8SPer Forlin next->dma_len = dma_len; 13909782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13919782aff8SPer Forlin } else 13929782aff8SPer Forlin host->dma_len = dma_len; 13939782aff8SPer Forlin 13949782aff8SPer Forlin return 0; 13959782aff8SPer Forlin } 13969782aff8SPer Forlin 1397a45c6cb8SMadhusudhan Chikkature /* 1398a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1399a45c6cb8SMadhusudhan Chikkature */ 14009d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 140170a3341aSDenis Karpov struct mmc_request *req) 1402a45c6cb8SMadhusudhan Chikkature { 140326b88520SRussell King struct dma_async_tx_descriptor *tx; 140426b88520SRussell King int ret = 0, i; 1405a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1406c5c98927SRussell King struct dma_chan *chan; 1407e5789608SPeter Ujfalusi struct dma_slave_config cfg = { 1408e5789608SPeter Ujfalusi .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1409e5789608SPeter Ujfalusi .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1410e5789608SPeter Ujfalusi .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1411e5789608SPeter Ujfalusi .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1412e5789608SPeter Ujfalusi .src_maxburst = data->blksz / 4, 1413e5789608SPeter Ujfalusi .dst_maxburst = data->blksz / 4, 1414e5789608SPeter Ujfalusi }; 1415a45c6cb8SMadhusudhan Chikkature 14160ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1417a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14180ccd76d4SJuha Yrjola struct scatterlist *sgl; 14190ccd76d4SJuha Yrjola 14200ccd76d4SJuha Yrjola sgl = data->sg + i; 14210ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14220ccd76d4SJuha Yrjola return -EINVAL; 14230ccd76d4SJuha Yrjola } 14240ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14250ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14260ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14270ccd76d4SJuha Yrjola */ 14280ccd76d4SJuha Yrjola return -EINVAL; 14290ccd76d4SJuha Yrjola 1430b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1431a45c6cb8SMadhusudhan Chikkature 1432c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1433c5c98927SRussell King 1434c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14359782aff8SPer Forlin if (ret) 14369782aff8SPer Forlin return ret; 1437a45c6cb8SMadhusudhan Chikkature 143826b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1439c5c98927SRussell King if (ret) 1440c5c98927SRussell King return ret; 1441a45c6cb8SMadhusudhan Chikkature 1442c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1443c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1444c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1445c5c98927SRussell King if (!tx) { 1446c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1447c5c98927SRussell King /* FIXME: cleanup */ 1448c5c98927SRussell King return -1; 1449c5c98927SRussell King } 1450c5c98927SRussell King 1451c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1452c5c98927SRussell King tx->callback_param = host; 1453c5c98927SRussell King 1454c5c98927SRussell King /* Does not fail */ 1455c5c98927SRussell King dmaengine_submit(tx); 1456c5c98927SRussell King 145726b88520SRussell King host->dma_ch = 1; 1458c5c98927SRussell King 1459a45c6cb8SMadhusudhan Chikkature return 0; 1460a45c6cb8SMadhusudhan Chikkature } 1461a45c6cb8SMadhusudhan Chikkature 146270a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1463a53210f5SRavikumar Kattekola unsigned long long timeout_ns, 1464e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1465a45c6cb8SMadhusudhan Chikkature { 1466a53210f5SRavikumar Kattekola unsigned long long timeout = timeout_ns; 1467a53210f5SRavikumar Kattekola unsigned int cycle_ns; 1468a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1469a45c6cb8SMadhusudhan Chikkature 1470a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1471a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1472a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1473a45c6cb8SMadhusudhan Chikkature clkd = 1; 1474a45c6cb8SMadhusudhan Chikkature 14756e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1476a53210f5SRavikumar Kattekola do_div(timeout, cycle_ns); 1477e2bf08d6SAdrian Hunter timeout += timeout_clks; 1478a45c6cb8SMadhusudhan Chikkature if (timeout) { 1479a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1480a45c6cb8SMadhusudhan Chikkature dto += 1; 1481a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1482a45c6cb8SMadhusudhan Chikkature } 1483a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1484a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1485a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1486a45c6cb8SMadhusudhan Chikkature dto += 1; 1487a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1488a45c6cb8SMadhusudhan Chikkature dto -= 13; 1489a45c6cb8SMadhusudhan Chikkature else 1490a45c6cb8SMadhusudhan Chikkature dto = 0; 1491a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1492a45c6cb8SMadhusudhan Chikkature dto = 14; 1493a45c6cb8SMadhusudhan Chikkature } 1494a45c6cb8SMadhusudhan Chikkature 1495a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1496a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1497a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1498a45c6cb8SMadhusudhan Chikkature } 1499a45c6cb8SMadhusudhan Chikkature 15009d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 15019d025334SBalaji T K { 15029d025334SBalaji T K struct mmc_request *req = host->mrq; 15039d025334SBalaji T K struct dma_chan *chan; 15049d025334SBalaji T K 15059d025334SBalaji T K if (!req->data) 15069d025334SBalaji T K return; 15079d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 15089d025334SBalaji T K | (req->data->blocks << 16)); 15099d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 15109d025334SBalaji T K req->data->timeout_clks); 15119d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 15129d025334SBalaji T K dma_async_issue_pending(chan); 15139d025334SBalaji T K } 15149d025334SBalaji T K 1515a45c6cb8SMadhusudhan Chikkature /* 1516a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1517a45c6cb8SMadhusudhan Chikkature */ 1518a45c6cb8SMadhusudhan Chikkature static int 151970a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1520a45c6cb8SMadhusudhan Chikkature { 1521a45c6cb8SMadhusudhan Chikkature int ret; 1522a53210f5SRavikumar Kattekola unsigned long long timeout; 15238cc9a3e7SKishon Vijay Abraham I 1524a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1525a45c6cb8SMadhusudhan Chikkature 1526a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1527a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 15288cc9a3e7SKishon Vijay Abraham I if (req->cmd->flags & MMC_RSP_BUSY) { 15298cc9a3e7SKishon Vijay Abraham I timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 15308cc9a3e7SKishon Vijay Abraham I 1531e2bf08d6SAdrian Hunter /* 1532e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 15338cc9a3e7SKishon Vijay Abraham I * busy signal and no indication of busy_timeout. 1534e2bf08d6SAdrian Hunter */ 15358cc9a3e7SKishon Vijay Abraham I if (!timeout) 15368cc9a3e7SKishon Vijay Abraham I timeout = 100000000U; 15378cc9a3e7SKishon Vijay Abraham I 15388cc9a3e7SKishon Vijay Abraham I set_data_timeout(host, timeout, 0); 15398cc9a3e7SKishon Vijay Abraham I } 1540a45c6cb8SMadhusudhan Chikkature return 0; 1541a45c6cb8SMadhusudhan Chikkature } 1542a45c6cb8SMadhusudhan Chikkature 1543a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15449d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1545a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1546b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1547a45c6cb8SMadhusudhan Chikkature return ret; 1548a45c6cb8SMadhusudhan Chikkature } 1549a45c6cb8SMadhusudhan Chikkature } 1550a45c6cb8SMadhusudhan Chikkature return 0; 1551a45c6cb8SMadhusudhan Chikkature } 1552a45c6cb8SMadhusudhan Chikkature 15539782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15549782aff8SPer Forlin int err) 15559782aff8SPer Forlin { 15569782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15579782aff8SPer Forlin struct mmc_data *data = mrq->data; 15589782aff8SPer Forlin 155926b88520SRussell King if (host->use_dma && data->host_cookie) { 1560c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1561c5c98927SRussell King 156226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1563feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 15649782aff8SPer Forlin data->host_cookie = 0; 15659782aff8SPer Forlin } 15669782aff8SPer Forlin } 15679782aff8SPer Forlin 1568d3c6aac3SLinus Walleij static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 15699782aff8SPer Forlin { 15709782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15719782aff8SPer Forlin 15729782aff8SPer Forlin if (mrq->data->host_cookie) { 15739782aff8SPer Forlin mrq->data->host_cookie = 0; 15749782aff8SPer Forlin return ; 15759782aff8SPer Forlin } 15769782aff8SPer Forlin 1577c5c98927SRussell King if (host->use_dma) { 1578c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1579c5c98927SRussell King 15809782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 158126b88520SRussell King &host->next_data, c)) 15829782aff8SPer Forlin mrq->data->host_cookie = 0; 15839782aff8SPer Forlin } 1584c5c98927SRussell King } 15859782aff8SPer Forlin 1586a45c6cb8SMadhusudhan Chikkature /* 1587a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1588a45c6cb8SMadhusudhan Chikkature */ 158970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1590a45c6cb8SMadhusudhan Chikkature { 159170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1592a3f406f8SJarkko Lavinen int err; 1593a45c6cb8SMadhusudhan Chikkature 1594b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1595b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1596b62f6228SAdrian Hunter if (host->protect_card) { 1597b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1598b62f6228SAdrian Hunter /* 1599b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1600b62f6228SAdrian Hunter * state by resetting the command and data state 1601b62f6228SAdrian Hunter * machines. 1602b62f6228SAdrian Hunter */ 1603b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1604b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1605b62f6228SAdrian Hunter host->reqs_blocked += 1; 1606b62f6228SAdrian Hunter } 1607b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1608b62f6228SAdrian Hunter if (req->data) 1609b62f6228SAdrian Hunter req->data->error = -EBADF; 1610b417577dSAdrian Hunter req->cmd->retries = 0; 1611b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1612b62f6228SAdrian Hunter return; 1613b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1614b62f6228SAdrian Hunter host->reqs_blocked = 0; 1615a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1616a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16176e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 161870a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1619a3f406f8SJarkko Lavinen if (err) { 1620a3f406f8SJarkko Lavinen req->cmd->error = err; 1621a3f406f8SJarkko Lavinen if (req->data) 1622a3f406f8SJarkko Lavinen req->data->error = err; 1623a3f406f8SJarkko Lavinen host->mrq = NULL; 1624a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1625a3f406f8SJarkko Lavinen return; 1626a3f406f8SJarkko Lavinen } 1627a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1628bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1629bf129e1cSBalaji T K return; 1630bf129e1cSBalaji T K } 1631a3f406f8SJarkko Lavinen 16329d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 163370a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1634a45c6cb8SMadhusudhan Chikkature } 1635a45c6cb8SMadhusudhan Chikkature 1636a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 163770a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1638a45c6cb8SMadhusudhan Chikkature { 163970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1640a3621465SAdrian Hunter int do_send_init_stream = 0; 1641a45c6cb8SMadhusudhan Chikkature 1642a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1643a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1644a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 16451ca4d359SAndreas Fenkart omap_hsmmc_set_power(host, 0, 0); 1646a45c6cb8SMadhusudhan Chikkature break; 1647a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 16481ca4d359SAndreas Fenkart omap_hsmmc_set_power(host, 1, ios->vdd); 1649a45c6cb8SMadhusudhan Chikkature break; 1650a3621465SAdrian Hunter case MMC_POWER_ON: 1651a3621465SAdrian Hunter do_send_init_stream = 1; 1652a3621465SAdrian Hunter break; 1653a3621465SAdrian Hunter } 1654a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1655a45c6cb8SMadhusudhan Chikkature } 1656a45c6cb8SMadhusudhan Chikkature 1657dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1658dd498effSDenis Karpov 16593796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1660a45c6cb8SMadhusudhan Chikkature 16614621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1662eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1663eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1664eb250826SDavid Brownell */ 1665a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16662cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1667a45c6cb8SMadhusudhan Chikkature /* 1668a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1669a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1670a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1671a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1672a45c6cb8SMadhusudhan Chikkature */ 167370a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1674a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1675a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1676a45c6cb8SMadhusudhan Chikkature } 1677a45c6cb8SMadhusudhan Chikkature } 1678a45c6cb8SMadhusudhan Chikkature 16795934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1680a45c6cb8SMadhusudhan Chikkature 1681a3621465SAdrian Hunter if (do_send_init_stream) 1682a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1683a45c6cb8SMadhusudhan Chikkature 16843796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 1685a45c6cb8SMadhusudhan Chikkature } 1686a45c6cb8SMadhusudhan Chikkature 1687a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1688a45c6cb8SMadhusudhan Chikkature { 168970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1690a45c6cb8SMadhusudhan Chikkature 1691b5cd43f0SAndreas Fenkart if (!host->card_detect) 1692a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 169380412ca8SAndreas Fenkart return host->card_detect(host->dev); 1694a45c6cb8SMadhusudhan Chikkature } 1695a45c6cb8SMadhusudhan Chikkature 16964816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16974816858cSGrazvydas Ignotas { 16984816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16994816858cSGrazvydas Ignotas 1700326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1701326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 17024816858cSGrazvydas Ignotas } 17034816858cSGrazvydas Ignotas 17042cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 17052cd3a2a5SAndreas Fenkart { 17062cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 17075a52b08bSBalaji T K u32 irq_mask, con; 17082cd3a2a5SAndreas Fenkart unsigned long flags; 17092cd3a2a5SAndreas Fenkart 17102cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17112cd3a2a5SAndreas Fenkart 17125a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17132cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17142cd3a2a5SAndreas Fenkart if (enable) { 17152cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17162cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17175a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17182cd3a2a5SAndreas Fenkart } else { 17192cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17202cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17215a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17222cd3a2a5SAndreas Fenkart } 17235a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17242cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17252cd3a2a5SAndreas Fenkart 17262cd3a2a5SAndreas Fenkart /* 17272cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17282cd3a2a5SAndreas Fenkart * but always disable immediately 17292cd3a2a5SAndreas Fenkart */ 17302cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17312cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17322cd3a2a5SAndreas Fenkart 17332cd3a2a5SAndreas Fenkart /* flush posted write */ 17342cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17352cd3a2a5SAndreas Fenkart 17362cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17372cd3a2a5SAndreas Fenkart } 17382cd3a2a5SAndreas Fenkart 17392cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17402cd3a2a5SAndreas Fenkart { 17412cd3a2a5SAndreas Fenkart int ret; 17422cd3a2a5SAndreas Fenkart 17432cd3a2a5SAndreas Fenkart /* 17442cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17452cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17462cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17472cd3a2a5SAndreas Fenkart * with functional clock disabled. 17482cd3a2a5SAndreas Fenkart */ 17492cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17502cd3a2a5SAndreas Fenkart return -ENODEV; 17512cd3a2a5SAndreas Fenkart 17525b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17532cd3a2a5SAndreas Fenkart if (ret) { 17542cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17552cd3a2a5SAndreas Fenkart goto err; 17562cd3a2a5SAndreas Fenkart } 17572cd3a2a5SAndreas Fenkart 17582cd3a2a5SAndreas Fenkart /* 17592cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17602cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17612cd3a2a5SAndreas Fenkart */ 17622cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1763455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1764ec5ab893SDan Carpenter if (IS_ERR(p)) { 1765ec5ab893SDan Carpenter ret = PTR_ERR(p); 1766455e5cd6SAndreas Fenkart goto err_free_irq; 1767455e5cd6SAndreas Fenkart } 1768455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1769455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1770455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1771455e5cd6SAndreas Fenkart ret = -EINVAL; 1772455e5cd6SAndreas Fenkart goto err_free_irq; 1773455e5cd6SAndreas Fenkart } 1774455e5cd6SAndreas Fenkart 1775455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1776455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1777455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1778455e5cd6SAndreas Fenkart ret = -EINVAL; 1779455e5cd6SAndreas Fenkart goto err_free_irq; 1780455e5cd6SAndreas Fenkart } 1781455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17822cd3a2a5SAndreas Fenkart } 17832cd3a2a5SAndreas Fenkart 17845a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17855a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17862cd3a2a5SAndreas Fenkart return 0; 17872cd3a2a5SAndreas Fenkart 1788455e5cd6SAndreas Fenkart err_free_irq: 17895b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17902cd3a2a5SAndreas Fenkart err: 17912cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17922cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17932cd3a2a5SAndreas Fenkart return ret; 17942cd3a2a5SAndreas Fenkart } 17952cd3a2a5SAndreas Fenkart 179670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17971b331e69SKim Kyuwon { 17981b331e69SKim Kyuwon u32 hctl, capa, value; 17991b331e69SKim Kyuwon 18001b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 18014621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 18021b331e69SKim Kyuwon hctl = SDVS30; 18031b331e69SKim Kyuwon capa = VS30 | VS18; 18041b331e69SKim Kyuwon } else { 18051b331e69SKim Kyuwon hctl = SDVS18; 18061b331e69SKim Kyuwon capa = VS18; 18071b331e69SKim Kyuwon } 18081b331e69SKim Kyuwon 18091b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 18101b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18111b331e69SKim Kyuwon 18121b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18131b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18141b331e69SKim Kyuwon 18151b331e69SKim Kyuwon /* Set SD bus power bit */ 1816e13bb300SAdrian Hunter set_sd_bus_power(host); 18171b331e69SKim Kyuwon } 18181b331e69SKim Kyuwon 1819afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1820afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1821afd8c29dSKuninori Morimoto { 1822afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1823afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1824afd8c29dSKuninori Morimoto return 1; 1825afd8c29dSKuninori Morimoto 1826afd8c29dSKuninori Morimoto return blk_size; 1827afd8c29dSKuninori Morimoto } 1828afd8c29dSKuninori Morimoto 1829afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18309782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18319782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 183270a3341aSDenis Karpov .request = omap_hsmmc_request, 183370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1834dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1835a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18364816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18372cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1838dd498effSDenis Karpov }; 1839dd498effSDenis Karpov 1840d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1841d900f712SDenis Karpov 184270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1843d900f712SDenis Karpov { 1844d900f712SDenis Karpov struct mmc_host *mmc = s->private; 184570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 184611dd62a7SDenis Karpov 1847bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1848bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1849bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1850bb0635f0SAndreas Fenkart 1851bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1852bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1853bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1854bb0635f0SAndreas Fenkart : "disabled"); 1855bb0635f0SAndreas Fenkart } 1856bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18575e2ea617SAdrian Hunter 1858fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1859bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1860d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1861d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1862bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1863bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1864d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1865d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1866d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1867d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1868d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1869d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1870d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1871d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1872d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1873d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18745e2ea617SAdrian Hunter 1875fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1876fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1877dd498effSDenis Karpov 1878d900f712SDenis Karpov return 0; 1879d900f712SDenis Karpov } 1880d900f712SDenis Karpov 188170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1882d900f712SDenis Karpov { 188370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1884d900f712SDenis Karpov } 1885d900f712SDenis Karpov 1886d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 188770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1888d900f712SDenis Karpov .read = seq_read, 1889d900f712SDenis Karpov .llseek = seq_lseek, 1890d900f712SDenis Karpov .release = single_release, 1891d900f712SDenis Karpov }; 1892d900f712SDenis Karpov 189370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1894d900f712SDenis Karpov { 1895d900f712SDenis Karpov if (mmc->debugfs_root) 1896d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1897d900f712SDenis Karpov mmc, &mmc_regs_fops); 1898d900f712SDenis Karpov } 1899d900f712SDenis Karpov 1900d900f712SDenis Karpov #else 1901d900f712SDenis Karpov 190270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1903d900f712SDenis Karpov { 1904d900f712SDenis Karpov } 1905d900f712SDenis Karpov 1906d900f712SDenis Karpov #endif 1907d900f712SDenis Karpov 190846856a68SRajendra Nayak #ifdef CONFIG_OF 190959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 191059445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 191159445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 191259445b10SNishanth Menon }; 191359445b10SNishanth Menon 191459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 191559445b10SNishanth Menon .reg_offset = 0x100, 191659445b10SNishanth Menon }; 19172cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19182cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19192cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19202cd3a2a5SAndreas Fenkart }; 192146856a68SRajendra Nayak 192246856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 192346856a68SRajendra Nayak { 192446856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 192546856a68SRajendra Nayak }, 192646856a68SRajendra Nayak { 192759445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 192859445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 192959445b10SNishanth Menon }, 193059445b10SNishanth Menon { 193146856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 193246856a68SRajendra Nayak }, 193346856a68SRajendra Nayak { 193446856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 193559445b10SNishanth Menon .data = &omap4_mmc_of_data, 193646856a68SRajendra Nayak }, 19372cd3a2a5SAndreas Fenkart { 19382cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19392cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19402cd3a2a5SAndreas Fenkart }, 194146856a68SRajendra Nayak {}, 1942b6d085f6SChris Ball }; 194346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 194446856a68SRajendra Nayak 194555143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 194646856a68SRajendra Nayak { 1947db863d89STony Lindgren struct omap_hsmmc_platform_data *pdata, *legacy; 194846856a68SRajendra Nayak struct device_node *np = dev->of_node; 194946856a68SRajendra Nayak 195046856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 195146856a68SRajendra Nayak if (!pdata) 195219df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 195346856a68SRajendra Nayak 1954db863d89STony Lindgren legacy = dev_get_platdata(dev); 1955db863d89STony Lindgren if (legacy && legacy->name) 1956db863d89STony Lindgren pdata->name = legacy->name; 1957db863d89STony Lindgren 195846856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 195946856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 196046856a68SRajendra Nayak 1961b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1962b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1963fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 196446856a68SRajendra Nayak 196546856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1966326119c9SAndreas Fenkart pdata->nonremovable = true; 1967326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 196846856a68SRajendra Nayak } 196946856a68SRajendra Nayak 197046856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1971326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 197246856a68SRajendra Nayak 1973cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1974326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1975cd587096SHebbar, Gururaja 197646856a68SRajendra Nayak return pdata; 197746856a68SRajendra Nayak } 197846856a68SRajendra Nayak #else 197955143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 198046856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 198146856a68SRajendra Nayak { 198219df45bcSBalaji T K return ERR_PTR(-EINVAL); 198346856a68SRajendra Nayak } 198446856a68SRajendra Nayak #endif 198546856a68SRajendra Nayak 1986c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1987a45c6cb8SMadhusudhan Chikkature { 198855143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1989a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 199070a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1991a45c6cb8SMadhusudhan Chikkature struct resource *res; 1992db0fefc5SAdrian Hunter int ret, irq; 199346856a68SRajendra Nayak const struct of_device_id *match; 199459445b10SNishanth Menon const struct omap_mmc_of_data *data; 199577fae219SBalaji T K void __iomem *base; 199646856a68SRajendra Nayak 199746856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 199846856a68SRajendra Nayak if (match) { 199946856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2000dc642c28SJan Luebbe 2001dc642c28SJan Luebbe if (IS_ERR(pdata)) 2002dc642c28SJan Luebbe return PTR_ERR(pdata); 2003dc642c28SJan Luebbe 200446856a68SRajendra Nayak if (match->data) { 200559445b10SNishanth Menon data = match->data; 200659445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 200759445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 200846856a68SRajendra Nayak } 200946856a68SRajendra Nayak } 2010a45c6cb8SMadhusudhan Chikkature 2011a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2012a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2013a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2014a45c6cb8SMadhusudhan Chikkature } 2015a45c6cb8SMadhusudhan Chikkature 2016a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2017a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2018a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2019a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2020a45c6cb8SMadhusudhan Chikkature 202177fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 202277fae219SBalaji T K if (IS_ERR(base)) 202377fae219SBalaji T K return PTR_ERR(base); 2024a45c6cb8SMadhusudhan Chikkature 202570a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2026a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2027a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20281e363e3bSAndreas Fenkart goto err; 2029a45c6cb8SMadhusudhan Chikkature } 2030a45c6cb8SMadhusudhan Chikkature 2031fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2032fdb9de12SNeilBrown if (ret) 2033fdb9de12SNeilBrown goto err1; 2034fdb9de12SNeilBrown 2035a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2036a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2037a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2038a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2039a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2040a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2041a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2042fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 204377fae219SBalaji T K host->base = base + pdata->reg_offset; 20446da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20459782aff8SPer Forlin host->next_data.cookie = 1; 2046bb2726b5STony Lindgren host->pbias_enabled = 0; 20473f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2048a45c6cb8SMadhusudhan Chikkature 204941afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20501e363e3bSAndreas Fenkart if (ret) 20511e363e3bSAndreas Fenkart goto err_gpio; 20521e363e3bSAndreas Fenkart 2053a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2054a45c6cb8SMadhusudhan Chikkature 20552cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20562cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20572cd3a2a5SAndreas Fenkart 205870a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2059dd498effSDenis Karpov 20606b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2061d418ed87SDaniel Mack 2062d418ed87SDaniel Mack if (pdata->max_freq > 0) 2063d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2064fdb9de12SNeilBrown else if (mmc->f_max == 0) 20656b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2066a45c6cb8SMadhusudhan Chikkature 20674dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2068a45c6cb8SMadhusudhan Chikkature 20699618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2070a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2071a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2072a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2073a45c6cb8SMadhusudhan Chikkature goto err1; 2074a45c6cb8SMadhusudhan Chikkature } 2075a45c6cb8SMadhusudhan Chikkature 20769b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20779b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2078afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20799b68256cSPaul Walmsley } 2080dd498effSDenis Karpov 20815b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2082fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2083fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2084fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2085fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2086a45c6cb8SMadhusudhan Chikkature 208792a3aebfSBalaji T K omap_hsmmc_context_save(host); 208892a3aebfSBalaji T K 20899618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2090a45c6cb8SMadhusudhan Chikkature /* 2091a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2092a45c6cb8SMadhusudhan Chikkature */ 2093cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2094cd03d9a8SRajendra Nayak host->dbclk = NULL; 209594c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2096cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2097cd03d9a8SRajendra Nayak host->dbclk = NULL; 20982bec0893SAdrian Hunter } 2099a45c6cb8SMadhusudhan Chikkature 21000ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21010ccd76d4SJuha Yrjola * as we want. */ 2102a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21030ccd76d4SJuha Yrjola 2104a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2105a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2106a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2107a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2108a45c6cb8SMadhusudhan Chikkature 210913189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 211093caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2111a45c6cb8SMadhusudhan Chikkature 2112326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21133a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2114a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2115a45c6cb8SMadhusudhan Chikkature 2116326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 211723d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 211823d99bb9SAdrian Hunter 2119fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 21206fdc75deSEliad Peller 212170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2122a45c6cb8SMadhusudhan Chikkature 212381eef6caSPeter Ujfalusi host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 212481eef6caSPeter Ujfalusi if (IS_ERR(host->rx_chan)) { 212581eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 212681eef6caSPeter Ujfalusi ret = PTR_ERR(host->rx_chan); 212726b88520SRussell King goto err_irq; 2128c5c98927SRussell King } 212926b88520SRussell King 213081eef6caSPeter Ujfalusi host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 213181eef6caSPeter Ujfalusi if (IS_ERR(host->tx_chan)) { 213281eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 213381eef6caSPeter Ujfalusi ret = PTR_ERR(host->tx_chan); 213426b88520SRussell King goto err_irq; 2135c5c98927SRussell King } 2136a45c6cb8SMadhusudhan Chikkature 2137a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2138e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2139a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2140a45c6cb8SMadhusudhan Chikkature if (ret) { 2141b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2142a45c6cb8SMadhusudhan Chikkature goto err_irq; 2143a45c6cb8SMadhusudhan Chikkature } 2144a45c6cb8SMadhusudhan Chikkature 2145db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2146db0fefc5SAdrian Hunter if (ret) 2147bb09d151SAndreas Fenkart goto err_irq; 2148db0fefc5SAdrian Hunter 2149326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2150a45c6cb8SMadhusudhan Chikkature 2151b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2152a45c6cb8SMadhusudhan Chikkature 21532cd3a2a5SAndreas Fenkart /* 21542cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21552cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21562cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21572cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21582cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21592cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21602cd3a2a5SAndreas Fenkart */ 21612cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21622cd3a2a5SAndreas Fenkart if (!ret) 21632cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21642cd3a2a5SAndreas Fenkart 2165b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2166b62f6228SAdrian Hunter 2167a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2168a45c6cb8SMadhusudhan Chikkature 2169326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2170a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2171a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2172a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2173a45c6cb8SMadhusudhan Chikkature } 2174cde592cbSAndreas Fenkart if (host->get_cover_state) { 2175a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2176a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2177a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2178db0fefc5SAdrian Hunter goto err_slot_name; 2179a45c6cb8SMadhusudhan Chikkature } 2180a45c6cb8SMadhusudhan Chikkature 218170a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2182fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2183fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2184d900f712SDenis Karpov 2185a45c6cb8SMadhusudhan Chikkature return 0; 2186a45c6cb8SMadhusudhan Chikkature 2187a45c6cb8SMadhusudhan Chikkature err_slot_name: 2188a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2189a45c6cb8SMadhusudhan Chikkature err_irq: 21905b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 219181eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->tx_chan)) 2192c5c98927SRussell King dma_release_channel(host->tx_chan); 219381eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->rx_chan)) 2194c5c98927SRussell King dma_release_channel(host->rx_chan); 2195814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2196d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 219737f6190dSTony Lindgren pm_runtime_disable(host->dev); 21989618195eSBalaji T K if (host->dbclk) 219994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2200a45c6cb8SMadhusudhan Chikkature err1: 22011e363e3bSAndreas Fenkart err_gpio: 2202a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2203db0fefc5SAdrian Hunter err: 2204a45c6cb8SMadhusudhan Chikkature return ret; 2205a45c6cb8SMadhusudhan Chikkature } 2206a45c6cb8SMadhusudhan Chikkature 22076e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2208a45c6cb8SMadhusudhan Chikkature { 220970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2210a45c6cb8SMadhusudhan Chikkature 2211fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2212a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2213a45c6cb8SMadhusudhan Chikkature 2214c5c98927SRussell King dma_release_channel(host->tx_chan); 2215c5c98927SRussell King dma_release_channel(host->rx_chan); 2216c5c98927SRussell King 2217814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2218fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2219fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22205b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22219618195eSBalaji T K if (host->dbclk) 222294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2223a45c6cb8SMadhusudhan Chikkature 22249d1f0286SBalaji T K mmc_free_host(host->mmc); 2225a45c6cb8SMadhusudhan Chikkature 2226a45c6cb8SMadhusudhan Chikkature return 0; 2227a45c6cb8SMadhusudhan Chikkature } 2228a45c6cb8SMadhusudhan Chikkature 22293d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2230a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2231a45c6cb8SMadhusudhan Chikkature { 2232927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2233927ce944SFelipe Balbi 2234927ce944SFelipe Balbi if (!host) 2235927ce944SFelipe Balbi return 0; 2236a45c6cb8SMadhusudhan Chikkature 2237fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 223831f9d463SEliad Peller 223931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22402cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22412cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22422cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 224331f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 224431f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 224531f9d463SEliad Peller } 2246927ce944SFelipe Balbi 2247cd03d9a8SRajendra Nayak if (host->dbclk) 224894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22493932afd5SUlf Hansson 2250fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22513932afd5SUlf Hansson return 0; 2252a45c6cb8SMadhusudhan Chikkature } 2253a45c6cb8SMadhusudhan Chikkature 2254a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2255a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2256a45c6cb8SMadhusudhan Chikkature { 2257927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2258927ce944SFelipe Balbi 2259927ce944SFelipe Balbi if (!host) 2260927ce944SFelipe Balbi return 0; 2261a45c6cb8SMadhusudhan Chikkature 2262fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 226311dd62a7SDenis Karpov 2264cd03d9a8SRajendra Nayak if (host->dbclk) 226594c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22662bec0893SAdrian Hunter 226731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 226870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22691b331e69SKim Kyuwon 2270b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2271fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2272fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22733932afd5SUlf Hansson return 0; 2274a45c6cb8SMadhusudhan Chikkature } 2275a45c6cb8SMadhusudhan Chikkature #endif 2276a45c6cb8SMadhusudhan Chikkature 2277fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2278fa4aa2d4SBalaji T K { 2279fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22802cd3a2a5SAndreas Fenkart unsigned long flags; 2281f945901fSAndreas Fenkart int ret = 0; 2282fa4aa2d4SBalaji T K 2283fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2284fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2285927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2286fa4aa2d4SBalaji T K 22872cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22882cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22892cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22902cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 22912cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22922cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2293f945901fSAndreas Fenkart 2294f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2295f945901fSAndreas Fenkart /* 2296f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2297f945901fSAndreas Fenkart * race condition: possible irq handler running on 2298f945901fSAndreas Fenkart * multi-core, abort 2299f945901fSAndreas Fenkart */ 2300f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23012cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2302f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2303f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2304f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2305f945901fSAndreas Fenkart ret = -EBUSY; 2306f945901fSAndreas Fenkart goto abort; 2307f945901fSAndreas Fenkart } 23082cd3a2a5SAndreas Fenkart 230997978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 231097978a44SAndreas Fenkart } else { 231197978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23122cd3a2a5SAndreas Fenkart } 231397978a44SAndreas Fenkart 2314f945901fSAndreas Fenkart abort: 23152cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2316f945901fSAndreas Fenkart return ret; 2317fa4aa2d4SBalaji T K } 2318fa4aa2d4SBalaji T K 2319fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2320fa4aa2d4SBalaji T K { 2321fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23222cd3a2a5SAndreas Fenkart unsigned long flags; 2323fa4aa2d4SBalaji T K 2324fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2325fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2326927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2327fa4aa2d4SBalaji T K 23282cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23292cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23302cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23312cd3a2a5SAndreas Fenkart 233297978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 233397978a44SAndreas Fenkart 233497978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23352cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23362cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23372cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 233897978a44SAndreas Fenkart } else { 233997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23402cd3a2a5SAndreas Fenkart } 23412cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2342fa4aa2d4SBalaji T K return 0; 2343fa4aa2d4SBalaji T K } 2344fa4aa2d4SBalaji T K 2345a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23463d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2347fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2348fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2349a791daa1SKevin Hilman }; 2350a791daa1SKevin Hilman 2351a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2352efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23530433c143SBill Pemberton .remove = omap_hsmmc_remove, 2354a45c6cb8SMadhusudhan Chikkature .driver = { 2355a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2356a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 235746856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2358a45c6cb8SMadhusudhan Chikkature }, 2359a45c6cb8SMadhusudhan Chikkature }; 2360a45c6cb8SMadhusudhan Chikkature 2361b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2362a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2363a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2364a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2365a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2366