1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 3246856a68SRajendra Nayak #include <linux/of_gpio.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 343451c067SRussell King #include <linux/omap-dma.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 39db0fefc5SAdrian Hunter #include <linux/gpio.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4368f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 44a45c6cb8SMadhusudhan Chikkature 45a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65cd587096SHebbar, Gururaja #define HSS (1 << 21) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 79a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 80a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 81a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 82a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 83a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 84a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 85a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 86a7e96879SVenkatraman S #define DMAE 0x1 87a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 88a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 89a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 90cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9103b5d924SBalaji T K #define DDR (1 << 19) 9273153010SJarkko Lavinen #define DW8 (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define OD 0x1 94a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 95a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 96a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 97a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 98a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10011dd62a7SDenis Karpov #define RESETDONE (1 << 0) 101a45c6cb8SMadhusudhan Chikkature 102a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 103a7e96879SVenkatraman S #define CC_EN (1 << 0) 104a7e96879SVenkatraman S #define TC_EN (1 << 1) 105a7e96879SVenkatraman S #define BWR_EN (1 << 4) 106a7e96879SVenkatraman S #define BRR_EN (1 << 5) 107a7e96879SVenkatraman S #define ERR_EN (1 << 15) 108a7e96879SVenkatraman S #define CTO_EN (1 << 16) 109a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 110a7e96879SVenkatraman S #define CEB_EN (1 << 18) 111a7e96879SVenkatraman S #define CIE_EN (1 << 19) 112a7e96879SVenkatraman S #define DTO_EN (1 << 20) 113a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 114a7e96879SVenkatraman S #define DEB_EN (1 << 22) 115a7e96879SVenkatraman S #define CERR_EN (1 << 28) 116a7e96879SVenkatraman S #define BADA_EN (1 << 29) 117a7e96879SVenkatraman S 118a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 119a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 120a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 121a7e96879SVenkatraman S 122fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1231e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1241e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1256b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1266b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1270005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 128a45c6cb8SMadhusudhan Chikkature 129e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 130e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 131e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 132e99448ffSBalaji T K 133a45c6cb8SMadhusudhan Chikkature /* 134a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 135a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 136a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 137a45c6cb8SMadhusudhan Chikkature */ 138a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 139a45c6cb8SMadhusudhan Chikkature 140a45c6cb8SMadhusudhan Chikkature /* 141a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 142a45c6cb8SMadhusudhan Chikkature */ 143a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 144a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 145a45c6cb8SMadhusudhan Chikkature 146a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 147a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 148a45c6cb8SMadhusudhan Chikkature 1499782aff8SPer Forlin struct omap_hsmmc_next { 1509782aff8SPer Forlin unsigned int dma_len; 1519782aff8SPer Forlin s32 cookie; 1529782aff8SPer Forlin }; 1539782aff8SPer Forlin 15470a3341aSDenis Karpov struct omap_hsmmc_host { 155a45c6cb8SMadhusudhan Chikkature struct device *dev; 156a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 157a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 158a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 159a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 160a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 161a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 162db0fefc5SAdrian Hunter /* 163db0fefc5SAdrian Hunter * vcc == configured supply 164db0fefc5SAdrian Hunter * vcc_aux == optional 165db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 166db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 167db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 168db0fefc5SAdrian Hunter */ 169db0fefc5SAdrian Hunter struct regulator *vcc; 170db0fefc5SAdrian Hunter struct regulator *vcc_aux; 171e99448ffSBalaji T K struct regulator *pbias; 172e99448ffSBalaji T K bool pbias_enabled; 173cf5ae40bSTony Lindgren int pbias_disable; 174a45c6cb8SMadhusudhan Chikkature void __iomem *base; 175a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1764dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 177a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1780ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 179a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 180a3621465SAdrian Hunter unsigned char power_mode; 181a45c6cb8SMadhusudhan Chikkature int suspended; 1820a82e06eSTony Lindgren u32 con; 1830a82e06eSTony Lindgren u32 hctl; 1840a82e06eSTony Lindgren u32 sysctl; 1850a82e06eSTony Lindgren u32 capa; 186a45c6cb8SMadhusudhan Chikkature int irq; 187a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 188c5c98927SRussell King struct dma_chan *tx_chan; 189c5c98927SRussell King struct dma_chan *rx_chan; 190a45c6cb8SMadhusudhan Chikkature int slot_id; 1914a694dc9SAdrian Hunter int response_busy; 19211dd62a7SDenis Karpov int context_loss; 193b62f6228SAdrian Hunter int protect_card; 194b62f6228SAdrian Hunter int reqs_blocked; 195db0fefc5SAdrian Hunter int use_reg; 196b417577dSAdrian Hunter int req_in_progress; 1979782aff8SPer Forlin struct omap_hsmmc_next next_data; 198a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 199a45c6cb8SMadhusudhan Chikkature }; 200a45c6cb8SMadhusudhan Chikkature 20159445b10SNishanth Menon struct omap_mmc_of_data { 20259445b10SNishanth Menon u32 reg_offset; 20359445b10SNishanth Menon u8 controller_flags; 20459445b10SNishanth Menon }; 20559445b10SNishanth Menon 206db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 207db0fefc5SAdrian Hunter { 2089ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2099ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 210db0fefc5SAdrian Hunter 211db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 212db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 213db0fefc5SAdrian Hunter } 214db0fefc5SAdrian Hunter 215db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 216db0fefc5SAdrian Hunter { 2179ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2189ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 219db0fefc5SAdrian Hunter 220db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 221db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 222db0fefc5SAdrian Hunter } 223db0fefc5SAdrian Hunter 224db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 225db0fefc5SAdrian Hunter { 2269ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2279ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 228db0fefc5SAdrian Hunter 229db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 230db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 231db0fefc5SAdrian Hunter } 232db0fefc5SAdrian Hunter 233db0fefc5SAdrian Hunter #ifdef CONFIG_PM 234db0fefc5SAdrian Hunter 235db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 236db0fefc5SAdrian Hunter { 2379ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2389ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 239db0fefc5SAdrian Hunter 240db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 241db0fefc5SAdrian Hunter return 0; 242db0fefc5SAdrian Hunter } 243db0fefc5SAdrian Hunter 244db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 245db0fefc5SAdrian Hunter { 2469ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2479ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 248db0fefc5SAdrian Hunter 249db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 250db0fefc5SAdrian Hunter return 0; 251db0fefc5SAdrian Hunter } 252db0fefc5SAdrian Hunter 253db0fefc5SAdrian Hunter #else 254db0fefc5SAdrian Hunter 255db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 256db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 257db0fefc5SAdrian Hunter 258db0fefc5SAdrian Hunter #endif 259db0fefc5SAdrian Hunter 260b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 261b702b106SAdrian Hunter 26269b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 263db0fefc5SAdrian Hunter int vdd) 264db0fefc5SAdrian Hunter { 265db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 266db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 267db0fefc5SAdrian Hunter int ret = 0; 268db0fefc5SAdrian Hunter 269db0fefc5SAdrian Hunter /* 270db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 271db0fefc5SAdrian Hunter * voltage always-on regulator. 272db0fefc5SAdrian Hunter */ 273db0fefc5SAdrian Hunter if (!host->vcc) 274db0fefc5SAdrian Hunter return 0; 2751f84b71bSRajendra Nayak /* 276cf5ae40bSTony Lindgren * With DT, never turn OFF the regulator for MMC1. This is because 2771f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2781f84b71bSRajendra Nayak * booting with Device tree 2791f84b71bSRajendra Nayak */ 280cf5ae40bSTony Lindgren if (host->pbias_disable && !vdd) 2811f84b71bSRajendra Nayak return 0; 282db0fefc5SAdrian Hunter 283db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 284db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 285db0fefc5SAdrian Hunter 286e99448ffSBalaji T K if (host->pbias) { 287e99448ffSBalaji T K if (host->pbias_enabled == 1) { 288e99448ffSBalaji T K ret = regulator_disable(host->pbias); 289e99448ffSBalaji T K if (!ret) 290e99448ffSBalaji T K host->pbias_enabled = 0; 291e99448ffSBalaji T K } 292e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 293e99448ffSBalaji T K } 294e99448ffSBalaji T K 295db0fefc5SAdrian Hunter /* 296db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 297db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 298db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 299db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 300db0fefc5SAdrian Hunter * 301db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 302db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 303db0fefc5SAdrian Hunter * 304db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 305db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 306db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 307db0fefc5SAdrian Hunter */ 308db0fefc5SAdrian Hunter if (power_on) { 309987fd49bSBalaji T K if (host->vcc) 31099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 311db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 312db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 313db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 314987fd49bSBalaji T K if (ret < 0 && host->vcc) 31599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31699fc5131SLinus Walleij host->vcc, 0); 317db0fefc5SAdrian Hunter } 318db0fefc5SAdrian Hunter } else { 31999fc5131SLinus Walleij /* Shut down the rail */ 3206da20c89SAdrian Hunter if (host->vcc_aux) 321db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 322987fd49bSBalaji T K if (host->vcc) { 32399fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 32499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 32599fc5131SLinus Walleij host->vcc, 0); 32699fc5131SLinus Walleij } 327db0fefc5SAdrian Hunter } 328db0fefc5SAdrian Hunter 329e99448ffSBalaji T K if (host->pbias) { 330e99448ffSBalaji T K if (vdd <= VDD_165_195) 331e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 332e99448ffSBalaji T K VDD_1V8); 333e99448ffSBalaji T K else 334e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 335e99448ffSBalaji T K VDD_3V0); 336e99448ffSBalaji T K if (ret < 0) 337e99448ffSBalaji T K goto error_set_power; 338e99448ffSBalaji T K 339e99448ffSBalaji T K if (host->pbias_enabled == 0) { 340e99448ffSBalaji T K ret = regulator_enable(host->pbias); 341e99448ffSBalaji T K if (!ret) 342e99448ffSBalaji T K host->pbias_enabled = 1; 343e99448ffSBalaji T K } 344e99448ffSBalaji T K } 345e99448ffSBalaji T K 346db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 347db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 348db0fefc5SAdrian Hunter 349e99448ffSBalaji T K error_set_power: 350db0fefc5SAdrian Hunter return ret; 351db0fefc5SAdrian Hunter } 352db0fefc5SAdrian Hunter 353db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 354db0fefc5SAdrian Hunter { 355db0fefc5SAdrian Hunter struct regulator *reg; 35664be9782Skishore kadiyala int ocr_value = 0; 357db0fefc5SAdrian Hunter 358f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 359db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 360987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 361987fd49bSBalaji T K PTR_ERR(reg)); 3621fdc90fbSNeilBrown return PTR_ERR(reg); 363db0fefc5SAdrian Hunter } else { 364db0fefc5SAdrian Hunter host->vcc = reg; 36564be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 36664be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 36764be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 36864be9782Skishore kadiyala } else { 36964be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3702cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 371e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 37264be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 37364be9782Skishore kadiyala return -EINVAL; 37464be9782Skishore kadiyala } 37564be9782Skishore kadiyala } 376987fd49bSBalaji T K } 377987fd49bSBalaji T K mmc_slot(host).set_power = omap_hsmmc_set_power; 378db0fefc5SAdrian Hunter 379db0fefc5SAdrian Hunter /* Allow an aux regulator */ 380f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 381db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 382db0fefc5SAdrian Hunter 383e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 384e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 385e99448ffSBalaji T K 386b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 387b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 388b1c1df7aSBalaji T K return 0; 389db0fefc5SAdrian Hunter /* 390987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 391987fd49bSBalaji T K * to increase usecount and then disable it. 392db0fefc5SAdrian Hunter */ 393987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 394e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 395e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 396e840ce13SAdrian Hunter 397987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 398987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 399db0fefc5SAdrian Hunter } 400db0fefc5SAdrian Hunter 401db0fefc5SAdrian Hunter return 0; 402db0fefc5SAdrian Hunter } 403db0fefc5SAdrian Hunter 404db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 405db0fefc5SAdrian Hunter { 406db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 407db0fefc5SAdrian Hunter } 408db0fefc5SAdrian Hunter 409b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 410b702b106SAdrian Hunter { 411b702b106SAdrian Hunter return 1; 412b702b106SAdrian Hunter } 413b702b106SAdrian Hunter 414b702b106SAdrian Hunter #else 415b702b106SAdrian Hunter 416b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 417b702b106SAdrian Hunter { 418b702b106SAdrian Hunter return -EINVAL; 419b702b106SAdrian Hunter } 420b702b106SAdrian Hunter 421b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 422b702b106SAdrian Hunter { 423b702b106SAdrian Hunter } 424b702b106SAdrian Hunter 425b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 426b702b106SAdrian Hunter { 427b702b106SAdrian Hunter return 0; 428b702b106SAdrian Hunter } 429b702b106SAdrian Hunter 430b702b106SAdrian Hunter #endif 431b702b106SAdrian Hunter 432b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 433b702b106SAdrian Hunter { 434b702b106SAdrian Hunter int ret; 435b702b106SAdrian Hunter 436b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 437b702b106SAdrian Hunter if (pdata->slots[0].cover) 438b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 439b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 440b702b106SAdrian Hunter else 441b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 442b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 443b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 444b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 445b702b106SAdrian Hunter if (ret) 446b702b106SAdrian Hunter return ret; 447b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 448b702b106SAdrian Hunter if (ret) 449b702b106SAdrian Hunter goto err_free_sp; 450b702b106SAdrian Hunter } else 451b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 452b702b106SAdrian Hunter 453b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 454b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 455b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 456b702b106SAdrian Hunter if (ret) 457b702b106SAdrian Hunter goto err_free_cd; 458b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 459b702b106SAdrian Hunter if (ret) 460b702b106SAdrian Hunter goto err_free_wp; 461b702b106SAdrian Hunter } else 462b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 463b702b106SAdrian Hunter 464b702b106SAdrian Hunter return 0; 465b702b106SAdrian Hunter 466b702b106SAdrian Hunter err_free_wp: 467b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 468b702b106SAdrian Hunter err_free_cd: 469b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 470b702b106SAdrian Hunter err_free_sp: 471b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 472b702b106SAdrian Hunter return ret; 473b702b106SAdrian Hunter } 474b702b106SAdrian Hunter 475b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 476b702b106SAdrian Hunter { 477b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 478b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 479b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 480b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 481b702b106SAdrian Hunter } 482b702b106SAdrian Hunter 483a45c6cb8SMadhusudhan Chikkature /* 484e0c7f99bSAndy Shevchenko * Start clock to the card 485e0c7f99bSAndy Shevchenko */ 486e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 487e0c7f99bSAndy Shevchenko { 488e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 489e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 490e0c7f99bSAndy Shevchenko } 491e0c7f99bSAndy Shevchenko 492e0c7f99bSAndy Shevchenko /* 493a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 494a45c6cb8SMadhusudhan Chikkature */ 49570a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 496a45c6cb8SMadhusudhan Chikkature { 497a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 498a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 499a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5007122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 501a45c6cb8SMadhusudhan Chikkature } 502a45c6cb8SMadhusudhan Chikkature 50393caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 50493caf8e6SAdrian Hunter struct mmc_command *cmd) 505b417577dSAdrian Hunter { 506b417577dSAdrian Hunter unsigned int irq_mask; 507b417577dSAdrian Hunter 508b417577dSAdrian Hunter if (host->use_dma) 509a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 510b417577dSAdrian Hunter else 511b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 512b417577dSAdrian Hunter 51393caf8e6SAdrian Hunter /* Disable timeout for erases */ 51493caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 515a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 51693caf8e6SAdrian Hunter 517b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 518b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 519b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 520b417577dSAdrian Hunter } 521b417577dSAdrian Hunter 522b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 523b417577dSAdrian Hunter { 524b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 525b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 526b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 527b417577dSAdrian Hunter } 528b417577dSAdrian Hunter 529ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 530d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 531ac330f44SAndy Shevchenko { 532ac330f44SAndy Shevchenko u16 dsor = 0; 533ac330f44SAndy Shevchenko 534ac330f44SAndy Shevchenko if (ios->clock) { 535d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 536ed164182SBalaji T K if (dsor > CLKD_MAX) 537ed164182SBalaji T K dsor = CLKD_MAX; 538ac330f44SAndy Shevchenko } 539ac330f44SAndy Shevchenko 540ac330f44SAndy Shevchenko return dsor; 541ac330f44SAndy Shevchenko } 542ac330f44SAndy Shevchenko 5435934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5445934df2fSAndy Shevchenko { 5455934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5465934df2fSAndy Shevchenko unsigned long regval; 5475934df2fSAndy Shevchenko unsigned long timeout; 548cd587096SHebbar, Gururaja unsigned long clkdiv; 5495934df2fSAndy Shevchenko 5508986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5515934df2fSAndy Shevchenko 5525934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5535934df2fSAndy Shevchenko 5545934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5555934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 556cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 557cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5585934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5595934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5605934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5615934df2fSAndy Shevchenko 5625934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5635934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5645934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5655934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5665934df2fSAndy Shevchenko cpu_relax(); 5675934df2fSAndy Shevchenko 568cd587096SHebbar, Gururaja /* 569cd587096SHebbar, Gururaja * Enable High-Speed Support 570cd587096SHebbar, Gururaja * Pre-Requisites 571cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 572cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 573cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 574cd587096SHebbar, Gururaja * in capabilities register 575cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 576cd587096SHebbar, Gururaja */ 577cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 578cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 579cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 580cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 581cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 582cd587096SHebbar, Gururaja regval |= HSPE; 583cd587096SHebbar, Gururaja else 584cd587096SHebbar, Gururaja regval &= ~HSPE; 585cd587096SHebbar, Gururaja 586cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 587cd587096SHebbar, Gururaja } 588cd587096SHebbar, Gururaja 5895934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5905934df2fSAndy Shevchenko } 5915934df2fSAndy Shevchenko 5923796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5933796fb8aSAndy Shevchenko { 5943796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5953796fb8aSAndy Shevchenko u32 con; 5963796fb8aSAndy Shevchenko 5973796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 59803b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 59903b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 60003b5d924SBalaji T K else 60103b5d924SBalaji T K con &= ~DDR; 6023796fb8aSAndy Shevchenko switch (ios->bus_width) { 6033796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6043796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6053796fb8aSAndy Shevchenko break; 6063796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6073796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6083796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6093796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6103796fb8aSAndy Shevchenko break; 6113796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6123796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6133796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6143796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6153796fb8aSAndy Shevchenko break; 6163796fb8aSAndy Shevchenko } 6173796fb8aSAndy Shevchenko } 6183796fb8aSAndy Shevchenko 6193796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6203796fb8aSAndy Shevchenko { 6213796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6223796fb8aSAndy Shevchenko u32 con; 6233796fb8aSAndy Shevchenko 6243796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6253796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6263796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6273796fb8aSAndy Shevchenko else 6283796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6293796fb8aSAndy Shevchenko } 6303796fb8aSAndy Shevchenko 63111dd62a7SDenis Karpov #ifdef CONFIG_PM 63211dd62a7SDenis Karpov 63311dd62a7SDenis Karpov /* 63411dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 63511dd62a7SDenis Karpov * power state change. 63611dd62a7SDenis Karpov */ 63770a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 63811dd62a7SDenis Karpov { 63911dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6403796fb8aSAndy Shevchenko u32 hctl, capa; 64111dd62a7SDenis Karpov unsigned long timeout; 64211dd62a7SDenis Karpov 6436c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 6446c31b215SVenkatraman S return 1; 64511dd62a7SDenis Karpov 6460a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6470a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6480a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6490a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6500a82e06eSTony Lindgren return 0; 6510a82e06eSTony Lindgren 6520a82e06eSTony Lindgren host->context_loss++; 6530a82e06eSTony Lindgren 654c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 65511dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 65611dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 65711dd62a7SDenis Karpov hctl = SDVS18; 65811dd62a7SDenis Karpov else 65911dd62a7SDenis Karpov hctl = SDVS30; 66011dd62a7SDenis Karpov capa = VS30 | VS18; 66111dd62a7SDenis Karpov } else { 66211dd62a7SDenis Karpov hctl = SDVS18; 66311dd62a7SDenis Karpov capa = VS18; 66411dd62a7SDenis Karpov } 66511dd62a7SDenis Karpov 66611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 66811dd62a7SDenis Karpov 66911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 67011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 67111dd62a7SDenis Karpov 67211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 67411dd62a7SDenis Karpov 67511dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 67611dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 67711dd62a7SDenis Karpov && time_before(jiffies, timeout)) 67811dd62a7SDenis Karpov ; 67911dd62a7SDenis Karpov 680b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 68111dd62a7SDenis Karpov 68211dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 68311dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 68411dd62a7SDenis Karpov goto out; 68511dd62a7SDenis Karpov 6863796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 68711dd62a7SDenis Karpov 6885934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 68911dd62a7SDenis Karpov 6903796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6913796fb8aSAndy Shevchenko 69211dd62a7SDenis Karpov out: 6930a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6940a82e06eSTony Lindgren host->context_loss); 69511dd62a7SDenis Karpov return 0; 69611dd62a7SDenis Karpov } 69711dd62a7SDenis Karpov 69811dd62a7SDenis Karpov /* 69911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 70011dd62a7SDenis Karpov */ 70170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70211dd62a7SDenis Karpov { 7030a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7040a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7050a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7060a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 70711dd62a7SDenis Karpov } 70811dd62a7SDenis Karpov 70911dd62a7SDenis Karpov #else 71011dd62a7SDenis Karpov 71170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 71211dd62a7SDenis Karpov { 71311dd62a7SDenis Karpov return 0; 71411dd62a7SDenis Karpov } 71511dd62a7SDenis Karpov 71670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 71711dd62a7SDenis Karpov { 71811dd62a7SDenis Karpov } 71911dd62a7SDenis Karpov 72011dd62a7SDenis Karpov #endif 72111dd62a7SDenis Karpov 722a45c6cb8SMadhusudhan Chikkature /* 723a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 724a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 725a45c6cb8SMadhusudhan Chikkature */ 72670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 727a45c6cb8SMadhusudhan Chikkature { 728a45c6cb8SMadhusudhan Chikkature int reg = 0; 729a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 730a45c6cb8SMadhusudhan Chikkature 731b62f6228SAdrian Hunter if (host->protect_card) 732b62f6228SAdrian Hunter return; 733b62f6228SAdrian Hunter 734a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 735b417577dSAdrian Hunter 736b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 737a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 738a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 739a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 740a45c6cb8SMadhusudhan Chikkature 741a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 742a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 743a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 744a45c6cb8SMadhusudhan Chikkature 745a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 746a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 747c653a6d4SAdrian Hunter 748c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 749c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 750c653a6d4SAdrian Hunter 751a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 752a45c6cb8SMadhusudhan Chikkature } 753a45c6cb8SMadhusudhan Chikkature 754a45c6cb8SMadhusudhan Chikkature static inline 75570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 756a45c6cb8SMadhusudhan Chikkature { 757a45c6cb8SMadhusudhan Chikkature int r = 1; 758a45c6cb8SMadhusudhan Chikkature 759191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 760191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 761a45c6cb8SMadhusudhan Chikkature return r; 762a45c6cb8SMadhusudhan Chikkature } 763a45c6cb8SMadhusudhan Chikkature 764a45c6cb8SMadhusudhan Chikkature static ssize_t 76570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 766a45c6cb8SMadhusudhan Chikkature char *buf) 767a45c6cb8SMadhusudhan Chikkature { 768a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 76970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 770a45c6cb8SMadhusudhan Chikkature 77170a3341aSDenis Karpov return sprintf(buf, "%s\n", 77270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 773a45c6cb8SMadhusudhan Chikkature } 774a45c6cb8SMadhusudhan Chikkature 77570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 776a45c6cb8SMadhusudhan Chikkature 777a45c6cb8SMadhusudhan Chikkature static ssize_t 77870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 779a45c6cb8SMadhusudhan Chikkature char *buf) 780a45c6cb8SMadhusudhan Chikkature { 781a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 78270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 783a45c6cb8SMadhusudhan Chikkature 784191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 785a45c6cb8SMadhusudhan Chikkature } 786a45c6cb8SMadhusudhan Chikkature 78770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 788a45c6cb8SMadhusudhan Chikkature 789a45c6cb8SMadhusudhan Chikkature /* 790a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 791a45c6cb8SMadhusudhan Chikkature */ 792a45c6cb8SMadhusudhan Chikkature static void 79370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 794a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 795a45c6cb8SMadhusudhan Chikkature { 796a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 797a45c6cb8SMadhusudhan Chikkature 7988986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 799a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 800a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 801a45c6cb8SMadhusudhan Chikkature 80293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 803a45c6cb8SMadhusudhan Chikkature 8044a694dc9SAdrian Hunter host->response_busy = 0; 805a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 806a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 807a45c6cb8SMadhusudhan Chikkature resptype = 1; 8084a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8094a694dc9SAdrian Hunter resptype = 3; 8104a694dc9SAdrian Hunter host->response_busy = 1; 8114a694dc9SAdrian Hunter } else 812a45c6cb8SMadhusudhan Chikkature resptype = 2; 813a45c6cb8SMadhusudhan Chikkature } 814a45c6cb8SMadhusudhan Chikkature 815a45c6cb8SMadhusudhan Chikkature /* 816a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 817a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 818a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 819a45c6cb8SMadhusudhan Chikkature */ 820a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 821a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 822a45c6cb8SMadhusudhan Chikkature 823a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 824a45c6cb8SMadhusudhan Chikkature 825a45c6cb8SMadhusudhan Chikkature if (data) { 826a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 827a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 828a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 829a45c6cb8SMadhusudhan Chikkature else 830a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 831a45c6cb8SMadhusudhan Chikkature } 832a45c6cb8SMadhusudhan Chikkature 833a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 834a7e96879SVenkatraman S cmdreg |= DMAE; 835a45c6cb8SMadhusudhan Chikkature 836b417577dSAdrian Hunter host->req_in_progress = 1; 8374dffd7a2SAdrian Hunter 838a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 839a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 840a45c6cb8SMadhusudhan Chikkature } 841a45c6cb8SMadhusudhan Chikkature 8420ccd76d4SJuha Yrjola static int 84370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8440ccd76d4SJuha Yrjola { 8450ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8460ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8470ccd76d4SJuha Yrjola else 8480ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8490ccd76d4SJuha Yrjola } 8500ccd76d4SJuha Yrjola 851c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 852c5c98927SRussell King struct mmc_data *data) 853c5c98927SRussell King { 854c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 855c5c98927SRussell King } 856c5c98927SRussell King 857b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 858b417577dSAdrian Hunter { 859b417577dSAdrian Hunter int dma_ch; 86031463b14SVenkatraman S unsigned long flags; 861b417577dSAdrian Hunter 86231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 863b417577dSAdrian Hunter host->req_in_progress = 0; 864b417577dSAdrian Hunter dma_ch = host->dma_ch; 86531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 866b417577dSAdrian Hunter 867b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 868b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 869b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 870b417577dSAdrian Hunter return; 871b417577dSAdrian Hunter host->mrq = NULL; 872b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 873b417577dSAdrian Hunter } 874b417577dSAdrian Hunter 875a45c6cb8SMadhusudhan Chikkature /* 876a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 877a45c6cb8SMadhusudhan Chikkature */ 878a45c6cb8SMadhusudhan Chikkature static void 87970a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 880a45c6cb8SMadhusudhan Chikkature { 8814a694dc9SAdrian Hunter if (!data) { 8824a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8834a694dc9SAdrian Hunter 88423050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 88523050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 88623050103SAdrian Hunter host->response_busy) { 88723050103SAdrian Hunter host->response_busy = 0; 88823050103SAdrian Hunter return; 88923050103SAdrian Hunter } 89023050103SAdrian Hunter 891b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8924a694dc9SAdrian Hunter return; 8934a694dc9SAdrian Hunter } 8944a694dc9SAdrian Hunter 895a45c6cb8SMadhusudhan Chikkature host->data = NULL; 896a45c6cb8SMadhusudhan Chikkature 897a45c6cb8SMadhusudhan Chikkature if (!data->error) 898a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 899a45c6cb8SMadhusudhan Chikkature else 900a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 901a45c6cb8SMadhusudhan Chikkature 902fe852273SMing Lei if (!data->stop) { 903dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 904fe852273SMing Lei return; 905dba3c29eSBalaji T K } 906fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 907a45c6cb8SMadhusudhan Chikkature } 908a45c6cb8SMadhusudhan Chikkature 909a45c6cb8SMadhusudhan Chikkature /* 910a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 911a45c6cb8SMadhusudhan Chikkature */ 912a45c6cb8SMadhusudhan Chikkature static void 91370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 914a45c6cb8SMadhusudhan Chikkature { 915a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 916a45c6cb8SMadhusudhan Chikkature 917a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 918a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 919a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 920a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 921a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 922a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 923a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 924a45c6cb8SMadhusudhan Chikkature } else { 925a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 926a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 927a45c6cb8SMadhusudhan Chikkature } 928a45c6cb8SMadhusudhan Chikkature } 929b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 930b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 931a45c6cb8SMadhusudhan Chikkature } 932a45c6cb8SMadhusudhan Chikkature 933a45c6cb8SMadhusudhan Chikkature /* 934a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 935a45c6cb8SMadhusudhan Chikkature */ 93670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 937a45c6cb8SMadhusudhan Chikkature { 938b417577dSAdrian Hunter int dma_ch; 93931463b14SVenkatraman S unsigned long flags; 940b417577dSAdrian Hunter 94182788ff5SJarkko Lavinen host->data->error = errno; 942a45c6cb8SMadhusudhan Chikkature 94331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 944b417577dSAdrian Hunter dma_ch = host->dma_ch; 945b417577dSAdrian Hunter host->dma_ch = -1; 94631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 947b417577dSAdrian Hunter 948b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 949c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 950c5c98927SRussell King 951c5c98927SRussell King dmaengine_terminate_all(chan); 952c5c98927SRussell King dma_unmap_sg(chan->device->dev, 953c5c98927SRussell King host->data->sg, host->data->sg_len, 95470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 955c5c98927SRussell King 956053bf34fSPer Forlin host->data->host_cookie = 0; 957a45c6cb8SMadhusudhan Chikkature } 958a45c6cb8SMadhusudhan Chikkature host->data = NULL; 959a45c6cb8SMadhusudhan Chikkature } 960a45c6cb8SMadhusudhan Chikkature 961a45c6cb8SMadhusudhan Chikkature /* 962a45c6cb8SMadhusudhan Chikkature * Readable error output 963a45c6cb8SMadhusudhan Chikkature */ 964a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 965699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 966a45c6cb8SMadhusudhan Chikkature { 967a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 96870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 969699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 970699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 971699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 972699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 973a45c6cb8SMadhusudhan Chikkature }; 974a45c6cb8SMadhusudhan Chikkature char res[256]; 975a45c6cb8SMadhusudhan Chikkature char *buf = res; 976a45c6cb8SMadhusudhan Chikkature int len, i; 977a45c6cb8SMadhusudhan Chikkature 978a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 979a45c6cb8SMadhusudhan Chikkature buf += len; 980a45c6cb8SMadhusudhan Chikkature 98170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 982a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 98370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 984a45c6cb8SMadhusudhan Chikkature buf += len; 985a45c6cb8SMadhusudhan Chikkature } 986a45c6cb8SMadhusudhan Chikkature 9878986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 988a45c6cb8SMadhusudhan Chikkature } 989699b958bSAdrian Hunter #else 990699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 991699b958bSAdrian Hunter u32 status) 992699b958bSAdrian Hunter { 993699b958bSAdrian Hunter } 994a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 995a45c6cb8SMadhusudhan Chikkature 9963ebf74b1SJean Pihet /* 9973ebf74b1SJean Pihet * MMC controller internal state machines reset 9983ebf74b1SJean Pihet * 9993ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10003ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10013ebf74b1SJean Pihet * Can be called from interrupt context 10023ebf74b1SJean Pihet */ 100370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10043ebf74b1SJean Pihet unsigned long bit) 10053ebf74b1SJean Pihet { 10063ebf74b1SJean Pihet unsigned long i = 0; 10071e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10083ebf74b1SJean Pihet 10093ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10103ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10113ebf74b1SJean Pihet 101207ad64b6SMadhusudhan Chikkature /* 101307ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 101407ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 101507ad64b6SMadhusudhan Chikkature */ 101607ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1017b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 101807ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10191e881786SJianpeng Ma udelay(1); 102007ad64b6SMadhusudhan Chikkature } 102107ad64b6SMadhusudhan Chikkature i = 0; 102207ad64b6SMadhusudhan Chikkature 10233ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10243ebf74b1SJean Pihet (i++ < limit)) 10251e881786SJianpeng Ma udelay(1); 10263ebf74b1SJean Pihet 10273ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10283ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10293ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10303ebf74b1SJean Pihet __func__); 10313ebf74b1SJean Pihet } 1032a45c6cb8SMadhusudhan Chikkature 103325e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 103425e1897bSBalaji T K int err, int end_cmd) 1035ae4bf788SVenkatraman S { 103625e1897bSBalaji T K if (end_cmd) { 103794d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 103825e1897bSBalaji T K if (host->cmd) 1039ae4bf788SVenkatraman S host->cmd->error = err; 104025e1897bSBalaji T K } 1041ae4bf788SVenkatraman S 1042ae4bf788SVenkatraman S if (host->data) { 1043ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1044ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1045dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1046dc7745bdSBalaji T K host->mrq->cmd->error = err; 1047ae4bf788SVenkatraman S } 1048ae4bf788SVenkatraman S 1049b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1050a45c6cb8SMadhusudhan Chikkature { 1051a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1052b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1053a45c6cb8SMadhusudhan Chikkature 1054a45c6cb8SMadhusudhan Chikkature data = host->data; 10558986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1056a45c6cb8SMadhusudhan Chikkature 1057a7e96879SVenkatraman S if (status & ERR_EN) { 1058699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10594a694dc9SAdrian Hunter 1060a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1061a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1062a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 106325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1064a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 106525e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 106625e1897bSBalaji T K 1067ae4bf788SVenkatraman S if (host->data || host->response_busy) { 106825e1897bSBalaji T K end_trans = !end_cmd; 1069ae4bf788SVenkatraman S host->response_busy = 0; 1070a45c6cb8SMadhusudhan Chikkature } 1071a45c6cb8SMadhusudhan Chikkature } 1072a45c6cb8SMadhusudhan Chikkature 10737472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1074a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 107570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1076a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 107770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1078b417577dSAdrian Hunter } 1079a45c6cb8SMadhusudhan Chikkature 1080b417577dSAdrian Hunter /* 1081b417577dSAdrian Hunter * MMC controller IRQ handler 1082b417577dSAdrian Hunter */ 1083b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1084b417577dSAdrian Hunter { 1085b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1086b417577dSAdrian Hunter int status; 1087b417577dSAdrian Hunter 1088b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10891f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1090b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10911f6b9fa4SVenkatraman S 1092b417577dSAdrian Hunter /* Flush posted write */ 1093b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10941f6b9fa4SVenkatraman S } 10954dffd7a2SAdrian Hunter 1096a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1097a45c6cb8SMadhusudhan Chikkature } 1098a45c6cb8SMadhusudhan Chikkature 109970a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1100e13bb300SAdrian Hunter { 1101e13bb300SAdrian Hunter unsigned long i; 1102e13bb300SAdrian Hunter 1103e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1104e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1105e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1106e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1107e13bb300SAdrian Hunter break; 1108e13bb300SAdrian Hunter cpu_relax(); 1109e13bb300SAdrian Hunter } 1110e13bb300SAdrian Hunter } 1111e13bb300SAdrian Hunter 1112a45c6cb8SMadhusudhan Chikkature /* 1113eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1114eb250826SDavid Brownell * 1115eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1116eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1117eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1118a45c6cb8SMadhusudhan Chikkature */ 111970a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1120a45c6cb8SMadhusudhan Chikkature { 1121a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1122a45c6cb8SMadhusudhan Chikkature int ret; 1123a45c6cb8SMadhusudhan Chikkature 1124a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1125fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1126cd03d9a8SRajendra Nayak if (host->dbclk) 112794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1128a45c6cb8SMadhusudhan Chikkature 1129a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1130a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1131a45c6cb8SMadhusudhan Chikkature 1132a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11332bec0893SAdrian Hunter if (!ret) 11342bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11352bec0893SAdrian Hunter vdd); 1136fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1137cd03d9a8SRajendra Nayak if (host->dbclk) 113894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11392bec0893SAdrian Hunter 1140a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1141a45c6cb8SMadhusudhan Chikkature goto err; 1142a45c6cb8SMadhusudhan Chikkature 1143a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1144a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1145a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1146eb250826SDavid Brownell 1147a45c6cb8SMadhusudhan Chikkature /* 1148a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1149a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 115070a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1151a45c6cb8SMadhusudhan Chikkature * 1152eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1153eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1154eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1155eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1156eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1157eb250826SDavid Brownell * 1158eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1159eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1160eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1161a45c6cb8SMadhusudhan Chikkature */ 1162eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1163a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1164eb250826SDavid Brownell else 1165eb250826SDavid Brownell reg_val |= SDVS30; 1166a45c6cb8SMadhusudhan Chikkature 1167a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1168e13bb300SAdrian Hunter set_sd_bus_power(host); 1169a45c6cb8SMadhusudhan Chikkature 1170a45c6cb8SMadhusudhan Chikkature return 0; 1171a45c6cb8SMadhusudhan Chikkature err: 1172b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1173a45c6cb8SMadhusudhan Chikkature return ret; 1174a45c6cb8SMadhusudhan Chikkature } 1175a45c6cb8SMadhusudhan Chikkature 1176b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1177b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1178b62f6228SAdrian Hunter { 1179b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1180b62f6228SAdrian Hunter return; 1181b62f6228SAdrian Hunter 1182b62f6228SAdrian Hunter host->reqs_blocked = 0; 1183b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1184b62f6228SAdrian Hunter if (host->protect_card) { 11852cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1186b62f6228SAdrian Hunter "card is now accessible\n", 1187b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1188b62f6228SAdrian Hunter host->protect_card = 0; 1189b62f6228SAdrian Hunter } 1190b62f6228SAdrian Hunter } else { 1191b62f6228SAdrian Hunter if (!host->protect_card) { 11922cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1193b62f6228SAdrian Hunter "card is now inaccessible\n", 1194b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1195b62f6228SAdrian Hunter host->protect_card = 1; 1196b62f6228SAdrian Hunter } 1197b62f6228SAdrian Hunter } 1198b62f6228SAdrian Hunter } 1199b62f6228SAdrian Hunter 1200a45c6cb8SMadhusudhan Chikkature /* 12017efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1202a45c6cb8SMadhusudhan Chikkature */ 12037efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1204a45c6cb8SMadhusudhan Chikkature { 12057efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1206249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1207a6b2240dSAdrian Hunter int carddetect; 1208249d0fa9SDavid Brownell 1209a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1210a6b2240dSAdrian Hunter 1211191d1f1dSDenis Karpov if (slot->card_detect) 1212db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1213b62f6228SAdrian Hunter else { 1214b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1215a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1216b62f6228SAdrian Hunter } 1217a6b2240dSAdrian Hunter 1218cdeebaddSMadhusudhan Chikkature if (carddetect) 1219a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1220cdeebaddSMadhusudhan Chikkature else 1221a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1222a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1223a45c6cb8SMadhusudhan Chikkature } 1224a45c6cb8SMadhusudhan Chikkature 1225c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12260ccd76d4SJuha Yrjola { 1227c5c98927SRussell King struct omap_hsmmc_host *host = param; 1228c5c98927SRussell King struct dma_chan *chan; 1229770d7432SAdrian Hunter struct mmc_data *data; 1230c5c98927SRussell King int req_in_progress; 1231a45c6cb8SMadhusudhan Chikkature 1232c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1233b417577dSAdrian Hunter if (host->dma_ch < 0) { 1234c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1235a45c6cb8SMadhusudhan Chikkature return; 1236b417577dSAdrian Hunter } 1237a45c6cb8SMadhusudhan Chikkature 1238770d7432SAdrian Hunter data = host->mrq->data; 1239c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12409782aff8SPer Forlin if (!data->host_cookie) 1241c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1242c5c98927SRussell King data->sg, data->sg_len, 1243b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1244b417577dSAdrian Hunter 1245b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1246a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1247c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1248b417577dSAdrian Hunter 1249b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1250b417577dSAdrian Hunter if (!req_in_progress) { 1251b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1252b417577dSAdrian Hunter 1253b417577dSAdrian Hunter host->mrq = NULL; 1254b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1255b417577dSAdrian Hunter } 1256a45c6cb8SMadhusudhan Chikkature } 1257a45c6cb8SMadhusudhan Chikkature 12589782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12599782aff8SPer Forlin struct mmc_data *data, 1260c5c98927SRussell King struct omap_hsmmc_next *next, 126126b88520SRussell King struct dma_chan *chan) 12629782aff8SPer Forlin { 12639782aff8SPer Forlin int dma_len; 12649782aff8SPer Forlin 12659782aff8SPer Forlin if (!next && data->host_cookie && 12669782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12672cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12689782aff8SPer Forlin " host->next_data.cookie %d\n", 12699782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12709782aff8SPer Forlin data->host_cookie = 0; 12719782aff8SPer Forlin } 12729782aff8SPer Forlin 12739782aff8SPer Forlin /* Check if next job is already prepared */ 1274b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 127526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12769782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12779782aff8SPer Forlin 12789782aff8SPer Forlin } else { 12799782aff8SPer Forlin dma_len = host->next_data.dma_len; 12809782aff8SPer Forlin host->next_data.dma_len = 0; 12819782aff8SPer Forlin } 12829782aff8SPer Forlin 12839782aff8SPer Forlin 12849782aff8SPer Forlin if (dma_len == 0) 12859782aff8SPer Forlin return -EINVAL; 12869782aff8SPer Forlin 12879782aff8SPer Forlin if (next) { 12889782aff8SPer Forlin next->dma_len = dma_len; 12899782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12909782aff8SPer Forlin } else 12919782aff8SPer Forlin host->dma_len = dma_len; 12929782aff8SPer Forlin 12939782aff8SPer Forlin return 0; 12949782aff8SPer Forlin } 12959782aff8SPer Forlin 1296a45c6cb8SMadhusudhan Chikkature /* 1297a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1298a45c6cb8SMadhusudhan Chikkature */ 129970a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 130070a3341aSDenis Karpov struct mmc_request *req) 1301a45c6cb8SMadhusudhan Chikkature { 130226b88520SRussell King struct dma_slave_config cfg; 130326b88520SRussell King struct dma_async_tx_descriptor *tx; 130426b88520SRussell King int ret = 0, i; 1305a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1306c5c98927SRussell King struct dma_chan *chan; 1307a45c6cb8SMadhusudhan Chikkature 13080ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1309a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13100ccd76d4SJuha Yrjola struct scatterlist *sgl; 13110ccd76d4SJuha Yrjola 13120ccd76d4SJuha Yrjola sgl = data->sg + i; 13130ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13140ccd76d4SJuha Yrjola return -EINVAL; 13150ccd76d4SJuha Yrjola } 13160ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13170ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13180ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13190ccd76d4SJuha Yrjola */ 13200ccd76d4SJuha Yrjola return -EINVAL; 13210ccd76d4SJuha Yrjola 1322b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1323a45c6cb8SMadhusudhan Chikkature 1324c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1325c5c98927SRussell King 1326c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1327c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1328c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1329c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1330c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1331c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1332c5c98927SRussell King 1333c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13349782aff8SPer Forlin if (ret) 13359782aff8SPer Forlin return ret; 1336a45c6cb8SMadhusudhan Chikkature 133726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1338c5c98927SRussell King if (ret) 1339c5c98927SRussell King return ret; 1340a45c6cb8SMadhusudhan Chikkature 1341c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1342c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1343c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1344c5c98927SRussell King if (!tx) { 1345c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1346c5c98927SRussell King /* FIXME: cleanup */ 1347c5c98927SRussell King return -1; 1348c5c98927SRussell King } 1349c5c98927SRussell King 1350c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1351c5c98927SRussell King tx->callback_param = host; 1352c5c98927SRussell King 1353c5c98927SRussell King /* Does not fail */ 1354c5c98927SRussell King dmaengine_submit(tx); 1355c5c98927SRussell King 135626b88520SRussell King host->dma_ch = 1; 1357c5c98927SRussell King 1358c5c98927SRussell King dma_async_issue_pending(chan); 1359a45c6cb8SMadhusudhan Chikkature 1360a45c6cb8SMadhusudhan Chikkature return 0; 1361a45c6cb8SMadhusudhan Chikkature } 1362a45c6cb8SMadhusudhan Chikkature 136370a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1364e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1365e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1366a45c6cb8SMadhusudhan Chikkature { 1367a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1368a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1369a45c6cb8SMadhusudhan Chikkature 1370a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1371a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1372a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1373a45c6cb8SMadhusudhan Chikkature clkd = 1; 1374a45c6cb8SMadhusudhan Chikkature 1375a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1376e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1377e2bf08d6SAdrian Hunter timeout += timeout_clks; 1378a45c6cb8SMadhusudhan Chikkature if (timeout) { 1379a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1380a45c6cb8SMadhusudhan Chikkature dto += 1; 1381a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1382a45c6cb8SMadhusudhan Chikkature } 1383a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1384a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1385a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1386a45c6cb8SMadhusudhan Chikkature dto += 1; 1387a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1388a45c6cb8SMadhusudhan Chikkature dto -= 13; 1389a45c6cb8SMadhusudhan Chikkature else 1390a45c6cb8SMadhusudhan Chikkature dto = 0; 1391a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1392a45c6cb8SMadhusudhan Chikkature dto = 14; 1393a45c6cb8SMadhusudhan Chikkature } 1394a45c6cb8SMadhusudhan Chikkature 1395a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1396a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1397a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1398a45c6cb8SMadhusudhan Chikkature } 1399a45c6cb8SMadhusudhan Chikkature 1400a45c6cb8SMadhusudhan Chikkature /* 1401a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1402a45c6cb8SMadhusudhan Chikkature */ 1403a45c6cb8SMadhusudhan Chikkature static int 140470a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1405a45c6cb8SMadhusudhan Chikkature { 1406a45c6cb8SMadhusudhan Chikkature int ret; 1407a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1408a45c6cb8SMadhusudhan Chikkature 1409a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1410a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1411e2bf08d6SAdrian Hunter /* 1412e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1413e2bf08d6SAdrian Hunter * busy signal. 1414e2bf08d6SAdrian Hunter */ 1415e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1416e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1417a45c6cb8SMadhusudhan Chikkature return 0; 1418a45c6cb8SMadhusudhan Chikkature } 1419a45c6cb8SMadhusudhan Chikkature 1420a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1421a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1422e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1423a45c6cb8SMadhusudhan Chikkature 1424a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 142570a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1426a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1427b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1428a45c6cb8SMadhusudhan Chikkature return ret; 1429a45c6cb8SMadhusudhan Chikkature } 1430a45c6cb8SMadhusudhan Chikkature } 1431a45c6cb8SMadhusudhan Chikkature return 0; 1432a45c6cb8SMadhusudhan Chikkature } 1433a45c6cb8SMadhusudhan Chikkature 14349782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14359782aff8SPer Forlin int err) 14369782aff8SPer Forlin { 14379782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14389782aff8SPer Forlin struct mmc_data *data = mrq->data; 14399782aff8SPer Forlin 144026b88520SRussell King if (host->use_dma && data->host_cookie) { 1441c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1442c5c98927SRussell King 144326b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14449782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14459782aff8SPer Forlin data->host_cookie = 0; 14469782aff8SPer Forlin } 14479782aff8SPer Forlin } 14489782aff8SPer Forlin 14499782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14509782aff8SPer Forlin bool is_first_req) 14519782aff8SPer Forlin { 14529782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14539782aff8SPer Forlin 14549782aff8SPer Forlin if (mrq->data->host_cookie) { 14559782aff8SPer Forlin mrq->data->host_cookie = 0; 14569782aff8SPer Forlin return ; 14579782aff8SPer Forlin } 14589782aff8SPer Forlin 1459c5c98927SRussell King if (host->use_dma) { 1460c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1461c5c98927SRussell King 14629782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 146326b88520SRussell King &host->next_data, c)) 14649782aff8SPer Forlin mrq->data->host_cookie = 0; 14659782aff8SPer Forlin } 1466c5c98927SRussell King } 14679782aff8SPer Forlin 1468a45c6cb8SMadhusudhan Chikkature /* 1469a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1470a45c6cb8SMadhusudhan Chikkature */ 147170a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1472a45c6cb8SMadhusudhan Chikkature { 147370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1474a3f406f8SJarkko Lavinen int err; 1475a45c6cb8SMadhusudhan Chikkature 1476b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1477b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1478b62f6228SAdrian Hunter if (host->protect_card) { 1479b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1480b62f6228SAdrian Hunter /* 1481b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1482b62f6228SAdrian Hunter * state by resetting the command and data state 1483b62f6228SAdrian Hunter * machines. 1484b62f6228SAdrian Hunter */ 1485b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1486b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1487b62f6228SAdrian Hunter host->reqs_blocked += 1; 1488b62f6228SAdrian Hunter } 1489b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1490b62f6228SAdrian Hunter if (req->data) 1491b62f6228SAdrian Hunter req->data->error = -EBADF; 1492b417577dSAdrian Hunter req->cmd->retries = 0; 1493b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1494b62f6228SAdrian Hunter return; 1495b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1496b62f6228SAdrian Hunter host->reqs_blocked = 0; 1497a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1498a45c6cb8SMadhusudhan Chikkature host->mrq = req; 149970a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1500a3f406f8SJarkko Lavinen if (err) { 1501a3f406f8SJarkko Lavinen req->cmd->error = err; 1502a3f406f8SJarkko Lavinen if (req->data) 1503a3f406f8SJarkko Lavinen req->data->error = err; 1504a3f406f8SJarkko Lavinen host->mrq = NULL; 1505a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1506a3f406f8SJarkko Lavinen return; 1507a3f406f8SJarkko Lavinen } 1508a3f406f8SJarkko Lavinen 150970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1510a45c6cb8SMadhusudhan Chikkature } 1511a45c6cb8SMadhusudhan Chikkature 1512a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 151370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1514a45c6cb8SMadhusudhan Chikkature { 151570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1516a3621465SAdrian Hunter int do_send_init_stream = 0; 1517a45c6cb8SMadhusudhan Chikkature 1518fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15195e2ea617SAdrian Hunter 1520a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1521a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1522a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1523a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1524a3621465SAdrian Hunter 0, 0); 1525a45c6cb8SMadhusudhan Chikkature break; 1526a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1527a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1528a3621465SAdrian Hunter 1, ios->vdd); 1529a45c6cb8SMadhusudhan Chikkature break; 1530a3621465SAdrian Hunter case MMC_POWER_ON: 1531a3621465SAdrian Hunter do_send_init_stream = 1; 1532a3621465SAdrian Hunter break; 1533a3621465SAdrian Hunter } 1534a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1535a45c6cb8SMadhusudhan Chikkature } 1536a45c6cb8SMadhusudhan Chikkature 1537dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1538dd498effSDenis Karpov 15393796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1540a45c6cb8SMadhusudhan Chikkature 15414621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1542eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1543eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1544eb250826SDavid Brownell */ 1545a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15461f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15471f84b71bSRajendra Nayak /* 15481f84b71bSRajendra Nayak * With pbias cell programming missing, this 1549cf5ae40bSTony Lindgren * can't be allowed on MMC1 when booting with device 15501f84b71bSRajendra Nayak * tree. 15511f84b71bSRajendra Nayak */ 1552cf5ae40bSTony Lindgren !host->pbias_disable) { 1553a45c6cb8SMadhusudhan Chikkature /* 1554a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1555a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1556a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1557a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1558a45c6cb8SMadhusudhan Chikkature */ 155970a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1560a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1561a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1562a45c6cb8SMadhusudhan Chikkature } 1563a45c6cb8SMadhusudhan Chikkature } 1564a45c6cb8SMadhusudhan Chikkature 15655934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1566a45c6cb8SMadhusudhan Chikkature 1567a3621465SAdrian Hunter if (do_send_init_stream) 1568a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1569a45c6cb8SMadhusudhan Chikkature 15703796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15715e2ea617SAdrian Hunter 1572fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1573a45c6cb8SMadhusudhan Chikkature } 1574a45c6cb8SMadhusudhan Chikkature 1575a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1576a45c6cb8SMadhusudhan Chikkature { 157770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1578a45c6cb8SMadhusudhan Chikkature 1579191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1580a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1581db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1582a45c6cb8SMadhusudhan Chikkature } 1583a45c6cb8SMadhusudhan Chikkature 1584a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1585a45c6cb8SMadhusudhan Chikkature { 158670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1587a45c6cb8SMadhusudhan Chikkature 1588191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1589a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1590191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1591a45c6cb8SMadhusudhan Chikkature } 1592a45c6cb8SMadhusudhan Chikkature 15934816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15944816858cSGrazvydas Ignotas { 15954816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15964816858cSGrazvydas Ignotas 15974816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15984816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15994816858cSGrazvydas Ignotas } 16004816858cSGrazvydas Ignotas 160170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 16021b331e69SKim Kyuwon { 16031b331e69SKim Kyuwon u32 hctl, capa, value; 16041b331e69SKim Kyuwon 16051b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 16064621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 16071b331e69SKim Kyuwon hctl = SDVS30; 16081b331e69SKim Kyuwon capa = VS30 | VS18; 16091b331e69SKim Kyuwon } else { 16101b331e69SKim Kyuwon hctl = SDVS18; 16111b331e69SKim Kyuwon capa = VS18; 16121b331e69SKim Kyuwon } 16131b331e69SKim Kyuwon 16141b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 16151b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 16161b331e69SKim Kyuwon 16171b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 16181b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 16191b331e69SKim Kyuwon 16201b331e69SKim Kyuwon /* Set SD bus power bit */ 1621e13bb300SAdrian Hunter set_sd_bus_power(host); 16221b331e69SKim Kyuwon } 16231b331e69SKim Kyuwon 162470a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1625dd498effSDenis Karpov { 162670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1627dd498effSDenis Karpov 1628fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1629fa4aa2d4SBalaji T K 1630dd498effSDenis Karpov return 0; 1631dd498effSDenis Karpov } 1632dd498effSDenis Karpov 1633907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1634dd498effSDenis Karpov { 163570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1636dd498effSDenis Karpov 1637fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1638fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1639fa4aa2d4SBalaji T K 1640dd498effSDenis Karpov return 0; 1641dd498effSDenis Karpov } 1642dd498effSDenis Karpov 164370a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 164470a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 164570a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16469782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16479782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 164870a3341aSDenis Karpov .request = omap_hsmmc_request, 164970a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1650dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1651dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16524816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1653dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1654dd498effSDenis Karpov }; 1655dd498effSDenis Karpov 1656d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1657d900f712SDenis Karpov 165870a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1659d900f712SDenis Karpov { 1660d900f712SDenis Karpov struct mmc_host *mmc = s->private; 166170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 166211dd62a7SDenis Karpov 16630a82e06eSTony Lindgren seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 16640a82e06eSTony Lindgren mmc->index, host->context_loss); 16655e2ea617SAdrian Hunter 1666fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1667d900f712SDenis Karpov 1668d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1669d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1670d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1671d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1672d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1673d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1674d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1675d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1676d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1677d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1678d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1679d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16805e2ea617SAdrian Hunter 1681fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1682fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1683dd498effSDenis Karpov 1684d900f712SDenis Karpov return 0; 1685d900f712SDenis Karpov } 1686d900f712SDenis Karpov 168770a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1688d900f712SDenis Karpov { 168970a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1690d900f712SDenis Karpov } 1691d900f712SDenis Karpov 1692d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 169370a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1694d900f712SDenis Karpov .read = seq_read, 1695d900f712SDenis Karpov .llseek = seq_lseek, 1696d900f712SDenis Karpov .release = single_release, 1697d900f712SDenis Karpov }; 1698d900f712SDenis Karpov 169970a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1700d900f712SDenis Karpov { 1701d900f712SDenis Karpov if (mmc->debugfs_root) 1702d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1703d900f712SDenis Karpov mmc, &mmc_regs_fops); 1704d900f712SDenis Karpov } 1705d900f712SDenis Karpov 1706d900f712SDenis Karpov #else 1707d900f712SDenis Karpov 170870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1709d900f712SDenis Karpov { 1710d900f712SDenis Karpov } 1711d900f712SDenis Karpov 1712d900f712SDenis Karpov #endif 1713d900f712SDenis Karpov 171446856a68SRajendra Nayak #ifdef CONFIG_OF 171559445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 171659445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 171759445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 171859445b10SNishanth Menon }; 171959445b10SNishanth Menon 172059445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 172159445b10SNishanth Menon .reg_offset = 0x100, 172259445b10SNishanth Menon }; 172346856a68SRajendra Nayak 172446856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 172546856a68SRajendra Nayak { 172646856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 172746856a68SRajendra Nayak }, 172846856a68SRajendra Nayak { 172959445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 173059445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 173159445b10SNishanth Menon }, 173259445b10SNishanth Menon { 173346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 173446856a68SRajendra Nayak }, 173546856a68SRajendra Nayak { 173646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 173759445b10SNishanth Menon .data = &omap4_mmc_of_data, 173846856a68SRajendra Nayak }, 173946856a68SRajendra Nayak {}, 1740b6d085f6SChris Ball }; 174146856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 174246856a68SRajendra Nayak 174346856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 174446856a68SRajendra Nayak { 174546856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 174646856a68SRajendra Nayak struct device_node *np = dev->of_node; 1747d8714e87SDaniel Mack u32 bus_width, max_freq; 1748dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1749dc642c28SJan Luebbe 1750dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1751dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1752dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1753dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 175446856a68SRajendra Nayak 175546856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 175646856a68SRajendra Nayak if (!pdata) 175746856a68SRajendra Nayak return NULL; /* out of memory */ 175846856a68SRajendra Nayak 175946856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 176046856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 176146856a68SRajendra Nayak 176246856a68SRajendra Nayak /* This driver only supports 1 slot */ 176346856a68SRajendra Nayak pdata->nr_slots = 1; 1764dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1765dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 176646856a68SRajendra Nayak 176746856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 176846856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 176946856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 177046856a68SRajendra Nayak } 17717f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 177246856a68SRajendra Nayak if (bus_width == 4) 177346856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 177446856a68SRajendra Nayak else if (bus_width == 8) 177546856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 177646856a68SRajendra Nayak 177746856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 177846856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 177946856a68SRajendra Nayak 1780d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1781d8714e87SDaniel Mack pdata->max_freq = max_freq; 1782d8714e87SDaniel Mack 1783cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1784cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1785cd587096SHebbar, Gururaja 1786c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 1787c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; 1788c9ae64dbSDaniel Mack 1789c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1790c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1791c9ae64dbSDaniel Mack 179246856a68SRajendra Nayak return pdata; 179346856a68SRajendra Nayak } 179446856a68SRajendra Nayak #else 179546856a68SRajendra Nayak static inline struct omap_mmc_platform_data 179646856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 179746856a68SRajendra Nayak { 179846856a68SRajendra Nayak return NULL; 179946856a68SRajendra Nayak } 180046856a68SRajendra Nayak #endif 180146856a68SRajendra Nayak 1802c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1803a45c6cb8SMadhusudhan Chikkature { 1804a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1805a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 180670a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1807a45c6cb8SMadhusudhan Chikkature struct resource *res; 1808db0fefc5SAdrian Hunter int ret, irq; 180946856a68SRajendra Nayak const struct of_device_id *match; 181026b88520SRussell King dma_cap_mask_t mask; 181126b88520SRussell King unsigned tx_req, rx_req; 181246b76035SDaniel Mack struct pinctrl *pinctrl; 181359445b10SNishanth Menon const struct omap_mmc_of_data *data; 181446856a68SRajendra Nayak 181546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 181646856a68SRajendra Nayak if (match) { 181746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1818dc642c28SJan Luebbe 1819dc642c28SJan Luebbe if (IS_ERR(pdata)) 1820dc642c28SJan Luebbe return PTR_ERR(pdata); 1821dc642c28SJan Luebbe 182246856a68SRajendra Nayak if (match->data) { 182359445b10SNishanth Menon data = match->data; 182459445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 182559445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 182646856a68SRajendra Nayak } 182746856a68SRajendra Nayak } 1828a45c6cb8SMadhusudhan Chikkature 1829a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1830a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1831a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1832a45c6cb8SMadhusudhan Chikkature } 1833a45c6cb8SMadhusudhan Chikkature 1834a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1835a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1836a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1837a45c6cb8SMadhusudhan Chikkature } 1838a45c6cb8SMadhusudhan Chikkature 1839a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1840a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1841a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1842a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1843a45c6cb8SMadhusudhan Chikkature 1844984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1845a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1846a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1847a45c6cb8SMadhusudhan Chikkature 1848db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1849db0fefc5SAdrian Hunter if (ret) 1850db0fefc5SAdrian Hunter goto err; 1851db0fefc5SAdrian Hunter 185270a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1853a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1854a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1855db0fefc5SAdrian Hunter goto err_alloc; 1856a45c6cb8SMadhusudhan Chikkature } 1857a45c6cb8SMadhusudhan Chikkature 1858a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1859a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1860a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1861a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1862a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1863a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1864a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1865a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1866fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1867a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18686da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18699782aff8SPer Forlin host->next_data.cookie = 1; 1870e99448ffSBalaji T K host->pbias_enabled = 0; 1871a45c6cb8SMadhusudhan Chikkature 1872a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1873a45c6cb8SMadhusudhan Chikkature 187470a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1875dd498effSDenis Karpov 18766b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1877d418ed87SDaniel Mack 1878d418ed87SDaniel Mack if (pdata->max_freq > 0) 1879d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1880d418ed87SDaniel Mack else 18816b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1882a45c6cb8SMadhusudhan Chikkature 18834dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1884a45c6cb8SMadhusudhan Chikkature 18856f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1886a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1887a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1888a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1889a45c6cb8SMadhusudhan Chikkature goto err1; 1890a45c6cb8SMadhusudhan Chikkature } 1891a45c6cb8SMadhusudhan Chikkature 18929b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18939b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18949b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18959b68256cSPaul Walmsley } 1896dd498effSDenis Karpov 1897fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1898fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1899fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1900fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1901a45c6cb8SMadhusudhan Chikkature 190292a3aebfSBalaji T K omap_hsmmc_context_save(host); 190392a3aebfSBalaji T K 1904cf5ae40bSTony Lindgren /* This can be removed once we support PBIAS with DT */ 1905e002264fSBalaji T K if (host->dev->of_node && res->start == 0x4809c000) 1906cf5ae40bSTony Lindgren host->pbias_disable = 1; 1907cf5ae40bSTony Lindgren 1908a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1909a45c6cb8SMadhusudhan Chikkature /* 1910a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1911a45c6cb8SMadhusudhan Chikkature */ 1912cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1913cd03d9a8SRajendra Nayak host->dbclk = NULL; 191494c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1915cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1916cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1917cd03d9a8SRajendra Nayak host->dbclk = NULL; 19182bec0893SAdrian Hunter } 1919a45c6cb8SMadhusudhan Chikkature 19200ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19210ccd76d4SJuha Yrjola * as we want. */ 1922a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19230ccd76d4SJuha Yrjola 1924a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1925a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1926a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1927a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1928a45c6cb8SMadhusudhan Chikkature 192913189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 193093caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1931a45c6cb8SMadhusudhan Chikkature 19323a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19333a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1934a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1935a45c6cb8SMadhusudhan Chikkature 1936191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 193723d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 193823d99bb9SAdrian Hunter 19396fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19406fdc75deSEliad Peller 194170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1942a45c6cb8SMadhusudhan Chikkature 19434a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 1944b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1945b7bf773bSBalaji T K if (!res) { 1946b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19479c17d08cSKevin Hilman ret = -ENXIO; 1948f3e2f1ddSGrazvydas Ignotas goto err_irq; 1949a45c6cb8SMadhusudhan Chikkature } 195026b88520SRussell King tx_req = res->start; 1951b7bf773bSBalaji T K 1952b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1953b7bf773bSBalaji T K if (!res) { 1954b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19559c17d08cSKevin Hilman ret = -ENXIO; 1956b7bf773bSBalaji T K goto err_irq; 1957b7bf773bSBalaji T K } 195826b88520SRussell King rx_req = res->start; 19594a29b559SSantosh Shilimkar } 1960c5c98927SRussell King 1961c5c98927SRussell King dma_cap_zero(mask); 1962c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 196326b88520SRussell King 1964d272fbf0SMatt Porter host->rx_chan = 1965d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1966d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1967d272fbf0SMatt Porter 1968c5c98927SRussell King if (!host->rx_chan) { 196926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 197004e8c7bcSKevin Hilman ret = -ENXIO; 197126b88520SRussell King goto err_irq; 1972c5c98927SRussell King } 197326b88520SRussell King 1974d272fbf0SMatt Porter host->tx_chan = 1975d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1976d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1977d272fbf0SMatt Porter 1978c5c98927SRussell King if (!host->tx_chan) { 197926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 198004e8c7bcSKevin Hilman ret = -ENXIO; 198126b88520SRussell King goto err_irq; 1982c5c98927SRussell King } 1983a45c6cb8SMadhusudhan Chikkature 1984a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1985d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1986a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1987a45c6cb8SMadhusudhan Chikkature if (ret) { 1988b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1989a45c6cb8SMadhusudhan Chikkature goto err_irq; 1990a45c6cb8SMadhusudhan Chikkature } 1991a45c6cb8SMadhusudhan Chikkature 1992a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1993a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1994b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 199570a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1996a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1997a45c6cb8SMadhusudhan Chikkature } 1998a45c6cb8SMadhusudhan Chikkature } 1999db0fefc5SAdrian Hunter 2000b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2001db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2002db0fefc5SAdrian Hunter if (ret) 2003db0fefc5SAdrian Hunter goto err_reg; 2004db0fefc5SAdrian Hunter host->use_reg = 1; 2005db0fefc5SAdrian Hunter } 2006db0fefc5SAdrian Hunter 2007b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 2008a45c6cb8SMadhusudhan Chikkature 2009a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2010e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 20117efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 20127efab4f3SNeilBrown NULL, 20137efab4f3SNeilBrown omap_hsmmc_detect, 2014db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2015a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2016a45c6cb8SMadhusudhan Chikkature if (ret) { 2017b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 2018a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2019a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2020a45c6cb8SMadhusudhan Chikkature } 202172f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 202272f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2023a45c6cb8SMadhusudhan Chikkature } 2024a45c6cb8SMadhusudhan Chikkature 2025b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2026a45c6cb8SMadhusudhan Chikkature 202746b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 202846b76035SDaniel Mack if (IS_ERR(pinctrl)) 202946b76035SDaniel Mack dev_warn(&pdev->dev, 203046b76035SDaniel Mack "pins are not configured from the driver\n"); 203146b76035SDaniel Mack 2032b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2033b62f6228SAdrian Hunter 2034a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2035a45c6cb8SMadhusudhan Chikkature 2036191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2037a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2038a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2039a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2040a45c6cb8SMadhusudhan Chikkature } 2041191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2042a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2043a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2044a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2045db0fefc5SAdrian Hunter goto err_slot_name; 2046a45c6cb8SMadhusudhan Chikkature } 2047a45c6cb8SMadhusudhan Chikkature 204870a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2049fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2050fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2051d900f712SDenis Karpov 2052a45c6cb8SMadhusudhan Chikkature return 0; 2053a45c6cb8SMadhusudhan Chikkature 2054a45c6cb8SMadhusudhan Chikkature err_slot_name: 2055a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2056a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2057db0fefc5SAdrian Hunter err_irq_cd: 2058db0fefc5SAdrian Hunter if (host->use_reg) 2059db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2060db0fefc5SAdrian Hunter err_reg: 2061db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2062db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2063a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2064a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2065a45c6cb8SMadhusudhan Chikkature err_irq: 2066c5c98927SRussell King if (host->tx_chan) 2067c5c98927SRussell King dma_release_channel(host->tx_chan); 2068c5c98927SRussell King if (host->rx_chan) 2069c5c98927SRussell King dma_release_channel(host->rx_chan); 2070d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 207137f6190dSTony Lindgren pm_runtime_disable(host->dev); 2072a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2073cd03d9a8SRajendra Nayak if (host->dbclk) { 207494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2075a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2076a45c6cb8SMadhusudhan Chikkature } 2077a45c6cb8SMadhusudhan Chikkature err1: 2078a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2079a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2080db0fefc5SAdrian Hunter err_alloc: 2081db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2082db0fefc5SAdrian Hunter err: 208348b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 208448b332f9SRussell King if (res) 2085984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2086a45c6cb8SMadhusudhan Chikkature return ret; 2087a45c6cb8SMadhusudhan Chikkature } 2088a45c6cb8SMadhusudhan Chikkature 20896e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2090a45c6cb8SMadhusudhan Chikkature { 209170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2092a45c6cb8SMadhusudhan Chikkature struct resource *res; 2093a45c6cb8SMadhusudhan Chikkature 2094fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2095a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2096db0fefc5SAdrian Hunter if (host->use_reg) 2097db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2098a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2099a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2100a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2101a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2102a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2103a45c6cb8SMadhusudhan Chikkature 2104c5c98927SRussell King if (host->tx_chan) 2105c5c98927SRussell King dma_release_channel(host->tx_chan); 2106c5c98927SRussell King if (host->rx_chan) 2107c5c98927SRussell King dma_release_channel(host->rx_chan); 2108c5c98927SRussell King 2109fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2110fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2111a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2112cd03d9a8SRajendra Nayak if (host->dbclk) { 211394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2114a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2115a45c6cb8SMadhusudhan Chikkature } 2116a45c6cb8SMadhusudhan Chikkature 21179ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2118a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 21199d1f0286SBalaji T K mmc_free_host(host->mmc); 2120a45c6cb8SMadhusudhan Chikkature 2121a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2122a45c6cb8SMadhusudhan Chikkature if (res) 2123984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2124a45c6cb8SMadhusudhan Chikkature 2125a45c6cb8SMadhusudhan Chikkature return 0; 2126a45c6cb8SMadhusudhan Chikkature } 2127a45c6cb8SMadhusudhan Chikkature 2128a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2129a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2130a48ce884SFelipe Balbi { 2131a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2132a48ce884SFelipe Balbi 2133a48ce884SFelipe Balbi if (host->pdata->suspend) 2134a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2135a48ce884SFelipe Balbi 2136a48ce884SFelipe Balbi return 0; 2137a48ce884SFelipe Balbi } 2138a48ce884SFelipe Balbi 2139a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2140a48ce884SFelipe Balbi { 2141a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2142a48ce884SFelipe Balbi 2143a48ce884SFelipe Balbi if (host->pdata->resume) 2144a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2145a48ce884SFelipe Balbi 2146a48ce884SFelipe Balbi } 2147a48ce884SFelipe Balbi 2148a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2149a45c6cb8SMadhusudhan Chikkature { 2150927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2151927ce944SFelipe Balbi 2152927ce944SFelipe Balbi if (!host) 2153927ce944SFelipe Balbi return 0; 2154a45c6cb8SMadhusudhan Chikkature 2155fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 215631f9d463SEliad Peller 215731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 215831f9d463SEliad Peller omap_hsmmc_disable_irq(host); 215931f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 216031f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 216131f9d463SEliad Peller } 2162927ce944SFelipe Balbi 2163cd03d9a8SRajendra Nayak if (host->dbclk) 216494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 21653932afd5SUlf Hansson 2166fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 21673932afd5SUlf Hansson return 0; 2168a45c6cb8SMadhusudhan Chikkature } 2169a45c6cb8SMadhusudhan Chikkature 2170a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2171a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2172a45c6cb8SMadhusudhan Chikkature { 2173927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2174927ce944SFelipe Balbi 2175927ce944SFelipe Balbi if (!host) 2176927ce944SFelipe Balbi return 0; 2177a45c6cb8SMadhusudhan Chikkature 2178fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 217911dd62a7SDenis Karpov 2180cd03d9a8SRajendra Nayak if (host->dbclk) 218194c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21822bec0893SAdrian Hunter 218331f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 218470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21851b331e69SKim Kyuwon 2186b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2187b62f6228SAdrian Hunter 2188fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2189fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 21903932afd5SUlf Hansson return 0; 2191a45c6cb8SMadhusudhan Chikkature } 2192a45c6cb8SMadhusudhan Chikkature 2193a45c6cb8SMadhusudhan Chikkature #else 2194a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2195a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 219670a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 219770a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2198a45c6cb8SMadhusudhan Chikkature #endif 2199a45c6cb8SMadhusudhan Chikkature 2200fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2201fa4aa2d4SBalaji T K { 2202fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2203fa4aa2d4SBalaji T K 2204fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2205fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2206927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2207fa4aa2d4SBalaji T K 2208fa4aa2d4SBalaji T K return 0; 2209fa4aa2d4SBalaji T K } 2210fa4aa2d4SBalaji T K 2211fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2212fa4aa2d4SBalaji T K { 2213fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2214fa4aa2d4SBalaji T K 2215fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2216fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2217927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2218fa4aa2d4SBalaji T K 2219fa4aa2d4SBalaji T K return 0; 2220fa4aa2d4SBalaji T K } 2221fa4aa2d4SBalaji T K 2222a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 222370a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 222470a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2225a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2226a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2227fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2228fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2229a791daa1SKevin Hilman }; 2230a791daa1SKevin Hilman 2231a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2232efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22330433c143SBill Pemberton .remove = omap_hsmmc_remove, 2234a45c6cb8SMadhusudhan Chikkature .driver = { 2235a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2236a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2237a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 223846856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2239a45c6cb8SMadhusudhan Chikkature }, 2240a45c6cb8SMadhusudhan Chikkature }; 2241a45c6cb8SMadhusudhan Chikkature 2242b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2243a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2244a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2245a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2246a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2247