1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22d900f712SDenis Karpov #include <linux/seq_file.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/workqueue.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3113189e78SJarkko Lavinen #include <linux/mmc/core.h> 3293caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 33a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 34a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 35db0fefc5SAdrian Hunter #include <linux/gpio.h> 36db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 37fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 38ce491cf8STony Lindgren #include <plat/dma.h> 39a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 40ce491cf8STony Lindgren #include <plat/board.h> 41ce491cf8STony Lindgren #include <plat/mmc.h> 42ce491cf8STony Lindgren #include <plat/cpu.h> 43a45c6cb8SMadhusudhan Chikkature 44a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 45a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 66a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 67eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 681b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 69a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 70a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 71a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 72a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 73a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 74a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 75a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 76a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 77a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 78a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 79a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 80a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 81a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 82ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 83ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8493caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 85a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 86a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 87a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 88a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 89a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 90a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 91a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9273153010SJarkko Lavinen #define DW8 (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define CC 0x1 94a45c6cb8SMadhusudhan Chikkature #define TC 0x02 95a45c6cb8SMadhusudhan Chikkature #define OD 0x1 96a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 97a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 98a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 99a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 100a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 101a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 102a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 103a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 104a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 105a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 106a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10711dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10811dd62a7SDenis Karpov #define RESETDONE (1 << 0) 109a45c6cb8SMadhusudhan Chikkature 110a45c6cb8SMadhusudhan Chikkature /* 111a45c6cb8SMadhusudhan Chikkature * FIXME: Most likely all the data using these _DEVID defines should come 112a45c6cb8SMadhusudhan Chikkature * from the platform_data, or implemented in controller and slot specific 113a45c6cb8SMadhusudhan Chikkature * functions. 114a45c6cb8SMadhusudhan Chikkature */ 115a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC1_DEVID 0 116a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC2_DEVID 1 117f3e2f1ddSGrazvydas Ignotas #define OMAP_MMC3_DEVID 2 11882cf818dSkishore kadiyala #define OMAP_MMC4_DEVID 3 11982cf818dSkishore kadiyala #define OMAP_MMC5_DEVID 4 120a45c6cb8SMadhusudhan Chikkature 121fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 122a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1236b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1246b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1250005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 126a45c6cb8SMadhusudhan Chikkature 127a45c6cb8SMadhusudhan Chikkature /* 128a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 129a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 130a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 131a45c6cb8SMadhusudhan Chikkature */ 132a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 133a45c6cb8SMadhusudhan Chikkature 134a45c6cb8SMadhusudhan Chikkature /* 135a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 136a45c6cb8SMadhusudhan Chikkature */ 137a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 138a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 139a45c6cb8SMadhusudhan Chikkature 140a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 141a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 142a45c6cb8SMadhusudhan Chikkature 1439782aff8SPer Forlin struct omap_hsmmc_next { 1449782aff8SPer Forlin unsigned int dma_len; 1459782aff8SPer Forlin s32 cookie; 1469782aff8SPer Forlin }; 1479782aff8SPer Forlin 14870a3341aSDenis Karpov struct omap_hsmmc_host { 149a45c6cb8SMadhusudhan Chikkature struct device *dev; 150a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 151a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 152a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 153a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 154a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 155a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 156db0fefc5SAdrian Hunter /* 157db0fefc5SAdrian Hunter * vcc == configured supply 158db0fefc5SAdrian Hunter * vcc_aux == optional 159db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 160db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 161db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 162db0fefc5SAdrian Hunter */ 163db0fefc5SAdrian Hunter struct regulator *vcc; 164db0fefc5SAdrian Hunter struct regulator *vcc_aux; 165a45c6cb8SMadhusudhan Chikkature struct work_struct mmc_carddetect_work; 166a45c6cb8SMadhusudhan Chikkature void __iomem *base; 167a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1684dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 169a45c6cb8SMadhusudhan Chikkature unsigned int id; 170a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1710ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 172a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 173a3621465SAdrian Hunter unsigned char power_mode; 174a45c6cb8SMadhusudhan Chikkature u32 *buffer; 175a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 176a45c6cb8SMadhusudhan Chikkature int suspended; 177a45c6cb8SMadhusudhan Chikkature int irq; 178a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 179f3e2f1ddSGrazvydas Ignotas int dma_line_tx, dma_line_rx; 180a45c6cb8SMadhusudhan Chikkature int slot_id; 1812bec0893SAdrian Hunter int got_dbclk; 1824a694dc9SAdrian Hunter int response_busy; 18311dd62a7SDenis Karpov int context_loss; 184dd498effSDenis Karpov int dpm_state; 185623821f7SAdrian Hunter int vdd; 186b62f6228SAdrian Hunter int protect_card; 187b62f6228SAdrian Hunter int reqs_blocked; 188db0fefc5SAdrian Hunter int use_reg; 189b417577dSAdrian Hunter int req_in_progress; 1909782aff8SPer Forlin struct omap_hsmmc_next next_data; 19111dd62a7SDenis Karpov 192a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 193a45c6cb8SMadhusudhan Chikkature }; 194a45c6cb8SMadhusudhan Chikkature 195db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 196db0fefc5SAdrian Hunter { 197db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 198db0fefc5SAdrian Hunter 199db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 200db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 201db0fefc5SAdrian Hunter } 202db0fefc5SAdrian Hunter 203db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 204db0fefc5SAdrian Hunter { 205db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 206db0fefc5SAdrian Hunter 207db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 208db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 209db0fefc5SAdrian Hunter } 210db0fefc5SAdrian Hunter 211db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 212db0fefc5SAdrian Hunter { 213db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 214db0fefc5SAdrian Hunter 215db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 216db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 217db0fefc5SAdrian Hunter } 218db0fefc5SAdrian Hunter 219db0fefc5SAdrian Hunter #ifdef CONFIG_PM 220db0fefc5SAdrian Hunter 221db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 222db0fefc5SAdrian Hunter { 223db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 224db0fefc5SAdrian Hunter 225db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 226db0fefc5SAdrian Hunter return 0; 227db0fefc5SAdrian Hunter } 228db0fefc5SAdrian Hunter 229db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 230db0fefc5SAdrian Hunter { 231db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 232db0fefc5SAdrian Hunter 233db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 234db0fefc5SAdrian Hunter return 0; 235db0fefc5SAdrian Hunter } 236db0fefc5SAdrian Hunter 237db0fefc5SAdrian Hunter #else 238db0fefc5SAdrian Hunter 239db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 240db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 241db0fefc5SAdrian Hunter 242db0fefc5SAdrian Hunter #endif 243db0fefc5SAdrian Hunter 244b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 245b702b106SAdrian Hunter 246db0fefc5SAdrian Hunter static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 247db0fefc5SAdrian Hunter int vdd) 248db0fefc5SAdrian Hunter { 249db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 250db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 251db0fefc5SAdrian Hunter int ret; 252db0fefc5SAdrian Hunter 253db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 254db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 255db0fefc5SAdrian Hunter 256db0fefc5SAdrian Hunter if (power_on) 25799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 258db0fefc5SAdrian Hunter else 25999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 260db0fefc5SAdrian Hunter 261db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 262db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 263db0fefc5SAdrian Hunter 264db0fefc5SAdrian Hunter return ret; 265db0fefc5SAdrian Hunter } 266db0fefc5SAdrian Hunter 2677715db5aSKishore Kadiyala static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, 268db0fefc5SAdrian Hunter int vdd) 269db0fefc5SAdrian Hunter { 270db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 271db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 272db0fefc5SAdrian Hunter int ret = 0; 273db0fefc5SAdrian Hunter 274db0fefc5SAdrian Hunter /* 275db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 276db0fefc5SAdrian Hunter * voltage always-on regulator. 277db0fefc5SAdrian Hunter */ 278db0fefc5SAdrian Hunter if (!host->vcc) 279db0fefc5SAdrian Hunter return 0; 280db0fefc5SAdrian Hunter 281db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 282db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 283db0fefc5SAdrian Hunter 284db0fefc5SAdrian Hunter /* 285db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 286db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 287db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 288db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 289db0fefc5SAdrian Hunter * 290db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 291db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 292db0fefc5SAdrian Hunter * 293db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 294db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 295db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 296db0fefc5SAdrian Hunter */ 297db0fefc5SAdrian Hunter if (power_on) { 29899fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 299db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 300db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 301db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 302db0fefc5SAdrian Hunter if (ret < 0) 30399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30499fc5131SLinus Walleij host->vcc, 0); 305db0fefc5SAdrian Hunter } 306db0fefc5SAdrian Hunter } else { 30799fc5131SLinus Walleij /* Shut down the rail */ 3086da20c89SAdrian Hunter if (host->vcc_aux) 309db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 31099fc5131SLinus Walleij if (!ret) { 31199fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31299fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31399fc5131SLinus Walleij host->vcc, 0); 31499fc5131SLinus Walleij } 315db0fefc5SAdrian Hunter } 316db0fefc5SAdrian Hunter 317db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 318db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 319db0fefc5SAdrian Hunter 320db0fefc5SAdrian Hunter return ret; 321db0fefc5SAdrian Hunter } 322db0fefc5SAdrian Hunter 3237715db5aSKishore Kadiyala static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, 3247715db5aSKishore Kadiyala int vdd) 3257715db5aSKishore Kadiyala { 3267715db5aSKishore Kadiyala return 0; 3277715db5aSKishore Kadiyala } 3287715db5aSKishore Kadiyala 329db0fefc5SAdrian Hunter static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 330db0fefc5SAdrian Hunter int vdd, int cardsleep) 331db0fefc5SAdrian Hunter { 332db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 333db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 334db0fefc5SAdrian Hunter int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 335db0fefc5SAdrian Hunter 336db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc, mode); 337db0fefc5SAdrian Hunter } 338db0fefc5SAdrian Hunter 3397715db5aSKishore Kadiyala static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, 340db0fefc5SAdrian Hunter int vdd, int cardsleep) 341db0fefc5SAdrian Hunter { 342db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 343db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 344db0fefc5SAdrian Hunter int err, mode; 345db0fefc5SAdrian Hunter 346db0fefc5SAdrian Hunter /* 347db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 348db0fefc5SAdrian Hunter * voltage always-on regulator. 349db0fefc5SAdrian Hunter */ 350db0fefc5SAdrian Hunter if (!host->vcc) 351db0fefc5SAdrian Hunter return 0; 352db0fefc5SAdrian Hunter 353db0fefc5SAdrian Hunter mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 354db0fefc5SAdrian Hunter 355db0fefc5SAdrian Hunter if (!host->vcc_aux) 356db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc, mode); 357db0fefc5SAdrian Hunter 358db0fefc5SAdrian Hunter if (cardsleep) { 359db0fefc5SAdrian Hunter /* VCC can be turned off if card is asleep */ 360db0fefc5SAdrian Hunter if (sleep) 36199fc5131SLinus Walleij err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 362db0fefc5SAdrian Hunter else 36399fc5131SLinus Walleij err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 364db0fefc5SAdrian Hunter } else 365db0fefc5SAdrian Hunter err = regulator_set_mode(host->vcc, mode); 366db0fefc5SAdrian Hunter if (err) 367db0fefc5SAdrian Hunter return err; 368e0eb2424SAdrian Hunter 369e0eb2424SAdrian Hunter if (!mmc_slot(host).vcc_aux_disable_is_sleep) 370db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc_aux, mode); 371e0eb2424SAdrian Hunter 372e0eb2424SAdrian Hunter if (sleep) 373e0eb2424SAdrian Hunter return regulator_disable(host->vcc_aux); 374e0eb2424SAdrian Hunter else 375e0eb2424SAdrian Hunter return regulator_enable(host->vcc_aux); 376db0fefc5SAdrian Hunter } 377db0fefc5SAdrian Hunter 3787715db5aSKishore Kadiyala static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, 3797715db5aSKishore Kadiyala int vdd, int cardsleep) 3807715db5aSKishore Kadiyala { 3817715db5aSKishore Kadiyala return 0; 3827715db5aSKishore Kadiyala } 3837715db5aSKishore Kadiyala 384db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 385db0fefc5SAdrian Hunter { 386db0fefc5SAdrian Hunter struct regulator *reg; 387db0fefc5SAdrian Hunter int ret = 0; 38864be9782Skishore kadiyala int ocr_value = 0; 389db0fefc5SAdrian Hunter 390db0fefc5SAdrian Hunter switch (host->id) { 391db0fefc5SAdrian Hunter case OMAP_MMC1_DEVID: 392db0fefc5SAdrian Hunter /* On-chip level shifting via PBIAS0/PBIAS1 */ 393db0fefc5SAdrian Hunter mmc_slot(host).set_power = omap_hsmmc_1_set_power; 394db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 395db0fefc5SAdrian Hunter break; 396db0fefc5SAdrian Hunter case OMAP_MMC2_DEVID: 397db0fefc5SAdrian Hunter case OMAP_MMC3_DEVID: 3987715db5aSKishore Kadiyala case OMAP_MMC5_DEVID: 399db0fefc5SAdrian Hunter /* Off-chip level shifting, or none */ 4007715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_235_set_power; 4017715db5aSKishore Kadiyala mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; 402db0fefc5SAdrian Hunter break; 4037715db5aSKishore Kadiyala case OMAP_MMC4_DEVID: 4047715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_4_set_power; 4057715db5aSKishore Kadiyala mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; 406db0fefc5SAdrian Hunter default: 407db0fefc5SAdrian Hunter pr_err("MMC%d configuration not supported!\n", host->id); 408db0fefc5SAdrian Hunter return -EINVAL; 409db0fefc5SAdrian Hunter } 410db0fefc5SAdrian Hunter 411db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 412db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 413db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 414db0fefc5SAdrian Hunter /* 415db0fefc5SAdrian Hunter * HACK: until fixed.c regulator is usable, 416db0fefc5SAdrian Hunter * we don't require a main regulator 417db0fefc5SAdrian Hunter * for MMC2 or MMC3 418db0fefc5SAdrian Hunter */ 419db0fefc5SAdrian Hunter if (host->id == OMAP_MMC1_DEVID) { 420db0fefc5SAdrian Hunter ret = PTR_ERR(reg); 421db0fefc5SAdrian Hunter goto err; 422db0fefc5SAdrian Hunter } 423db0fefc5SAdrian Hunter } else { 424db0fefc5SAdrian Hunter host->vcc = reg; 42564be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 42664be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 42764be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 42864be9782Skishore kadiyala } else { 42964be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 43064be9782Skishore kadiyala pr_err("MMC%d ocrmask %x is not supported\n", 43164be9782Skishore kadiyala host->id, mmc_slot(host).ocr_mask); 43264be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 43364be9782Skishore kadiyala return -EINVAL; 43464be9782Skishore kadiyala } 43564be9782Skishore kadiyala } 436db0fefc5SAdrian Hunter 437db0fefc5SAdrian Hunter /* Allow an aux regulator */ 438db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 439db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 440db0fefc5SAdrian Hunter 441b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 442b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 443b1c1df7aSBalaji T K return 0; 444db0fefc5SAdrian Hunter /* 445db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 446db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 447db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 448db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 449db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 450db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 451db0fefc5SAdrian Hunter */ 452e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 453e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 454e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 455e840ce13SAdrian Hunter 456e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 457e840ce13SAdrian Hunter 1, vdd); 458e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 459e840ce13SAdrian Hunter 0, 0); 460db0fefc5SAdrian Hunter } 461db0fefc5SAdrian Hunter } 462db0fefc5SAdrian Hunter 463db0fefc5SAdrian Hunter return 0; 464db0fefc5SAdrian Hunter 465db0fefc5SAdrian Hunter err: 466db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 467db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = NULL; 468db0fefc5SAdrian Hunter return ret; 469db0fefc5SAdrian Hunter } 470db0fefc5SAdrian Hunter 471db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 472db0fefc5SAdrian Hunter { 473db0fefc5SAdrian Hunter regulator_put(host->vcc); 474db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 475db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 476db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = NULL; 477db0fefc5SAdrian Hunter } 478db0fefc5SAdrian Hunter 479b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 480b702b106SAdrian Hunter { 481b702b106SAdrian Hunter return 1; 482b702b106SAdrian Hunter } 483b702b106SAdrian Hunter 484b702b106SAdrian Hunter #else 485b702b106SAdrian Hunter 486b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 487b702b106SAdrian Hunter { 488b702b106SAdrian Hunter return -EINVAL; 489b702b106SAdrian Hunter } 490b702b106SAdrian Hunter 491b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 492b702b106SAdrian Hunter { 493b702b106SAdrian Hunter } 494b702b106SAdrian Hunter 495b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 496b702b106SAdrian Hunter { 497b702b106SAdrian Hunter return 0; 498b702b106SAdrian Hunter } 499b702b106SAdrian Hunter 500b702b106SAdrian Hunter #endif 501b702b106SAdrian Hunter 502b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 503b702b106SAdrian Hunter { 504b702b106SAdrian Hunter int ret; 505b702b106SAdrian Hunter 506b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 507b702b106SAdrian Hunter if (pdata->slots[0].cover) 508b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 509b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 510b702b106SAdrian Hunter else 511b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 512b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 513b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 514b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 515b702b106SAdrian Hunter if (ret) 516b702b106SAdrian Hunter return ret; 517b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 518b702b106SAdrian Hunter if (ret) 519b702b106SAdrian Hunter goto err_free_sp; 520b702b106SAdrian Hunter } else 521b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 522b702b106SAdrian Hunter 523b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 524b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 525b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 526b702b106SAdrian Hunter if (ret) 527b702b106SAdrian Hunter goto err_free_cd; 528b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 529b702b106SAdrian Hunter if (ret) 530b702b106SAdrian Hunter goto err_free_wp; 531b702b106SAdrian Hunter } else 532b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 533b702b106SAdrian Hunter 534b702b106SAdrian Hunter return 0; 535b702b106SAdrian Hunter 536b702b106SAdrian Hunter err_free_wp: 537b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 538b702b106SAdrian Hunter err_free_cd: 539b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 540b702b106SAdrian Hunter err_free_sp: 541b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 542b702b106SAdrian Hunter return ret; 543b702b106SAdrian Hunter } 544b702b106SAdrian Hunter 545b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 546b702b106SAdrian Hunter { 547b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 548b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 549b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 550b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 551b702b106SAdrian Hunter } 552b702b106SAdrian Hunter 553a45c6cb8SMadhusudhan Chikkature /* 554e0c7f99bSAndy Shevchenko * Start clock to the card 555e0c7f99bSAndy Shevchenko */ 556e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 557e0c7f99bSAndy Shevchenko { 558e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 559e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 560e0c7f99bSAndy Shevchenko } 561e0c7f99bSAndy Shevchenko 562e0c7f99bSAndy Shevchenko /* 563a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 564a45c6cb8SMadhusudhan Chikkature */ 56570a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 566a45c6cb8SMadhusudhan Chikkature { 567a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 568a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 569a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 570a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 571a45c6cb8SMadhusudhan Chikkature } 572a45c6cb8SMadhusudhan Chikkature 57393caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 57493caf8e6SAdrian Hunter struct mmc_command *cmd) 575b417577dSAdrian Hunter { 576b417577dSAdrian Hunter unsigned int irq_mask; 577b417577dSAdrian Hunter 578b417577dSAdrian Hunter if (host->use_dma) 579b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 580b417577dSAdrian Hunter else 581b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 582b417577dSAdrian Hunter 58393caf8e6SAdrian Hunter /* Disable timeout for erases */ 58493caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 58593caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 58693caf8e6SAdrian Hunter 587b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 588b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 589b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 590b417577dSAdrian Hunter } 591b417577dSAdrian Hunter 592b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 593b417577dSAdrian Hunter { 594b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 595b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 596b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 597b417577dSAdrian Hunter } 598b417577dSAdrian Hunter 599ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 600d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 601ac330f44SAndy Shevchenko { 602ac330f44SAndy Shevchenko u16 dsor = 0; 603ac330f44SAndy Shevchenko 604ac330f44SAndy Shevchenko if (ios->clock) { 605d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 606ac330f44SAndy Shevchenko if (dsor > 250) 607ac330f44SAndy Shevchenko dsor = 250; 608ac330f44SAndy Shevchenko } 609ac330f44SAndy Shevchenko 610ac330f44SAndy Shevchenko return dsor; 611ac330f44SAndy Shevchenko } 612ac330f44SAndy Shevchenko 6135934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6145934df2fSAndy Shevchenko { 6155934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6165934df2fSAndy Shevchenko unsigned long regval; 6175934df2fSAndy Shevchenko unsigned long timeout; 6185934df2fSAndy Shevchenko 6195934df2fSAndy Shevchenko dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6205934df2fSAndy Shevchenko 6215934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6225934df2fSAndy Shevchenko 6235934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6245934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 625d83b6e03SBalaji TK regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); 6265934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6275934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6285934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6295934df2fSAndy Shevchenko 6305934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6315934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6325934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6335934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6345934df2fSAndy Shevchenko cpu_relax(); 6355934df2fSAndy Shevchenko 6365934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6375934df2fSAndy Shevchenko } 6385934df2fSAndy Shevchenko 6393796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6403796fb8aSAndy Shevchenko { 6413796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6423796fb8aSAndy Shevchenko u32 con; 6433796fb8aSAndy Shevchenko 6443796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6453796fb8aSAndy Shevchenko switch (ios->bus_width) { 6463796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6473796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6483796fb8aSAndy Shevchenko break; 6493796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6503796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6513796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6523796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6533796fb8aSAndy Shevchenko break; 6543796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6553796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6563796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6573796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6583796fb8aSAndy Shevchenko break; 6593796fb8aSAndy Shevchenko } 6603796fb8aSAndy Shevchenko } 6613796fb8aSAndy Shevchenko 6623796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6633796fb8aSAndy Shevchenko { 6643796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6653796fb8aSAndy Shevchenko u32 con; 6663796fb8aSAndy Shevchenko 6673796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6683796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6693796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6703796fb8aSAndy Shevchenko else 6713796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6723796fb8aSAndy Shevchenko } 6733796fb8aSAndy Shevchenko 67411dd62a7SDenis Karpov #ifdef CONFIG_PM 67511dd62a7SDenis Karpov 67611dd62a7SDenis Karpov /* 67711dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 67811dd62a7SDenis Karpov * power state change. 67911dd62a7SDenis Karpov */ 68070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 68111dd62a7SDenis Karpov { 68211dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 68311dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 68411dd62a7SDenis Karpov int context_loss = 0; 6853796fb8aSAndy Shevchenko u32 hctl, capa; 68611dd62a7SDenis Karpov unsigned long timeout; 68711dd62a7SDenis Karpov 68811dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 68911dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 69011dd62a7SDenis Karpov if (context_loss < 0) 69111dd62a7SDenis Karpov return 1; 69211dd62a7SDenis Karpov } 69311dd62a7SDenis Karpov 69411dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 69511dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 69611dd62a7SDenis Karpov if (host->context_loss == context_loss) 69711dd62a7SDenis Karpov return 1; 69811dd62a7SDenis Karpov 69911dd62a7SDenis Karpov /* Wait for hardware reset */ 70011dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 70111dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 70211dd62a7SDenis Karpov && time_before(jiffies, timeout)) 70311dd62a7SDenis Karpov ; 70411dd62a7SDenis Karpov 70511dd62a7SDenis Karpov /* Do software reset */ 70611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 70711dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 70811dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 70911dd62a7SDenis Karpov && time_before(jiffies, timeout)) 71011dd62a7SDenis Karpov ; 71111dd62a7SDenis Karpov 71211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 71311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 71411dd62a7SDenis Karpov 71511dd62a7SDenis Karpov if (host->id == OMAP_MMC1_DEVID) { 71611dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 71711dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 71811dd62a7SDenis Karpov hctl = SDVS18; 71911dd62a7SDenis Karpov else 72011dd62a7SDenis Karpov hctl = SDVS30; 72111dd62a7SDenis Karpov capa = VS30 | VS18; 72211dd62a7SDenis Karpov } else { 72311dd62a7SDenis Karpov hctl = SDVS18; 72411dd62a7SDenis Karpov capa = VS18; 72511dd62a7SDenis Karpov } 72611dd62a7SDenis Karpov 72711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 72811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 72911dd62a7SDenis Karpov 73011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 73111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 73211dd62a7SDenis Karpov 73311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 73411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 73511dd62a7SDenis Karpov 73611dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 73711dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 73811dd62a7SDenis Karpov && time_before(jiffies, timeout)) 73911dd62a7SDenis Karpov ; 74011dd62a7SDenis Karpov 741b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 74211dd62a7SDenis Karpov 74311dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 74411dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 74511dd62a7SDenis Karpov goto out; 74611dd62a7SDenis Karpov 7473796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 74811dd62a7SDenis Karpov 7495934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 75011dd62a7SDenis Karpov 7513796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7523796fb8aSAndy Shevchenko 75311dd62a7SDenis Karpov out: 75411dd62a7SDenis Karpov host->context_loss = context_loss; 75511dd62a7SDenis Karpov 75611dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 75711dd62a7SDenis Karpov return 0; 75811dd62a7SDenis Karpov } 75911dd62a7SDenis Karpov 76011dd62a7SDenis Karpov /* 76111dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 76211dd62a7SDenis Karpov */ 76370a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 76411dd62a7SDenis Karpov { 76511dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 76611dd62a7SDenis Karpov int context_loss; 76711dd62a7SDenis Karpov 76811dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 76911dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 77011dd62a7SDenis Karpov if (context_loss < 0) 77111dd62a7SDenis Karpov return; 77211dd62a7SDenis Karpov host->context_loss = context_loss; 77311dd62a7SDenis Karpov } 77411dd62a7SDenis Karpov } 77511dd62a7SDenis Karpov 77611dd62a7SDenis Karpov #else 77711dd62a7SDenis Karpov 77870a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 77911dd62a7SDenis Karpov { 78011dd62a7SDenis Karpov return 0; 78111dd62a7SDenis Karpov } 78211dd62a7SDenis Karpov 78370a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 78411dd62a7SDenis Karpov { 78511dd62a7SDenis Karpov } 78611dd62a7SDenis Karpov 78711dd62a7SDenis Karpov #endif 78811dd62a7SDenis Karpov 789a45c6cb8SMadhusudhan Chikkature /* 790a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 791a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 792a45c6cb8SMadhusudhan Chikkature */ 79370a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 794a45c6cb8SMadhusudhan Chikkature { 795a45c6cb8SMadhusudhan Chikkature int reg = 0; 796a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 797a45c6cb8SMadhusudhan Chikkature 798b62f6228SAdrian Hunter if (host->protect_card) 799b62f6228SAdrian Hunter return; 800b62f6228SAdrian Hunter 801a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 802b417577dSAdrian Hunter 803b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 804a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 805a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 806a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 807a45c6cb8SMadhusudhan Chikkature 808a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 809a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 810a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 811a45c6cb8SMadhusudhan Chikkature 812a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 813a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 814c653a6d4SAdrian Hunter 815c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 816c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 817c653a6d4SAdrian Hunter 818a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 819a45c6cb8SMadhusudhan Chikkature } 820a45c6cb8SMadhusudhan Chikkature 821a45c6cb8SMadhusudhan Chikkature static inline 82270a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 823a45c6cb8SMadhusudhan Chikkature { 824a45c6cb8SMadhusudhan Chikkature int r = 1; 825a45c6cb8SMadhusudhan Chikkature 826191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 827191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 828a45c6cb8SMadhusudhan Chikkature return r; 829a45c6cb8SMadhusudhan Chikkature } 830a45c6cb8SMadhusudhan Chikkature 831a45c6cb8SMadhusudhan Chikkature static ssize_t 83270a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 833a45c6cb8SMadhusudhan Chikkature char *buf) 834a45c6cb8SMadhusudhan Chikkature { 835a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 83670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 837a45c6cb8SMadhusudhan Chikkature 83870a3341aSDenis Karpov return sprintf(buf, "%s\n", 83970a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 840a45c6cb8SMadhusudhan Chikkature } 841a45c6cb8SMadhusudhan Chikkature 84270a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 843a45c6cb8SMadhusudhan Chikkature 844a45c6cb8SMadhusudhan Chikkature static ssize_t 84570a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 846a45c6cb8SMadhusudhan Chikkature char *buf) 847a45c6cb8SMadhusudhan Chikkature { 848a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 84970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 850a45c6cb8SMadhusudhan Chikkature 851191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 852a45c6cb8SMadhusudhan Chikkature } 853a45c6cb8SMadhusudhan Chikkature 85470a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 855a45c6cb8SMadhusudhan Chikkature 856a45c6cb8SMadhusudhan Chikkature /* 857a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 858a45c6cb8SMadhusudhan Chikkature */ 859a45c6cb8SMadhusudhan Chikkature static void 86070a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 861a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 862a45c6cb8SMadhusudhan Chikkature { 863a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 864a45c6cb8SMadhusudhan Chikkature 865a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 866a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 867a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 868a45c6cb8SMadhusudhan Chikkature 86993caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 870a45c6cb8SMadhusudhan Chikkature 8714a694dc9SAdrian Hunter host->response_busy = 0; 872a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 873a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 874a45c6cb8SMadhusudhan Chikkature resptype = 1; 8754a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8764a694dc9SAdrian Hunter resptype = 3; 8774a694dc9SAdrian Hunter host->response_busy = 1; 8784a694dc9SAdrian Hunter } else 879a45c6cb8SMadhusudhan Chikkature resptype = 2; 880a45c6cb8SMadhusudhan Chikkature } 881a45c6cb8SMadhusudhan Chikkature 882a45c6cb8SMadhusudhan Chikkature /* 883a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 884a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 885a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 886a45c6cb8SMadhusudhan Chikkature */ 887a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 888a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 889a45c6cb8SMadhusudhan Chikkature 890a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 891a45c6cb8SMadhusudhan Chikkature 892a45c6cb8SMadhusudhan Chikkature if (data) { 893a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 894a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 895a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 896a45c6cb8SMadhusudhan Chikkature else 897a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 898a45c6cb8SMadhusudhan Chikkature } 899a45c6cb8SMadhusudhan Chikkature 900a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 901a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 902a45c6cb8SMadhusudhan Chikkature 903b417577dSAdrian Hunter host->req_in_progress = 1; 9044dffd7a2SAdrian Hunter 905a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 906a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 907a45c6cb8SMadhusudhan Chikkature } 908a45c6cb8SMadhusudhan Chikkature 9090ccd76d4SJuha Yrjola static int 91070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9110ccd76d4SJuha Yrjola { 9120ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9130ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9140ccd76d4SJuha Yrjola else 9150ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9160ccd76d4SJuha Yrjola } 9170ccd76d4SJuha Yrjola 918b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 919b417577dSAdrian Hunter { 920b417577dSAdrian Hunter int dma_ch; 921b417577dSAdrian Hunter 922b417577dSAdrian Hunter spin_lock(&host->irq_lock); 923b417577dSAdrian Hunter host->req_in_progress = 0; 924b417577dSAdrian Hunter dma_ch = host->dma_ch; 925b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 926b417577dSAdrian Hunter 927b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 928b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 929b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 930b417577dSAdrian Hunter return; 931b417577dSAdrian Hunter host->mrq = NULL; 932b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 933b417577dSAdrian Hunter } 934b417577dSAdrian Hunter 935a45c6cb8SMadhusudhan Chikkature /* 936a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 937a45c6cb8SMadhusudhan Chikkature */ 938a45c6cb8SMadhusudhan Chikkature static void 93970a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 940a45c6cb8SMadhusudhan Chikkature { 9414a694dc9SAdrian Hunter if (!data) { 9424a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9434a694dc9SAdrian Hunter 94423050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 94523050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 94623050103SAdrian Hunter host->response_busy) { 94723050103SAdrian Hunter host->response_busy = 0; 94823050103SAdrian Hunter return; 94923050103SAdrian Hunter } 95023050103SAdrian Hunter 951b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9524a694dc9SAdrian Hunter return; 9534a694dc9SAdrian Hunter } 9544a694dc9SAdrian Hunter 955a45c6cb8SMadhusudhan Chikkature host->data = NULL; 956a45c6cb8SMadhusudhan Chikkature 957a45c6cb8SMadhusudhan Chikkature if (!data->error) 958a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 959a45c6cb8SMadhusudhan Chikkature else 960a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 961a45c6cb8SMadhusudhan Chikkature 962a45c6cb8SMadhusudhan Chikkature if (!data->stop) { 963b417577dSAdrian Hunter omap_hsmmc_request_done(host, data->mrq); 964a45c6cb8SMadhusudhan Chikkature return; 965a45c6cb8SMadhusudhan Chikkature } 96670a3341aSDenis Karpov omap_hsmmc_start_command(host, data->stop, NULL); 967a45c6cb8SMadhusudhan Chikkature } 968a45c6cb8SMadhusudhan Chikkature 969a45c6cb8SMadhusudhan Chikkature /* 970a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 971a45c6cb8SMadhusudhan Chikkature */ 972a45c6cb8SMadhusudhan Chikkature static void 97370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 974a45c6cb8SMadhusudhan Chikkature { 975a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 976a45c6cb8SMadhusudhan Chikkature 977a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 978a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 979a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 980a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 981a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 982a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 983a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 984a45c6cb8SMadhusudhan Chikkature } else { 985a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 986a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 987a45c6cb8SMadhusudhan Chikkature } 988a45c6cb8SMadhusudhan Chikkature } 989b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 990b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 991a45c6cb8SMadhusudhan Chikkature } 992a45c6cb8SMadhusudhan Chikkature 993a45c6cb8SMadhusudhan Chikkature /* 994a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 995a45c6cb8SMadhusudhan Chikkature */ 99670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 997a45c6cb8SMadhusudhan Chikkature { 998b417577dSAdrian Hunter int dma_ch; 999b417577dSAdrian Hunter 100082788ff5SJarkko Lavinen host->data->error = errno; 1001a45c6cb8SMadhusudhan Chikkature 1002b417577dSAdrian Hunter spin_lock(&host->irq_lock); 1003b417577dSAdrian Hunter dma_ch = host->dma_ch; 1004b417577dSAdrian Hunter host->dma_ch = -1; 1005b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1006b417577dSAdrian Hunter 1007b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1008a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, 1009a9120c33SPer Forlin host->data->sg_len, 101070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1011b417577dSAdrian Hunter omap_free_dma(dma_ch); 1012053bf34fSPer Forlin host->data->host_cookie = 0; 1013a45c6cb8SMadhusudhan Chikkature } 1014a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1015a45c6cb8SMadhusudhan Chikkature } 1016a45c6cb8SMadhusudhan Chikkature 1017a45c6cb8SMadhusudhan Chikkature /* 1018a45c6cb8SMadhusudhan Chikkature * Readable error output 1019a45c6cb8SMadhusudhan Chikkature */ 1020a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1021699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1022a45c6cb8SMadhusudhan Chikkature { 1023a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 102470a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1025699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1026699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1027699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1028699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1029a45c6cb8SMadhusudhan Chikkature }; 1030a45c6cb8SMadhusudhan Chikkature char res[256]; 1031a45c6cb8SMadhusudhan Chikkature char *buf = res; 1032a45c6cb8SMadhusudhan Chikkature int len, i; 1033a45c6cb8SMadhusudhan Chikkature 1034a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1035a45c6cb8SMadhusudhan Chikkature buf += len; 1036a45c6cb8SMadhusudhan Chikkature 103770a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1038a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 103970a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1040a45c6cb8SMadhusudhan Chikkature buf += len; 1041a45c6cb8SMadhusudhan Chikkature } 1042a45c6cb8SMadhusudhan Chikkature 1043a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 1044a45c6cb8SMadhusudhan Chikkature } 1045699b958bSAdrian Hunter #else 1046699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1047699b958bSAdrian Hunter u32 status) 1048699b958bSAdrian Hunter { 1049699b958bSAdrian Hunter } 1050a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1051a45c6cb8SMadhusudhan Chikkature 10523ebf74b1SJean Pihet /* 10533ebf74b1SJean Pihet * MMC controller internal state machines reset 10543ebf74b1SJean Pihet * 10553ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10563ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10573ebf74b1SJean Pihet * Can be called from interrupt context 10583ebf74b1SJean Pihet */ 105970a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10603ebf74b1SJean Pihet unsigned long bit) 10613ebf74b1SJean Pihet { 10623ebf74b1SJean Pihet unsigned long i = 0; 10633ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 10643ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 10653ebf74b1SJean Pihet 10663ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10673ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10683ebf74b1SJean Pihet 106907ad64b6SMadhusudhan Chikkature /* 107007ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 107107ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 107207ad64b6SMadhusudhan Chikkature */ 107307ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1074b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 107507ad64b6SMadhusudhan Chikkature && (i++ < limit)) 107607ad64b6SMadhusudhan Chikkature cpu_relax(); 107707ad64b6SMadhusudhan Chikkature } 107807ad64b6SMadhusudhan Chikkature i = 0; 107907ad64b6SMadhusudhan Chikkature 10803ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10813ebf74b1SJean Pihet (i++ < limit)) 10823ebf74b1SJean Pihet cpu_relax(); 10833ebf74b1SJean Pihet 10843ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10853ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10863ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10873ebf74b1SJean Pihet __func__); 10883ebf74b1SJean Pihet } 1089a45c6cb8SMadhusudhan Chikkature 1090b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1091a45c6cb8SMadhusudhan Chikkature { 1092a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1093b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1094a45c6cb8SMadhusudhan Chikkature 1095b417577dSAdrian Hunter if (!host->req_in_progress) { 1096b417577dSAdrian Hunter do { 1097b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, status); 109800adadc1SKevin Hilman /* Flush posted write */ 1099b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1100b417577dSAdrian Hunter } while (status & INT_EN_MASK); 1101b417577dSAdrian Hunter return; 1102a45c6cb8SMadhusudhan Chikkature } 1103a45c6cb8SMadhusudhan Chikkature 1104a45c6cb8SMadhusudhan Chikkature data = host->data; 1105a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1106a45c6cb8SMadhusudhan Chikkature 1107a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 1108699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 1109a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 1110a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 1111a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 1112a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 111370a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 1114191d1f1dSDenis Karpov SRC); 1115a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 1116a45c6cb8SMadhusudhan Chikkature } else { 1117a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 1118a45c6cb8SMadhusudhan Chikkature } 1119a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1120a45c6cb8SMadhusudhan Chikkature } 11214a694dc9SAdrian Hunter if (host->data || host->response_busy) { 11224a694dc9SAdrian Hunter if (host->data) 112370a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 112470a3341aSDenis Karpov -ETIMEDOUT); 11254a694dc9SAdrian Hunter host->response_busy = 0; 112670a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1127c232f457SJean Pihet } 1128a45c6cb8SMadhusudhan Chikkature } 1129a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 1130a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 11314a694dc9SAdrian Hunter if (host->data || host->response_busy) { 11324a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 11334a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 11344a694dc9SAdrian Hunter 11354a694dc9SAdrian Hunter if (host->data) 113670a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 1137a45c6cb8SMadhusudhan Chikkature else 11384a694dc9SAdrian Hunter host->mrq->cmd->error = err; 11394a694dc9SAdrian Hunter host->response_busy = 0; 114070a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1141a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1142a45c6cb8SMadhusudhan Chikkature } 1143a45c6cb8SMadhusudhan Chikkature } 1144a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 1145a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1146a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 1147a45c6cb8SMadhusudhan Chikkature if (host->cmd) 1148a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1149a45c6cb8SMadhusudhan Chikkature if (host->data) 1150a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1151a45c6cb8SMadhusudhan Chikkature } 1152a45c6cb8SMadhusudhan Chikkature } 1153a45c6cb8SMadhusudhan Chikkature 1154a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 1155a45c6cb8SMadhusudhan Chikkature 1156a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 115770a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 11580a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 115970a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1160b417577dSAdrian Hunter } 1161a45c6cb8SMadhusudhan Chikkature 1162b417577dSAdrian Hunter /* 1163b417577dSAdrian Hunter * MMC controller IRQ handler 1164b417577dSAdrian Hunter */ 1165b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1166b417577dSAdrian Hunter { 1167b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1168b417577dSAdrian Hunter int status; 1169b417577dSAdrian Hunter 1170b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1171b417577dSAdrian Hunter do { 1172b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 1173b417577dSAdrian Hunter /* Flush posted write */ 1174b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1175b417577dSAdrian Hunter } while (status & INT_EN_MASK); 11764dffd7a2SAdrian Hunter 1177a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1178a45c6cb8SMadhusudhan Chikkature } 1179a45c6cb8SMadhusudhan Chikkature 118070a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1181e13bb300SAdrian Hunter { 1182e13bb300SAdrian Hunter unsigned long i; 1183e13bb300SAdrian Hunter 1184e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1185e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1186e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1187e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1188e13bb300SAdrian Hunter break; 1189e13bb300SAdrian Hunter cpu_relax(); 1190e13bb300SAdrian Hunter } 1191e13bb300SAdrian Hunter } 1192e13bb300SAdrian Hunter 1193a45c6cb8SMadhusudhan Chikkature /* 1194eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1195eb250826SDavid Brownell * 1196eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1197eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1198eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1199a45c6cb8SMadhusudhan Chikkature */ 120070a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1201a45c6cb8SMadhusudhan Chikkature { 1202a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1203a45c6cb8SMadhusudhan Chikkature int ret; 1204a45c6cb8SMadhusudhan Chikkature 1205a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1206fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 12072bec0893SAdrian Hunter if (host->got_dbclk) 1208a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1209a45c6cb8SMadhusudhan Chikkature 1210a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1211a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1212a45c6cb8SMadhusudhan Chikkature 1213a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12142bec0893SAdrian Hunter if (!ret) 12152bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 12162bec0893SAdrian Hunter vdd); 1217fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 12182bec0893SAdrian Hunter if (host->got_dbclk) 12192bec0893SAdrian Hunter clk_enable(host->dbclk); 12202bec0893SAdrian Hunter 1221a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1222a45c6cb8SMadhusudhan Chikkature goto err; 1223a45c6cb8SMadhusudhan Chikkature 1224a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1225a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1226a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1227eb250826SDavid Brownell 1228a45c6cb8SMadhusudhan Chikkature /* 1229a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1230a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 123170a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1232a45c6cb8SMadhusudhan Chikkature * 1233eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1234eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1235eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1236eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1237eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1238eb250826SDavid Brownell * 1239eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1240eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1241eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1242a45c6cb8SMadhusudhan Chikkature */ 1243eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1244a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1245eb250826SDavid Brownell else 1246eb250826SDavid Brownell reg_val |= SDVS30; 1247a45c6cb8SMadhusudhan Chikkature 1248a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1249e13bb300SAdrian Hunter set_sd_bus_power(host); 1250a45c6cb8SMadhusudhan Chikkature 1251a45c6cb8SMadhusudhan Chikkature return 0; 1252a45c6cb8SMadhusudhan Chikkature err: 1253a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1254a45c6cb8SMadhusudhan Chikkature return ret; 1255a45c6cb8SMadhusudhan Chikkature } 1256a45c6cb8SMadhusudhan Chikkature 1257b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1258b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1259b62f6228SAdrian Hunter { 1260b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1261b62f6228SAdrian Hunter return; 1262b62f6228SAdrian Hunter 1263b62f6228SAdrian Hunter host->reqs_blocked = 0; 1264b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1265b62f6228SAdrian Hunter if (host->protect_card) { 1266a3c76eb9SGirish K S pr_info("%s: cover is closed, " 1267b62f6228SAdrian Hunter "card is now accessible\n", 1268b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1269b62f6228SAdrian Hunter host->protect_card = 0; 1270b62f6228SAdrian Hunter } 1271b62f6228SAdrian Hunter } else { 1272b62f6228SAdrian Hunter if (!host->protect_card) { 12733f8ddb03SLinus Torvalds pr_info("%s: cover is open, " 1274b62f6228SAdrian Hunter "card is now inaccessible\n", 1275b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1276b62f6228SAdrian Hunter host->protect_card = 1; 1277b62f6228SAdrian Hunter } 1278b62f6228SAdrian Hunter } 1279b62f6228SAdrian Hunter } 1280b62f6228SAdrian Hunter 1281a45c6cb8SMadhusudhan Chikkature /* 1282a45c6cb8SMadhusudhan Chikkature * Work Item to notify the core about card insertion/removal 1283a45c6cb8SMadhusudhan Chikkature */ 128470a3341aSDenis Karpov static void omap_hsmmc_detect(struct work_struct *work) 1285a45c6cb8SMadhusudhan Chikkature { 128670a3341aSDenis Karpov struct omap_hsmmc_host *host = 128770a3341aSDenis Karpov container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1288249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1289a6b2240dSAdrian Hunter int carddetect; 1290249d0fa9SDavid Brownell 1291a6b2240dSAdrian Hunter if (host->suspended) 1292a6b2240dSAdrian Hunter return; 1293a45c6cb8SMadhusudhan Chikkature 1294a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1295a6b2240dSAdrian Hunter 1296191d1f1dSDenis Karpov if (slot->card_detect) 1297db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1298b62f6228SAdrian Hunter else { 1299b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1300a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1301b62f6228SAdrian Hunter } 1302a6b2240dSAdrian Hunter 1303cdeebaddSMadhusudhan Chikkature if (carddetect) 1304a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1305cdeebaddSMadhusudhan Chikkature else 1306a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1307a45c6cb8SMadhusudhan Chikkature } 1308a45c6cb8SMadhusudhan Chikkature 1309a45c6cb8SMadhusudhan Chikkature /* 1310a45c6cb8SMadhusudhan Chikkature * ISR for handling card insertion and removal 1311a45c6cb8SMadhusudhan Chikkature */ 131270a3341aSDenis Karpov static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1313a45c6cb8SMadhusudhan Chikkature { 131470a3341aSDenis Karpov struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1315a45c6cb8SMadhusudhan Chikkature 1316a6b2240dSAdrian Hunter if (host->suspended) 1317a6b2240dSAdrian Hunter return IRQ_HANDLED; 1318a45c6cb8SMadhusudhan Chikkature schedule_work(&host->mmc_carddetect_work); 1319a45c6cb8SMadhusudhan Chikkature 1320a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1321a45c6cb8SMadhusudhan Chikkature } 1322a45c6cb8SMadhusudhan Chikkature 132370a3341aSDenis Karpov static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 13240ccd76d4SJuha Yrjola struct mmc_data *data) 13250ccd76d4SJuha Yrjola { 13260ccd76d4SJuha Yrjola int sync_dev; 13270ccd76d4SJuha Yrjola 1328f3e2f1ddSGrazvydas Ignotas if (data->flags & MMC_DATA_WRITE) 1329f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_tx; 13300ccd76d4SJuha Yrjola else 1331f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_rx; 13320ccd76d4SJuha Yrjola return sync_dev; 13330ccd76d4SJuha Yrjola } 13340ccd76d4SJuha Yrjola 133570a3341aSDenis Karpov static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 13360ccd76d4SJuha Yrjola struct mmc_data *data, 13370ccd76d4SJuha Yrjola struct scatterlist *sgl) 13380ccd76d4SJuha Yrjola { 13390ccd76d4SJuha Yrjola int blksz, nblk, dma_ch; 13400ccd76d4SJuha Yrjola 13410ccd76d4SJuha Yrjola dma_ch = host->dma_ch; 13420ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) { 13430ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 13440ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 13450ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 13460ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 13470ccd76d4SJuha Yrjola } else { 13480ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 13490ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 13500ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 13510ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 13520ccd76d4SJuha Yrjola } 13530ccd76d4SJuha Yrjola 13540ccd76d4SJuha Yrjola blksz = host->data->blksz; 13550ccd76d4SJuha Yrjola nblk = sg_dma_len(sgl) / blksz; 13560ccd76d4SJuha Yrjola 13570ccd76d4SJuha Yrjola omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 13580ccd76d4SJuha Yrjola blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 135970a3341aSDenis Karpov omap_hsmmc_get_dma_sync_dev(host, data), 13600ccd76d4SJuha Yrjola !(data->flags & MMC_DATA_WRITE)); 13610ccd76d4SJuha Yrjola 13620ccd76d4SJuha Yrjola omap_start_dma(dma_ch); 13630ccd76d4SJuha Yrjola } 13640ccd76d4SJuha Yrjola 1365a45c6cb8SMadhusudhan Chikkature /* 1366a45c6cb8SMadhusudhan Chikkature * DMA call back function 1367a45c6cb8SMadhusudhan Chikkature */ 1368b417577dSAdrian Hunter static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1369a45c6cb8SMadhusudhan Chikkature { 1370b417577dSAdrian Hunter struct omap_hsmmc_host *host = cb_data; 1371770d7432SAdrian Hunter struct mmc_data *data; 1372b417577dSAdrian Hunter int dma_ch, req_in_progress; 1373a45c6cb8SMadhusudhan Chikkature 1374f3584e5eSVenkatraman S if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1375f3584e5eSVenkatraman S dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1376f3584e5eSVenkatraman S ch_status); 1377f3584e5eSVenkatraman S return; 1378f3584e5eSVenkatraman S } 1379a45c6cb8SMadhusudhan Chikkature 1380b417577dSAdrian Hunter spin_lock(&host->irq_lock); 1381b417577dSAdrian Hunter if (host->dma_ch < 0) { 1382b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1383a45c6cb8SMadhusudhan Chikkature return; 1384b417577dSAdrian Hunter } 1385a45c6cb8SMadhusudhan Chikkature 1386770d7432SAdrian Hunter data = host->mrq->data; 13870ccd76d4SJuha Yrjola host->dma_sg_idx++; 13880ccd76d4SJuha Yrjola if (host->dma_sg_idx < host->dma_len) { 13890ccd76d4SJuha Yrjola /* Fire up the next transfer. */ 1390b417577dSAdrian Hunter omap_hsmmc_config_dma_params(host, data, 1391b417577dSAdrian Hunter data->sg + host->dma_sg_idx); 1392b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 13930ccd76d4SJuha Yrjola return; 13940ccd76d4SJuha Yrjola } 13950ccd76d4SJuha Yrjola 13969782aff8SPer Forlin if (!data->host_cookie) 1397a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1398b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1399b417577dSAdrian Hunter 1400b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1401b417577dSAdrian Hunter dma_ch = host->dma_ch; 1402a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1403b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1404b417577dSAdrian Hunter 1405b417577dSAdrian Hunter omap_free_dma(dma_ch); 1406b417577dSAdrian Hunter 1407b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1408b417577dSAdrian Hunter if (!req_in_progress) { 1409b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1410b417577dSAdrian Hunter 1411b417577dSAdrian Hunter host->mrq = NULL; 1412b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1413b417577dSAdrian Hunter } 1414a45c6cb8SMadhusudhan Chikkature } 1415a45c6cb8SMadhusudhan Chikkature 14169782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 14179782aff8SPer Forlin struct mmc_data *data, 14189782aff8SPer Forlin struct omap_hsmmc_next *next) 14199782aff8SPer Forlin { 14209782aff8SPer Forlin int dma_len; 14219782aff8SPer Forlin 14229782aff8SPer Forlin if (!next && data->host_cookie && 14239782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 1424a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 14259782aff8SPer Forlin " host->next_data.cookie %d\n", 14269782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 14279782aff8SPer Forlin data->host_cookie = 0; 14289782aff8SPer Forlin } 14299782aff8SPer Forlin 14309782aff8SPer Forlin /* Check if next job is already prepared */ 14319782aff8SPer Forlin if (next || 14329782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 14339782aff8SPer Forlin dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 14349782aff8SPer Forlin data->sg_len, 14359782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14369782aff8SPer Forlin 14379782aff8SPer Forlin } else { 14389782aff8SPer Forlin dma_len = host->next_data.dma_len; 14399782aff8SPer Forlin host->next_data.dma_len = 0; 14409782aff8SPer Forlin } 14419782aff8SPer Forlin 14429782aff8SPer Forlin 14439782aff8SPer Forlin if (dma_len == 0) 14449782aff8SPer Forlin return -EINVAL; 14459782aff8SPer Forlin 14469782aff8SPer Forlin if (next) { 14479782aff8SPer Forlin next->dma_len = dma_len; 14489782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 14499782aff8SPer Forlin } else 14509782aff8SPer Forlin host->dma_len = dma_len; 14519782aff8SPer Forlin 14529782aff8SPer Forlin return 0; 14539782aff8SPer Forlin } 14549782aff8SPer Forlin 1455a45c6cb8SMadhusudhan Chikkature /* 1456a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1457a45c6cb8SMadhusudhan Chikkature */ 145870a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 145970a3341aSDenis Karpov struct mmc_request *req) 1460a45c6cb8SMadhusudhan Chikkature { 1461b417577dSAdrian Hunter int dma_ch = 0, ret = 0, i; 1462a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1463a45c6cb8SMadhusudhan Chikkature 14640ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1465a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14660ccd76d4SJuha Yrjola struct scatterlist *sgl; 14670ccd76d4SJuha Yrjola 14680ccd76d4SJuha Yrjola sgl = data->sg + i; 14690ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14700ccd76d4SJuha Yrjola return -EINVAL; 14710ccd76d4SJuha Yrjola } 14720ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14730ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14740ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14750ccd76d4SJuha Yrjola */ 14760ccd76d4SJuha Yrjola return -EINVAL; 14770ccd76d4SJuha Yrjola 1478b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1479a45c6cb8SMadhusudhan Chikkature 148070a3341aSDenis Karpov ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 148170a3341aSDenis Karpov "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1482a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 14830ccd76d4SJuha Yrjola dev_err(mmc_dev(host->mmc), 1484a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 1485a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 1486a45c6cb8SMadhusudhan Chikkature return ret; 1487a45c6cb8SMadhusudhan Chikkature } 14889782aff8SPer Forlin ret = omap_hsmmc_pre_dma_transfer(host, data, NULL); 14899782aff8SPer Forlin if (ret) 14909782aff8SPer Forlin return ret; 1491a45c6cb8SMadhusudhan Chikkature 1492a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 14930ccd76d4SJuha Yrjola host->dma_sg_idx = 0; 1494a45c6cb8SMadhusudhan Chikkature 149570a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, data, data->sg); 1496a45c6cb8SMadhusudhan Chikkature 1497a45c6cb8SMadhusudhan Chikkature return 0; 1498a45c6cb8SMadhusudhan Chikkature } 1499a45c6cb8SMadhusudhan Chikkature 150070a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1501e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1502e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1503a45c6cb8SMadhusudhan Chikkature { 1504a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1505a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1506a45c6cb8SMadhusudhan Chikkature 1507a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1508a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1509a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1510a45c6cb8SMadhusudhan Chikkature clkd = 1; 1511a45c6cb8SMadhusudhan Chikkature 1512a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1513e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1514e2bf08d6SAdrian Hunter timeout += timeout_clks; 1515a45c6cb8SMadhusudhan Chikkature if (timeout) { 1516a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1517a45c6cb8SMadhusudhan Chikkature dto += 1; 1518a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1519a45c6cb8SMadhusudhan Chikkature } 1520a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1521a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1522a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1523a45c6cb8SMadhusudhan Chikkature dto += 1; 1524a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1525a45c6cb8SMadhusudhan Chikkature dto -= 13; 1526a45c6cb8SMadhusudhan Chikkature else 1527a45c6cb8SMadhusudhan Chikkature dto = 0; 1528a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1529a45c6cb8SMadhusudhan Chikkature dto = 14; 1530a45c6cb8SMadhusudhan Chikkature } 1531a45c6cb8SMadhusudhan Chikkature 1532a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1533a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1534a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1535a45c6cb8SMadhusudhan Chikkature } 1536a45c6cb8SMadhusudhan Chikkature 1537a45c6cb8SMadhusudhan Chikkature /* 1538a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1539a45c6cb8SMadhusudhan Chikkature */ 1540a45c6cb8SMadhusudhan Chikkature static int 154170a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1542a45c6cb8SMadhusudhan Chikkature { 1543a45c6cb8SMadhusudhan Chikkature int ret; 1544a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1545a45c6cb8SMadhusudhan Chikkature 1546a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1547a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1548e2bf08d6SAdrian Hunter /* 1549e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1550e2bf08d6SAdrian Hunter * busy signal. 1551e2bf08d6SAdrian Hunter */ 1552e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1553e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1554a45c6cb8SMadhusudhan Chikkature return 0; 1555a45c6cb8SMadhusudhan Chikkature } 1556a45c6cb8SMadhusudhan Chikkature 1557a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1558a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1559e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1560a45c6cb8SMadhusudhan Chikkature 1561a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 156270a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1563a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1564a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1565a45c6cb8SMadhusudhan Chikkature return ret; 1566a45c6cb8SMadhusudhan Chikkature } 1567a45c6cb8SMadhusudhan Chikkature } 1568a45c6cb8SMadhusudhan Chikkature return 0; 1569a45c6cb8SMadhusudhan Chikkature } 1570a45c6cb8SMadhusudhan Chikkature 15719782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15729782aff8SPer Forlin int err) 15739782aff8SPer Forlin { 15749782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15759782aff8SPer Forlin struct mmc_data *data = mrq->data; 15769782aff8SPer Forlin 15779782aff8SPer Forlin if (host->use_dma) { 1578053bf34fSPer Forlin if (data->host_cookie) 1579053bf34fSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 1580053bf34fSPer Forlin data->sg_len, 15819782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15829782aff8SPer Forlin data->host_cookie = 0; 15839782aff8SPer Forlin } 15849782aff8SPer Forlin } 15859782aff8SPer Forlin 15869782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15879782aff8SPer Forlin bool is_first_req) 15889782aff8SPer Forlin { 15899782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15909782aff8SPer Forlin 15919782aff8SPer Forlin if (mrq->data->host_cookie) { 15929782aff8SPer Forlin mrq->data->host_cookie = 0; 15939782aff8SPer Forlin return ; 15949782aff8SPer Forlin } 15959782aff8SPer Forlin 15969782aff8SPer Forlin if (host->use_dma) 15979782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 15989782aff8SPer Forlin &host->next_data)) 15999782aff8SPer Forlin mrq->data->host_cookie = 0; 16009782aff8SPer Forlin } 16019782aff8SPer Forlin 1602a45c6cb8SMadhusudhan Chikkature /* 1603a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1604a45c6cb8SMadhusudhan Chikkature */ 160570a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1606a45c6cb8SMadhusudhan Chikkature { 160770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1608a3f406f8SJarkko Lavinen int err; 1609a45c6cb8SMadhusudhan Chikkature 1610b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1611b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1612b62f6228SAdrian Hunter if (host->protect_card) { 1613b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1614b62f6228SAdrian Hunter /* 1615b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1616b62f6228SAdrian Hunter * state by resetting the command and data state 1617b62f6228SAdrian Hunter * machines. 1618b62f6228SAdrian Hunter */ 1619b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1620b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1621b62f6228SAdrian Hunter host->reqs_blocked += 1; 1622b62f6228SAdrian Hunter } 1623b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1624b62f6228SAdrian Hunter if (req->data) 1625b62f6228SAdrian Hunter req->data->error = -EBADF; 1626b417577dSAdrian Hunter req->cmd->retries = 0; 1627b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1628b62f6228SAdrian Hunter return; 1629b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1630b62f6228SAdrian Hunter host->reqs_blocked = 0; 1631a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1632a45c6cb8SMadhusudhan Chikkature host->mrq = req; 163370a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1634a3f406f8SJarkko Lavinen if (err) { 1635a3f406f8SJarkko Lavinen req->cmd->error = err; 1636a3f406f8SJarkko Lavinen if (req->data) 1637a3f406f8SJarkko Lavinen req->data->error = err; 1638a3f406f8SJarkko Lavinen host->mrq = NULL; 1639a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1640a3f406f8SJarkko Lavinen return; 1641a3f406f8SJarkko Lavinen } 1642a3f406f8SJarkko Lavinen 164370a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1644a45c6cb8SMadhusudhan Chikkature } 1645a45c6cb8SMadhusudhan Chikkature 1646a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 164770a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1648a45c6cb8SMadhusudhan Chikkature { 164970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1650a3621465SAdrian Hunter int do_send_init_stream = 0; 1651a45c6cb8SMadhusudhan Chikkature 1652fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16535e2ea617SAdrian Hunter 1654a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1655a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1656a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1657a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1658a3621465SAdrian Hunter 0, 0); 1659623821f7SAdrian Hunter host->vdd = 0; 1660a45c6cb8SMadhusudhan Chikkature break; 1661a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1662a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1663a3621465SAdrian Hunter 1, ios->vdd); 1664623821f7SAdrian Hunter host->vdd = ios->vdd; 1665a45c6cb8SMadhusudhan Chikkature break; 1666a3621465SAdrian Hunter case MMC_POWER_ON: 1667a3621465SAdrian Hunter do_send_init_stream = 1; 1668a3621465SAdrian Hunter break; 1669a3621465SAdrian Hunter } 1670a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1671a45c6cb8SMadhusudhan Chikkature } 1672a45c6cb8SMadhusudhan Chikkature 1673dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1674dd498effSDenis Karpov 16753796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1676a45c6cb8SMadhusudhan Chikkature 16774621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1678eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1679eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1680eb250826SDavid Brownell */ 1681a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1682a45c6cb8SMadhusudhan Chikkature (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1683a45c6cb8SMadhusudhan Chikkature /* 1684a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1685a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1686a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1687a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1688a45c6cb8SMadhusudhan Chikkature */ 168970a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1690a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1691a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1692a45c6cb8SMadhusudhan Chikkature } 1693a45c6cb8SMadhusudhan Chikkature } 1694a45c6cb8SMadhusudhan Chikkature 16955934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1696a45c6cb8SMadhusudhan Chikkature 1697a3621465SAdrian Hunter if (do_send_init_stream) 1698a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1699a45c6cb8SMadhusudhan Chikkature 17003796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 17015e2ea617SAdrian Hunter 1702fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1703a45c6cb8SMadhusudhan Chikkature } 1704a45c6cb8SMadhusudhan Chikkature 1705a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1706a45c6cb8SMadhusudhan Chikkature { 170770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1708a45c6cb8SMadhusudhan Chikkature 1709191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1710a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1711db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1712a45c6cb8SMadhusudhan Chikkature } 1713a45c6cb8SMadhusudhan Chikkature 1714a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1715a45c6cb8SMadhusudhan Chikkature { 171670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1717a45c6cb8SMadhusudhan Chikkature 1718191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1719a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1720191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1721a45c6cb8SMadhusudhan Chikkature } 1722a45c6cb8SMadhusudhan Chikkature 17234816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17244816858cSGrazvydas Ignotas { 17254816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17264816858cSGrazvydas Ignotas 17274816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 17284816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 17294816858cSGrazvydas Ignotas } 17304816858cSGrazvydas Ignotas 173170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17321b331e69SKim Kyuwon { 17331b331e69SKim Kyuwon u32 hctl, capa, value; 17341b331e69SKim Kyuwon 17351b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17364621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17371b331e69SKim Kyuwon hctl = SDVS30; 17381b331e69SKim Kyuwon capa = VS30 | VS18; 17391b331e69SKim Kyuwon } else { 17401b331e69SKim Kyuwon hctl = SDVS18; 17411b331e69SKim Kyuwon capa = VS18; 17421b331e69SKim Kyuwon } 17431b331e69SKim Kyuwon 17441b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17451b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17461b331e69SKim Kyuwon 17471b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17481b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17491b331e69SKim Kyuwon 17501b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 17511b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 17521b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 17531b331e69SKim Kyuwon 17541b331e69SKim Kyuwon /* Set SD bus power bit */ 1755e13bb300SAdrian Hunter set_sd_bus_power(host); 17561b331e69SKim Kyuwon } 17571b331e69SKim Kyuwon 175870a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1759dd498effSDenis Karpov { 176070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1761dd498effSDenis Karpov 1762fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1763fa4aa2d4SBalaji T K 1764dd498effSDenis Karpov return 0; 1765dd498effSDenis Karpov } 1766dd498effSDenis Karpov 176770a3341aSDenis Karpov static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1768dd498effSDenis Karpov { 176970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1770dd498effSDenis Karpov 1771fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1772fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1773fa4aa2d4SBalaji T K 1774dd498effSDenis Karpov return 0; 1775dd498effSDenis Karpov } 1776dd498effSDenis Karpov 177770a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 177870a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 177970a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 17809782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17819782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 178270a3341aSDenis Karpov .request = omap_hsmmc_request, 178370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1784dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1785dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 17864816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1787dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1788dd498effSDenis Karpov }; 1789dd498effSDenis Karpov 1790d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1791d900f712SDenis Karpov 179270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1793d900f712SDenis Karpov { 1794d900f712SDenis Karpov struct mmc_host *mmc = s->private; 179570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 179611dd62a7SDenis Karpov int context_loss = 0; 179711dd62a7SDenis Karpov 179870a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 179970a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1800d900f712SDenis Karpov 18015e2ea617SAdrian Hunter seq_printf(s, "mmc%d:\n" 18025e2ea617SAdrian Hunter " enabled:\t%d\n" 1803dd498effSDenis Karpov " dpm_state:\t%d\n" 18045e2ea617SAdrian Hunter " nesting_cnt:\t%d\n" 180511dd62a7SDenis Karpov " ctx_loss:\t%d:%d\n" 18065e2ea617SAdrian Hunter "\nregs:\n", 1807dd498effSDenis Karpov mmc->index, mmc->enabled ? 1 : 0, 1808dd498effSDenis Karpov host->dpm_state, mmc->nesting_cnt, 180911dd62a7SDenis Karpov host->context_loss, context_loss); 18105e2ea617SAdrian Hunter 18117a8c2cefSBalaji T K if (host->suspended) { 1812dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1813dd498effSDenis Karpov return 0; 1814dd498effSDenis Karpov } 1815dd498effSDenis Karpov 1816fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1817d900f712SDenis Karpov 1818d900f712SDenis Karpov seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1819d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1820d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1821d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1822d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1823d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1824d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1825d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1826d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1827d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1828d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1829d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1830d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1831d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18325e2ea617SAdrian Hunter 1833fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1834fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1835dd498effSDenis Karpov 1836d900f712SDenis Karpov return 0; 1837d900f712SDenis Karpov } 1838d900f712SDenis Karpov 183970a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1840d900f712SDenis Karpov { 184170a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1842d900f712SDenis Karpov } 1843d900f712SDenis Karpov 1844d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 184570a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1846d900f712SDenis Karpov .read = seq_read, 1847d900f712SDenis Karpov .llseek = seq_lseek, 1848d900f712SDenis Karpov .release = single_release, 1849d900f712SDenis Karpov }; 1850d900f712SDenis Karpov 185170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1852d900f712SDenis Karpov { 1853d900f712SDenis Karpov if (mmc->debugfs_root) 1854d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1855d900f712SDenis Karpov mmc, &mmc_regs_fops); 1856d900f712SDenis Karpov } 1857d900f712SDenis Karpov 1858d900f712SDenis Karpov #else 1859d900f712SDenis Karpov 186070a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1861d900f712SDenis Karpov { 1862d900f712SDenis Karpov } 1863d900f712SDenis Karpov 1864d900f712SDenis Karpov #endif 1865d900f712SDenis Karpov 186670a3341aSDenis Karpov static int __init omap_hsmmc_probe(struct platform_device *pdev) 1867a45c6cb8SMadhusudhan Chikkature { 1868a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1869a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 187070a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1871a45c6cb8SMadhusudhan Chikkature struct resource *res; 1872db0fefc5SAdrian Hunter int ret, irq; 1873a45c6cb8SMadhusudhan Chikkature 1874a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1875a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1876a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1877a45c6cb8SMadhusudhan Chikkature } 1878a45c6cb8SMadhusudhan Chikkature 1879a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1880a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1881a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1882a45c6cb8SMadhusudhan Chikkature } 1883a45c6cb8SMadhusudhan Chikkature 1884a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1885a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1886a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1887a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1888a45c6cb8SMadhusudhan Chikkature 188991a0b089Skishore kadiyala res->start += pdata->reg_offset; 189091a0b089Skishore kadiyala res->end += pdata->reg_offset; 1891984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1892a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1893a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1894a45c6cb8SMadhusudhan Chikkature 1895db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1896db0fefc5SAdrian Hunter if (ret) 1897db0fefc5SAdrian Hunter goto err; 1898db0fefc5SAdrian Hunter 189970a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1900a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1901a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1902db0fefc5SAdrian Hunter goto err_alloc; 1903a45c6cb8SMadhusudhan Chikkature } 1904a45c6cb8SMadhusudhan Chikkature 1905a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1906a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1907a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1908a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1909a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1910a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 1911a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1912a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1913a45c6cb8SMadhusudhan Chikkature host->id = pdev->id; 1914a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1915a45c6cb8SMadhusudhan Chikkature host->mapbase = res->start; 1916a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 19176da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 19189782aff8SPer Forlin host->next_data.cookie = 1; 1919a45c6cb8SMadhusudhan Chikkature 1920a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 192170a3341aSDenis Karpov INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 1922a45c6cb8SMadhusudhan Chikkature 192370a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1924dd498effSDenis Karpov 1925e0eb2424SAdrian Hunter /* 1926e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1927e0eb2424SAdrian Hunter * no off state. 1928e0eb2424SAdrian Hunter */ 1929e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1930e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1931e0eb2424SAdrian Hunter 19326b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 19336b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1934a45c6cb8SMadhusudhan Chikkature 19354dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1936a45c6cb8SMadhusudhan Chikkature 19376f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1938a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1939a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1940a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1941a45c6cb8SMadhusudhan Chikkature goto err1; 1942a45c6cb8SMadhusudhan Chikkature } 1943a45c6cb8SMadhusudhan Chikkature 194470a3341aSDenis Karpov omap_hsmmc_context_save(host); 194511dd62a7SDenis Karpov 19465e2ea617SAdrian Hunter mmc->caps |= MMC_CAP_DISABLE; 19479b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 19489b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 19499b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 19509b68256cSPaul Walmsley } 1951dd498effSDenis Karpov 1952fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1953fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1954fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1955fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1956a45c6cb8SMadhusudhan Chikkature 19572bec0893SAdrian Hunter if (cpu_is_omap2430()) { 1958a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1959a45c6cb8SMadhusudhan Chikkature /* 1960a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1961a45c6cb8SMadhusudhan Chikkature */ 1962a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->dbclk)) 19632bec0893SAdrian Hunter dev_warn(mmc_dev(host->mmc), 19642bec0893SAdrian Hunter "Failed to get debounce clock\n"); 1965a45c6cb8SMadhusudhan Chikkature else 19662bec0893SAdrian Hunter host->got_dbclk = 1; 19672bec0893SAdrian Hunter 19682bec0893SAdrian Hunter if (host->got_dbclk) 1969a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1970a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 1971a45c6cb8SMadhusudhan Chikkature " clk failed\n"); 19722bec0893SAdrian Hunter } 1973a45c6cb8SMadhusudhan Chikkature 19740ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19750ccd76d4SJuha Yrjola * as we want. */ 1976a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19770ccd76d4SJuha Yrjola 1978a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1979a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1980a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1981a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1982a45c6cb8SMadhusudhan Chikkature 198313189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 198493caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1985a45c6cb8SMadhusudhan Chikkature 19863a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19873a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1988a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1989a45c6cb8SMadhusudhan Chikkature 1990191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 199123d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 199223d99bb9SAdrian Hunter 199370a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1994a45c6cb8SMadhusudhan Chikkature 1995f3e2f1ddSGrazvydas Ignotas /* Select DMA lines */ 1996f3e2f1ddSGrazvydas Ignotas switch (host->id) { 1997f3e2f1ddSGrazvydas Ignotas case OMAP_MMC1_DEVID: 1998f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 1999f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2000f3e2f1ddSGrazvydas Ignotas break; 2001f3e2f1ddSGrazvydas Ignotas case OMAP_MMC2_DEVID: 2002f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2003f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2004f3e2f1ddSGrazvydas Ignotas break; 2005f3e2f1ddSGrazvydas Ignotas case OMAP_MMC3_DEVID: 2006f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2007f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2008f3e2f1ddSGrazvydas Ignotas break; 200982cf818dSkishore kadiyala case OMAP_MMC4_DEVID: 201082cf818dSkishore kadiyala host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 201182cf818dSkishore kadiyala host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 201282cf818dSkishore kadiyala break; 201382cf818dSkishore kadiyala case OMAP_MMC5_DEVID: 201482cf818dSkishore kadiyala host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 201582cf818dSkishore kadiyala host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 201682cf818dSkishore kadiyala break; 2017f3e2f1ddSGrazvydas Ignotas default: 2018f3e2f1ddSGrazvydas Ignotas dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2019f3e2f1ddSGrazvydas Ignotas goto err_irq; 2020a45c6cb8SMadhusudhan Chikkature } 2021a45c6cb8SMadhusudhan Chikkature 2022a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2023d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 2024a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2025a45c6cb8SMadhusudhan Chikkature if (ret) { 2026a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2027a45c6cb8SMadhusudhan Chikkature goto err_irq; 2028a45c6cb8SMadhusudhan Chikkature } 2029a45c6cb8SMadhusudhan Chikkature 2030a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 2031a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 203270a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 203370a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 2034a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 2035a45c6cb8SMadhusudhan Chikkature } 2036a45c6cb8SMadhusudhan Chikkature } 2037db0fefc5SAdrian Hunter 2038b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2039db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2040db0fefc5SAdrian Hunter if (ret) 2041db0fefc5SAdrian Hunter goto err_reg; 2042db0fefc5SAdrian Hunter host->use_reg = 1; 2043db0fefc5SAdrian Hunter } 2044db0fefc5SAdrian Hunter 2045b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 2046a45c6cb8SMadhusudhan Chikkature 2047a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2048e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 2049a45c6cb8SMadhusudhan Chikkature ret = request_irq(mmc_slot(host).card_detect_irq, 205070a3341aSDenis Karpov omap_hsmmc_cd_handler, 2051d9618e9fSYong Zhang IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 2052a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2053a45c6cb8SMadhusudhan Chikkature if (ret) { 2054a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2055a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2056a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2057a45c6cb8SMadhusudhan Chikkature } 205872f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 205972f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2060a45c6cb8SMadhusudhan Chikkature } 2061a45c6cb8SMadhusudhan Chikkature 2062b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2063a45c6cb8SMadhusudhan Chikkature 2064b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2065b62f6228SAdrian Hunter 2066a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2067a45c6cb8SMadhusudhan Chikkature 2068191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2069a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2070a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2071a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2072a45c6cb8SMadhusudhan Chikkature } 2073191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2074a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2075a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2076a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2077db0fefc5SAdrian Hunter goto err_slot_name; 2078a45c6cb8SMadhusudhan Chikkature } 2079a45c6cb8SMadhusudhan Chikkature 208070a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2081fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2082fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2083d900f712SDenis Karpov 2084a45c6cb8SMadhusudhan Chikkature return 0; 2085a45c6cb8SMadhusudhan Chikkature 2086a45c6cb8SMadhusudhan Chikkature err_slot_name: 2087a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2088a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2089db0fefc5SAdrian Hunter err_irq_cd: 2090db0fefc5SAdrian Hunter if (host->use_reg) 2091db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2092db0fefc5SAdrian Hunter err_reg: 2093db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2094db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2095a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2096a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2097a45c6cb8SMadhusudhan Chikkature err_irq: 2098fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2099fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2100a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 21012bec0893SAdrian Hunter if (host->got_dbclk) { 2102a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2103a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2104a45c6cb8SMadhusudhan Chikkature } 2105a45c6cb8SMadhusudhan Chikkature err1: 2106a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2107db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 2108a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2109db0fefc5SAdrian Hunter err_alloc: 2110db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2111db0fefc5SAdrian Hunter err: 2112984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2113a45c6cb8SMadhusudhan Chikkature return ret; 2114a45c6cb8SMadhusudhan Chikkature } 2115a45c6cb8SMadhusudhan Chikkature 211670a3341aSDenis Karpov static int omap_hsmmc_remove(struct platform_device *pdev) 2117a45c6cb8SMadhusudhan Chikkature { 211870a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2119a45c6cb8SMadhusudhan Chikkature struct resource *res; 2120a45c6cb8SMadhusudhan Chikkature 2121a45c6cb8SMadhusudhan Chikkature if (host) { 2122fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2123a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2124db0fefc5SAdrian Hunter if (host->use_reg) 2125db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2126a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2127a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2128a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2129a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2130a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 21310d9ee5b2STejun Heo flush_work_sync(&host->mmc_carddetect_work); 2132a45c6cb8SMadhusudhan Chikkature 2133fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2134fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2135a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 21362bec0893SAdrian Hunter if (host->got_dbclk) { 2137a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2138a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2139a45c6cb8SMadhusudhan Chikkature } 2140a45c6cb8SMadhusudhan Chikkature 2141a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2142a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2143db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2144a45c6cb8SMadhusudhan Chikkature } 2145a45c6cb8SMadhusudhan Chikkature 2146a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2147a45c6cb8SMadhusudhan Chikkature if (res) 2148984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2149a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2150a45c6cb8SMadhusudhan Chikkature 2151a45c6cb8SMadhusudhan Chikkature return 0; 2152a45c6cb8SMadhusudhan Chikkature } 2153a45c6cb8SMadhusudhan Chikkature 2154a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2155a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2156a45c6cb8SMadhusudhan Chikkature { 2157a45c6cb8SMadhusudhan Chikkature int ret = 0; 2158a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 215970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2160a45c6cb8SMadhusudhan Chikkature 2161a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2162a45c6cb8SMadhusudhan Chikkature return 0; 2163a45c6cb8SMadhusudhan Chikkature 2164a45c6cb8SMadhusudhan Chikkature if (host) { 2165fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2166a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2167a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2168a45c6cb8SMadhusudhan Chikkature ret = host->pdata->suspend(&pdev->dev, 2169a45c6cb8SMadhusudhan Chikkature host->slot_id); 2170a6b2240dSAdrian Hunter if (ret) { 2171a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2172a45c6cb8SMadhusudhan Chikkature "Unable to handle MMC board" 2173a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2174a6b2240dSAdrian Hunter host->suspended = 0; 2175a6b2240dSAdrian Hunter return ret; 2176a45c6cb8SMadhusudhan Chikkature } 2177a6b2240dSAdrian Hunter } 2178a6b2240dSAdrian Hunter cancel_work_sync(&host->mmc_carddetect_work); 21791a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2180fa4aa2d4SBalaji T K 2181a6b2240dSAdrian Hunter if (ret == 0) { 2182b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2183a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 21840683af48SJarkko Lavinen OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 21852bec0893SAdrian Hunter if (host->got_dbclk) 2186a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2187a6b2240dSAdrian Hunter } else { 2188a6b2240dSAdrian Hunter host->suspended = 0; 2189a6b2240dSAdrian Hunter if (host->pdata->resume) { 2190a6b2240dSAdrian Hunter ret = host->pdata->resume(&pdev->dev, 2191a6b2240dSAdrian Hunter host->slot_id); 2192a6b2240dSAdrian Hunter if (ret) 2193a6b2240dSAdrian Hunter dev_dbg(mmc_dev(host->mmc), 2194a6b2240dSAdrian Hunter "Unmask interrupt failed\n"); 2195a6b2240dSAdrian Hunter } 2196a6b2240dSAdrian Hunter } 2197fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2198a45c6cb8SMadhusudhan Chikkature } 2199a45c6cb8SMadhusudhan Chikkature return ret; 2200a45c6cb8SMadhusudhan Chikkature } 2201a45c6cb8SMadhusudhan Chikkature 2202a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2203a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2204a45c6cb8SMadhusudhan Chikkature { 2205a45c6cb8SMadhusudhan Chikkature int ret = 0; 2206a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 220770a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2208a45c6cb8SMadhusudhan Chikkature 2209a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2210a45c6cb8SMadhusudhan Chikkature return 0; 2211a45c6cb8SMadhusudhan Chikkature 2212a45c6cb8SMadhusudhan Chikkature if (host) { 2213fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 221411dd62a7SDenis Karpov 22152bec0893SAdrian Hunter if (host->got_dbclk) 22162bec0893SAdrian Hunter clk_enable(host->dbclk); 22172bec0893SAdrian Hunter 221870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22191b331e69SKim Kyuwon 2220a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2221a45c6cb8SMadhusudhan Chikkature ret = host->pdata->resume(&pdev->dev, host->slot_id); 2222a45c6cb8SMadhusudhan Chikkature if (ret) 2223a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2224a45c6cb8SMadhusudhan Chikkature "Unmask interrupt failed\n"); 2225a45c6cb8SMadhusudhan Chikkature } 2226a45c6cb8SMadhusudhan Chikkature 2227b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2228b62f6228SAdrian Hunter 2229a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2230a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2231a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2232a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2233fa4aa2d4SBalaji T K 2234fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2235fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2236a45c6cb8SMadhusudhan Chikkature } 2237a45c6cb8SMadhusudhan Chikkature 2238a45c6cb8SMadhusudhan Chikkature return ret; 2239a45c6cb8SMadhusudhan Chikkature 2240a45c6cb8SMadhusudhan Chikkature } 2241a45c6cb8SMadhusudhan Chikkature 2242a45c6cb8SMadhusudhan Chikkature #else 224370a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 224470a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2245a45c6cb8SMadhusudhan Chikkature #endif 2246a45c6cb8SMadhusudhan Chikkature 2247fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2248fa4aa2d4SBalaji T K { 2249fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2250fa4aa2d4SBalaji T K 2251fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2252fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2253fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "disabled\n"); 2254fa4aa2d4SBalaji T K 2255fa4aa2d4SBalaji T K return 0; 2256fa4aa2d4SBalaji T K } 2257fa4aa2d4SBalaji T K 2258fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2259fa4aa2d4SBalaji T K { 2260fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2261fa4aa2d4SBalaji T K 2262fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2263fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2264fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "enabled\n"); 2265fa4aa2d4SBalaji T K 2266fa4aa2d4SBalaji T K return 0; 2267fa4aa2d4SBalaji T K } 2268fa4aa2d4SBalaji T K 2269a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 227070a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 227170a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2272fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2273fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2274a791daa1SKevin Hilman }; 2275a791daa1SKevin Hilman 2276a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2277a791daa1SKevin Hilman .remove = omap_hsmmc_remove, 2278a45c6cb8SMadhusudhan Chikkature .driver = { 2279a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2280a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2281a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 2282a45c6cb8SMadhusudhan Chikkature }, 2283a45c6cb8SMadhusudhan Chikkature }; 2284a45c6cb8SMadhusudhan Chikkature 228570a3341aSDenis Karpov static int __init omap_hsmmc_init(void) 2286a45c6cb8SMadhusudhan Chikkature { 2287a45c6cb8SMadhusudhan Chikkature /* Register the MMC driver */ 22888753298aSRoger Quadros return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2289a45c6cb8SMadhusudhan Chikkature } 2290a45c6cb8SMadhusudhan Chikkature 229170a3341aSDenis Karpov static void __exit omap_hsmmc_cleanup(void) 2292a45c6cb8SMadhusudhan Chikkature { 2293a45c6cb8SMadhusudhan Chikkature /* Unregister MMC driver */ 229470a3341aSDenis Karpov platform_driver_unregister(&omap_hsmmc_driver); 2295a45c6cb8SMadhusudhan Chikkature } 2296a45c6cb8SMadhusudhan Chikkature 229770a3341aSDenis Karpov module_init(omap_hsmmc_init); 229870a3341aSDenis Karpov module_exit(omap_hsmmc_cleanup); 2299a45c6cb8SMadhusudhan Chikkature 2300a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2301a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2302a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2303a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2304