1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3046856a68SRajendra Nayak #include <linux/of.h> 3146856a68SRajendra Nayak #include <linux/of_gpio.h> 3246856a68SRajendra Nayak #include <linux/of_device.h> 333451c067SRussell King #include <linux/omap-dma.h> 34a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3513189e78SJarkko Lavinen #include <linux/mmc/core.h> 3693caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 37a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 38db0fefc5SAdrian Hunter #include <linux/gpio.h> 39db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4046b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 41fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4268f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 43a45c6cb8SMadhusudhan Chikkature 44a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4511dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 46a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 61a45c6cb8SMadhusudhan Chikkature 62a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 63a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 64cd587096SHebbar, Gururaja #define HSS (1 << 21) 65a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 66a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 67eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 681b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 69a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 70a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 71a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 72a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 73a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 74a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 75a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 76a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 77a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 78a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 79a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 80a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 81a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 82a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 83a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 84a7e96879SVenkatraman S #define DMAE 0x1 85a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 86a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 87a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 88cd587096SHebbar, Gururaja #define HSPE (1 << 2) 8903b5d924SBalaji T K #define DDR (1 << 19) 9073153010SJarkko Lavinen #define DW8 (1 << 5) 91a45c6cb8SMadhusudhan Chikkature #define OD 0x1 92a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 93a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 94a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 95a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 96a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9711dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 9811dd62a7SDenis Karpov #define RESETDONE (1 << 0) 99a45c6cb8SMadhusudhan Chikkature 100a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 101a7e96879SVenkatraman S #define CC_EN (1 << 0) 102a7e96879SVenkatraman S #define TC_EN (1 << 1) 103a7e96879SVenkatraman S #define BWR_EN (1 << 4) 104a7e96879SVenkatraman S #define BRR_EN (1 << 5) 105a7e96879SVenkatraman S #define ERR_EN (1 << 15) 106a7e96879SVenkatraman S #define CTO_EN (1 << 16) 107a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 108a7e96879SVenkatraman S #define CEB_EN (1 << 18) 109a7e96879SVenkatraman S #define CIE_EN (1 << 19) 110a7e96879SVenkatraman S #define DTO_EN (1 << 20) 111a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 112a7e96879SVenkatraman S #define DEB_EN (1 << 22) 113a7e96879SVenkatraman S #define CERR_EN (1 << 28) 114a7e96879SVenkatraman S #define BADA_EN (1 << 29) 115a7e96879SVenkatraman S 116a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 117a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 118a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 119a7e96879SVenkatraman S 120fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 121a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1226b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1236b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1240005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 125a45c6cb8SMadhusudhan Chikkature 126a45c6cb8SMadhusudhan Chikkature /* 127a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 128a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 129a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 130a45c6cb8SMadhusudhan Chikkature */ 131a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 132a45c6cb8SMadhusudhan Chikkature 133a45c6cb8SMadhusudhan Chikkature /* 134a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 135a45c6cb8SMadhusudhan Chikkature */ 136a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 137a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 138a45c6cb8SMadhusudhan Chikkature 139a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 140a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 141a45c6cb8SMadhusudhan Chikkature 1429782aff8SPer Forlin struct omap_hsmmc_next { 1439782aff8SPer Forlin unsigned int dma_len; 1449782aff8SPer Forlin s32 cookie; 1459782aff8SPer Forlin }; 1469782aff8SPer Forlin 14770a3341aSDenis Karpov struct omap_hsmmc_host { 148a45c6cb8SMadhusudhan Chikkature struct device *dev; 149a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 150a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 151a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 152a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 153a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 154a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 155db0fefc5SAdrian Hunter /* 156db0fefc5SAdrian Hunter * vcc == configured supply 157db0fefc5SAdrian Hunter * vcc_aux == optional 158db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 159db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 160db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 161db0fefc5SAdrian Hunter */ 162db0fefc5SAdrian Hunter struct regulator *vcc; 163db0fefc5SAdrian Hunter struct regulator *vcc_aux; 164cf5ae40bSTony Lindgren int pbias_disable; 165a45c6cb8SMadhusudhan Chikkature void __iomem *base; 166a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1674dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 168a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1690ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 170a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 171a3621465SAdrian Hunter unsigned char power_mode; 172a45c6cb8SMadhusudhan Chikkature int suspended; 173a45c6cb8SMadhusudhan Chikkature int irq; 174a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 175c5c98927SRussell King struct dma_chan *tx_chan; 176c5c98927SRussell King struct dma_chan *rx_chan; 177a45c6cb8SMadhusudhan Chikkature int slot_id; 1784a694dc9SAdrian Hunter int response_busy; 17911dd62a7SDenis Karpov int context_loss; 180b62f6228SAdrian Hunter int protect_card; 181b62f6228SAdrian Hunter int reqs_blocked; 182db0fefc5SAdrian Hunter int use_reg; 183b417577dSAdrian Hunter int req_in_progress; 1849782aff8SPer Forlin struct omap_hsmmc_next next_data; 18511dd62a7SDenis Karpov 186a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 187a45c6cb8SMadhusudhan Chikkature }; 188a45c6cb8SMadhusudhan Chikkature 189db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 190db0fefc5SAdrian Hunter { 1919ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 1929ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 193db0fefc5SAdrian Hunter 194db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 195db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 196db0fefc5SAdrian Hunter } 197db0fefc5SAdrian Hunter 198db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 199db0fefc5SAdrian Hunter { 2009ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2019ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 202db0fefc5SAdrian Hunter 203db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 204db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 205db0fefc5SAdrian Hunter } 206db0fefc5SAdrian Hunter 207db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 208db0fefc5SAdrian Hunter { 2099ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2109ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 211db0fefc5SAdrian Hunter 212db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 213db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 214db0fefc5SAdrian Hunter } 215db0fefc5SAdrian Hunter 216db0fefc5SAdrian Hunter #ifdef CONFIG_PM 217db0fefc5SAdrian Hunter 218db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 219db0fefc5SAdrian Hunter { 2209ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2219ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 222db0fefc5SAdrian Hunter 223db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 224db0fefc5SAdrian Hunter return 0; 225db0fefc5SAdrian Hunter } 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 228db0fefc5SAdrian Hunter { 2299ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2309ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 231db0fefc5SAdrian Hunter 232db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 233db0fefc5SAdrian Hunter return 0; 234db0fefc5SAdrian Hunter } 235db0fefc5SAdrian Hunter 236db0fefc5SAdrian Hunter #else 237db0fefc5SAdrian Hunter 238db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 239db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 240db0fefc5SAdrian Hunter 241db0fefc5SAdrian Hunter #endif 242db0fefc5SAdrian Hunter 243b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 244b702b106SAdrian Hunter 24569b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 246db0fefc5SAdrian Hunter int vdd) 247db0fefc5SAdrian Hunter { 248db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 249db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 250db0fefc5SAdrian Hunter int ret = 0; 251db0fefc5SAdrian Hunter 252db0fefc5SAdrian Hunter /* 253db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 254db0fefc5SAdrian Hunter * voltage always-on regulator. 255db0fefc5SAdrian Hunter */ 256db0fefc5SAdrian Hunter if (!host->vcc) 257db0fefc5SAdrian Hunter return 0; 2581f84b71bSRajendra Nayak /* 259cf5ae40bSTony Lindgren * With DT, never turn OFF the regulator for MMC1. This is because 2601f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2611f84b71bSRajendra Nayak * booting with Device tree 2621f84b71bSRajendra Nayak */ 263cf5ae40bSTony Lindgren if (host->pbias_disable && !vdd) 2641f84b71bSRajendra Nayak return 0; 265db0fefc5SAdrian Hunter 266db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 267db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 268db0fefc5SAdrian Hunter 269db0fefc5SAdrian Hunter /* 270db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 271db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 272db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 273db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 274db0fefc5SAdrian Hunter * 275db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 276db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 277db0fefc5SAdrian Hunter * 278db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 279db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 280db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 281db0fefc5SAdrian Hunter */ 282db0fefc5SAdrian Hunter if (power_on) { 28399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 284db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 285db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 286db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 287db0fefc5SAdrian Hunter if (ret < 0) 28899fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 28999fc5131SLinus Walleij host->vcc, 0); 290db0fefc5SAdrian Hunter } 291db0fefc5SAdrian Hunter } else { 29299fc5131SLinus Walleij /* Shut down the rail */ 2936da20c89SAdrian Hunter if (host->vcc_aux) 294db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 29599fc5131SLinus Walleij if (!ret) { 29699fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 29799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 29899fc5131SLinus Walleij host->vcc, 0); 29999fc5131SLinus Walleij } 300db0fefc5SAdrian Hunter } 301db0fefc5SAdrian Hunter 302db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 303db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 304db0fefc5SAdrian Hunter 305db0fefc5SAdrian Hunter return ret; 306db0fefc5SAdrian Hunter } 307db0fefc5SAdrian Hunter 308db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 309db0fefc5SAdrian Hunter { 310db0fefc5SAdrian Hunter struct regulator *reg; 31164be9782Skishore kadiyala int ocr_value = 0; 312db0fefc5SAdrian Hunter 313db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 314db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 315b1e056aeSVenkatraman S dev_err(host->dev, "vmmc regulator missing\n"); 3161fdc90fbSNeilBrown return PTR_ERR(reg); 317db0fefc5SAdrian Hunter } else { 3181fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 319db0fefc5SAdrian Hunter host->vcc = reg; 32064be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 32164be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 32264be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 32364be9782Skishore kadiyala } else { 32464be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3252cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 326e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 32764be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 32864be9782Skishore kadiyala return -EINVAL; 32964be9782Skishore kadiyala } 33064be9782Skishore kadiyala } 331db0fefc5SAdrian Hunter 332db0fefc5SAdrian Hunter /* Allow an aux regulator */ 333db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 334db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 335db0fefc5SAdrian Hunter 336b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 337b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 338b1c1df7aSBalaji T K return 0; 339db0fefc5SAdrian Hunter /* 340db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 341db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 342db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 343db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 344db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 345db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 346db0fefc5SAdrian Hunter */ 347e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 348e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 349e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 350e840ce13SAdrian Hunter 351e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 352e840ce13SAdrian Hunter 1, vdd); 353e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 354e840ce13SAdrian Hunter 0, 0); 355db0fefc5SAdrian Hunter } 356db0fefc5SAdrian Hunter } 357db0fefc5SAdrian Hunter 358db0fefc5SAdrian Hunter return 0; 359db0fefc5SAdrian Hunter } 360db0fefc5SAdrian Hunter 361db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 362db0fefc5SAdrian Hunter { 363db0fefc5SAdrian Hunter regulator_put(host->vcc); 364db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 365db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 366db0fefc5SAdrian Hunter } 367db0fefc5SAdrian Hunter 368b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 369b702b106SAdrian Hunter { 370b702b106SAdrian Hunter return 1; 371b702b106SAdrian Hunter } 372b702b106SAdrian Hunter 373b702b106SAdrian Hunter #else 374b702b106SAdrian Hunter 375b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 376b702b106SAdrian Hunter { 377b702b106SAdrian Hunter return -EINVAL; 378b702b106SAdrian Hunter } 379b702b106SAdrian Hunter 380b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 381b702b106SAdrian Hunter { 382b702b106SAdrian Hunter } 383b702b106SAdrian Hunter 384b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 385b702b106SAdrian Hunter { 386b702b106SAdrian Hunter return 0; 387b702b106SAdrian Hunter } 388b702b106SAdrian Hunter 389b702b106SAdrian Hunter #endif 390b702b106SAdrian Hunter 391b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 392b702b106SAdrian Hunter { 393b702b106SAdrian Hunter int ret; 394b702b106SAdrian Hunter 395b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 396b702b106SAdrian Hunter if (pdata->slots[0].cover) 397b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 398b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 399b702b106SAdrian Hunter else 400b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 401b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 402b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 403b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 404b702b106SAdrian Hunter if (ret) 405b702b106SAdrian Hunter return ret; 406b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 407b702b106SAdrian Hunter if (ret) 408b702b106SAdrian Hunter goto err_free_sp; 409b702b106SAdrian Hunter } else 410b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 411b702b106SAdrian Hunter 412b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 413b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 414b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 415b702b106SAdrian Hunter if (ret) 416b702b106SAdrian Hunter goto err_free_cd; 417b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 418b702b106SAdrian Hunter if (ret) 419b702b106SAdrian Hunter goto err_free_wp; 420b702b106SAdrian Hunter } else 421b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 422b702b106SAdrian Hunter 423b702b106SAdrian Hunter return 0; 424b702b106SAdrian Hunter 425b702b106SAdrian Hunter err_free_wp: 426b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 427b702b106SAdrian Hunter err_free_cd: 428b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 429b702b106SAdrian Hunter err_free_sp: 430b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 431b702b106SAdrian Hunter return ret; 432b702b106SAdrian Hunter } 433b702b106SAdrian Hunter 434b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 435b702b106SAdrian Hunter { 436b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 437b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 438b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 439b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 440b702b106SAdrian Hunter } 441b702b106SAdrian Hunter 442a45c6cb8SMadhusudhan Chikkature /* 443e0c7f99bSAndy Shevchenko * Start clock to the card 444e0c7f99bSAndy Shevchenko */ 445e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 446e0c7f99bSAndy Shevchenko { 447e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 448e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 449e0c7f99bSAndy Shevchenko } 450e0c7f99bSAndy Shevchenko 451e0c7f99bSAndy Shevchenko /* 452a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 453a45c6cb8SMadhusudhan Chikkature */ 45470a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 455a45c6cb8SMadhusudhan Chikkature { 456a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 457a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 458a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4597122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 460a45c6cb8SMadhusudhan Chikkature } 461a45c6cb8SMadhusudhan Chikkature 46293caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 46393caf8e6SAdrian Hunter struct mmc_command *cmd) 464b417577dSAdrian Hunter { 465b417577dSAdrian Hunter unsigned int irq_mask; 466b417577dSAdrian Hunter 467b417577dSAdrian Hunter if (host->use_dma) 468a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 469b417577dSAdrian Hunter else 470b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 471b417577dSAdrian Hunter 47293caf8e6SAdrian Hunter /* Disable timeout for erases */ 47393caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 474a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 47593caf8e6SAdrian Hunter 476b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 477b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 478b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 479b417577dSAdrian Hunter } 480b417577dSAdrian Hunter 481b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 482b417577dSAdrian Hunter { 483b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 484b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 485b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 486b417577dSAdrian Hunter } 487b417577dSAdrian Hunter 488ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 489d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 490ac330f44SAndy Shevchenko { 491ac330f44SAndy Shevchenko u16 dsor = 0; 492ac330f44SAndy Shevchenko 493ac330f44SAndy Shevchenko if (ios->clock) { 494d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 495ac330f44SAndy Shevchenko if (dsor > 250) 496ac330f44SAndy Shevchenko dsor = 250; 497ac330f44SAndy Shevchenko } 498ac330f44SAndy Shevchenko 499ac330f44SAndy Shevchenko return dsor; 500ac330f44SAndy Shevchenko } 501ac330f44SAndy Shevchenko 5025934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5035934df2fSAndy Shevchenko { 5045934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5055934df2fSAndy Shevchenko unsigned long regval; 5065934df2fSAndy Shevchenko unsigned long timeout; 507cd587096SHebbar, Gururaja unsigned long clkdiv; 5085934df2fSAndy Shevchenko 5098986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5105934df2fSAndy Shevchenko 5115934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5125934df2fSAndy Shevchenko 5135934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5145934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 515cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 516cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5175934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5185934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5195934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5205934df2fSAndy Shevchenko 5215934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5225934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5235934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5245934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5255934df2fSAndy Shevchenko cpu_relax(); 5265934df2fSAndy Shevchenko 527cd587096SHebbar, Gururaja /* 528cd587096SHebbar, Gururaja * Enable High-Speed Support 529cd587096SHebbar, Gururaja * Pre-Requisites 530cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 531cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 532cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 533cd587096SHebbar, Gururaja * in capabilities register 534cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 535cd587096SHebbar, Gururaja */ 536cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 537cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 538cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 539cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 540cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 541cd587096SHebbar, Gururaja regval |= HSPE; 542cd587096SHebbar, Gururaja else 543cd587096SHebbar, Gururaja regval &= ~HSPE; 544cd587096SHebbar, Gururaja 545cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 546cd587096SHebbar, Gururaja } 547cd587096SHebbar, Gururaja 5485934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5495934df2fSAndy Shevchenko } 5505934df2fSAndy Shevchenko 5513796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5523796fb8aSAndy Shevchenko { 5533796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5543796fb8aSAndy Shevchenko u32 con; 5553796fb8aSAndy Shevchenko 5563796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 55703b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 55803b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 55903b5d924SBalaji T K else 56003b5d924SBalaji T K con &= ~DDR; 5613796fb8aSAndy Shevchenko switch (ios->bus_width) { 5623796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5633796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5643796fb8aSAndy Shevchenko break; 5653796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5663796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5673796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5683796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5693796fb8aSAndy Shevchenko break; 5703796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5713796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5723796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5733796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5743796fb8aSAndy Shevchenko break; 5753796fb8aSAndy Shevchenko } 5763796fb8aSAndy Shevchenko } 5773796fb8aSAndy Shevchenko 5783796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5793796fb8aSAndy Shevchenko { 5803796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5813796fb8aSAndy Shevchenko u32 con; 5823796fb8aSAndy Shevchenko 5833796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5843796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5853796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5863796fb8aSAndy Shevchenko else 5873796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5883796fb8aSAndy Shevchenko } 5893796fb8aSAndy Shevchenko 59011dd62a7SDenis Karpov #ifdef CONFIG_PM 59111dd62a7SDenis Karpov 59211dd62a7SDenis Karpov /* 59311dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 59411dd62a7SDenis Karpov * power state change. 59511dd62a7SDenis Karpov */ 59670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 59711dd62a7SDenis Karpov { 59811dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 59911dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 60011dd62a7SDenis Karpov int context_loss = 0; 6013796fb8aSAndy Shevchenko u32 hctl, capa; 60211dd62a7SDenis Karpov unsigned long timeout; 60311dd62a7SDenis Karpov 60411dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 60511dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 60611dd62a7SDenis Karpov if (context_loss < 0) 60711dd62a7SDenis Karpov return 1; 60811dd62a7SDenis Karpov } 60911dd62a7SDenis Karpov 61011dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 61111dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 61211dd62a7SDenis Karpov if (host->context_loss == context_loss) 61311dd62a7SDenis Karpov return 1; 61411dd62a7SDenis Karpov 6156c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 6166c31b215SVenkatraman S return 1; 61711dd62a7SDenis Karpov 618c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 61911dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 62011dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 62111dd62a7SDenis Karpov hctl = SDVS18; 62211dd62a7SDenis Karpov else 62311dd62a7SDenis Karpov hctl = SDVS30; 62411dd62a7SDenis Karpov capa = VS30 | VS18; 62511dd62a7SDenis Karpov } else { 62611dd62a7SDenis Karpov hctl = SDVS18; 62711dd62a7SDenis Karpov capa = VS18; 62811dd62a7SDenis Karpov } 62911dd62a7SDenis Karpov 63011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 63211dd62a7SDenis Karpov 63311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 63411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 63511dd62a7SDenis Karpov 63611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 63811dd62a7SDenis Karpov 63911dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 64011dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 64111dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64211dd62a7SDenis Karpov ; 64311dd62a7SDenis Karpov 644b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 64511dd62a7SDenis Karpov 64611dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 64711dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 64811dd62a7SDenis Karpov goto out; 64911dd62a7SDenis Karpov 6503796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 65111dd62a7SDenis Karpov 6525934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 65311dd62a7SDenis Karpov 6543796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6553796fb8aSAndy Shevchenko 65611dd62a7SDenis Karpov out: 65711dd62a7SDenis Karpov host->context_loss = context_loss; 65811dd62a7SDenis Karpov 65911dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 66011dd62a7SDenis Karpov return 0; 66111dd62a7SDenis Karpov } 66211dd62a7SDenis Karpov 66311dd62a7SDenis Karpov /* 66411dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 66511dd62a7SDenis Karpov */ 66670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 66711dd62a7SDenis Karpov { 66811dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 66911dd62a7SDenis Karpov int context_loss; 67011dd62a7SDenis Karpov 67111dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 67211dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 67311dd62a7SDenis Karpov if (context_loss < 0) 67411dd62a7SDenis Karpov return; 67511dd62a7SDenis Karpov host->context_loss = context_loss; 67611dd62a7SDenis Karpov } 67711dd62a7SDenis Karpov } 67811dd62a7SDenis Karpov 67911dd62a7SDenis Karpov #else 68011dd62a7SDenis Karpov 68170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 68211dd62a7SDenis Karpov { 68311dd62a7SDenis Karpov return 0; 68411dd62a7SDenis Karpov } 68511dd62a7SDenis Karpov 68670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 68711dd62a7SDenis Karpov { 68811dd62a7SDenis Karpov } 68911dd62a7SDenis Karpov 69011dd62a7SDenis Karpov #endif 69111dd62a7SDenis Karpov 692a45c6cb8SMadhusudhan Chikkature /* 693a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 694a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 695a45c6cb8SMadhusudhan Chikkature */ 69670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 697a45c6cb8SMadhusudhan Chikkature { 698a45c6cb8SMadhusudhan Chikkature int reg = 0; 699a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 700a45c6cb8SMadhusudhan Chikkature 701b62f6228SAdrian Hunter if (host->protect_card) 702b62f6228SAdrian Hunter return; 703b62f6228SAdrian Hunter 704a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 705b417577dSAdrian Hunter 706b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 707a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 708a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 709a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 710a45c6cb8SMadhusudhan Chikkature 711a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 712a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 713a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 714a45c6cb8SMadhusudhan Chikkature 715a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 716a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 717c653a6d4SAdrian Hunter 718c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 719c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 720c653a6d4SAdrian Hunter 721a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 722a45c6cb8SMadhusudhan Chikkature } 723a45c6cb8SMadhusudhan Chikkature 724a45c6cb8SMadhusudhan Chikkature static inline 72570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 726a45c6cb8SMadhusudhan Chikkature { 727a45c6cb8SMadhusudhan Chikkature int r = 1; 728a45c6cb8SMadhusudhan Chikkature 729191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 730191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 731a45c6cb8SMadhusudhan Chikkature return r; 732a45c6cb8SMadhusudhan Chikkature } 733a45c6cb8SMadhusudhan Chikkature 734a45c6cb8SMadhusudhan Chikkature static ssize_t 73570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 736a45c6cb8SMadhusudhan Chikkature char *buf) 737a45c6cb8SMadhusudhan Chikkature { 738a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 73970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 740a45c6cb8SMadhusudhan Chikkature 74170a3341aSDenis Karpov return sprintf(buf, "%s\n", 74270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 743a45c6cb8SMadhusudhan Chikkature } 744a45c6cb8SMadhusudhan Chikkature 74570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 746a45c6cb8SMadhusudhan Chikkature 747a45c6cb8SMadhusudhan Chikkature static ssize_t 74870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 749a45c6cb8SMadhusudhan Chikkature char *buf) 750a45c6cb8SMadhusudhan Chikkature { 751a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 75270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 753a45c6cb8SMadhusudhan Chikkature 754191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 755a45c6cb8SMadhusudhan Chikkature } 756a45c6cb8SMadhusudhan Chikkature 75770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 758a45c6cb8SMadhusudhan Chikkature 759a45c6cb8SMadhusudhan Chikkature /* 760a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 761a45c6cb8SMadhusudhan Chikkature */ 762a45c6cb8SMadhusudhan Chikkature static void 76370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 764a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 765a45c6cb8SMadhusudhan Chikkature { 766a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 767a45c6cb8SMadhusudhan Chikkature 7688986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 769a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 770a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 771a45c6cb8SMadhusudhan Chikkature 77293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 773a45c6cb8SMadhusudhan Chikkature 7744a694dc9SAdrian Hunter host->response_busy = 0; 775a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 776a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 777a45c6cb8SMadhusudhan Chikkature resptype = 1; 7784a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7794a694dc9SAdrian Hunter resptype = 3; 7804a694dc9SAdrian Hunter host->response_busy = 1; 7814a694dc9SAdrian Hunter } else 782a45c6cb8SMadhusudhan Chikkature resptype = 2; 783a45c6cb8SMadhusudhan Chikkature } 784a45c6cb8SMadhusudhan Chikkature 785a45c6cb8SMadhusudhan Chikkature /* 786a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 787a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 788a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 789a45c6cb8SMadhusudhan Chikkature */ 790a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 791a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 792a45c6cb8SMadhusudhan Chikkature 793a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 794a45c6cb8SMadhusudhan Chikkature 795a45c6cb8SMadhusudhan Chikkature if (data) { 796a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 797a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 798a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 799a45c6cb8SMadhusudhan Chikkature else 800a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 801a45c6cb8SMadhusudhan Chikkature } 802a45c6cb8SMadhusudhan Chikkature 803a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 804a7e96879SVenkatraman S cmdreg |= DMAE; 805a45c6cb8SMadhusudhan Chikkature 806b417577dSAdrian Hunter host->req_in_progress = 1; 8074dffd7a2SAdrian Hunter 808a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 809a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 810a45c6cb8SMadhusudhan Chikkature } 811a45c6cb8SMadhusudhan Chikkature 8120ccd76d4SJuha Yrjola static int 81370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8140ccd76d4SJuha Yrjola { 8150ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8160ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8170ccd76d4SJuha Yrjola else 8180ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8190ccd76d4SJuha Yrjola } 8200ccd76d4SJuha Yrjola 821c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 822c5c98927SRussell King struct mmc_data *data) 823c5c98927SRussell King { 824c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 825c5c98927SRussell King } 826c5c98927SRussell King 827b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 828b417577dSAdrian Hunter { 829b417577dSAdrian Hunter int dma_ch; 83031463b14SVenkatraman S unsigned long flags; 831b417577dSAdrian Hunter 83231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 833b417577dSAdrian Hunter host->req_in_progress = 0; 834b417577dSAdrian Hunter dma_ch = host->dma_ch; 83531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 836b417577dSAdrian Hunter 837b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 838b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 839b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 840b417577dSAdrian Hunter return; 841b417577dSAdrian Hunter host->mrq = NULL; 842b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 843b417577dSAdrian Hunter } 844b417577dSAdrian Hunter 845a45c6cb8SMadhusudhan Chikkature /* 846a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 847a45c6cb8SMadhusudhan Chikkature */ 848a45c6cb8SMadhusudhan Chikkature static void 84970a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 850a45c6cb8SMadhusudhan Chikkature { 8514a694dc9SAdrian Hunter if (!data) { 8524a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8534a694dc9SAdrian Hunter 85423050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 85523050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 85623050103SAdrian Hunter host->response_busy) { 85723050103SAdrian Hunter host->response_busy = 0; 85823050103SAdrian Hunter return; 85923050103SAdrian Hunter } 86023050103SAdrian Hunter 861b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8624a694dc9SAdrian Hunter return; 8634a694dc9SAdrian Hunter } 8644a694dc9SAdrian Hunter 865a45c6cb8SMadhusudhan Chikkature host->data = NULL; 866a45c6cb8SMadhusudhan Chikkature 867a45c6cb8SMadhusudhan Chikkature if (!data->error) 868a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 869a45c6cb8SMadhusudhan Chikkature else 870a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 871a45c6cb8SMadhusudhan Chikkature 872fe852273SMing Lei if (!data->stop) { 873dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 874fe852273SMing Lei return; 875dba3c29eSBalaji T K } 876fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 877a45c6cb8SMadhusudhan Chikkature } 878a45c6cb8SMadhusudhan Chikkature 879a45c6cb8SMadhusudhan Chikkature /* 880a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 881a45c6cb8SMadhusudhan Chikkature */ 882a45c6cb8SMadhusudhan Chikkature static void 88370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 884a45c6cb8SMadhusudhan Chikkature { 885a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 886a45c6cb8SMadhusudhan Chikkature 887a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 888a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 889a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 890a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 891a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 892a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 893a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 894a45c6cb8SMadhusudhan Chikkature } else { 895a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 896a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 897a45c6cb8SMadhusudhan Chikkature } 898a45c6cb8SMadhusudhan Chikkature } 899b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 900b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 901a45c6cb8SMadhusudhan Chikkature } 902a45c6cb8SMadhusudhan Chikkature 903a45c6cb8SMadhusudhan Chikkature /* 904a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 905a45c6cb8SMadhusudhan Chikkature */ 90670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 907a45c6cb8SMadhusudhan Chikkature { 908b417577dSAdrian Hunter int dma_ch; 90931463b14SVenkatraman S unsigned long flags; 910b417577dSAdrian Hunter 91182788ff5SJarkko Lavinen host->data->error = errno; 912a45c6cb8SMadhusudhan Chikkature 91331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 914b417577dSAdrian Hunter dma_ch = host->dma_ch; 915b417577dSAdrian Hunter host->dma_ch = -1; 91631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 917b417577dSAdrian Hunter 918b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 919c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 920c5c98927SRussell King 921c5c98927SRussell King dmaengine_terminate_all(chan); 922c5c98927SRussell King dma_unmap_sg(chan->device->dev, 923c5c98927SRussell King host->data->sg, host->data->sg_len, 92470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 925c5c98927SRussell King 926053bf34fSPer Forlin host->data->host_cookie = 0; 927a45c6cb8SMadhusudhan Chikkature } 928a45c6cb8SMadhusudhan Chikkature host->data = NULL; 929a45c6cb8SMadhusudhan Chikkature } 930a45c6cb8SMadhusudhan Chikkature 931a45c6cb8SMadhusudhan Chikkature /* 932a45c6cb8SMadhusudhan Chikkature * Readable error output 933a45c6cb8SMadhusudhan Chikkature */ 934a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 935699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 936a45c6cb8SMadhusudhan Chikkature { 937a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 93870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 939699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 940699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 941699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 942699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 943a45c6cb8SMadhusudhan Chikkature }; 944a45c6cb8SMadhusudhan Chikkature char res[256]; 945a45c6cb8SMadhusudhan Chikkature char *buf = res; 946a45c6cb8SMadhusudhan Chikkature int len, i; 947a45c6cb8SMadhusudhan Chikkature 948a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 949a45c6cb8SMadhusudhan Chikkature buf += len; 950a45c6cb8SMadhusudhan Chikkature 95170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 952a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 95370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 954a45c6cb8SMadhusudhan Chikkature buf += len; 955a45c6cb8SMadhusudhan Chikkature } 956a45c6cb8SMadhusudhan Chikkature 9578986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 958a45c6cb8SMadhusudhan Chikkature } 959699b958bSAdrian Hunter #else 960699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 961699b958bSAdrian Hunter u32 status) 962699b958bSAdrian Hunter { 963699b958bSAdrian Hunter } 964a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 965a45c6cb8SMadhusudhan Chikkature 9663ebf74b1SJean Pihet /* 9673ebf74b1SJean Pihet * MMC controller internal state machines reset 9683ebf74b1SJean Pihet * 9693ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9703ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9713ebf74b1SJean Pihet * Can be called from interrupt context 9723ebf74b1SJean Pihet */ 97370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9743ebf74b1SJean Pihet unsigned long bit) 9753ebf74b1SJean Pihet { 9763ebf74b1SJean Pihet unsigned long i = 0; 9773ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 9783ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 9793ebf74b1SJean Pihet 9803ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9813ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9823ebf74b1SJean Pihet 98307ad64b6SMadhusudhan Chikkature /* 98407ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 98507ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 98607ad64b6SMadhusudhan Chikkature */ 98707ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 988b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 98907ad64b6SMadhusudhan Chikkature && (i++ < limit)) 99007ad64b6SMadhusudhan Chikkature cpu_relax(); 99107ad64b6SMadhusudhan Chikkature } 99207ad64b6SMadhusudhan Chikkature i = 0; 99307ad64b6SMadhusudhan Chikkature 9943ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9953ebf74b1SJean Pihet (i++ < limit)) 9963ebf74b1SJean Pihet cpu_relax(); 9973ebf74b1SJean Pihet 9983ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9993ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10003ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10013ebf74b1SJean Pihet __func__); 10023ebf74b1SJean Pihet } 1003a45c6cb8SMadhusudhan Chikkature 100425e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 100525e1897bSBalaji T K int err, int end_cmd) 1006ae4bf788SVenkatraman S { 100725e1897bSBalaji T K if (end_cmd) { 100894d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 100925e1897bSBalaji T K if (host->cmd) 1010ae4bf788SVenkatraman S host->cmd->error = err; 101125e1897bSBalaji T K } 1012ae4bf788SVenkatraman S 1013ae4bf788SVenkatraman S if (host->data) { 1014ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1015ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1016dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1017dc7745bdSBalaji T K host->mrq->cmd->error = err; 1018ae4bf788SVenkatraman S } 1019ae4bf788SVenkatraman S 1020b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1021a45c6cb8SMadhusudhan Chikkature { 1022a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1023b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1024a45c6cb8SMadhusudhan Chikkature 1025a45c6cb8SMadhusudhan Chikkature data = host->data; 10268986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1027a45c6cb8SMadhusudhan Chikkature 1028a7e96879SVenkatraman S if (status & ERR_EN) { 1029699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10304a694dc9SAdrian Hunter 1031a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1032a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1033a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 103425e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1035a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 103625e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 103725e1897bSBalaji T K 1038ae4bf788SVenkatraman S if (host->data || host->response_busy) { 103925e1897bSBalaji T K end_trans = !end_cmd; 1040ae4bf788SVenkatraman S host->response_busy = 0; 1041a45c6cb8SMadhusudhan Chikkature } 1042a45c6cb8SMadhusudhan Chikkature } 1043a45c6cb8SMadhusudhan Chikkature 1044a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 104570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1046a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 104770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1048b417577dSAdrian Hunter } 1049a45c6cb8SMadhusudhan Chikkature 1050b417577dSAdrian Hunter /* 1051b417577dSAdrian Hunter * MMC controller IRQ handler 1052b417577dSAdrian Hunter */ 1053b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1054b417577dSAdrian Hunter { 1055b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1056b417577dSAdrian Hunter int status; 1057b417577dSAdrian Hunter 1058b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10591f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1060b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10611f6b9fa4SVenkatraman S 1062b417577dSAdrian Hunter /* Flush posted write */ 10631f6b9fa4SVenkatraman S OMAP_HSMMC_WRITE(host->base, STAT, status); 1064b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10651f6b9fa4SVenkatraman S } 10664dffd7a2SAdrian Hunter 1067a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1068a45c6cb8SMadhusudhan Chikkature } 1069a45c6cb8SMadhusudhan Chikkature 107070a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1071e13bb300SAdrian Hunter { 1072e13bb300SAdrian Hunter unsigned long i; 1073e13bb300SAdrian Hunter 1074e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1075e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1076e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1077e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1078e13bb300SAdrian Hunter break; 1079e13bb300SAdrian Hunter cpu_relax(); 1080e13bb300SAdrian Hunter } 1081e13bb300SAdrian Hunter } 1082e13bb300SAdrian Hunter 1083a45c6cb8SMadhusudhan Chikkature /* 1084eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1085eb250826SDavid Brownell * 1086eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1087eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1088eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1089a45c6cb8SMadhusudhan Chikkature */ 109070a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1091a45c6cb8SMadhusudhan Chikkature { 1092a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1093a45c6cb8SMadhusudhan Chikkature int ret; 1094a45c6cb8SMadhusudhan Chikkature 1095a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1096fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1097cd03d9a8SRajendra Nayak if (host->dbclk) 109894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1099a45c6cb8SMadhusudhan Chikkature 1100a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1101a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1102a45c6cb8SMadhusudhan Chikkature 1103a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11042bec0893SAdrian Hunter if (!ret) 11052bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11062bec0893SAdrian Hunter vdd); 1107fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1108cd03d9a8SRajendra Nayak if (host->dbclk) 110994c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11102bec0893SAdrian Hunter 1111a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1112a45c6cb8SMadhusudhan Chikkature goto err; 1113a45c6cb8SMadhusudhan Chikkature 1114a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1115a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1116a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1117eb250826SDavid Brownell 1118a45c6cb8SMadhusudhan Chikkature /* 1119a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1120a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 112170a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1122a45c6cb8SMadhusudhan Chikkature * 1123eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1124eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1125eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1126eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1127eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1128eb250826SDavid Brownell * 1129eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1130eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1131eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1132a45c6cb8SMadhusudhan Chikkature */ 1133eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1134a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1135eb250826SDavid Brownell else 1136eb250826SDavid Brownell reg_val |= SDVS30; 1137a45c6cb8SMadhusudhan Chikkature 1138a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1139e13bb300SAdrian Hunter set_sd_bus_power(host); 1140a45c6cb8SMadhusudhan Chikkature 1141a45c6cb8SMadhusudhan Chikkature return 0; 1142a45c6cb8SMadhusudhan Chikkature err: 1143b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1144a45c6cb8SMadhusudhan Chikkature return ret; 1145a45c6cb8SMadhusudhan Chikkature } 1146a45c6cb8SMadhusudhan Chikkature 1147b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1148b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1149b62f6228SAdrian Hunter { 1150b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1151b62f6228SAdrian Hunter return; 1152b62f6228SAdrian Hunter 1153b62f6228SAdrian Hunter host->reqs_blocked = 0; 1154b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1155b62f6228SAdrian Hunter if (host->protect_card) { 11562cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1157b62f6228SAdrian Hunter "card is now accessible\n", 1158b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1159b62f6228SAdrian Hunter host->protect_card = 0; 1160b62f6228SAdrian Hunter } 1161b62f6228SAdrian Hunter } else { 1162b62f6228SAdrian Hunter if (!host->protect_card) { 11632cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1164b62f6228SAdrian Hunter "card is now inaccessible\n", 1165b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1166b62f6228SAdrian Hunter host->protect_card = 1; 1167b62f6228SAdrian Hunter } 1168b62f6228SAdrian Hunter } 1169b62f6228SAdrian Hunter } 1170b62f6228SAdrian Hunter 1171a45c6cb8SMadhusudhan Chikkature /* 11727efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1173a45c6cb8SMadhusudhan Chikkature */ 11747efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1175a45c6cb8SMadhusudhan Chikkature { 11767efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1177249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1178a6b2240dSAdrian Hunter int carddetect; 1179249d0fa9SDavid Brownell 1180a6b2240dSAdrian Hunter if (host->suspended) 11817efab4f3SNeilBrown return IRQ_HANDLED; 1182a45c6cb8SMadhusudhan Chikkature 1183a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1184a6b2240dSAdrian Hunter 1185191d1f1dSDenis Karpov if (slot->card_detect) 1186db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1187b62f6228SAdrian Hunter else { 1188b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1189a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1190b62f6228SAdrian Hunter } 1191a6b2240dSAdrian Hunter 1192cdeebaddSMadhusudhan Chikkature if (carddetect) 1193a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1194cdeebaddSMadhusudhan Chikkature else 1195a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1196a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1197a45c6cb8SMadhusudhan Chikkature } 1198a45c6cb8SMadhusudhan Chikkature 1199c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12000ccd76d4SJuha Yrjola { 1201c5c98927SRussell King struct omap_hsmmc_host *host = param; 1202c5c98927SRussell King struct dma_chan *chan; 1203770d7432SAdrian Hunter struct mmc_data *data; 1204c5c98927SRussell King int req_in_progress; 1205a45c6cb8SMadhusudhan Chikkature 1206c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1207b417577dSAdrian Hunter if (host->dma_ch < 0) { 1208c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1209a45c6cb8SMadhusudhan Chikkature return; 1210b417577dSAdrian Hunter } 1211a45c6cb8SMadhusudhan Chikkature 1212770d7432SAdrian Hunter data = host->mrq->data; 1213c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12149782aff8SPer Forlin if (!data->host_cookie) 1215c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1216c5c98927SRussell King data->sg, data->sg_len, 1217b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1218b417577dSAdrian Hunter 1219b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1220a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1221c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1222b417577dSAdrian Hunter 1223b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1224b417577dSAdrian Hunter if (!req_in_progress) { 1225b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1226b417577dSAdrian Hunter 1227b417577dSAdrian Hunter host->mrq = NULL; 1228b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1229b417577dSAdrian Hunter } 1230a45c6cb8SMadhusudhan Chikkature } 1231a45c6cb8SMadhusudhan Chikkature 12329782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12339782aff8SPer Forlin struct mmc_data *data, 1234c5c98927SRussell King struct omap_hsmmc_next *next, 123526b88520SRussell King struct dma_chan *chan) 12369782aff8SPer Forlin { 12379782aff8SPer Forlin int dma_len; 12389782aff8SPer Forlin 12399782aff8SPer Forlin if (!next && data->host_cookie && 12409782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12412cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12429782aff8SPer Forlin " host->next_data.cookie %d\n", 12439782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12449782aff8SPer Forlin data->host_cookie = 0; 12459782aff8SPer Forlin } 12469782aff8SPer Forlin 12479782aff8SPer Forlin /* Check if next job is already prepared */ 12489782aff8SPer Forlin if (next || 12499782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 125026b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12519782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12529782aff8SPer Forlin 12539782aff8SPer Forlin } else { 12549782aff8SPer Forlin dma_len = host->next_data.dma_len; 12559782aff8SPer Forlin host->next_data.dma_len = 0; 12569782aff8SPer Forlin } 12579782aff8SPer Forlin 12589782aff8SPer Forlin 12599782aff8SPer Forlin if (dma_len == 0) 12609782aff8SPer Forlin return -EINVAL; 12619782aff8SPer Forlin 12629782aff8SPer Forlin if (next) { 12639782aff8SPer Forlin next->dma_len = dma_len; 12649782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12659782aff8SPer Forlin } else 12669782aff8SPer Forlin host->dma_len = dma_len; 12679782aff8SPer Forlin 12689782aff8SPer Forlin return 0; 12699782aff8SPer Forlin } 12709782aff8SPer Forlin 1271a45c6cb8SMadhusudhan Chikkature /* 1272a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1273a45c6cb8SMadhusudhan Chikkature */ 127470a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 127570a3341aSDenis Karpov struct mmc_request *req) 1276a45c6cb8SMadhusudhan Chikkature { 127726b88520SRussell King struct dma_slave_config cfg; 127826b88520SRussell King struct dma_async_tx_descriptor *tx; 127926b88520SRussell King int ret = 0, i; 1280a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1281c5c98927SRussell King struct dma_chan *chan; 1282a45c6cb8SMadhusudhan Chikkature 12830ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1284a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12850ccd76d4SJuha Yrjola struct scatterlist *sgl; 12860ccd76d4SJuha Yrjola 12870ccd76d4SJuha Yrjola sgl = data->sg + i; 12880ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12890ccd76d4SJuha Yrjola return -EINVAL; 12900ccd76d4SJuha Yrjola } 12910ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12920ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12930ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12940ccd76d4SJuha Yrjola */ 12950ccd76d4SJuha Yrjola return -EINVAL; 12960ccd76d4SJuha Yrjola 1297b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1298a45c6cb8SMadhusudhan Chikkature 1299c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1300c5c98927SRussell King 1301c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1302c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1303c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1304c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1305c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1306c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1307c5c98927SRussell King 1308c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13099782aff8SPer Forlin if (ret) 13109782aff8SPer Forlin return ret; 1311a45c6cb8SMadhusudhan Chikkature 131226b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1313c5c98927SRussell King if (ret) 1314c5c98927SRussell King return ret; 1315a45c6cb8SMadhusudhan Chikkature 1316c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1317c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1318c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1319c5c98927SRussell King if (!tx) { 1320c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1321c5c98927SRussell King /* FIXME: cleanup */ 1322c5c98927SRussell King return -1; 1323c5c98927SRussell King } 1324c5c98927SRussell King 1325c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1326c5c98927SRussell King tx->callback_param = host; 1327c5c98927SRussell King 1328c5c98927SRussell King /* Does not fail */ 1329c5c98927SRussell King dmaengine_submit(tx); 1330c5c98927SRussell King 133126b88520SRussell King host->dma_ch = 1; 1332c5c98927SRussell King 1333c5c98927SRussell King dma_async_issue_pending(chan); 1334a45c6cb8SMadhusudhan Chikkature 1335a45c6cb8SMadhusudhan Chikkature return 0; 1336a45c6cb8SMadhusudhan Chikkature } 1337a45c6cb8SMadhusudhan Chikkature 133870a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1339e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1340e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1341a45c6cb8SMadhusudhan Chikkature { 1342a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1343a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1344a45c6cb8SMadhusudhan Chikkature 1345a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1346a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1347a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1348a45c6cb8SMadhusudhan Chikkature clkd = 1; 1349a45c6cb8SMadhusudhan Chikkature 1350a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1351e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1352e2bf08d6SAdrian Hunter timeout += timeout_clks; 1353a45c6cb8SMadhusudhan Chikkature if (timeout) { 1354a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1355a45c6cb8SMadhusudhan Chikkature dto += 1; 1356a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1357a45c6cb8SMadhusudhan Chikkature } 1358a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1359a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1360a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1361a45c6cb8SMadhusudhan Chikkature dto += 1; 1362a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1363a45c6cb8SMadhusudhan Chikkature dto -= 13; 1364a45c6cb8SMadhusudhan Chikkature else 1365a45c6cb8SMadhusudhan Chikkature dto = 0; 1366a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1367a45c6cb8SMadhusudhan Chikkature dto = 14; 1368a45c6cb8SMadhusudhan Chikkature } 1369a45c6cb8SMadhusudhan Chikkature 1370a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1371a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1372a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1373a45c6cb8SMadhusudhan Chikkature } 1374a45c6cb8SMadhusudhan Chikkature 1375a45c6cb8SMadhusudhan Chikkature /* 1376a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1377a45c6cb8SMadhusudhan Chikkature */ 1378a45c6cb8SMadhusudhan Chikkature static int 137970a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1380a45c6cb8SMadhusudhan Chikkature { 1381a45c6cb8SMadhusudhan Chikkature int ret; 1382a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1383a45c6cb8SMadhusudhan Chikkature 1384a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1385a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1386e2bf08d6SAdrian Hunter /* 1387e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1388e2bf08d6SAdrian Hunter * busy signal. 1389e2bf08d6SAdrian Hunter */ 1390e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1391e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1392a45c6cb8SMadhusudhan Chikkature return 0; 1393a45c6cb8SMadhusudhan Chikkature } 1394a45c6cb8SMadhusudhan Chikkature 1395a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1396a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1397e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1398a45c6cb8SMadhusudhan Chikkature 1399a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 140070a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1401a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1402b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1403a45c6cb8SMadhusudhan Chikkature return ret; 1404a45c6cb8SMadhusudhan Chikkature } 1405a45c6cb8SMadhusudhan Chikkature } 1406a45c6cb8SMadhusudhan Chikkature return 0; 1407a45c6cb8SMadhusudhan Chikkature } 1408a45c6cb8SMadhusudhan Chikkature 14099782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14109782aff8SPer Forlin int err) 14119782aff8SPer Forlin { 14129782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14139782aff8SPer Forlin struct mmc_data *data = mrq->data; 14149782aff8SPer Forlin 141526b88520SRussell King if (host->use_dma && data->host_cookie) { 1416c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1417c5c98927SRussell King 141826b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14199782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14209782aff8SPer Forlin data->host_cookie = 0; 14219782aff8SPer Forlin } 14229782aff8SPer Forlin } 14239782aff8SPer Forlin 14249782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14259782aff8SPer Forlin bool is_first_req) 14269782aff8SPer Forlin { 14279782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14289782aff8SPer Forlin 14299782aff8SPer Forlin if (mrq->data->host_cookie) { 14309782aff8SPer Forlin mrq->data->host_cookie = 0; 14319782aff8SPer Forlin return ; 14329782aff8SPer Forlin } 14339782aff8SPer Forlin 1434c5c98927SRussell King if (host->use_dma) { 1435c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1436c5c98927SRussell King 14379782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 143826b88520SRussell King &host->next_data, c)) 14399782aff8SPer Forlin mrq->data->host_cookie = 0; 14409782aff8SPer Forlin } 1441c5c98927SRussell King } 14429782aff8SPer Forlin 1443a45c6cb8SMadhusudhan Chikkature /* 1444a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1445a45c6cb8SMadhusudhan Chikkature */ 144670a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1447a45c6cb8SMadhusudhan Chikkature { 144870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1449a3f406f8SJarkko Lavinen int err; 1450a45c6cb8SMadhusudhan Chikkature 1451b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1452b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1453b62f6228SAdrian Hunter if (host->protect_card) { 1454b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1455b62f6228SAdrian Hunter /* 1456b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1457b62f6228SAdrian Hunter * state by resetting the command and data state 1458b62f6228SAdrian Hunter * machines. 1459b62f6228SAdrian Hunter */ 1460b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1461b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1462b62f6228SAdrian Hunter host->reqs_blocked += 1; 1463b62f6228SAdrian Hunter } 1464b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1465b62f6228SAdrian Hunter if (req->data) 1466b62f6228SAdrian Hunter req->data->error = -EBADF; 1467b417577dSAdrian Hunter req->cmd->retries = 0; 1468b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1469b62f6228SAdrian Hunter return; 1470b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1471b62f6228SAdrian Hunter host->reqs_blocked = 0; 1472a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1473a45c6cb8SMadhusudhan Chikkature host->mrq = req; 147470a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1475a3f406f8SJarkko Lavinen if (err) { 1476a3f406f8SJarkko Lavinen req->cmd->error = err; 1477a3f406f8SJarkko Lavinen if (req->data) 1478a3f406f8SJarkko Lavinen req->data->error = err; 1479a3f406f8SJarkko Lavinen host->mrq = NULL; 1480a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1481a3f406f8SJarkko Lavinen return; 1482a3f406f8SJarkko Lavinen } 1483a3f406f8SJarkko Lavinen 148470a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1485a45c6cb8SMadhusudhan Chikkature } 1486a45c6cb8SMadhusudhan Chikkature 1487a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 148870a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1489a45c6cb8SMadhusudhan Chikkature { 149070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1491a3621465SAdrian Hunter int do_send_init_stream = 0; 1492a45c6cb8SMadhusudhan Chikkature 1493fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14945e2ea617SAdrian Hunter 1495a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1496a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1497a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1498a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1499a3621465SAdrian Hunter 0, 0); 1500a45c6cb8SMadhusudhan Chikkature break; 1501a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1502a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1503a3621465SAdrian Hunter 1, ios->vdd); 1504a45c6cb8SMadhusudhan Chikkature break; 1505a3621465SAdrian Hunter case MMC_POWER_ON: 1506a3621465SAdrian Hunter do_send_init_stream = 1; 1507a3621465SAdrian Hunter break; 1508a3621465SAdrian Hunter } 1509a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1510a45c6cb8SMadhusudhan Chikkature } 1511a45c6cb8SMadhusudhan Chikkature 1512dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1513dd498effSDenis Karpov 15143796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1515a45c6cb8SMadhusudhan Chikkature 15164621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1517eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1518eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1519eb250826SDavid Brownell */ 1520a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15211f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15221f84b71bSRajendra Nayak /* 15231f84b71bSRajendra Nayak * With pbias cell programming missing, this 1524cf5ae40bSTony Lindgren * can't be allowed on MMC1 when booting with device 15251f84b71bSRajendra Nayak * tree. 15261f84b71bSRajendra Nayak */ 1527cf5ae40bSTony Lindgren !host->pbias_disable) { 1528a45c6cb8SMadhusudhan Chikkature /* 1529a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1530a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1531a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1532a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1533a45c6cb8SMadhusudhan Chikkature */ 153470a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1535a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1536a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1537a45c6cb8SMadhusudhan Chikkature } 1538a45c6cb8SMadhusudhan Chikkature } 1539a45c6cb8SMadhusudhan Chikkature 15405934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1541a45c6cb8SMadhusudhan Chikkature 1542a3621465SAdrian Hunter if (do_send_init_stream) 1543a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1544a45c6cb8SMadhusudhan Chikkature 15453796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15465e2ea617SAdrian Hunter 1547fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1548a45c6cb8SMadhusudhan Chikkature } 1549a45c6cb8SMadhusudhan Chikkature 1550a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1551a45c6cb8SMadhusudhan Chikkature { 155270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1553a45c6cb8SMadhusudhan Chikkature 1554191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1555a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1556db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1557a45c6cb8SMadhusudhan Chikkature } 1558a45c6cb8SMadhusudhan Chikkature 1559a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1560a45c6cb8SMadhusudhan Chikkature { 156170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1562a45c6cb8SMadhusudhan Chikkature 1563191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1564a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1565191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1566a45c6cb8SMadhusudhan Chikkature } 1567a45c6cb8SMadhusudhan Chikkature 15684816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15694816858cSGrazvydas Ignotas { 15704816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15714816858cSGrazvydas Ignotas 15724816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15734816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15744816858cSGrazvydas Ignotas } 15754816858cSGrazvydas Ignotas 157670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15771b331e69SKim Kyuwon { 15781b331e69SKim Kyuwon u32 hctl, capa, value; 15791b331e69SKim Kyuwon 15801b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15814621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15821b331e69SKim Kyuwon hctl = SDVS30; 15831b331e69SKim Kyuwon capa = VS30 | VS18; 15841b331e69SKim Kyuwon } else { 15851b331e69SKim Kyuwon hctl = SDVS18; 15861b331e69SKim Kyuwon capa = VS18; 15871b331e69SKim Kyuwon } 15881b331e69SKim Kyuwon 15891b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15901b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15911b331e69SKim Kyuwon 15921b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15931b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15941b331e69SKim Kyuwon 15951b331e69SKim Kyuwon /* Set SD bus power bit */ 1596e13bb300SAdrian Hunter set_sd_bus_power(host); 15971b331e69SKim Kyuwon } 15981b331e69SKim Kyuwon 159970a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1600dd498effSDenis Karpov { 160170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1602dd498effSDenis Karpov 1603fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1604fa4aa2d4SBalaji T K 1605dd498effSDenis Karpov return 0; 1606dd498effSDenis Karpov } 1607dd498effSDenis Karpov 1608907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1609dd498effSDenis Karpov { 161070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1611dd498effSDenis Karpov 1612fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1613fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1614fa4aa2d4SBalaji T K 1615dd498effSDenis Karpov return 0; 1616dd498effSDenis Karpov } 1617dd498effSDenis Karpov 161870a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 161970a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 162070a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16219782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16229782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 162370a3341aSDenis Karpov .request = omap_hsmmc_request, 162470a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1625dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1626dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16274816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1628dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1629dd498effSDenis Karpov }; 1630dd498effSDenis Karpov 1631d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1632d900f712SDenis Karpov 163370a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1634d900f712SDenis Karpov { 1635d900f712SDenis Karpov struct mmc_host *mmc = s->private; 163670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 163711dd62a7SDenis Karpov int context_loss = 0; 163811dd62a7SDenis Karpov 163970a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 164070a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1641d900f712SDenis Karpov 1642907d2e7cSAdrian Hunter seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", 1643907d2e7cSAdrian Hunter mmc->index, host->context_loss, context_loss); 16445e2ea617SAdrian Hunter 16457a8c2cefSBalaji T K if (host->suspended) { 1646dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1647dd498effSDenis Karpov return 0; 1648dd498effSDenis Karpov } 1649dd498effSDenis Karpov 1650fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1651d900f712SDenis Karpov 1652d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1653d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1654d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1655d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1656d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1657d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1658d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1659d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1660d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1661d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1662d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1663d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16645e2ea617SAdrian Hunter 1665fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1666fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1667dd498effSDenis Karpov 1668d900f712SDenis Karpov return 0; 1669d900f712SDenis Karpov } 1670d900f712SDenis Karpov 167170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1672d900f712SDenis Karpov { 167370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1674d900f712SDenis Karpov } 1675d900f712SDenis Karpov 1676d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 167770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1678d900f712SDenis Karpov .read = seq_read, 1679d900f712SDenis Karpov .llseek = seq_lseek, 1680d900f712SDenis Karpov .release = single_release, 1681d900f712SDenis Karpov }; 1682d900f712SDenis Karpov 168370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1684d900f712SDenis Karpov { 1685d900f712SDenis Karpov if (mmc->debugfs_root) 1686d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1687d900f712SDenis Karpov mmc, &mmc_regs_fops); 1688d900f712SDenis Karpov } 1689d900f712SDenis Karpov 1690d900f712SDenis Karpov #else 1691d900f712SDenis Karpov 169270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1693d900f712SDenis Karpov { 1694d900f712SDenis Karpov } 1695d900f712SDenis Karpov 1696d900f712SDenis Karpov #endif 1697d900f712SDenis Karpov 169846856a68SRajendra Nayak #ifdef CONFIG_OF 169946856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 170046856a68SRajendra Nayak 170146856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 170246856a68SRajendra Nayak { 170346856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 170446856a68SRajendra Nayak }, 170546856a68SRajendra Nayak { 170646856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 170746856a68SRajendra Nayak }, 170846856a68SRajendra Nayak { 170946856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 171046856a68SRajendra Nayak .data = &omap4_reg_offset, 171146856a68SRajendra Nayak }, 171246856a68SRajendra Nayak {}, 1713b6d085f6SChris Ball }; 171446856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 171546856a68SRajendra Nayak 171646856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 171746856a68SRajendra Nayak { 171846856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 171946856a68SRajendra Nayak struct device_node *np = dev->of_node; 1720d8714e87SDaniel Mack u32 bus_width, max_freq; 1721dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1722dc642c28SJan Luebbe 1723dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1724dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1725dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1726dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 172746856a68SRajendra Nayak 172846856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 172946856a68SRajendra Nayak if (!pdata) 173046856a68SRajendra Nayak return NULL; /* out of memory */ 173146856a68SRajendra Nayak 173246856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 173346856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 173446856a68SRajendra Nayak 173546856a68SRajendra Nayak /* This driver only supports 1 slot */ 173646856a68SRajendra Nayak pdata->nr_slots = 1; 1737dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1738dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 173946856a68SRajendra Nayak 174046856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 174146856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 174246856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 174346856a68SRajendra Nayak } 17447f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 174546856a68SRajendra Nayak if (bus_width == 4) 174646856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 174746856a68SRajendra Nayak else if (bus_width == 8) 174846856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 174946856a68SRajendra Nayak 175046856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 175146856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 175246856a68SRajendra Nayak 1753d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1754d8714e87SDaniel Mack pdata->max_freq = max_freq; 1755d8714e87SDaniel Mack 1756cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1757cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1758cd587096SHebbar, Gururaja 175946856a68SRajendra Nayak return pdata; 176046856a68SRajendra Nayak } 176146856a68SRajendra Nayak #else 176246856a68SRajendra Nayak static inline struct omap_mmc_platform_data 176346856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 176446856a68SRajendra Nayak { 176546856a68SRajendra Nayak return NULL; 176646856a68SRajendra Nayak } 176746856a68SRajendra Nayak #endif 176846856a68SRajendra Nayak 1769c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1770a45c6cb8SMadhusudhan Chikkature { 1771a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1772a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 177370a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1774a45c6cb8SMadhusudhan Chikkature struct resource *res; 1775db0fefc5SAdrian Hunter int ret, irq; 177646856a68SRajendra Nayak const struct of_device_id *match; 177726b88520SRussell King dma_cap_mask_t mask; 177826b88520SRussell King unsigned tx_req, rx_req; 177946b76035SDaniel Mack struct pinctrl *pinctrl; 178046856a68SRajendra Nayak 178146856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 178246856a68SRajendra Nayak if (match) { 178346856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1784dc642c28SJan Luebbe 1785dc642c28SJan Luebbe if (IS_ERR(pdata)) 1786dc642c28SJan Luebbe return PTR_ERR(pdata); 1787dc642c28SJan Luebbe 178846856a68SRajendra Nayak if (match->data) { 1789efc9b736SUwe Kleine-König const u16 *offsetp = match->data; 179046856a68SRajendra Nayak pdata->reg_offset = *offsetp; 179146856a68SRajendra Nayak } 179246856a68SRajendra Nayak } 1793a45c6cb8SMadhusudhan Chikkature 1794a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1795a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1796a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1797a45c6cb8SMadhusudhan Chikkature } 1798a45c6cb8SMadhusudhan Chikkature 1799a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1800a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1801a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1802a45c6cb8SMadhusudhan Chikkature } 1803a45c6cb8SMadhusudhan Chikkature 1804a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1805a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1806a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1807a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1808a45c6cb8SMadhusudhan Chikkature 1809984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1810a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1811a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1812a45c6cb8SMadhusudhan Chikkature 1813db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1814db0fefc5SAdrian Hunter if (ret) 1815db0fefc5SAdrian Hunter goto err; 1816db0fefc5SAdrian Hunter 181770a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1818a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1819a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1820db0fefc5SAdrian Hunter goto err_alloc; 1821a45c6cb8SMadhusudhan Chikkature } 1822a45c6cb8SMadhusudhan Chikkature 1823a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1824a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1825a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1826a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1827a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1828a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1829a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1830a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1831fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1832a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18336da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18349782aff8SPer Forlin host->next_data.cookie = 1; 1835a45c6cb8SMadhusudhan Chikkature 1836a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1837a45c6cb8SMadhusudhan Chikkature 183870a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1839dd498effSDenis Karpov 1840e0eb2424SAdrian Hunter /* 1841e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1842e0eb2424SAdrian Hunter * no off state. 1843e0eb2424SAdrian Hunter */ 1844e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1845e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1846e0eb2424SAdrian Hunter 18476b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1848d418ed87SDaniel Mack 1849d418ed87SDaniel Mack if (pdata->max_freq > 0) 1850d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1851d418ed87SDaniel Mack else 18526b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1853a45c6cb8SMadhusudhan Chikkature 18544dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1855a45c6cb8SMadhusudhan Chikkature 18566f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1857a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1858a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1859a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1860a45c6cb8SMadhusudhan Chikkature goto err1; 1861a45c6cb8SMadhusudhan Chikkature } 1862a45c6cb8SMadhusudhan Chikkature 18639b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18649b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18659b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18669b68256cSPaul Walmsley } 1867dd498effSDenis Karpov 1868fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1869fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1870fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1871fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1872a45c6cb8SMadhusudhan Chikkature 187392a3aebfSBalaji T K omap_hsmmc_context_save(host); 187492a3aebfSBalaji T K 1875cf5ae40bSTony Lindgren /* This can be removed once we support PBIAS with DT */ 1876cf5ae40bSTony Lindgren if (host->dev->of_node && host->mapbase == 0x4809c000) 1877cf5ae40bSTony Lindgren host->pbias_disable = 1; 1878cf5ae40bSTony Lindgren 1879a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1880a45c6cb8SMadhusudhan Chikkature /* 1881a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1882a45c6cb8SMadhusudhan Chikkature */ 1883cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1884cd03d9a8SRajendra Nayak host->dbclk = NULL; 188594c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1886cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1887cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1888cd03d9a8SRajendra Nayak host->dbclk = NULL; 18892bec0893SAdrian Hunter } 1890a45c6cb8SMadhusudhan Chikkature 18910ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18920ccd76d4SJuha Yrjola * as we want. */ 1893a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18940ccd76d4SJuha Yrjola 1895a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1896a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1897a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1898a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1899a45c6cb8SMadhusudhan Chikkature 190013189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 190193caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1902a45c6cb8SMadhusudhan Chikkature 19033a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19043a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1905a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1906a45c6cb8SMadhusudhan Chikkature 1907191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 190823d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 190923d99bb9SAdrian Hunter 19106fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19116fdc75deSEliad Peller 191270a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1913a45c6cb8SMadhusudhan Chikkature 1914b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1915b7bf773bSBalaji T K if (!res) { 1916b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19179c17d08cSKevin Hilman ret = -ENXIO; 1918f3e2f1ddSGrazvydas Ignotas goto err_irq; 1919a45c6cb8SMadhusudhan Chikkature } 192026b88520SRussell King tx_req = res->start; 1921b7bf773bSBalaji T K 1922b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1923b7bf773bSBalaji T K if (!res) { 1924b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19259c17d08cSKevin Hilman ret = -ENXIO; 1926b7bf773bSBalaji T K goto err_irq; 1927b7bf773bSBalaji T K } 192826b88520SRussell King rx_req = res->start; 1929c5c98927SRussell King 1930c5c98927SRussell King dma_cap_zero(mask); 1931c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 193226b88520SRussell King 1933d272fbf0SMatt Porter host->rx_chan = 1934d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1935d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1936d272fbf0SMatt Porter 1937c5c98927SRussell King if (!host->rx_chan) { 193826b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 193904e8c7bcSKevin Hilman ret = -ENXIO; 194026b88520SRussell King goto err_irq; 1941c5c98927SRussell King } 194226b88520SRussell King 1943d272fbf0SMatt Porter host->tx_chan = 1944d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1945d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1946d272fbf0SMatt Porter 1947c5c98927SRussell King if (!host->tx_chan) { 194826b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 194904e8c7bcSKevin Hilman ret = -ENXIO; 195026b88520SRussell King goto err_irq; 1951c5c98927SRussell King } 1952a45c6cb8SMadhusudhan Chikkature 1953a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1954d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1955a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1956a45c6cb8SMadhusudhan Chikkature if (ret) { 1957b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1958a45c6cb8SMadhusudhan Chikkature goto err_irq; 1959a45c6cb8SMadhusudhan Chikkature } 1960a45c6cb8SMadhusudhan Chikkature 1961a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1962a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1963b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 196470a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1965a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1966a45c6cb8SMadhusudhan Chikkature } 1967a45c6cb8SMadhusudhan Chikkature } 1968db0fefc5SAdrian Hunter 1969b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1970db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1971db0fefc5SAdrian Hunter if (ret) 1972db0fefc5SAdrian Hunter goto err_reg; 1973db0fefc5SAdrian Hunter host->use_reg = 1; 1974db0fefc5SAdrian Hunter } 1975db0fefc5SAdrian Hunter 1976b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1977a45c6cb8SMadhusudhan Chikkature 1978a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1979e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19807efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19817efab4f3SNeilBrown NULL, 19827efab4f3SNeilBrown omap_hsmmc_detect, 1983db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1984a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1985a45c6cb8SMadhusudhan Chikkature if (ret) { 1986b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 1987a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1988a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1989a45c6cb8SMadhusudhan Chikkature } 199072f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 199172f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1992a45c6cb8SMadhusudhan Chikkature } 1993a45c6cb8SMadhusudhan Chikkature 1994b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1995a45c6cb8SMadhusudhan Chikkature 199646b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 199746b76035SDaniel Mack if (IS_ERR(pinctrl)) 199846b76035SDaniel Mack dev_warn(&pdev->dev, 199946b76035SDaniel Mack "pins are not configured from the driver\n"); 200046b76035SDaniel Mack 2001b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2002b62f6228SAdrian Hunter 2003a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2004a45c6cb8SMadhusudhan Chikkature 2005191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2006a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2007a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2008a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2009a45c6cb8SMadhusudhan Chikkature } 2010191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2011a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2012a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2013a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2014db0fefc5SAdrian Hunter goto err_slot_name; 2015a45c6cb8SMadhusudhan Chikkature } 2016a45c6cb8SMadhusudhan Chikkature 201770a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2018fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2019fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2020d900f712SDenis Karpov 2021a45c6cb8SMadhusudhan Chikkature return 0; 2022a45c6cb8SMadhusudhan Chikkature 2023a45c6cb8SMadhusudhan Chikkature err_slot_name: 2024a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2025a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2026db0fefc5SAdrian Hunter err_irq_cd: 2027db0fefc5SAdrian Hunter if (host->use_reg) 2028db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2029db0fefc5SAdrian Hunter err_reg: 2030db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2031db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2032a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2033a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2034a45c6cb8SMadhusudhan Chikkature err_irq: 2035c5c98927SRussell King if (host->tx_chan) 2036c5c98927SRussell King dma_release_channel(host->tx_chan); 2037c5c98927SRussell King if (host->rx_chan) 2038c5c98927SRussell King dma_release_channel(host->rx_chan); 2039d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 204037f6190dSTony Lindgren pm_runtime_disable(host->dev); 2041a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2042cd03d9a8SRajendra Nayak if (host->dbclk) { 204394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2044a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2045a45c6cb8SMadhusudhan Chikkature } 2046a45c6cb8SMadhusudhan Chikkature err1: 2047a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2048db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 2049a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2050db0fefc5SAdrian Hunter err_alloc: 2051db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2052db0fefc5SAdrian Hunter err: 205348b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 205448b332f9SRussell King if (res) 2055984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2056a45c6cb8SMadhusudhan Chikkature return ret; 2057a45c6cb8SMadhusudhan Chikkature } 2058a45c6cb8SMadhusudhan Chikkature 20596e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2060a45c6cb8SMadhusudhan Chikkature { 206170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2062a45c6cb8SMadhusudhan Chikkature struct resource *res; 2063a45c6cb8SMadhusudhan Chikkature 2064fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2065a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2066db0fefc5SAdrian Hunter if (host->use_reg) 2067db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2068a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2069a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2070a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2071a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2072a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2073a45c6cb8SMadhusudhan Chikkature 2074c5c98927SRussell King if (host->tx_chan) 2075c5c98927SRussell King dma_release_channel(host->tx_chan); 2076c5c98927SRussell King if (host->rx_chan) 2077c5c98927SRussell King dma_release_channel(host->rx_chan); 2078c5c98927SRussell King 2079fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2080fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2081a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2082cd03d9a8SRajendra Nayak if (host->dbclk) { 208394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2084a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2085a45c6cb8SMadhusudhan Chikkature } 2086a45c6cb8SMadhusudhan Chikkature 20879ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2088a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 20899d1f0286SBalaji T K mmc_free_host(host->mmc); 2090a45c6cb8SMadhusudhan Chikkature 2091a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2092a45c6cb8SMadhusudhan Chikkature if (res) 2093984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2094a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2095a45c6cb8SMadhusudhan Chikkature 2096a45c6cb8SMadhusudhan Chikkature return 0; 2097a45c6cb8SMadhusudhan Chikkature } 2098a45c6cb8SMadhusudhan Chikkature 2099a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2100a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2101a48ce884SFelipe Balbi { 2102a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2103a48ce884SFelipe Balbi 2104a48ce884SFelipe Balbi if (host->pdata->suspend) 2105a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2106a48ce884SFelipe Balbi 2107a48ce884SFelipe Balbi return 0; 2108a48ce884SFelipe Balbi } 2109a48ce884SFelipe Balbi 2110a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2111a48ce884SFelipe Balbi { 2112a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2113a48ce884SFelipe Balbi 2114a48ce884SFelipe Balbi if (host->pdata->resume) 2115a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2116a48ce884SFelipe Balbi 2117a48ce884SFelipe Balbi } 2118a48ce884SFelipe Balbi 2119a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2120a45c6cb8SMadhusudhan Chikkature { 2121a45c6cb8SMadhusudhan Chikkature int ret = 0; 2122927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2123927ce944SFelipe Balbi 2124927ce944SFelipe Balbi if (!host) 2125927ce944SFelipe Balbi return 0; 2126a45c6cb8SMadhusudhan Chikkature 2127a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2128a45c6cb8SMadhusudhan Chikkature return 0; 2129a45c6cb8SMadhusudhan Chikkature 2130fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2131a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 21321a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2133fa4aa2d4SBalaji T K 213431f9d463SEliad Peller if (ret) { 2135a6b2240dSAdrian Hunter host->suspended = 0; 213631f9d463SEliad Peller goto err; 2137a6b2240dSAdrian Hunter } 213831f9d463SEliad Peller 213931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 214031f9d463SEliad Peller omap_hsmmc_disable_irq(host); 214131f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 214231f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 214331f9d463SEliad Peller } 2144927ce944SFelipe Balbi 2145cd03d9a8SRajendra Nayak if (host->dbclk) 214694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 214731f9d463SEliad Peller err: 2148fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2149a45c6cb8SMadhusudhan Chikkature return ret; 2150a45c6cb8SMadhusudhan Chikkature } 2151a45c6cb8SMadhusudhan Chikkature 2152a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2153a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2154a45c6cb8SMadhusudhan Chikkature { 2155a45c6cb8SMadhusudhan Chikkature int ret = 0; 2156927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2157927ce944SFelipe Balbi 2158927ce944SFelipe Balbi if (!host) 2159927ce944SFelipe Balbi return 0; 2160a45c6cb8SMadhusudhan Chikkature 2161a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2162a45c6cb8SMadhusudhan Chikkature return 0; 2163a45c6cb8SMadhusudhan Chikkature 2164fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 216511dd62a7SDenis Karpov 2166cd03d9a8SRajendra Nayak if (host->dbclk) 216794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21682bec0893SAdrian Hunter 216931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 217070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21711b331e69SKim Kyuwon 2172b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2173b62f6228SAdrian Hunter 2174a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2175a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2176a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2177a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2178fa4aa2d4SBalaji T K 2179fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2180fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2181a45c6cb8SMadhusudhan Chikkature 2182a45c6cb8SMadhusudhan Chikkature return ret; 2183a45c6cb8SMadhusudhan Chikkature 2184a45c6cb8SMadhusudhan Chikkature } 2185a45c6cb8SMadhusudhan Chikkature 2186a45c6cb8SMadhusudhan Chikkature #else 2187a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2188a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 218970a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 219070a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2191a45c6cb8SMadhusudhan Chikkature #endif 2192a45c6cb8SMadhusudhan Chikkature 2193fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2194fa4aa2d4SBalaji T K { 2195fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2196fa4aa2d4SBalaji T K 2197fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2198fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2199927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2200fa4aa2d4SBalaji T K 2201fa4aa2d4SBalaji T K return 0; 2202fa4aa2d4SBalaji T K } 2203fa4aa2d4SBalaji T K 2204fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2205fa4aa2d4SBalaji T K { 2206fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2207fa4aa2d4SBalaji T K 2208fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2209fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2210927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2211fa4aa2d4SBalaji T K 2212fa4aa2d4SBalaji T K return 0; 2213fa4aa2d4SBalaji T K } 2214fa4aa2d4SBalaji T K 2215a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 221670a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 221770a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2218a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2219a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2220fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2221fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2222a791daa1SKevin Hilman }; 2223a791daa1SKevin Hilman 2224a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2225efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22260433c143SBill Pemberton .remove = omap_hsmmc_remove, 2227a45c6cb8SMadhusudhan Chikkature .driver = { 2228a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2229a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2230a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 223146856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2232a45c6cb8SMadhusudhan Chikkature }, 2233a45c6cb8SMadhusudhan Chikkature }; 2234a45c6cb8SMadhusudhan Chikkature 2235b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2236a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2237a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2238a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2239a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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