1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22d900f712SDenis Karpov #include <linux/seq_file.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 2946856a68SRajendra Nayak #include <linux/of.h> 3046856a68SRajendra Nayak #include <linux/of_gpio.h> 3146856a68SRajendra Nayak #include <linux/of_device.h> 32a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3313189e78SJarkko Lavinen #include <linux/mmc/core.h> 3493caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 37db0fefc5SAdrian Hunter #include <linux/gpio.h> 38db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 39fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 40ce491cf8STony Lindgren #include <plat/dma.h> 41a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 42ce491cf8STony Lindgren #include <plat/board.h> 43ce491cf8STony Lindgren #include <plat/mmc.h> 44ce491cf8STony Lindgren #include <plat/cpu.h> 45a45c6cb8SMadhusudhan Chikkature 46a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 4811dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 64a45c6cb8SMadhusudhan Chikkature 65a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 66a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 67a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 68a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 69eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 701b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 71a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 72a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 73a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 74a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 75a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 76a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 77a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 78a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 79a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 80a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 81a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 82a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 83a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 84ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 85ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8693caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 87a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 88dba3c29eSBalaji T K #define ACEN_ACMD12 (1 << 2) 89a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 90a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 91a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 92a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 94a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9503b5d924SBalaji T K #define DDR (1 << 19) 9673153010SJarkko Lavinen #define DW8 (1 << 5) 97a45c6cb8SMadhusudhan Chikkature #define CC 0x1 98a45c6cb8SMadhusudhan Chikkature #define TC 0x02 99a45c6cb8SMadhusudhan Chikkature #define OD 0x1 100a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 101a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 102a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 103a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 104a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 105a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 106a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 107a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 108a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 109a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 110a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11111dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 11211dd62a7SDenis Karpov #define RESETDONE (1 << 0) 113a45c6cb8SMadhusudhan Chikkature 114fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 115a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1166b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1176b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1180005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 119a45c6cb8SMadhusudhan Chikkature 120dba3c29eSBalaji T K #define AUTO_CMD12 (1 << 0) /* Auto CMD12 support */ 121a45c6cb8SMadhusudhan Chikkature /* 122a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 123a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 124a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 125a45c6cb8SMadhusudhan Chikkature */ 126a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 127a45c6cb8SMadhusudhan Chikkature 128a45c6cb8SMadhusudhan Chikkature /* 129a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 130a45c6cb8SMadhusudhan Chikkature */ 131a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 132a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 133a45c6cb8SMadhusudhan Chikkature 134a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 135a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 136a45c6cb8SMadhusudhan Chikkature 1379782aff8SPer Forlin struct omap_hsmmc_next { 1389782aff8SPer Forlin unsigned int dma_len; 1399782aff8SPer Forlin s32 cookie; 1409782aff8SPer Forlin }; 1419782aff8SPer Forlin 14270a3341aSDenis Karpov struct omap_hsmmc_host { 143a45c6cb8SMadhusudhan Chikkature struct device *dev; 144a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 145a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 146a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 147a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 148a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 149a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 150db0fefc5SAdrian Hunter /* 151db0fefc5SAdrian Hunter * vcc == configured supply 152db0fefc5SAdrian Hunter * vcc_aux == optional 153db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 154db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 155db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 156db0fefc5SAdrian Hunter */ 157db0fefc5SAdrian Hunter struct regulator *vcc; 158db0fefc5SAdrian Hunter struct regulator *vcc_aux; 159a45c6cb8SMadhusudhan Chikkature void __iomem *base; 160a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1614dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 162a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1630ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 164a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 165a3621465SAdrian Hunter unsigned char power_mode; 166a45c6cb8SMadhusudhan Chikkature u32 *buffer; 167a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 168a45c6cb8SMadhusudhan Chikkature int suspended; 169a45c6cb8SMadhusudhan Chikkature int irq; 170a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 171f3e2f1ddSGrazvydas Ignotas int dma_line_tx, dma_line_rx; 172a45c6cb8SMadhusudhan Chikkature int slot_id; 1734a694dc9SAdrian Hunter int response_busy; 17411dd62a7SDenis Karpov int context_loss; 175623821f7SAdrian Hunter int vdd; 176b62f6228SAdrian Hunter int protect_card; 177b62f6228SAdrian Hunter int reqs_blocked; 178db0fefc5SAdrian Hunter int use_reg; 179b417577dSAdrian Hunter int req_in_progress; 180dba3c29eSBalaji T K unsigned int flags; 1819782aff8SPer Forlin struct omap_hsmmc_next next_data; 18211dd62a7SDenis Karpov 183a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 184a45c6cb8SMadhusudhan Chikkature }; 185a45c6cb8SMadhusudhan Chikkature 186db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 187db0fefc5SAdrian Hunter { 188db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 189db0fefc5SAdrian Hunter 190db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 191db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 192db0fefc5SAdrian Hunter } 193db0fefc5SAdrian Hunter 194db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 195db0fefc5SAdrian Hunter { 196db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 197db0fefc5SAdrian Hunter 198db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 199db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 200db0fefc5SAdrian Hunter } 201db0fefc5SAdrian Hunter 202db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 203db0fefc5SAdrian Hunter { 204db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 205db0fefc5SAdrian Hunter 206db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 207db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 208db0fefc5SAdrian Hunter } 209db0fefc5SAdrian Hunter 210db0fefc5SAdrian Hunter #ifdef CONFIG_PM 211db0fefc5SAdrian Hunter 212db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 213db0fefc5SAdrian Hunter { 214db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 215db0fefc5SAdrian Hunter 216db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 217db0fefc5SAdrian Hunter return 0; 218db0fefc5SAdrian Hunter } 219db0fefc5SAdrian Hunter 220db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 221db0fefc5SAdrian Hunter { 222db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 223db0fefc5SAdrian Hunter 224db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 225db0fefc5SAdrian Hunter return 0; 226db0fefc5SAdrian Hunter } 227db0fefc5SAdrian Hunter 228db0fefc5SAdrian Hunter #else 229db0fefc5SAdrian Hunter 230db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 231db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 232db0fefc5SAdrian Hunter 233db0fefc5SAdrian Hunter #endif 234db0fefc5SAdrian Hunter 235b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 236b702b106SAdrian Hunter 23769b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 238db0fefc5SAdrian Hunter int vdd) 239db0fefc5SAdrian Hunter { 240db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 241db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 242db0fefc5SAdrian Hunter int ret = 0; 243db0fefc5SAdrian Hunter 244db0fefc5SAdrian Hunter /* 245db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 246db0fefc5SAdrian Hunter * voltage always-on regulator. 247db0fefc5SAdrian Hunter */ 248db0fefc5SAdrian Hunter if (!host->vcc) 249db0fefc5SAdrian Hunter return 0; 2501f84b71bSRajendra Nayak /* 2511f84b71bSRajendra Nayak * With DT, never turn OFF the regulator. This is because 2521f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2531f84b71bSRajendra Nayak * booting with Device tree 2541f84b71bSRajendra Nayak */ 2554d048f91SRajendra Nayak if (dev->of_node && !vdd) 2561f84b71bSRajendra Nayak return 0; 257db0fefc5SAdrian Hunter 258db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 259db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 260db0fefc5SAdrian Hunter 261db0fefc5SAdrian Hunter /* 262db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 263db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 264db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 265db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 266db0fefc5SAdrian Hunter * 267db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 268db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 269db0fefc5SAdrian Hunter * 270db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 271db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 272db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 273db0fefc5SAdrian Hunter */ 274db0fefc5SAdrian Hunter if (power_on) { 27599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 276db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 277db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 278db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 279db0fefc5SAdrian Hunter if (ret < 0) 28099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 28199fc5131SLinus Walleij host->vcc, 0); 282db0fefc5SAdrian Hunter } 283db0fefc5SAdrian Hunter } else { 28499fc5131SLinus Walleij /* Shut down the rail */ 2856da20c89SAdrian Hunter if (host->vcc_aux) 286db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 28799fc5131SLinus Walleij if (!ret) { 28899fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 28999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 29099fc5131SLinus Walleij host->vcc, 0); 29199fc5131SLinus Walleij } 292db0fefc5SAdrian Hunter } 293db0fefc5SAdrian Hunter 294db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 295db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 296db0fefc5SAdrian Hunter 297db0fefc5SAdrian Hunter return ret; 298db0fefc5SAdrian Hunter } 299db0fefc5SAdrian Hunter 300db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 301db0fefc5SAdrian Hunter { 302db0fefc5SAdrian Hunter struct regulator *reg; 30364be9782Skishore kadiyala int ocr_value = 0; 304db0fefc5SAdrian Hunter 30569b07eceSRajendra Nayak mmc_slot(host).set_power = omap_hsmmc_set_power; 306db0fefc5SAdrian Hunter 307db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 308db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 309db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 310db0fefc5SAdrian Hunter } else { 311db0fefc5SAdrian Hunter host->vcc = reg; 31264be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 31364be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 31464be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 31564be9782Skishore kadiyala } else { 31664be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3172cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 318e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 31964be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 32064be9782Skishore kadiyala return -EINVAL; 32164be9782Skishore kadiyala } 32264be9782Skishore kadiyala } 323db0fefc5SAdrian Hunter 324db0fefc5SAdrian Hunter /* Allow an aux regulator */ 325db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 326db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 327db0fefc5SAdrian Hunter 328b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 329b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 330b1c1df7aSBalaji T K return 0; 331db0fefc5SAdrian Hunter /* 332db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 333db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 334db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 335db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 336db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 337db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 338db0fefc5SAdrian Hunter */ 339e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 340e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 341e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 342e840ce13SAdrian Hunter 343e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 344e840ce13SAdrian Hunter 1, vdd); 345e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 346e840ce13SAdrian Hunter 0, 0); 347db0fefc5SAdrian Hunter } 348db0fefc5SAdrian Hunter } 349db0fefc5SAdrian Hunter 350db0fefc5SAdrian Hunter return 0; 351db0fefc5SAdrian Hunter } 352db0fefc5SAdrian Hunter 353db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 354db0fefc5SAdrian Hunter { 355db0fefc5SAdrian Hunter regulator_put(host->vcc); 356db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 357db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 358db0fefc5SAdrian Hunter } 359db0fefc5SAdrian Hunter 360b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 361b702b106SAdrian Hunter { 362b702b106SAdrian Hunter return 1; 363b702b106SAdrian Hunter } 364b702b106SAdrian Hunter 365b702b106SAdrian Hunter #else 366b702b106SAdrian Hunter 367b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 368b702b106SAdrian Hunter { 369b702b106SAdrian Hunter return -EINVAL; 370b702b106SAdrian Hunter } 371b702b106SAdrian Hunter 372b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 373b702b106SAdrian Hunter { 374b702b106SAdrian Hunter } 375b702b106SAdrian Hunter 376b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 377b702b106SAdrian Hunter { 378b702b106SAdrian Hunter return 0; 379b702b106SAdrian Hunter } 380b702b106SAdrian Hunter 381b702b106SAdrian Hunter #endif 382b702b106SAdrian Hunter 383b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 384b702b106SAdrian Hunter { 385b702b106SAdrian Hunter int ret; 386b702b106SAdrian Hunter 387b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 388b702b106SAdrian Hunter if (pdata->slots[0].cover) 389b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 390b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 391b702b106SAdrian Hunter else 392b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 393b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 394b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 395b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 396b702b106SAdrian Hunter if (ret) 397b702b106SAdrian Hunter return ret; 398b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 399b702b106SAdrian Hunter if (ret) 400b702b106SAdrian Hunter goto err_free_sp; 401b702b106SAdrian Hunter } else 402b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 403b702b106SAdrian Hunter 404b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 405b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 406b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 407b702b106SAdrian Hunter if (ret) 408b702b106SAdrian Hunter goto err_free_cd; 409b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 410b702b106SAdrian Hunter if (ret) 411b702b106SAdrian Hunter goto err_free_wp; 412b702b106SAdrian Hunter } else 413b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 414b702b106SAdrian Hunter 415b702b106SAdrian Hunter return 0; 416b702b106SAdrian Hunter 417b702b106SAdrian Hunter err_free_wp: 418b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 419b702b106SAdrian Hunter err_free_cd: 420b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 421b702b106SAdrian Hunter err_free_sp: 422b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 423b702b106SAdrian Hunter return ret; 424b702b106SAdrian Hunter } 425b702b106SAdrian Hunter 426b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 427b702b106SAdrian Hunter { 428b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 429b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 430b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 431b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 432b702b106SAdrian Hunter } 433b702b106SAdrian Hunter 434a45c6cb8SMadhusudhan Chikkature /* 435e0c7f99bSAndy Shevchenko * Start clock to the card 436e0c7f99bSAndy Shevchenko */ 437e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 438e0c7f99bSAndy Shevchenko { 439e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 440e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 441e0c7f99bSAndy Shevchenko } 442e0c7f99bSAndy Shevchenko 443e0c7f99bSAndy Shevchenko /* 444a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 445a45c6cb8SMadhusudhan Chikkature */ 44670a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 447a45c6cb8SMadhusudhan Chikkature { 448a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 449a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 450a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 451a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 452a45c6cb8SMadhusudhan Chikkature } 453a45c6cb8SMadhusudhan Chikkature 45493caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 45593caf8e6SAdrian Hunter struct mmc_command *cmd) 456b417577dSAdrian Hunter { 457b417577dSAdrian Hunter unsigned int irq_mask; 458b417577dSAdrian Hunter 459b417577dSAdrian Hunter if (host->use_dma) 460b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 461b417577dSAdrian Hunter else 462b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 463b417577dSAdrian Hunter 46493caf8e6SAdrian Hunter /* Disable timeout for erases */ 46593caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 46693caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 46793caf8e6SAdrian Hunter 468b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 469b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 470b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 471b417577dSAdrian Hunter } 472b417577dSAdrian Hunter 473b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 474b417577dSAdrian Hunter { 475b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 476b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 477b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 478b417577dSAdrian Hunter } 479b417577dSAdrian Hunter 480ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 481d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 482ac330f44SAndy Shevchenko { 483ac330f44SAndy Shevchenko u16 dsor = 0; 484ac330f44SAndy Shevchenko 485ac330f44SAndy Shevchenko if (ios->clock) { 486d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 487ac330f44SAndy Shevchenko if (dsor > 250) 488ac330f44SAndy Shevchenko dsor = 250; 489ac330f44SAndy Shevchenko } 490ac330f44SAndy Shevchenko 491ac330f44SAndy Shevchenko return dsor; 492ac330f44SAndy Shevchenko } 493ac330f44SAndy Shevchenko 4945934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 4955934df2fSAndy Shevchenko { 4965934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 4975934df2fSAndy Shevchenko unsigned long regval; 4985934df2fSAndy Shevchenko unsigned long timeout; 4995934df2fSAndy Shevchenko 5005934df2fSAndy Shevchenko dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5015934df2fSAndy Shevchenko 5025934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5035934df2fSAndy Shevchenko 5045934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5055934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 506d83b6e03SBalaji TK regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); 5075934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5085934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5095934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5105934df2fSAndy Shevchenko 5115934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5125934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5135934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5145934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5155934df2fSAndy Shevchenko cpu_relax(); 5165934df2fSAndy Shevchenko 5175934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5185934df2fSAndy Shevchenko } 5195934df2fSAndy Shevchenko 5203796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5213796fb8aSAndy Shevchenko { 5223796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5233796fb8aSAndy Shevchenko u32 con; 5243796fb8aSAndy Shevchenko 5253796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 52603b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 52703b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 52803b5d924SBalaji T K else 52903b5d924SBalaji T K con &= ~DDR; 5303796fb8aSAndy Shevchenko switch (ios->bus_width) { 5313796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5323796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5333796fb8aSAndy Shevchenko break; 5343796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5353796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5363796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5373796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5383796fb8aSAndy Shevchenko break; 5393796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5403796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5413796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5423796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5433796fb8aSAndy Shevchenko break; 5443796fb8aSAndy Shevchenko } 5453796fb8aSAndy Shevchenko } 5463796fb8aSAndy Shevchenko 5473796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5483796fb8aSAndy Shevchenko { 5493796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5503796fb8aSAndy Shevchenko u32 con; 5513796fb8aSAndy Shevchenko 5523796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5533796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5543796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5553796fb8aSAndy Shevchenko else 5563796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5573796fb8aSAndy Shevchenko } 5583796fb8aSAndy Shevchenko 55911dd62a7SDenis Karpov #ifdef CONFIG_PM 56011dd62a7SDenis Karpov 56111dd62a7SDenis Karpov /* 56211dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 56311dd62a7SDenis Karpov * power state change. 56411dd62a7SDenis Karpov */ 56570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 56611dd62a7SDenis Karpov { 56711dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 56811dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 56911dd62a7SDenis Karpov int context_loss = 0; 5703796fb8aSAndy Shevchenko u32 hctl, capa; 57111dd62a7SDenis Karpov unsigned long timeout; 57211dd62a7SDenis Karpov 57311dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 57411dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 57511dd62a7SDenis Karpov if (context_loss < 0) 57611dd62a7SDenis Karpov return 1; 57711dd62a7SDenis Karpov } 57811dd62a7SDenis Karpov 57911dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 58011dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 58111dd62a7SDenis Karpov if (host->context_loss == context_loss) 58211dd62a7SDenis Karpov return 1; 58311dd62a7SDenis Karpov 58411dd62a7SDenis Karpov /* Wait for hardware reset */ 58511dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 58611dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 58711dd62a7SDenis Karpov && time_before(jiffies, timeout)) 58811dd62a7SDenis Karpov ; 58911dd62a7SDenis Karpov 59011dd62a7SDenis Karpov /* Do software reset */ 59111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 59211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 59311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 59411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 59511dd62a7SDenis Karpov ; 59611dd62a7SDenis Karpov 59711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 59811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 59911dd62a7SDenis Karpov 600c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 60111dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 60211dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 60311dd62a7SDenis Karpov hctl = SDVS18; 60411dd62a7SDenis Karpov else 60511dd62a7SDenis Karpov hctl = SDVS30; 60611dd62a7SDenis Karpov capa = VS30 | VS18; 60711dd62a7SDenis Karpov } else { 60811dd62a7SDenis Karpov hctl = SDVS18; 60911dd62a7SDenis Karpov capa = VS18; 61011dd62a7SDenis Karpov } 61111dd62a7SDenis Karpov 61211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 61311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 61411dd62a7SDenis Karpov 61511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 61611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 61711dd62a7SDenis Karpov 61811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 61911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 62011dd62a7SDenis Karpov 62111dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 62211dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 62311dd62a7SDenis Karpov && time_before(jiffies, timeout)) 62411dd62a7SDenis Karpov ; 62511dd62a7SDenis Karpov 626b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 62711dd62a7SDenis Karpov 62811dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 62911dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 63011dd62a7SDenis Karpov goto out; 63111dd62a7SDenis Karpov 6323796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 63311dd62a7SDenis Karpov 6345934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 63511dd62a7SDenis Karpov 6363796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6373796fb8aSAndy Shevchenko 63811dd62a7SDenis Karpov out: 63911dd62a7SDenis Karpov host->context_loss = context_loss; 64011dd62a7SDenis Karpov 64111dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 64211dd62a7SDenis Karpov return 0; 64311dd62a7SDenis Karpov } 64411dd62a7SDenis Karpov 64511dd62a7SDenis Karpov /* 64611dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 64711dd62a7SDenis Karpov */ 64870a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 64911dd62a7SDenis Karpov { 65011dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 65111dd62a7SDenis Karpov int context_loss; 65211dd62a7SDenis Karpov 65311dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 65411dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 65511dd62a7SDenis Karpov if (context_loss < 0) 65611dd62a7SDenis Karpov return; 65711dd62a7SDenis Karpov host->context_loss = context_loss; 65811dd62a7SDenis Karpov } 65911dd62a7SDenis Karpov } 66011dd62a7SDenis Karpov 66111dd62a7SDenis Karpov #else 66211dd62a7SDenis Karpov 66370a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 66411dd62a7SDenis Karpov { 66511dd62a7SDenis Karpov return 0; 66611dd62a7SDenis Karpov } 66711dd62a7SDenis Karpov 66870a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 66911dd62a7SDenis Karpov { 67011dd62a7SDenis Karpov } 67111dd62a7SDenis Karpov 67211dd62a7SDenis Karpov #endif 67311dd62a7SDenis Karpov 674a45c6cb8SMadhusudhan Chikkature /* 675a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 676a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 677a45c6cb8SMadhusudhan Chikkature */ 67870a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 679a45c6cb8SMadhusudhan Chikkature { 680a45c6cb8SMadhusudhan Chikkature int reg = 0; 681a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 682a45c6cb8SMadhusudhan Chikkature 683b62f6228SAdrian Hunter if (host->protect_card) 684b62f6228SAdrian Hunter return; 685b62f6228SAdrian Hunter 686a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 687b417577dSAdrian Hunter 688b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 689a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 690a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 691a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 692a45c6cb8SMadhusudhan Chikkature 693a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 694a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 695a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 696a45c6cb8SMadhusudhan Chikkature 697a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 698a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 699c653a6d4SAdrian Hunter 700c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 701c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 702c653a6d4SAdrian Hunter 703a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 704a45c6cb8SMadhusudhan Chikkature } 705a45c6cb8SMadhusudhan Chikkature 706a45c6cb8SMadhusudhan Chikkature static inline 70770a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 708a45c6cb8SMadhusudhan Chikkature { 709a45c6cb8SMadhusudhan Chikkature int r = 1; 710a45c6cb8SMadhusudhan Chikkature 711191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 712191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 713a45c6cb8SMadhusudhan Chikkature return r; 714a45c6cb8SMadhusudhan Chikkature } 715a45c6cb8SMadhusudhan Chikkature 716a45c6cb8SMadhusudhan Chikkature static ssize_t 71770a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 718a45c6cb8SMadhusudhan Chikkature char *buf) 719a45c6cb8SMadhusudhan Chikkature { 720a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 72170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 722a45c6cb8SMadhusudhan Chikkature 72370a3341aSDenis Karpov return sprintf(buf, "%s\n", 72470a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 725a45c6cb8SMadhusudhan Chikkature } 726a45c6cb8SMadhusudhan Chikkature 72770a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 728a45c6cb8SMadhusudhan Chikkature 729a45c6cb8SMadhusudhan Chikkature static ssize_t 73070a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 731a45c6cb8SMadhusudhan Chikkature char *buf) 732a45c6cb8SMadhusudhan Chikkature { 733a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 73470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 735a45c6cb8SMadhusudhan Chikkature 736191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 737a45c6cb8SMadhusudhan Chikkature } 738a45c6cb8SMadhusudhan Chikkature 73970a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 740a45c6cb8SMadhusudhan Chikkature 741a45c6cb8SMadhusudhan Chikkature /* 742a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 743a45c6cb8SMadhusudhan Chikkature */ 744a45c6cb8SMadhusudhan Chikkature static void 74570a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 746a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 747a45c6cb8SMadhusudhan Chikkature { 748a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 749a45c6cb8SMadhusudhan Chikkature 750a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 751a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 752a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 753a45c6cb8SMadhusudhan Chikkature 75493caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 755a45c6cb8SMadhusudhan Chikkature 7564a694dc9SAdrian Hunter host->response_busy = 0; 757a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 758a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 759a45c6cb8SMadhusudhan Chikkature resptype = 1; 7604a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7614a694dc9SAdrian Hunter resptype = 3; 7624a694dc9SAdrian Hunter host->response_busy = 1; 7634a694dc9SAdrian Hunter } else 764a45c6cb8SMadhusudhan Chikkature resptype = 2; 765a45c6cb8SMadhusudhan Chikkature } 766a45c6cb8SMadhusudhan Chikkature 767a45c6cb8SMadhusudhan Chikkature /* 768a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 769a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 770a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 771a45c6cb8SMadhusudhan Chikkature */ 772a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 773a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 774a45c6cb8SMadhusudhan Chikkature 775a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 776dba3c29eSBalaji T K if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode)) 777dba3c29eSBalaji T K cmdreg |= ACEN_ACMD12; 778a45c6cb8SMadhusudhan Chikkature 779a45c6cb8SMadhusudhan Chikkature if (data) { 780a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 781a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 782a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 783a45c6cb8SMadhusudhan Chikkature else 784a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 785a45c6cb8SMadhusudhan Chikkature } 786a45c6cb8SMadhusudhan Chikkature 787a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 788a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 789a45c6cb8SMadhusudhan Chikkature 790b417577dSAdrian Hunter host->req_in_progress = 1; 7914dffd7a2SAdrian Hunter 792a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 793a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 794a45c6cb8SMadhusudhan Chikkature } 795a45c6cb8SMadhusudhan Chikkature 7960ccd76d4SJuha Yrjola static int 79770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 7980ccd76d4SJuha Yrjola { 7990ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8000ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8010ccd76d4SJuha Yrjola else 8020ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8030ccd76d4SJuha Yrjola } 8040ccd76d4SJuha Yrjola 805b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 806b417577dSAdrian Hunter { 807b417577dSAdrian Hunter int dma_ch; 80831463b14SVenkatraman S unsigned long flags; 809b417577dSAdrian Hunter 81031463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 811b417577dSAdrian Hunter host->req_in_progress = 0; 812b417577dSAdrian Hunter dma_ch = host->dma_ch; 81331463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 814b417577dSAdrian Hunter 815b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 816b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 817b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 818b417577dSAdrian Hunter return; 819b417577dSAdrian Hunter host->mrq = NULL; 820b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 821b417577dSAdrian Hunter } 822b417577dSAdrian Hunter 823a45c6cb8SMadhusudhan Chikkature /* 824a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 825a45c6cb8SMadhusudhan Chikkature */ 826a45c6cb8SMadhusudhan Chikkature static void 82770a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 828a45c6cb8SMadhusudhan Chikkature { 8294a694dc9SAdrian Hunter if (!data) { 8304a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8314a694dc9SAdrian Hunter 83223050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 83323050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 83423050103SAdrian Hunter host->response_busy) { 83523050103SAdrian Hunter host->response_busy = 0; 83623050103SAdrian Hunter return; 83723050103SAdrian Hunter } 83823050103SAdrian Hunter 839b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8404a694dc9SAdrian Hunter return; 8414a694dc9SAdrian Hunter } 8424a694dc9SAdrian Hunter 843a45c6cb8SMadhusudhan Chikkature host->data = NULL; 844a45c6cb8SMadhusudhan Chikkature 845a45c6cb8SMadhusudhan Chikkature if (!data->error) 846a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 847a45c6cb8SMadhusudhan Chikkature else 848a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 849a45c6cb8SMadhusudhan Chikkature 850dba3c29eSBalaji T K if (data->stop && ((!(host->flags & AUTO_CMD12)) || data->error)) { 85170a3341aSDenis Karpov omap_hsmmc_start_command(host, data->stop, NULL); 852dba3c29eSBalaji T K } else { 853dba3c29eSBalaji T K if (data->stop) 854dba3c29eSBalaji T K data->stop->resp[0] = OMAP_HSMMC_READ(host->base, 855dba3c29eSBalaji T K RSP76); 856dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 857dba3c29eSBalaji T K } 858a45c6cb8SMadhusudhan Chikkature } 859a45c6cb8SMadhusudhan Chikkature 860a45c6cb8SMadhusudhan Chikkature /* 861a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 862a45c6cb8SMadhusudhan Chikkature */ 863a45c6cb8SMadhusudhan Chikkature static void 86470a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 865a45c6cb8SMadhusudhan Chikkature { 866a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 867a45c6cb8SMadhusudhan Chikkature 868a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 869a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 870a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 871a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 872a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 873a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 874a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 875a45c6cb8SMadhusudhan Chikkature } else { 876a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 877a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 878a45c6cb8SMadhusudhan Chikkature } 879a45c6cb8SMadhusudhan Chikkature } 880b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 881b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 882a45c6cb8SMadhusudhan Chikkature } 883a45c6cb8SMadhusudhan Chikkature 884a45c6cb8SMadhusudhan Chikkature /* 885a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 886a45c6cb8SMadhusudhan Chikkature */ 88770a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 888a45c6cb8SMadhusudhan Chikkature { 889b417577dSAdrian Hunter int dma_ch; 89031463b14SVenkatraman S unsigned long flags; 891b417577dSAdrian Hunter 89282788ff5SJarkko Lavinen host->data->error = errno; 893a45c6cb8SMadhusudhan Chikkature 89431463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 895b417577dSAdrian Hunter dma_ch = host->dma_ch; 896b417577dSAdrian Hunter host->dma_ch = -1; 89731463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 898b417577dSAdrian Hunter 899b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 900a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, 901a9120c33SPer Forlin host->data->sg_len, 90270a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 903b417577dSAdrian Hunter omap_free_dma(dma_ch); 904053bf34fSPer Forlin host->data->host_cookie = 0; 905a45c6cb8SMadhusudhan Chikkature } 906a45c6cb8SMadhusudhan Chikkature host->data = NULL; 907a45c6cb8SMadhusudhan Chikkature } 908a45c6cb8SMadhusudhan Chikkature 909a45c6cb8SMadhusudhan Chikkature /* 910a45c6cb8SMadhusudhan Chikkature * Readable error output 911a45c6cb8SMadhusudhan Chikkature */ 912a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 913699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 914a45c6cb8SMadhusudhan Chikkature { 915a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 91670a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 917699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 918699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 919699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 920699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 921a45c6cb8SMadhusudhan Chikkature }; 922a45c6cb8SMadhusudhan Chikkature char res[256]; 923a45c6cb8SMadhusudhan Chikkature char *buf = res; 924a45c6cb8SMadhusudhan Chikkature int len, i; 925a45c6cb8SMadhusudhan Chikkature 926a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 927a45c6cb8SMadhusudhan Chikkature buf += len; 928a45c6cb8SMadhusudhan Chikkature 92970a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 930a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 93170a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 932a45c6cb8SMadhusudhan Chikkature buf += len; 933a45c6cb8SMadhusudhan Chikkature } 934a45c6cb8SMadhusudhan Chikkature 935a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 936a45c6cb8SMadhusudhan Chikkature } 937699b958bSAdrian Hunter #else 938699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 939699b958bSAdrian Hunter u32 status) 940699b958bSAdrian Hunter { 941699b958bSAdrian Hunter } 942a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 943a45c6cb8SMadhusudhan Chikkature 9443ebf74b1SJean Pihet /* 9453ebf74b1SJean Pihet * MMC controller internal state machines reset 9463ebf74b1SJean Pihet * 9473ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9483ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9493ebf74b1SJean Pihet * Can be called from interrupt context 9503ebf74b1SJean Pihet */ 95170a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9523ebf74b1SJean Pihet unsigned long bit) 9533ebf74b1SJean Pihet { 9543ebf74b1SJean Pihet unsigned long i = 0; 9553ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 9563ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 9573ebf74b1SJean Pihet 9583ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9593ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9603ebf74b1SJean Pihet 96107ad64b6SMadhusudhan Chikkature /* 96207ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 96307ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 96407ad64b6SMadhusudhan Chikkature */ 96507ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 966b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 96707ad64b6SMadhusudhan Chikkature && (i++ < limit)) 96807ad64b6SMadhusudhan Chikkature cpu_relax(); 96907ad64b6SMadhusudhan Chikkature } 97007ad64b6SMadhusudhan Chikkature i = 0; 97107ad64b6SMadhusudhan Chikkature 9723ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9733ebf74b1SJean Pihet (i++ < limit)) 9743ebf74b1SJean Pihet cpu_relax(); 9753ebf74b1SJean Pihet 9763ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9773ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9783ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 9793ebf74b1SJean Pihet __func__); 9803ebf74b1SJean Pihet } 981a45c6cb8SMadhusudhan Chikkature 982b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 983a45c6cb8SMadhusudhan Chikkature { 984a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 985b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 986a45c6cb8SMadhusudhan Chikkature 987b417577dSAdrian Hunter if (!host->req_in_progress) { 988b417577dSAdrian Hunter do { 989b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, status); 99000adadc1SKevin Hilman /* Flush posted write */ 991b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 992b417577dSAdrian Hunter } while (status & INT_EN_MASK); 993b417577dSAdrian Hunter return; 994a45c6cb8SMadhusudhan Chikkature } 995a45c6cb8SMadhusudhan Chikkature 996a45c6cb8SMadhusudhan Chikkature data = host->data; 997a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 998a45c6cb8SMadhusudhan Chikkature 999a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 1000699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 1001a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 1002a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 1003a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 1004a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 100570a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 1006191d1f1dSDenis Karpov SRC); 1007a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 1008a45c6cb8SMadhusudhan Chikkature } else { 1009a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 1010a45c6cb8SMadhusudhan Chikkature } 1011a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1012a45c6cb8SMadhusudhan Chikkature } 10134a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10144a694dc9SAdrian Hunter if (host->data) 101570a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 101670a3341aSDenis Karpov -ETIMEDOUT); 10174a694dc9SAdrian Hunter host->response_busy = 0; 101870a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1019c232f457SJean Pihet } 1020a45c6cb8SMadhusudhan Chikkature } 1021a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 1022a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 10234a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10244a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 10254a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 10264a694dc9SAdrian Hunter 10274a694dc9SAdrian Hunter if (host->data) 102870a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 1029a45c6cb8SMadhusudhan Chikkature else 10304a694dc9SAdrian Hunter host->mrq->cmd->error = err; 10314a694dc9SAdrian Hunter host->response_busy = 0; 103270a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1033a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1034a45c6cb8SMadhusudhan Chikkature } 1035a45c6cb8SMadhusudhan Chikkature } 1036a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 1037a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1038a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 1039a45c6cb8SMadhusudhan Chikkature if (host->cmd) 1040a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1041a45c6cb8SMadhusudhan Chikkature if (host->data) 1042a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1043a45c6cb8SMadhusudhan Chikkature } 1044a45c6cb8SMadhusudhan Chikkature } 1045a45c6cb8SMadhusudhan Chikkature 1046a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 1047a45c6cb8SMadhusudhan Chikkature 1048a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 104970a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 10500a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 105170a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1052b417577dSAdrian Hunter } 1053a45c6cb8SMadhusudhan Chikkature 1054b417577dSAdrian Hunter /* 1055b417577dSAdrian Hunter * MMC controller IRQ handler 1056b417577dSAdrian Hunter */ 1057b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1058b417577dSAdrian Hunter { 1059b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1060b417577dSAdrian Hunter int status; 1061b417577dSAdrian Hunter 1062b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1063b417577dSAdrian Hunter do { 1064b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 1065b417577dSAdrian Hunter /* Flush posted write */ 1066b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1067b417577dSAdrian Hunter } while (status & INT_EN_MASK); 10684dffd7a2SAdrian Hunter 1069a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1070a45c6cb8SMadhusudhan Chikkature } 1071a45c6cb8SMadhusudhan Chikkature 107270a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1073e13bb300SAdrian Hunter { 1074e13bb300SAdrian Hunter unsigned long i; 1075e13bb300SAdrian Hunter 1076e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1077e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1078e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1079e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1080e13bb300SAdrian Hunter break; 1081e13bb300SAdrian Hunter cpu_relax(); 1082e13bb300SAdrian Hunter } 1083e13bb300SAdrian Hunter } 1084e13bb300SAdrian Hunter 1085a45c6cb8SMadhusudhan Chikkature /* 1086eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1087eb250826SDavid Brownell * 1088eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1089eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1090eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1091a45c6cb8SMadhusudhan Chikkature */ 109270a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1093a45c6cb8SMadhusudhan Chikkature { 1094a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1095a45c6cb8SMadhusudhan Chikkature int ret; 1096a45c6cb8SMadhusudhan Chikkature 1097a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1098fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1099cd03d9a8SRajendra Nayak if (host->dbclk) 1100a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1101a45c6cb8SMadhusudhan Chikkature 1102a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1103a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1104a45c6cb8SMadhusudhan Chikkature 1105a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11062bec0893SAdrian Hunter if (!ret) 11072bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11082bec0893SAdrian Hunter vdd); 1109fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1110cd03d9a8SRajendra Nayak if (host->dbclk) 11112bec0893SAdrian Hunter clk_enable(host->dbclk); 11122bec0893SAdrian Hunter 1113a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1114a45c6cb8SMadhusudhan Chikkature goto err; 1115a45c6cb8SMadhusudhan Chikkature 1116a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1117a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1118a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1119eb250826SDavid Brownell 1120a45c6cb8SMadhusudhan Chikkature /* 1121a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1122a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 112370a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1124a45c6cb8SMadhusudhan Chikkature * 1125eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1126eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1127eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1128eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1129eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1130eb250826SDavid Brownell * 1131eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1132eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1133eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1134a45c6cb8SMadhusudhan Chikkature */ 1135eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1136a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1137eb250826SDavid Brownell else 1138eb250826SDavid Brownell reg_val |= SDVS30; 1139a45c6cb8SMadhusudhan Chikkature 1140a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1141e13bb300SAdrian Hunter set_sd_bus_power(host); 1142a45c6cb8SMadhusudhan Chikkature 1143a45c6cb8SMadhusudhan Chikkature return 0; 1144a45c6cb8SMadhusudhan Chikkature err: 1145a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1146a45c6cb8SMadhusudhan Chikkature return ret; 1147a45c6cb8SMadhusudhan Chikkature } 1148a45c6cb8SMadhusudhan Chikkature 1149b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1150b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1151b62f6228SAdrian Hunter { 1152b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1153b62f6228SAdrian Hunter return; 1154b62f6228SAdrian Hunter 1155b62f6228SAdrian Hunter host->reqs_blocked = 0; 1156b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1157b62f6228SAdrian Hunter if (host->protect_card) { 11582cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1159b62f6228SAdrian Hunter "card is now accessible\n", 1160b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1161b62f6228SAdrian Hunter host->protect_card = 0; 1162b62f6228SAdrian Hunter } 1163b62f6228SAdrian Hunter } else { 1164b62f6228SAdrian Hunter if (!host->protect_card) { 11652cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1166b62f6228SAdrian Hunter "card is now inaccessible\n", 1167b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1168b62f6228SAdrian Hunter host->protect_card = 1; 1169b62f6228SAdrian Hunter } 1170b62f6228SAdrian Hunter } 1171b62f6228SAdrian Hunter } 1172b62f6228SAdrian Hunter 1173a45c6cb8SMadhusudhan Chikkature /* 11747efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1175a45c6cb8SMadhusudhan Chikkature */ 11767efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1177a45c6cb8SMadhusudhan Chikkature { 11787efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1179249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1180a6b2240dSAdrian Hunter int carddetect; 1181249d0fa9SDavid Brownell 1182a6b2240dSAdrian Hunter if (host->suspended) 11837efab4f3SNeilBrown return IRQ_HANDLED; 1184a45c6cb8SMadhusudhan Chikkature 1185a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1186a6b2240dSAdrian Hunter 1187191d1f1dSDenis Karpov if (slot->card_detect) 1188db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1189b62f6228SAdrian Hunter else { 1190b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1191a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1192b62f6228SAdrian Hunter } 1193a6b2240dSAdrian Hunter 1194cdeebaddSMadhusudhan Chikkature if (carddetect) 1195a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1196cdeebaddSMadhusudhan Chikkature else 1197a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1198a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1199a45c6cb8SMadhusudhan Chikkature } 1200a45c6cb8SMadhusudhan Chikkature 120170a3341aSDenis Karpov static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 12020ccd76d4SJuha Yrjola struct mmc_data *data) 12030ccd76d4SJuha Yrjola { 12040ccd76d4SJuha Yrjola int sync_dev; 12050ccd76d4SJuha Yrjola 1206f3e2f1ddSGrazvydas Ignotas if (data->flags & MMC_DATA_WRITE) 1207f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_tx; 12080ccd76d4SJuha Yrjola else 1209f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_rx; 12100ccd76d4SJuha Yrjola return sync_dev; 12110ccd76d4SJuha Yrjola } 12120ccd76d4SJuha Yrjola 121370a3341aSDenis Karpov static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 12140ccd76d4SJuha Yrjola struct mmc_data *data, 12150ccd76d4SJuha Yrjola struct scatterlist *sgl) 12160ccd76d4SJuha Yrjola { 12170ccd76d4SJuha Yrjola int blksz, nblk, dma_ch; 12180ccd76d4SJuha Yrjola 12190ccd76d4SJuha Yrjola dma_ch = host->dma_ch; 12200ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) { 12210ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 12220ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 12230ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 12240ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 12250ccd76d4SJuha Yrjola } else { 12260ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 12270ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 12280ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 12290ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 12300ccd76d4SJuha Yrjola } 12310ccd76d4SJuha Yrjola 12320ccd76d4SJuha Yrjola blksz = host->data->blksz; 12330ccd76d4SJuha Yrjola nblk = sg_dma_len(sgl) / blksz; 12340ccd76d4SJuha Yrjola 12350ccd76d4SJuha Yrjola omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 12360ccd76d4SJuha Yrjola blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 123770a3341aSDenis Karpov omap_hsmmc_get_dma_sync_dev(host, data), 12380ccd76d4SJuha Yrjola !(data->flags & MMC_DATA_WRITE)); 12390ccd76d4SJuha Yrjola 12400ccd76d4SJuha Yrjola omap_start_dma(dma_ch); 12410ccd76d4SJuha Yrjola } 12420ccd76d4SJuha Yrjola 1243a45c6cb8SMadhusudhan Chikkature /* 1244a45c6cb8SMadhusudhan Chikkature * DMA call back function 1245a45c6cb8SMadhusudhan Chikkature */ 1246b417577dSAdrian Hunter static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1247a45c6cb8SMadhusudhan Chikkature { 1248b417577dSAdrian Hunter struct omap_hsmmc_host *host = cb_data; 1249770d7432SAdrian Hunter struct mmc_data *data; 1250b417577dSAdrian Hunter int dma_ch, req_in_progress; 125131463b14SVenkatraman S unsigned long flags; 1252a45c6cb8SMadhusudhan Chikkature 1253f3584e5eSVenkatraman S if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1254f3584e5eSVenkatraman S dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1255f3584e5eSVenkatraman S ch_status); 1256f3584e5eSVenkatraman S return; 1257f3584e5eSVenkatraman S } 1258a45c6cb8SMadhusudhan Chikkature 125931463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1260b417577dSAdrian Hunter if (host->dma_ch < 0) { 126131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1262a45c6cb8SMadhusudhan Chikkature return; 1263b417577dSAdrian Hunter } 1264a45c6cb8SMadhusudhan Chikkature 1265770d7432SAdrian Hunter data = host->mrq->data; 12660ccd76d4SJuha Yrjola host->dma_sg_idx++; 12670ccd76d4SJuha Yrjola if (host->dma_sg_idx < host->dma_len) { 12680ccd76d4SJuha Yrjola /* Fire up the next transfer. */ 1269b417577dSAdrian Hunter omap_hsmmc_config_dma_params(host, data, 1270b417577dSAdrian Hunter data->sg + host->dma_sg_idx); 127131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 12720ccd76d4SJuha Yrjola return; 12730ccd76d4SJuha Yrjola } 12740ccd76d4SJuha Yrjola 12759782aff8SPer Forlin if (!data->host_cookie) 1276a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1277b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1278b417577dSAdrian Hunter 1279b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1280b417577dSAdrian Hunter dma_ch = host->dma_ch; 1281a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 128231463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1283b417577dSAdrian Hunter 1284b417577dSAdrian Hunter omap_free_dma(dma_ch); 1285b417577dSAdrian Hunter 1286b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1287b417577dSAdrian Hunter if (!req_in_progress) { 1288b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1289b417577dSAdrian Hunter 1290b417577dSAdrian Hunter host->mrq = NULL; 1291b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1292b417577dSAdrian Hunter } 1293a45c6cb8SMadhusudhan Chikkature } 1294a45c6cb8SMadhusudhan Chikkature 12959782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12969782aff8SPer Forlin struct mmc_data *data, 12979782aff8SPer Forlin struct omap_hsmmc_next *next) 12989782aff8SPer Forlin { 12999782aff8SPer Forlin int dma_len; 13009782aff8SPer Forlin 13019782aff8SPer Forlin if (!next && data->host_cookie && 13029782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13032cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13049782aff8SPer Forlin " host->next_data.cookie %d\n", 13059782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13069782aff8SPer Forlin data->host_cookie = 0; 13079782aff8SPer Forlin } 13089782aff8SPer Forlin 13099782aff8SPer Forlin /* Check if next job is already prepared */ 13109782aff8SPer Forlin if (next || 13119782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 13129782aff8SPer Forlin dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 13139782aff8SPer Forlin data->sg_len, 13149782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13159782aff8SPer Forlin 13169782aff8SPer Forlin } else { 13179782aff8SPer Forlin dma_len = host->next_data.dma_len; 13189782aff8SPer Forlin host->next_data.dma_len = 0; 13199782aff8SPer Forlin } 13209782aff8SPer Forlin 13219782aff8SPer Forlin 13229782aff8SPer Forlin if (dma_len == 0) 13239782aff8SPer Forlin return -EINVAL; 13249782aff8SPer Forlin 13259782aff8SPer Forlin if (next) { 13269782aff8SPer Forlin next->dma_len = dma_len; 13279782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13289782aff8SPer Forlin } else 13299782aff8SPer Forlin host->dma_len = dma_len; 13309782aff8SPer Forlin 13319782aff8SPer Forlin return 0; 13329782aff8SPer Forlin } 13339782aff8SPer Forlin 1334a45c6cb8SMadhusudhan Chikkature /* 1335a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1336a45c6cb8SMadhusudhan Chikkature */ 133770a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 133870a3341aSDenis Karpov struct mmc_request *req) 1339a45c6cb8SMadhusudhan Chikkature { 1340b417577dSAdrian Hunter int dma_ch = 0, ret = 0, i; 1341a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1342a45c6cb8SMadhusudhan Chikkature 13430ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1344a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13450ccd76d4SJuha Yrjola struct scatterlist *sgl; 13460ccd76d4SJuha Yrjola 13470ccd76d4SJuha Yrjola sgl = data->sg + i; 13480ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13490ccd76d4SJuha Yrjola return -EINVAL; 13500ccd76d4SJuha Yrjola } 13510ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13520ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13530ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13540ccd76d4SJuha Yrjola */ 13550ccd76d4SJuha Yrjola return -EINVAL; 13560ccd76d4SJuha Yrjola 1357b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1358a45c6cb8SMadhusudhan Chikkature 135970a3341aSDenis Karpov ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 136070a3341aSDenis Karpov "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1361a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 13620ccd76d4SJuha Yrjola dev_err(mmc_dev(host->mmc), 1363a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 1364a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 1365a45c6cb8SMadhusudhan Chikkature return ret; 1366a45c6cb8SMadhusudhan Chikkature } 13679782aff8SPer Forlin ret = omap_hsmmc_pre_dma_transfer(host, data, NULL); 13689782aff8SPer Forlin if (ret) 13699782aff8SPer Forlin return ret; 1370a45c6cb8SMadhusudhan Chikkature 1371a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 13720ccd76d4SJuha Yrjola host->dma_sg_idx = 0; 1373a45c6cb8SMadhusudhan Chikkature 137470a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, data, data->sg); 1375a45c6cb8SMadhusudhan Chikkature 1376a45c6cb8SMadhusudhan Chikkature return 0; 1377a45c6cb8SMadhusudhan Chikkature } 1378a45c6cb8SMadhusudhan Chikkature 137970a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1380e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1381e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1382a45c6cb8SMadhusudhan Chikkature { 1383a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1384a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1385a45c6cb8SMadhusudhan Chikkature 1386a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1387a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1388a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1389a45c6cb8SMadhusudhan Chikkature clkd = 1; 1390a45c6cb8SMadhusudhan Chikkature 1391a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1392e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1393e2bf08d6SAdrian Hunter timeout += timeout_clks; 1394a45c6cb8SMadhusudhan Chikkature if (timeout) { 1395a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1396a45c6cb8SMadhusudhan Chikkature dto += 1; 1397a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1398a45c6cb8SMadhusudhan Chikkature } 1399a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1400a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1401a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1402a45c6cb8SMadhusudhan Chikkature dto += 1; 1403a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1404a45c6cb8SMadhusudhan Chikkature dto -= 13; 1405a45c6cb8SMadhusudhan Chikkature else 1406a45c6cb8SMadhusudhan Chikkature dto = 0; 1407a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1408a45c6cb8SMadhusudhan Chikkature dto = 14; 1409a45c6cb8SMadhusudhan Chikkature } 1410a45c6cb8SMadhusudhan Chikkature 1411a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1412a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1413a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1414a45c6cb8SMadhusudhan Chikkature } 1415a45c6cb8SMadhusudhan Chikkature 1416a45c6cb8SMadhusudhan Chikkature /* 1417a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1418a45c6cb8SMadhusudhan Chikkature */ 1419a45c6cb8SMadhusudhan Chikkature static int 142070a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1421a45c6cb8SMadhusudhan Chikkature { 1422a45c6cb8SMadhusudhan Chikkature int ret; 1423a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1424a45c6cb8SMadhusudhan Chikkature 1425a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1426a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1427e2bf08d6SAdrian Hunter /* 1428e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1429e2bf08d6SAdrian Hunter * busy signal. 1430e2bf08d6SAdrian Hunter */ 1431e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1432e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1433a45c6cb8SMadhusudhan Chikkature return 0; 1434a45c6cb8SMadhusudhan Chikkature } 1435a45c6cb8SMadhusudhan Chikkature 1436a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1437a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1438e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1439a45c6cb8SMadhusudhan Chikkature 1440a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 144170a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1442a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1443a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1444a45c6cb8SMadhusudhan Chikkature return ret; 1445a45c6cb8SMadhusudhan Chikkature } 1446a45c6cb8SMadhusudhan Chikkature } 1447a45c6cb8SMadhusudhan Chikkature return 0; 1448a45c6cb8SMadhusudhan Chikkature } 1449a45c6cb8SMadhusudhan Chikkature 14509782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14519782aff8SPer Forlin int err) 14529782aff8SPer Forlin { 14539782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14549782aff8SPer Forlin struct mmc_data *data = mrq->data; 14559782aff8SPer Forlin 14569782aff8SPer Forlin if (host->use_dma) { 1457053bf34fSPer Forlin if (data->host_cookie) 1458053bf34fSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 1459053bf34fSPer Forlin data->sg_len, 14609782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14619782aff8SPer Forlin data->host_cookie = 0; 14629782aff8SPer Forlin } 14639782aff8SPer Forlin } 14649782aff8SPer Forlin 14659782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14669782aff8SPer Forlin bool is_first_req) 14679782aff8SPer Forlin { 14689782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14699782aff8SPer Forlin 14709782aff8SPer Forlin if (mrq->data->host_cookie) { 14719782aff8SPer Forlin mrq->data->host_cookie = 0; 14729782aff8SPer Forlin return ; 14739782aff8SPer Forlin } 14749782aff8SPer Forlin 14759782aff8SPer Forlin if (host->use_dma) 14769782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 14779782aff8SPer Forlin &host->next_data)) 14789782aff8SPer Forlin mrq->data->host_cookie = 0; 14799782aff8SPer Forlin } 14809782aff8SPer Forlin 1481a45c6cb8SMadhusudhan Chikkature /* 1482a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1483a45c6cb8SMadhusudhan Chikkature */ 148470a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1485a45c6cb8SMadhusudhan Chikkature { 148670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1487a3f406f8SJarkko Lavinen int err; 1488a45c6cb8SMadhusudhan Chikkature 1489b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1490b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1491b62f6228SAdrian Hunter if (host->protect_card) { 1492b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1493b62f6228SAdrian Hunter /* 1494b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1495b62f6228SAdrian Hunter * state by resetting the command and data state 1496b62f6228SAdrian Hunter * machines. 1497b62f6228SAdrian Hunter */ 1498b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1499b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1500b62f6228SAdrian Hunter host->reqs_blocked += 1; 1501b62f6228SAdrian Hunter } 1502b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1503b62f6228SAdrian Hunter if (req->data) 1504b62f6228SAdrian Hunter req->data->error = -EBADF; 1505b417577dSAdrian Hunter req->cmd->retries = 0; 1506b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1507b62f6228SAdrian Hunter return; 1508b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1509b62f6228SAdrian Hunter host->reqs_blocked = 0; 1510a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1511a45c6cb8SMadhusudhan Chikkature host->mrq = req; 151270a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1513a3f406f8SJarkko Lavinen if (err) { 1514a3f406f8SJarkko Lavinen req->cmd->error = err; 1515a3f406f8SJarkko Lavinen if (req->data) 1516a3f406f8SJarkko Lavinen req->data->error = err; 1517a3f406f8SJarkko Lavinen host->mrq = NULL; 1518a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1519a3f406f8SJarkko Lavinen return; 1520a3f406f8SJarkko Lavinen } 1521a3f406f8SJarkko Lavinen 152270a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1523a45c6cb8SMadhusudhan Chikkature } 1524a45c6cb8SMadhusudhan Chikkature 1525a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 152670a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1527a45c6cb8SMadhusudhan Chikkature { 152870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1529a3621465SAdrian Hunter int do_send_init_stream = 0; 1530a45c6cb8SMadhusudhan Chikkature 1531fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15325e2ea617SAdrian Hunter 1533a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1534a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1535a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1536a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1537a3621465SAdrian Hunter 0, 0); 1538623821f7SAdrian Hunter host->vdd = 0; 1539a45c6cb8SMadhusudhan Chikkature break; 1540a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1541a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1542a3621465SAdrian Hunter 1, ios->vdd); 1543623821f7SAdrian Hunter host->vdd = ios->vdd; 1544a45c6cb8SMadhusudhan Chikkature break; 1545a3621465SAdrian Hunter case MMC_POWER_ON: 1546a3621465SAdrian Hunter do_send_init_stream = 1; 1547a3621465SAdrian Hunter break; 1548a3621465SAdrian Hunter } 1549a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1550a45c6cb8SMadhusudhan Chikkature } 1551a45c6cb8SMadhusudhan Chikkature 1552dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1553dd498effSDenis Karpov 15543796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1555a45c6cb8SMadhusudhan Chikkature 15564621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1557eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1558eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1559eb250826SDavid Brownell */ 1560a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15611f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15621f84b71bSRajendra Nayak /* 15631f84b71bSRajendra Nayak * With pbias cell programming missing, this 15641f84b71bSRajendra Nayak * can't be allowed when booting with device 15651f84b71bSRajendra Nayak * tree. 15661f84b71bSRajendra Nayak */ 15674d048f91SRajendra Nayak !host->dev->of_node) { 1568a45c6cb8SMadhusudhan Chikkature /* 1569a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1570a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1571a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1572a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1573a45c6cb8SMadhusudhan Chikkature */ 157470a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1575a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1576a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1577a45c6cb8SMadhusudhan Chikkature } 1578a45c6cb8SMadhusudhan Chikkature } 1579a45c6cb8SMadhusudhan Chikkature 15805934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1581a45c6cb8SMadhusudhan Chikkature 1582a3621465SAdrian Hunter if (do_send_init_stream) 1583a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1584a45c6cb8SMadhusudhan Chikkature 15853796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15865e2ea617SAdrian Hunter 1587fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1588a45c6cb8SMadhusudhan Chikkature } 1589a45c6cb8SMadhusudhan Chikkature 1590a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1591a45c6cb8SMadhusudhan Chikkature { 159270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1593a45c6cb8SMadhusudhan Chikkature 1594191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1595a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1596db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1597a45c6cb8SMadhusudhan Chikkature } 1598a45c6cb8SMadhusudhan Chikkature 1599a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1600a45c6cb8SMadhusudhan Chikkature { 160170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1602a45c6cb8SMadhusudhan Chikkature 1603191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1604a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1605191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1606a45c6cb8SMadhusudhan Chikkature } 1607a45c6cb8SMadhusudhan Chikkature 16084816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16094816858cSGrazvydas Ignotas { 16104816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16114816858cSGrazvydas Ignotas 16124816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 16134816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 16144816858cSGrazvydas Ignotas } 16154816858cSGrazvydas Ignotas 161670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 16171b331e69SKim Kyuwon { 16181b331e69SKim Kyuwon u32 hctl, capa, value; 16191b331e69SKim Kyuwon 16201b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 16214621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 16221b331e69SKim Kyuwon hctl = SDVS30; 16231b331e69SKim Kyuwon capa = VS30 | VS18; 16241b331e69SKim Kyuwon } else { 16251b331e69SKim Kyuwon hctl = SDVS18; 16261b331e69SKim Kyuwon capa = VS18; 16271b331e69SKim Kyuwon } 16281b331e69SKim Kyuwon 16291b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 16301b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 16311b331e69SKim Kyuwon 16321b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 16331b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 16341b331e69SKim Kyuwon 16351b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 16361b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 16371b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 16381b331e69SKim Kyuwon 16391b331e69SKim Kyuwon /* Set SD bus power bit */ 1640e13bb300SAdrian Hunter set_sd_bus_power(host); 16411b331e69SKim Kyuwon } 16421b331e69SKim Kyuwon 164370a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1644dd498effSDenis Karpov { 164570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1646dd498effSDenis Karpov 1647fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1648fa4aa2d4SBalaji T K 1649dd498effSDenis Karpov return 0; 1650dd498effSDenis Karpov } 1651dd498effSDenis Karpov 1652907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1653dd498effSDenis Karpov { 165470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1655dd498effSDenis Karpov 1656fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1657fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1658fa4aa2d4SBalaji T K 1659dd498effSDenis Karpov return 0; 1660dd498effSDenis Karpov } 1661dd498effSDenis Karpov 166270a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 166370a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 166470a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16659782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16669782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 166770a3341aSDenis Karpov .request = omap_hsmmc_request, 166870a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1669dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1670dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16714816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1672dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1673dd498effSDenis Karpov }; 1674dd498effSDenis Karpov 1675d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1676d900f712SDenis Karpov 167770a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1678d900f712SDenis Karpov { 1679d900f712SDenis Karpov struct mmc_host *mmc = s->private; 168070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 168111dd62a7SDenis Karpov int context_loss = 0; 168211dd62a7SDenis Karpov 168370a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 168470a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1685d900f712SDenis Karpov 1686907d2e7cSAdrian Hunter seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", 1687907d2e7cSAdrian Hunter mmc->index, host->context_loss, context_loss); 16885e2ea617SAdrian Hunter 16897a8c2cefSBalaji T K if (host->suspended) { 1690dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1691dd498effSDenis Karpov return 0; 1692dd498effSDenis Karpov } 1693dd498effSDenis Karpov 1694fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1695d900f712SDenis Karpov 1696d900f712SDenis Karpov seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1697d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1698d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1699d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1700d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1701d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1702d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1703d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1704d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1705d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1706d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1707d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1708d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1709d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 17105e2ea617SAdrian Hunter 1711fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1712fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1713dd498effSDenis Karpov 1714d900f712SDenis Karpov return 0; 1715d900f712SDenis Karpov } 1716d900f712SDenis Karpov 171770a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1718d900f712SDenis Karpov { 171970a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1720d900f712SDenis Karpov } 1721d900f712SDenis Karpov 1722d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 172370a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1724d900f712SDenis Karpov .read = seq_read, 1725d900f712SDenis Karpov .llseek = seq_lseek, 1726d900f712SDenis Karpov .release = single_release, 1727d900f712SDenis Karpov }; 1728d900f712SDenis Karpov 172970a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1730d900f712SDenis Karpov { 1731d900f712SDenis Karpov if (mmc->debugfs_root) 1732d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1733d900f712SDenis Karpov mmc, &mmc_regs_fops); 1734d900f712SDenis Karpov } 1735d900f712SDenis Karpov 1736d900f712SDenis Karpov #else 1737d900f712SDenis Karpov 173870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1739d900f712SDenis Karpov { 1740d900f712SDenis Karpov } 1741d900f712SDenis Karpov 1742d900f712SDenis Karpov #endif 1743d900f712SDenis Karpov 174446856a68SRajendra Nayak #ifdef CONFIG_OF 174546856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 174646856a68SRajendra Nayak 174746856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 174846856a68SRajendra Nayak { 174946856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 175046856a68SRajendra Nayak }, 175146856a68SRajendra Nayak { 175246856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 175346856a68SRajendra Nayak }, 175446856a68SRajendra Nayak { 175546856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 175646856a68SRajendra Nayak .data = &omap4_reg_offset, 175746856a68SRajendra Nayak }, 175846856a68SRajendra Nayak {}, 1759b6d085f6SChris Ball }; 176046856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 176146856a68SRajendra Nayak 176246856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 176346856a68SRajendra Nayak { 176446856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 176546856a68SRajendra Nayak struct device_node *np = dev->of_node; 176646856a68SRajendra Nayak u32 bus_width; 176746856a68SRajendra Nayak 176846856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 176946856a68SRajendra Nayak if (!pdata) 177046856a68SRajendra Nayak return NULL; /* out of memory */ 177146856a68SRajendra Nayak 177246856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 177346856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 177446856a68SRajendra Nayak 177546856a68SRajendra Nayak /* This driver only supports 1 slot */ 177646856a68SRajendra Nayak pdata->nr_slots = 1; 177746856a68SRajendra Nayak pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0); 177846856a68SRajendra Nayak pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 177946856a68SRajendra Nayak 178046856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 178146856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 178246856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 178346856a68SRajendra Nayak } 178446856a68SRajendra Nayak of_property_read_u32(np, "ti,bus-width", &bus_width); 178546856a68SRajendra Nayak if (bus_width == 4) 178646856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 178746856a68SRajendra Nayak else if (bus_width == 8) 178846856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 178946856a68SRajendra Nayak 179046856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 179146856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 179246856a68SRajendra Nayak 179346856a68SRajendra Nayak return pdata; 179446856a68SRajendra Nayak } 179546856a68SRajendra Nayak #else 179646856a68SRajendra Nayak static inline struct omap_mmc_platform_data 179746856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 179846856a68SRajendra Nayak { 179946856a68SRajendra Nayak return NULL; 180046856a68SRajendra Nayak } 180146856a68SRajendra Nayak #endif 180246856a68SRajendra Nayak 1803efa25fd3SFelipe Balbi static int __devinit omap_hsmmc_probe(struct platform_device *pdev) 1804a45c6cb8SMadhusudhan Chikkature { 1805a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1806a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 180770a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1808a45c6cb8SMadhusudhan Chikkature struct resource *res; 1809db0fefc5SAdrian Hunter int ret, irq; 181046856a68SRajendra Nayak const struct of_device_id *match; 181146856a68SRajendra Nayak 181246856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 181346856a68SRajendra Nayak if (match) { 181446856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 181546856a68SRajendra Nayak if (match->data) { 181646856a68SRajendra Nayak u16 *offsetp = match->data; 181746856a68SRajendra Nayak pdata->reg_offset = *offsetp; 181846856a68SRajendra Nayak } 181946856a68SRajendra Nayak } 1820a45c6cb8SMadhusudhan Chikkature 1821a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1822a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1823a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1824a45c6cb8SMadhusudhan Chikkature } 1825a45c6cb8SMadhusudhan Chikkature 1826a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1827a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1828a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1829a45c6cb8SMadhusudhan Chikkature } 1830a45c6cb8SMadhusudhan Chikkature 1831a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1832a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1833a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1834a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1835a45c6cb8SMadhusudhan Chikkature 1836984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1837a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1838a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1839a45c6cb8SMadhusudhan Chikkature 1840db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1841db0fefc5SAdrian Hunter if (ret) 1842db0fefc5SAdrian Hunter goto err; 1843db0fefc5SAdrian Hunter 184470a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1845a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1846a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1847db0fefc5SAdrian Hunter goto err_alloc; 1848a45c6cb8SMadhusudhan Chikkature } 1849a45c6cb8SMadhusudhan Chikkature 1850a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1851a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1852a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1853a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1854a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1855a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 1856a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1857a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1858a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1859fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1860a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18616da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 1862dba3c29eSBalaji T K host->flags = AUTO_CMD12; 18639782aff8SPer Forlin host->next_data.cookie = 1; 1864a45c6cb8SMadhusudhan Chikkature 1865a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1866a45c6cb8SMadhusudhan Chikkature 186770a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1868dd498effSDenis Karpov 1869e0eb2424SAdrian Hunter /* 1870e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1871e0eb2424SAdrian Hunter * no off state. 1872e0eb2424SAdrian Hunter */ 1873e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1874e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1875e0eb2424SAdrian Hunter 18766b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1877d418ed87SDaniel Mack 1878d418ed87SDaniel Mack if (pdata->max_freq > 0) 1879d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1880d418ed87SDaniel Mack else 18816b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1882a45c6cb8SMadhusudhan Chikkature 18834dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1884a45c6cb8SMadhusudhan Chikkature 18856f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1886a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1887a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1888a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1889a45c6cb8SMadhusudhan Chikkature goto err1; 1890a45c6cb8SMadhusudhan Chikkature } 1891a45c6cb8SMadhusudhan Chikkature 18929b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18939b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18949b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18959b68256cSPaul Walmsley } 1896dd498effSDenis Karpov 1897fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1898fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1899fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1900fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1901a45c6cb8SMadhusudhan Chikkature 190292a3aebfSBalaji T K omap_hsmmc_context_save(host); 190392a3aebfSBalaji T K 1904a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1905a45c6cb8SMadhusudhan Chikkature /* 1906a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1907a45c6cb8SMadhusudhan Chikkature */ 1908cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1909cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n"); 1910cd03d9a8SRajendra Nayak host->dbclk = NULL; 1911cd03d9a8SRajendra Nayak } else if (clk_enable(host->dbclk) != 0) { 1912cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1913cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1914cd03d9a8SRajendra Nayak host->dbclk = NULL; 19152bec0893SAdrian Hunter } 1916a45c6cb8SMadhusudhan Chikkature 19170ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19180ccd76d4SJuha Yrjola * as we want. */ 1919a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19200ccd76d4SJuha Yrjola 1921a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1922a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1923a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1924a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1925a45c6cb8SMadhusudhan Chikkature 192613189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 192793caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1928a45c6cb8SMadhusudhan Chikkature 19293a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19303a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1931a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1932a45c6cb8SMadhusudhan Chikkature 1933191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 193423d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 193523d99bb9SAdrian Hunter 19366fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19376fdc75deSEliad Peller 193870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1939a45c6cb8SMadhusudhan Chikkature 1940b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1941b7bf773bSBalaji T K if (!res) { 1942b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 1943f3e2f1ddSGrazvydas Ignotas goto err_irq; 1944a45c6cb8SMadhusudhan Chikkature } 1945b7bf773bSBalaji T K host->dma_line_tx = res->start; 1946b7bf773bSBalaji T K 1947b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1948b7bf773bSBalaji T K if (!res) { 1949b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 1950b7bf773bSBalaji T K goto err_irq; 1951b7bf773bSBalaji T K } 1952b7bf773bSBalaji T K host->dma_line_rx = res->start; 1953a45c6cb8SMadhusudhan Chikkature 1954a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1955d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1956a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1957a45c6cb8SMadhusudhan Chikkature if (ret) { 1958a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1959a45c6cb8SMadhusudhan Chikkature goto err_irq; 1960a45c6cb8SMadhusudhan Chikkature } 1961a45c6cb8SMadhusudhan Chikkature 1962a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1963a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 196470a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 196570a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1966a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1967a45c6cb8SMadhusudhan Chikkature } 1968a45c6cb8SMadhusudhan Chikkature } 1969db0fefc5SAdrian Hunter 1970b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1971db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1972db0fefc5SAdrian Hunter if (ret) 1973db0fefc5SAdrian Hunter goto err_reg; 1974db0fefc5SAdrian Hunter host->use_reg = 1; 1975db0fefc5SAdrian Hunter } 1976db0fefc5SAdrian Hunter 1977b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1978a45c6cb8SMadhusudhan Chikkature 1979a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1980e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19817efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19827efab4f3SNeilBrown NULL, 19837efab4f3SNeilBrown omap_hsmmc_detect, 1984d9618e9fSYong Zhang IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1985a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1986a45c6cb8SMadhusudhan Chikkature if (ret) { 1987a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1988a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1989a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1990a45c6cb8SMadhusudhan Chikkature } 199172f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 199272f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1993a45c6cb8SMadhusudhan Chikkature } 1994a45c6cb8SMadhusudhan Chikkature 1995b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1996a45c6cb8SMadhusudhan Chikkature 1997b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1998b62f6228SAdrian Hunter 1999a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2000a45c6cb8SMadhusudhan Chikkature 2001191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2002a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2003a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2004a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2005a45c6cb8SMadhusudhan Chikkature } 2006191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2007a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2008a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2009a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2010db0fefc5SAdrian Hunter goto err_slot_name; 2011a45c6cb8SMadhusudhan Chikkature } 2012a45c6cb8SMadhusudhan Chikkature 201370a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2014fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2015fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2016d900f712SDenis Karpov 2017a45c6cb8SMadhusudhan Chikkature return 0; 2018a45c6cb8SMadhusudhan Chikkature 2019a45c6cb8SMadhusudhan Chikkature err_slot_name: 2020a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2021a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2022db0fefc5SAdrian Hunter err_irq_cd: 2023db0fefc5SAdrian Hunter if (host->use_reg) 2024db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2025db0fefc5SAdrian Hunter err_reg: 2026db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2027db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2028a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2029a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2030a45c6cb8SMadhusudhan Chikkature err_irq: 2031d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 203237f6190dSTony Lindgren pm_runtime_disable(host->dev); 2033a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2034cd03d9a8SRajendra Nayak if (host->dbclk) { 2035a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2036a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2037a45c6cb8SMadhusudhan Chikkature } 2038a45c6cb8SMadhusudhan Chikkature err1: 2039a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2040db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 2041a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2042db0fefc5SAdrian Hunter err_alloc: 2043db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2044db0fefc5SAdrian Hunter err: 2045984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2046a45c6cb8SMadhusudhan Chikkature return ret; 2047a45c6cb8SMadhusudhan Chikkature } 2048a45c6cb8SMadhusudhan Chikkature 2049efa25fd3SFelipe Balbi static int __devexit omap_hsmmc_remove(struct platform_device *pdev) 2050a45c6cb8SMadhusudhan Chikkature { 205170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2052a45c6cb8SMadhusudhan Chikkature struct resource *res; 2053a45c6cb8SMadhusudhan Chikkature 2054fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2055a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2056db0fefc5SAdrian Hunter if (host->use_reg) 2057db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2058a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2059a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2060a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2061a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2062a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2063a45c6cb8SMadhusudhan Chikkature 2064fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2065fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2066a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2067cd03d9a8SRajendra Nayak if (host->dbclk) { 2068a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2069a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2070a45c6cb8SMadhusudhan Chikkature } 2071a45c6cb8SMadhusudhan Chikkature 2072a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2073a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2074db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2075a45c6cb8SMadhusudhan Chikkature 2076a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2077a45c6cb8SMadhusudhan Chikkature if (res) 2078984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2079a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2080a45c6cb8SMadhusudhan Chikkature 2081a45c6cb8SMadhusudhan Chikkature return 0; 2082a45c6cb8SMadhusudhan Chikkature } 2083a45c6cb8SMadhusudhan Chikkature 2084a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2085a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2086a45c6cb8SMadhusudhan Chikkature { 2087a45c6cb8SMadhusudhan Chikkature int ret = 0; 2088927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2089927ce944SFelipe Balbi 2090927ce944SFelipe Balbi if (!host) 2091927ce944SFelipe Balbi return 0; 2092a45c6cb8SMadhusudhan Chikkature 2093a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2094a45c6cb8SMadhusudhan Chikkature return 0; 2095a45c6cb8SMadhusudhan Chikkature 2096fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2097a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2098a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2099927ce944SFelipe Balbi ret = host->pdata->suspend(dev, host->slot_id); 2100a6b2240dSAdrian Hunter if (ret) { 2101927ce944SFelipe Balbi dev_dbg(dev, "Unable to handle MMC board" 2102a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2103a6b2240dSAdrian Hunter host->suspended = 0; 2104a6b2240dSAdrian Hunter return ret; 2105a45c6cb8SMadhusudhan Chikkature } 2106a6b2240dSAdrian Hunter } 21071a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2108fa4aa2d4SBalaji T K 210931f9d463SEliad Peller if (ret) { 2110a6b2240dSAdrian Hunter host->suspended = 0; 2111a6b2240dSAdrian Hunter if (host->pdata->resume) { 2112927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2113a6b2240dSAdrian Hunter if (ret) 2114927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2115a6b2240dSAdrian Hunter } 211631f9d463SEliad Peller goto err; 2117a6b2240dSAdrian Hunter } 211831f9d463SEliad Peller 211931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 212031f9d463SEliad Peller omap_hsmmc_disable_irq(host); 212131f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 212231f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 212331f9d463SEliad Peller } 2124927ce944SFelipe Balbi 2125cd03d9a8SRajendra Nayak if (host->dbclk) 212631f9d463SEliad Peller clk_disable(host->dbclk); 212731f9d463SEliad Peller err: 2128fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2129a45c6cb8SMadhusudhan Chikkature return ret; 2130a45c6cb8SMadhusudhan Chikkature } 2131a45c6cb8SMadhusudhan Chikkature 2132a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2133a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2134a45c6cb8SMadhusudhan Chikkature { 2135a45c6cb8SMadhusudhan Chikkature int ret = 0; 2136927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2137927ce944SFelipe Balbi 2138927ce944SFelipe Balbi if (!host) 2139927ce944SFelipe Balbi return 0; 2140a45c6cb8SMadhusudhan Chikkature 2141a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2142a45c6cb8SMadhusudhan Chikkature return 0; 2143a45c6cb8SMadhusudhan Chikkature 2144fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 214511dd62a7SDenis Karpov 2146cd03d9a8SRajendra Nayak if (host->dbclk) 21472bec0893SAdrian Hunter clk_enable(host->dbclk); 21482bec0893SAdrian Hunter 214931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 215070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21511b331e69SKim Kyuwon 2152a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2153927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2154a45c6cb8SMadhusudhan Chikkature if (ret) 2155927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2156a45c6cb8SMadhusudhan Chikkature } 2157a45c6cb8SMadhusudhan Chikkature 2158b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2159b62f6228SAdrian Hunter 2160a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2161a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2162a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2163a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2164fa4aa2d4SBalaji T K 2165fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2166fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2167a45c6cb8SMadhusudhan Chikkature 2168a45c6cb8SMadhusudhan Chikkature return ret; 2169a45c6cb8SMadhusudhan Chikkature 2170a45c6cb8SMadhusudhan Chikkature } 2171a45c6cb8SMadhusudhan Chikkature 2172a45c6cb8SMadhusudhan Chikkature #else 217370a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 217470a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2175a45c6cb8SMadhusudhan Chikkature #endif 2176a45c6cb8SMadhusudhan Chikkature 2177fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2178fa4aa2d4SBalaji T K { 2179fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2180fa4aa2d4SBalaji T K 2181fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2182fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2183927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2184fa4aa2d4SBalaji T K 2185fa4aa2d4SBalaji T K return 0; 2186fa4aa2d4SBalaji T K } 2187fa4aa2d4SBalaji T K 2188fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2189fa4aa2d4SBalaji T K { 2190fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2191fa4aa2d4SBalaji T K 2192fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2193fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2194927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2195fa4aa2d4SBalaji T K 2196fa4aa2d4SBalaji T K return 0; 2197fa4aa2d4SBalaji T K } 2198fa4aa2d4SBalaji T K 2199a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 220070a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 220170a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2202fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2203fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2204a791daa1SKevin Hilman }; 2205a791daa1SKevin Hilman 2206a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2207efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 2208efa25fd3SFelipe Balbi .remove = __devexit_p(omap_hsmmc_remove), 2209a45c6cb8SMadhusudhan Chikkature .driver = { 2210a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2211a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2212a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 221346856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2214a45c6cb8SMadhusudhan Chikkature }, 2215a45c6cb8SMadhusudhan Chikkature }; 2216a45c6cb8SMadhusudhan Chikkature 2217b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2218a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2219a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2220a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2221a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2222