1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184e99448ffSBalaji T K struct regulator *pbias; 185e99448ffSBalaji T K bool pbias_enabled; 186a45c6cb8SMadhusudhan Chikkature void __iomem *base; 187a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1884dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 189a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1900ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 191a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 192a3621465SAdrian Hunter unsigned char power_mode; 193a45c6cb8SMadhusudhan Chikkature int suspended; 1940a82e06eSTony Lindgren u32 con; 1950a82e06eSTony Lindgren u32 hctl; 1960a82e06eSTony Lindgren u32 sysctl; 1970a82e06eSTony Lindgren u32 capa; 198a45c6cb8SMadhusudhan Chikkature int irq; 1992cd3a2a5SAndreas Fenkart int wake_irq; 200a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 201c5c98927SRussell King struct dma_chan *tx_chan; 202c5c98927SRussell King struct dma_chan *rx_chan; 2034a694dc9SAdrian Hunter int response_busy; 20411dd62a7SDenis Karpov int context_loss; 205b62f6228SAdrian Hunter int protect_card; 206b62f6228SAdrian Hunter int reqs_blocked; 207b417577dSAdrian Hunter int req_in_progress; 2086e3076c2SBalaji T K unsigned long clk_rate; 209a2e77152SBalaji T K unsigned int flags; 2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2129782aff8SPer Forlin struct omap_hsmmc_next next_data; 21355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 214b5cd43f0SAndreas Fenkart 215b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 216b5cd43f0SAndreas Fenkart * 217b5cd43f0SAndreas Fenkart * possible return values: 218b5cd43f0SAndreas Fenkart * 0 - closed 219b5cd43f0SAndreas Fenkart * 1 - open 220b5cd43f0SAndreas Fenkart */ 22180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 222b5cd43f0SAndreas Fenkart 22380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 224a45c6cb8SMadhusudhan Chikkature }; 225a45c6cb8SMadhusudhan Chikkature 22659445b10SNishanth Menon struct omap_mmc_of_data { 22759445b10SNishanth Menon u32 reg_offset; 22859445b10SNishanth Menon u8 controller_flags; 22959445b10SNishanth Menon }; 23059445b10SNishanth Menon 231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232bf129e1cSBalaji T K 23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236db0fefc5SAdrian Hunter 23741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 241db0fefc5SAdrian Hunter { 2429ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243db0fefc5SAdrian Hunter 24441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 247b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 248b702b106SAdrian Hunter 2492a17f844SKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc, int vdd) 2502a17f844SKishon Vijay Abraham I { 2512a17f844SKishon Vijay Abraham I int ret; 2522a17f844SKishon Vijay Abraham I 2532a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2542a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 2552a17f844SKishon Vijay Abraham I if (ret) 2562a17f844SKishon Vijay Abraham I return ret; 2572a17f844SKishon Vijay Abraham I } 2582a17f844SKishon Vijay Abraham I 2592a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 2602a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 2612a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2622a17f844SKishon Vijay Abraham I if (ret) { 2632a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2642a17f844SKishon Vijay Abraham I goto err_vqmmc; 2652a17f844SKishon Vijay Abraham I } 2662a17f844SKishon Vijay Abraham I } 2672a17f844SKishon Vijay Abraham I 2682a17f844SKishon Vijay Abraham I return 0; 2692a17f844SKishon Vijay Abraham I 2702a17f844SKishon Vijay Abraham I err_vqmmc: 2712a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) 2722a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2732a17f844SKishon Vijay Abraham I 2742a17f844SKishon Vijay Abraham I return ret; 2752a17f844SKishon Vijay Abraham I } 2762a17f844SKishon Vijay Abraham I 2772a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2782a17f844SKishon Vijay Abraham I { 2792a17f844SKishon Vijay Abraham I int ret; 2802a17f844SKishon Vijay Abraham I int status; 2812a17f844SKishon Vijay Abraham I 2822a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 2832a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2842a17f844SKishon Vijay Abraham I if (ret) { 2852a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2862a17f844SKishon Vijay Abraham I return ret; 2872a17f844SKishon Vijay Abraham I } 2882a17f844SKishon Vijay Abraham I } 2892a17f844SKishon Vijay Abraham I 2902a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2912a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2922a17f844SKishon Vijay Abraham I if (ret) 2932a17f844SKishon Vijay Abraham I goto err_set_ocr; 2942a17f844SKishon Vijay Abraham I } 2952a17f844SKishon Vijay Abraham I 2962a17f844SKishon Vijay Abraham I return 0; 2972a17f844SKishon Vijay Abraham I 2982a17f844SKishon Vijay Abraham I err_set_ocr: 2992a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 3002a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3012a17f844SKishon Vijay Abraham I if (status) 3022a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3032a17f844SKishon Vijay Abraham I } 3042a17f844SKishon Vijay Abraham I 3052a17f844SKishon Vijay Abraham I return ret; 3062a17f844SKishon Vijay Abraham I } 3072a17f844SKishon Vijay Abraham I 308ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 309ec85c95eSKishon Vijay Abraham I int vdd) 310ec85c95eSKishon Vijay Abraham I { 311ec85c95eSKishon Vijay Abraham I int ret; 312ec85c95eSKishon Vijay Abraham I 313ec85c95eSKishon Vijay Abraham I if (!host->pbias) 314ec85c95eSKishon Vijay Abraham I return 0; 315ec85c95eSKishon Vijay Abraham I 316ec85c95eSKishon Vijay Abraham I if (power_on) { 317ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 318ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 319ec85c95eSKishon Vijay Abraham I VDD_1V8); 320ec85c95eSKishon Vijay Abraham I else 321ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 322ec85c95eSKishon Vijay Abraham I VDD_3V0); 323ec85c95eSKishon Vijay Abraham I if (ret < 0) { 324ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 325ec85c95eSKishon Vijay Abraham I return ret; 326ec85c95eSKishon Vijay Abraham I } 327ec85c95eSKishon Vijay Abraham I 328ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 0) { 329ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 330ec85c95eSKishon Vijay Abraham I if (ret) { 331ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 332ec85c95eSKishon Vijay Abraham I return ret; 333ec85c95eSKishon Vijay Abraham I } 334ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 1; 335ec85c95eSKishon Vijay Abraham I } 336ec85c95eSKishon Vijay Abraham I } else { 337ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 1) { 338ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 339ec85c95eSKishon Vijay Abraham I if (ret) { 340ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 341ec85c95eSKishon Vijay Abraham I return ret; 342ec85c95eSKishon Vijay Abraham I } 343ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 0; 344ec85c95eSKishon Vijay Abraham I } 345ec85c95eSKishon Vijay Abraham I } 346ec85c95eSKishon Vijay Abraham I 347ec85c95eSKishon Vijay Abraham I return 0; 348ec85c95eSKishon Vijay Abraham I } 349ec85c95eSKishon Vijay Abraham I 35080412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 351db0fefc5SAdrian Hunter { 352db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 353db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 354aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 355db0fefc5SAdrian Hunter int ret = 0; 356db0fefc5SAdrian Hunter 357f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 358f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 359f7f0f035SAndreas Fenkart 360db0fefc5SAdrian Hunter /* 361db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 362db0fefc5SAdrian Hunter * voltage always-on regulator. 363db0fefc5SAdrian Hunter */ 364aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 365db0fefc5SAdrian Hunter return 0; 366db0fefc5SAdrian Hunter 367326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 36880412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 369db0fefc5SAdrian Hunter 370ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 371ec85c95eSKishon Vijay Abraham I if (ret) 372229f3292SKishon Vijay Abraham I return ret; 373e99448ffSBalaji T K 374db0fefc5SAdrian Hunter /* 375db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 376db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 377db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 378db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 379db0fefc5SAdrian Hunter * 380db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 381db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 382db0fefc5SAdrian Hunter * 383db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 384db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 385db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 386db0fefc5SAdrian Hunter */ 387db0fefc5SAdrian Hunter if (power_on) { 3882a17f844SKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc, vdd); 389229f3292SKishon Vijay Abraham I if (ret) 390229f3292SKishon Vijay Abraham I return ret; 39197fe7e5aSKishon Vijay Abraham I 39297fe7e5aSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 39397fe7e5aSKishon Vijay Abraham I if (ret) 39497fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 395db0fefc5SAdrian Hunter } else { 3962a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 397229f3292SKishon Vijay Abraham I if (ret) 398229f3292SKishon Vijay Abraham I return ret; 39999fc5131SLinus Walleij } 400db0fefc5SAdrian Hunter 401326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 40280412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 403db0fefc5SAdrian Hunter 404229f3292SKishon Vijay Abraham I return 0; 405229f3292SKishon Vijay Abraham I 406229f3292SKishon Vijay Abraham I err_set_voltage: 4072a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 408229f3292SKishon Vijay Abraham I 409db0fefc5SAdrian Hunter return ret; 410db0fefc5SAdrian Hunter } 411db0fefc5SAdrian Hunter 412c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 413c8518efaSKishon Vijay Abraham I { 414c8518efaSKishon Vijay Abraham I int ret; 415c8518efaSKishon Vijay Abraham I 416c8518efaSKishon Vijay Abraham I if (!reg) 417c8518efaSKishon Vijay Abraham I return 0; 418c8518efaSKishon Vijay Abraham I 419c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 420c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 421c8518efaSKishon Vijay Abraham I if (ret) 422c8518efaSKishon Vijay Abraham I return ret; 423c8518efaSKishon Vijay Abraham I 424c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 425c8518efaSKishon Vijay Abraham I if (ret) 426c8518efaSKishon Vijay Abraham I return ret; 427c8518efaSKishon Vijay Abraham I } 428c8518efaSKishon Vijay Abraham I 429c8518efaSKishon Vijay Abraham I return 0; 430c8518efaSKishon Vijay Abraham I } 431c8518efaSKishon Vijay Abraham I 432c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 433c8518efaSKishon Vijay Abraham I { 434c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 435c8518efaSKishon Vijay Abraham I int ret; 436c8518efaSKishon Vijay Abraham I 437c8518efaSKishon Vijay Abraham I /* 438c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 439c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 440c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 441c8518efaSKishon Vijay Abraham I */ 442c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 443c8518efaSKishon Vijay Abraham I if (ret) { 444c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 445c8518efaSKishon Vijay Abraham I return ret; 446c8518efaSKishon Vijay Abraham I } 447c8518efaSKishon Vijay Abraham I 448c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 449c8518efaSKishon Vijay Abraham I if (ret) { 450c8518efaSKishon Vijay Abraham I dev_err(host->dev, 451c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 452c8518efaSKishon Vijay Abraham I return ret; 453c8518efaSKishon Vijay Abraham I } 454c8518efaSKishon Vijay Abraham I 455c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 456c8518efaSKishon Vijay Abraham I if (ret) { 457c8518efaSKishon Vijay Abraham I dev_err(host->dev, 458c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 459c8518efaSKishon Vijay Abraham I return ret; 460c8518efaSKishon Vijay Abraham I } 461c8518efaSKishon Vijay Abraham I 462c8518efaSKishon Vijay Abraham I return 0; 463c8518efaSKishon Vijay Abraham I } 464c8518efaSKishon Vijay Abraham I 465db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 466db0fefc5SAdrian Hunter { 46764be9782Skishore kadiyala int ocr_value = 0; 4687d607f91SKishon Vijay Abraham I int ret; 469aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 470db0fefc5SAdrian Hunter 471f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 472f7f0f035SAndreas Fenkart return 0; 473f7f0f035SAndreas Fenkart 474aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 475aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 476aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 4777d607f91SKishon Vijay Abraham I if (ret != -ENODEV) 4787d607f91SKishon Vijay Abraham I return ret; 4797d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 480aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 481aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 482db0fefc5SAdrian Hunter } else { 483aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 484b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 485326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 486987fd49bSBalaji T K } 487db0fefc5SAdrian Hunter 488db0fefc5SAdrian Hunter /* Allow an aux regulator */ 489aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 490aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 491aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 4926a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 4936a9b2ff0SKishon Vijay Abraham I return ret; 4946a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 495aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 496aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 4976a9b2ff0SKishon Vijay Abraham I } 498db0fefc5SAdrian Hunter 499c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 500c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 501c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 5026a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 5036a9b2ff0SKishon Vijay Abraham I return ret; 5046a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 505c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 506c299dc39SKishon Vijay Abraham I host->pbias = NULL; 5076a9b2ff0SKishon Vijay Abraham I } 508e99448ffSBalaji T K 509b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 510326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 511b1c1df7aSBalaji T K return 0; 512e840ce13SAdrian Hunter 513c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 514c8518efaSKishon Vijay Abraham I if (ret) 515c8518efaSKishon Vijay Abraham I return ret; 516db0fefc5SAdrian Hunter 517db0fefc5SAdrian Hunter return 0; 518db0fefc5SAdrian Hunter } 519db0fefc5SAdrian Hunter 520b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 521b702b106SAdrian Hunter { 522b702b106SAdrian Hunter return 1; 523b702b106SAdrian Hunter } 524b702b106SAdrian Hunter 525b702b106SAdrian Hunter #else 526b702b106SAdrian Hunter 527f7f0f035SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 528f7f0f035SAndreas Fenkart { 529f7f0f035SAndreas Fenkart return 0; 530f7f0f035SAndreas Fenkart } 531f7f0f035SAndreas Fenkart 532b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 533b702b106SAdrian Hunter { 534b702b106SAdrian Hunter return -EINVAL; 535b702b106SAdrian Hunter } 536b702b106SAdrian Hunter 537b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 538b702b106SAdrian Hunter { 539b702b106SAdrian Hunter return 0; 540b702b106SAdrian Hunter } 541b702b106SAdrian Hunter 542b702b106SAdrian Hunter #endif 543b702b106SAdrian Hunter 544cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 54541afa314SNeilBrown 54641afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 54741afa314SNeilBrown struct omap_hsmmc_host *host, 5481e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 549b702b106SAdrian Hunter { 550b702b106SAdrian Hunter int ret; 551b702b106SAdrian Hunter 552b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 553b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 554b702b106SAdrian Hunter if (ret) 555b702b106SAdrian Hunter return ret; 556cde592cbSAndreas Fenkart 557cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 558cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 559b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 560b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 561cde592cbSAndreas Fenkart if (ret) 562cde592cbSAndreas Fenkart return ret; 563cde592cbSAndreas Fenkart 564cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 565326119c9SAndreas Fenkart } 566b702b106SAdrian Hunter 567326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 56841afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 569b702b106SAdrian Hunter if (ret) 57041afa314SNeilBrown return ret; 571326119c9SAndreas Fenkart } 572b702b106SAdrian Hunter 573b702b106SAdrian Hunter return 0; 574b702b106SAdrian Hunter } 575b702b106SAdrian Hunter 576a45c6cb8SMadhusudhan Chikkature /* 577e0c7f99bSAndy Shevchenko * Start clock to the card 578e0c7f99bSAndy Shevchenko */ 579e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 580e0c7f99bSAndy Shevchenko { 581e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 582e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 583e0c7f99bSAndy Shevchenko } 584e0c7f99bSAndy Shevchenko 585e0c7f99bSAndy Shevchenko /* 586a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 587a45c6cb8SMadhusudhan Chikkature */ 58870a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 589a45c6cb8SMadhusudhan Chikkature { 590a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 591a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 592a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5937122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 594a45c6cb8SMadhusudhan Chikkature } 595a45c6cb8SMadhusudhan Chikkature 59693caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 59793caf8e6SAdrian Hunter struct mmc_command *cmd) 598b417577dSAdrian Hunter { 5992cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 6002cd3a2a5SAndreas Fenkart unsigned long flags; 601b417577dSAdrian Hunter 602b417577dSAdrian Hunter if (host->use_dma) 6032cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 604b417577dSAdrian Hunter 60593caf8e6SAdrian Hunter /* Disable timeout for erases */ 60693caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 607a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 60893caf8e6SAdrian Hunter 6092cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 610b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 611b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6122cd3a2a5SAndreas Fenkart 6132cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 6142cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6152cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 616b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 6172cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 618b417577dSAdrian Hunter } 619b417577dSAdrian Hunter 620b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 621b417577dSAdrian Hunter { 6222cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 6232cd3a2a5SAndreas Fenkart unsigned long flags; 6242cd3a2a5SAndreas Fenkart 6252cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 6262cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 6272cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6282cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 6292cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6302cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 631b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 6322cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 633b417577dSAdrian Hunter } 634b417577dSAdrian Hunter 635ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 636d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 637ac330f44SAndy Shevchenko { 638ac330f44SAndy Shevchenko u16 dsor = 0; 639ac330f44SAndy Shevchenko 640ac330f44SAndy Shevchenko if (ios->clock) { 641d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 642ed164182SBalaji T K if (dsor > CLKD_MAX) 643ed164182SBalaji T K dsor = CLKD_MAX; 644ac330f44SAndy Shevchenko } 645ac330f44SAndy Shevchenko 646ac330f44SAndy Shevchenko return dsor; 647ac330f44SAndy Shevchenko } 648ac330f44SAndy Shevchenko 6495934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6505934df2fSAndy Shevchenko { 6515934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6525934df2fSAndy Shevchenko unsigned long regval; 6535934df2fSAndy Shevchenko unsigned long timeout; 654cd587096SHebbar, Gururaja unsigned long clkdiv; 6555934df2fSAndy Shevchenko 6568986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6575934df2fSAndy Shevchenko 6585934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6595934df2fSAndy Shevchenko 6605934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6615934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 662cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 663cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6645934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6655934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6665934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6675934df2fSAndy Shevchenko 6685934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6695934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6705934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6715934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6725934df2fSAndy Shevchenko cpu_relax(); 6735934df2fSAndy Shevchenko 674cd587096SHebbar, Gururaja /* 675cd587096SHebbar, Gururaja * Enable High-Speed Support 676cd587096SHebbar, Gururaja * Pre-Requisites 677cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 678cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 679cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 680cd587096SHebbar, Gururaja * in capabilities register 681cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 682cd587096SHebbar, Gururaja */ 683326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6845438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 685903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 686cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 687cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 688cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 689cd587096SHebbar, Gururaja regval |= HSPE; 690cd587096SHebbar, Gururaja else 691cd587096SHebbar, Gururaja regval &= ~HSPE; 692cd587096SHebbar, Gururaja 693cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 694cd587096SHebbar, Gururaja } 695cd587096SHebbar, Gururaja 6965934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6975934df2fSAndy Shevchenko } 6985934df2fSAndy Shevchenko 6993796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 7003796fb8aSAndy Shevchenko { 7013796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7023796fb8aSAndy Shevchenko u32 con; 7033796fb8aSAndy Shevchenko 7043796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 705903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 706903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 70703b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 70803b5d924SBalaji T K else 70903b5d924SBalaji T K con &= ~DDR; 7103796fb8aSAndy Shevchenko switch (ios->bus_width) { 7113796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 7123796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 7133796fb8aSAndy Shevchenko break; 7143796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 7153796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7163796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7173796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 7183796fb8aSAndy Shevchenko break; 7193796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 7203796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7213796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7223796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 7233796fb8aSAndy Shevchenko break; 7243796fb8aSAndy Shevchenko } 7253796fb8aSAndy Shevchenko } 7263796fb8aSAndy Shevchenko 7273796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 7283796fb8aSAndy Shevchenko { 7293796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7303796fb8aSAndy Shevchenko u32 con; 7313796fb8aSAndy Shevchenko 7323796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 7333796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 7343796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 7353796fb8aSAndy Shevchenko else 7363796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 7373796fb8aSAndy Shevchenko } 7383796fb8aSAndy Shevchenko 73911dd62a7SDenis Karpov #ifdef CONFIG_PM 74011dd62a7SDenis Karpov 74111dd62a7SDenis Karpov /* 74211dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 74311dd62a7SDenis Karpov * power state change. 74411dd62a7SDenis Karpov */ 74570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 74611dd62a7SDenis Karpov { 74711dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7483796fb8aSAndy Shevchenko u32 hctl, capa; 74911dd62a7SDenis Karpov unsigned long timeout; 75011dd62a7SDenis Karpov 7510a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7520a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7530a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7540a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7550a82e06eSTony Lindgren return 0; 7560a82e06eSTony Lindgren 7570a82e06eSTony Lindgren host->context_loss++; 7580a82e06eSTony Lindgren 759c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 76011dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 76111dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 76211dd62a7SDenis Karpov hctl = SDVS18; 76311dd62a7SDenis Karpov else 76411dd62a7SDenis Karpov hctl = SDVS30; 76511dd62a7SDenis Karpov capa = VS30 | VS18; 76611dd62a7SDenis Karpov } else { 76711dd62a7SDenis Karpov hctl = SDVS18; 76811dd62a7SDenis Karpov capa = VS18; 76911dd62a7SDenis Karpov } 77011dd62a7SDenis Karpov 7715a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7725a52b08bSBalaji T K hctl |= IWE; 7735a52b08bSBalaji T K 77411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 77511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 77611dd62a7SDenis Karpov 77711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 77811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 77911dd62a7SDenis Karpov 78011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 78111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 78211dd62a7SDenis Karpov 78311dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 78411dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 78511dd62a7SDenis Karpov && time_before(jiffies, timeout)) 78611dd62a7SDenis Karpov ; 78711dd62a7SDenis Karpov 7882cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7892cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7902cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 79111dd62a7SDenis Karpov 79211dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 79311dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 79411dd62a7SDenis Karpov goto out; 79511dd62a7SDenis Karpov 7963796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 79711dd62a7SDenis Karpov 7985934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 79911dd62a7SDenis Karpov 8003796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 8013796fb8aSAndy Shevchenko 80211dd62a7SDenis Karpov out: 8030a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 8040a82e06eSTony Lindgren host->context_loss); 80511dd62a7SDenis Karpov return 0; 80611dd62a7SDenis Karpov } 80711dd62a7SDenis Karpov 80811dd62a7SDenis Karpov /* 80911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 81011dd62a7SDenis Karpov */ 81170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 81211dd62a7SDenis Karpov { 8130a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 8140a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 8150a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 8160a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 81711dd62a7SDenis Karpov } 81811dd62a7SDenis Karpov 81911dd62a7SDenis Karpov #else 82011dd62a7SDenis Karpov 82170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 82211dd62a7SDenis Karpov { 82311dd62a7SDenis Karpov return 0; 82411dd62a7SDenis Karpov } 82511dd62a7SDenis Karpov 82670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 82711dd62a7SDenis Karpov { 82811dd62a7SDenis Karpov } 82911dd62a7SDenis Karpov 83011dd62a7SDenis Karpov #endif 83111dd62a7SDenis Karpov 832a45c6cb8SMadhusudhan Chikkature /* 833a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 834a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 835a45c6cb8SMadhusudhan Chikkature */ 83670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 837a45c6cb8SMadhusudhan Chikkature { 838a45c6cb8SMadhusudhan Chikkature int reg = 0; 839a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 840a45c6cb8SMadhusudhan Chikkature 841b62f6228SAdrian Hunter if (host->protect_card) 842b62f6228SAdrian Hunter return; 843b62f6228SAdrian Hunter 844a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 845b417577dSAdrian Hunter 846b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 847a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 848a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 849a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 850a45c6cb8SMadhusudhan Chikkature 851a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 852a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 853a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 854a45c6cb8SMadhusudhan Chikkature 855a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 856a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 857c653a6d4SAdrian Hunter 858c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 859c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 860c653a6d4SAdrian Hunter 861a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 862a45c6cb8SMadhusudhan Chikkature } 863a45c6cb8SMadhusudhan Chikkature 864a45c6cb8SMadhusudhan Chikkature static inline 86570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 866a45c6cb8SMadhusudhan Chikkature { 867a45c6cb8SMadhusudhan Chikkature int r = 1; 868a45c6cb8SMadhusudhan Chikkature 869b5cd43f0SAndreas Fenkart if (host->get_cover_state) 87080412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 871a45c6cb8SMadhusudhan Chikkature return r; 872a45c6cb8SMadhusudhan Chikkature } 873a45c6cb8SMadhusudhan Chikkature 874a45c6cb8SMadhusudhan Chikkature static ssize_t 87570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 876a45c6cb8SMadhusudhan Chikkature char *buf) 877a45c6cb8SMadhusudhan Chikkature { 878a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 87970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 880a45c6cb8SMadhusudhan Chikkature 88170a3341aSDenis Karpov return sprintf(buf, "%s\n", 88270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 883a45c6cb8SMadhusudhan Chikkature } 884a45c6cb8SMadhusudhan Chikkature 88570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 886a45c6cb8SMadhusudhan Chikkature 887a45c6cb8SMadhusudhan Chikkature static ssize_t 88870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 889a45c6cb8SMadhusudhan Chikkature char *buf) 890a45c6cb8SMadhusudhan Chikkature { 891a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 89270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 893a45c6cb8SMadhusudhan Chikkature 894326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 895a45c6cb8SMadhusudhan Chikkature } 896a45c6cb8SMadhusudhan Chikkature 89770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 898a45c6cb8SMadhusudhan Chikkature 899a45c6cb8SMadhusudhan Chikkature /* 900a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 901a45c6cb8SMadhusudhan Chikkature */ 902a45c6cb8SMadhusudhan Chikkature static void 90370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 904a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 905a45c6cb8SMadhusudhan Chikkature { 906a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 907a45c6cb8SMadhusudhan Chikkature 9088986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 909a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 910a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 911a45c6cb8SMadhusudhan Chikkature 91293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 913a45c6cb8SMadhusudhan Chikkature 9144a694dc9SAdrian Hunter host->response_busy = 0; 915a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 916a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 917a45c6cb8SMadhusudhan Chikkature resptype = 1; 9184a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 9194a694dc9SAdrian Hunter resptype = 3; 9204a694dc9SAdrian Hunter host->response_busy = 1; 9214a694dc9SAdrian Hunter } else 922a45c6cb8SMadhusudhan Chikkature resptype = 2; 923a45c6cb8SMadhusudhan Chikkature } 924a45c6cb8SMadhusudhan Chikkature 925a45c6cb8SMadhusudhan Chikkature /* 926a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 927a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 928a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 929a45c6cb8SMadhusudhan Chikkature */ 930a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 931a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 932a45c6cb8SMadhusudhan Chikkature 933a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 934a45c6cb8SMadhusudhan Chikkature 935a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 936a2e77152SBalaji T K host->mrq->sbc) { 937a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 938a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 939a2e77152SBalaji T K } 940a45c6cb8SMadhusudhan Chikkature if (data) { 941a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 942a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 943a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 944a45c6cb8SMadhusudhan Chikkature else 945a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 946a45c6cb8SMadhusudhan Chikkature } 947a45c6cb8SMadhusudhan Chikkature 948a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 949a7e96879SVenkatraman S cmdreg |= DMAE; 950a45c6cb8SMadhusudhan Chikkature 951b417577dSAdrian Hunter host->req_in_progress = 1; 9524dffd7a2SAdrian Hunter 953a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 954a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 955a45c6cb8SMadhusudhan Chikkature } 956a45c6cb8SMadhusudhan Chikkature 9570ccd76d4SJuha Yrjola static int 95870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9590ccd76d4SJuha Yrjola { 9600ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9610ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9620ccd76d4SJuha Yrjola else 9630ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9640ccd76d4SJuha Yrjola } 9650ccd76d4SJuha Yrjola 966c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 967c5c98927SRussell King struct mmc_data *data) 968c5c98927SRussell King { 969c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 970c5c98927SRussell King } 971c5c98927SRussell King 972b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 973b417577dSAdrian Hunter { 974b417577dSAdrian Hunter int dma_ch; 97531463b14SVenkatraman S unsigned long flags; 976b417577dSAdrian Hunter 97731463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 978b417577dSAdrian Hunter host->req_in_progress = 0; 979b417577dSAdrian Hunter dma_ch = host->dma_ch; 98031463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 981b417577dSAdrian Hunter 982b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 983b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 984b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 985b417577dSAdrian Hunter return; 986b417577dSAdrian Hunter host->mrq = NULL; 987b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 988f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 989f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 990b417577dSAdrian Hunter } 991b417577dSAdrian Hunter 992a45c6cb8SMadhusudhan Chikkature /* 993a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 994a45c6cb8SMadhusudhan Chikkature */ 995a45c6cb8SMadhusudhan Chikkature static void 99670a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 997a45c6cb8SMadhusudhan Chikkature { 9984a694dc9SAdrian Hunter if (!data) { 9994a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 10004a694dc9SAdrian Hunter 100123050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 100223050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 100323050103SAdrian Hunter host->response_busy) { 100423050103SAdrian Hunter host->response_busy = 0; 100523050103SAdrian Hunter return; 100623050103SAdrian Hunter } 100723050103SAdrian Hunter 1008b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 10094a694dc9SAdrian Hunter return; 10104a694dc9SAdrian Hunter } 10114a694dc9SAdrian Hunter 1012a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1013a45c6cb8SMadhusudhan Chikkature 1014a45c6cb8SMadhusudhan Chikkature if (!data->error) 1015a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 1016a45c6cb8SMadhusudhan Chikkature else 1017a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 1018a45c6cb8SMadhusudhan Chikkature 1019bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 1020fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 1021bf129e1cSBalaji T K else 1022bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 1023a45c6cb8SMadhusudhan Chikkature } 1024a45c6cb8SMadhusudhan Chikkature 1025a45c6cb8SMadhusudhan Chikkature /* 1026a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 1027a45c6cb8SMadhusudhan Chikkature */ 1028a45c6cb8SMadhusudhan Chikkature static void 102970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 1030a45c6cb8SMadhusudhan Chikkature { 1031bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 1032a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 10332177fa94SBalaji T K host->cmd = NULL; 1034bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 1035bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 1036bf129e1cSBalaji T K host->mrq->data); 1037bf129e1cSBalaji T K return; 1038bf129e1cSBalaji T K } 1039bf129e1cSBalaji T K 10402177fa94SBalaji T K host->cmd = NULL; 10412177fa94SBalaji T K 1042a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 1043a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 1044a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 1045a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1046a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1047a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1048a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1049a45c6cb8SMadhusudhan Chikkature } else { 1050a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1051a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1052a45c6cb8SMadhusudhan Chikkature } 1053a45c6cb8SMadhusudhan Chikkature } 1054b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1055d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1056a45c6cb8SMadhusudhan Chikkature } 1057a45c6cb8SMadhusudhan Chikkature 1058a45c6cb8SMadhusudhan Chikkature /* 1059a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1060a45c6cb8SMadhusudhan Chikkature */ 106170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1062a45c6cb8SMadhusudhan Chikkature { 1063b417577dSAdrian Hunter int dma_ch; 106431463b14SVenkatraman S unsigned long flags; 1065b417577dSAdrian Hunter 106682788ff5SJarkko Lavinen host->data->error = errno; 1067a45c6cb8SMadhusudhan Chikkature 106831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1069b417577dSAdrian Hunter dma_ch = host->dma_ch; 1070b417577dSAdrian Hunter host->dma_ch = -1; 107131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1072b417577dSAdrian Hunter 1073b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1074c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1075c5c98927SRussell King 1076c5c98927SRussell King dmaengine_terminate_all(chan); 1077c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1078c5c98927SRussell King host->data->sg, host->data->sg_len, 107970a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1080c5c98927SRussell King 1081053bf34fSPer Forlin host->data->host_cookie = 0; 1082a45c6cb8SMadhusudhan Chikkature } 1083a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1084a45c6cb8SMadhusudhan Chikkature } 1085a45c6cb8SMadhusudhan Chikkature 1086a45c6cb8SMadhusudhan Chikkature /* 1087a45c6cb8SMadhusudhan Chikkature * Readable error output 1088a45c6cb8SMadhusudhan Chikkature */ 1089a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1090699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1091a45c6cb8SMadhusudhan Chikkature { 1092a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 109370a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1094699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1095699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1096699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1097699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1098a45c6cb8SMadhusudhan Chikkature }; 1099a45c6cb8SMadhusudhan Chikkature char res[256]; 1100a45c6cb8SMadhusudhan Chikkature char *buf = res; 1101a45c6cb8SMadhusudhan Chikkature int len, i; 1102a45c6cb8SMadhusudhan Chikkature 1103a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1104a45c6cb8SMadhusudhan Chikkature buf += len; 1105a45c6cb8SMadhusudhan Chikkature 110670a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1107a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 110870a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1109a45c6cb8SMadhusudhan Chikkature buf += len; 1110a45c6cb8SMadhusudhan Chikkature } 1111a45c6cb8SMadhusudhan Chikkature 11128986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1113a45c6cb8SMadhusudhan Chikkature } 1114699b958bSAdrian Hunter #else 1115699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1116699b958bSAdrian Hunter u32 status) 1117699b958bSAdrian Hunter { 1118699b958bSAdrian Hunter } 1119a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1120a45c6cb8SMadhusudhan Chikkature 11213ebf74b1SJean Pihet /* 11223ebf74b1SJean Pihet * MMC controller internal state machines reset 11233ebf74b1SJean Pihet * 11243ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 11253ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 11263ebf74b1SJean Pihet * Can be called from interrupt context 11273ebf74b1SJean Pihet */ 112870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 11293ebf74b1SJean Pihet unsigned long bit) 11303ebf74b1SJean Pihet { 11313ebf74b1SJean Pihet unsigned long i = 0; 11321e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 11333ebf74b1SJean Pihet 11343ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 11353ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 11363ebf74b1SJean Pihet 113707ad64b6SMadhusudhan Chikkature /* 113807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 113907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 114007ad64b6SMadhusudhan Chikkature */ 1141326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1142b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 114307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 11441e881786SJianpeng Ma udelay(1); 114507ad64b6SMadhusudhan Chikkature } 114607ad64b6SMadhusudhan Chikkature i = 0; 114707ad64b6SMadhusudhan Chikkature 11483ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 11493ebf74b1SJean Pihet (i++ < limit)) 11501e881786SJianpeng Ma udelay(1); 11513ebf74b1SJean Pihet 11523ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11533ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11543ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11553ebf74b1SJean Pihet __func__); 11563ebf74b1SJean Pihet } 1157a45c6cb8SMadhusudhan Chikkature 115825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 115925e1897bSBalaji T K int err, int end_cmd) 1160ae4bf788SVenkatraman S { 116125e1897bSBalaji T K if (end_cmd) { 116294d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 116325e1897bSBalaji T K if (host->cmd) 1164ae4bf788SVenkatraman S host->cmd->error = err; 116525e1897bSBalaji T K } 1166ae4bf788SVenkatraman S 1167ae4bf788SVenkatraman S if (host->data) { 1168ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1169ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1170dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1171dc7745bdSBalaji T K host->mrq->cmd->error = err; 1172ae4bf788SVenkatraman S } 1173ae4bf788SVenkatraman S 1174b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1175a45c6cb8SMadhusudhan Chikkature { 1176a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1177b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1178a2e77152SBalaji T K int error = 0; 1179a45c6cb8SMadhusudhan Chikkature 1180a45c6cb8SMadhusudhan Chikkature data = host->data; 11818986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1182a45c6cb8SMadhusudhan Chikkature 1183a7e96879SVenkatraman S if (status & ERR_EN) { 1184699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11854a694dc9SAdrian Hunter 1186a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1187a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1188408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1189408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1190408806f7SKishon Vijay Abraham I host->response_busy = 0; 1191408806f7SKishon Vijay Abraham I } 1192a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 119325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11945027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11955027cd1eSVignesh R BADA_EN)) 119625e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 119725e1897bSBalaji T K 1198a2e77152SBalaji T K if (status & ACE_EN) { 1199a2e77152SBalaji T K u32 ac12; 1200a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1201a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1202a2e77152SBalaji T K end_cmd = 1; 1203a2e77152SBalaji T K if (ac12 & ACTO) 1204a2e77152SBalaji T K error = -ETIMEDOUT; 1205a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1206a2e77152SBalaji T K error = -EILSEQ; 1207a2e77152SBalaji T K host->mrq->sbc->error = error; 1208a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1209a2e77152SBalaji T K } 1210a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1211a2e77152SBalaji T K } 1212a45c6cb8SMadhusudhan Chikkature } 1213a45c6cb8SMadhusudhan Chikkature 12147472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1215a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 121670a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1217a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 121870a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1219b417577dSAdrian Hunter } 1220a45c6cb8SMadhusudhan Chikkature 1221b417577dSAdrian Hunter /* 1222b417577dSAdrian Hunter * MMC controller IRQ handler 1223b417577dSAdrian Hunter */ 1224b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1225b417577dSAdrian Hunter { 1226b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1227b417577dSAdrian Hunter int status; 1228b417577dSAdrian Hunter 1229b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12302cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 12312cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1232b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 12331f6b9fa4SVenkatraman S 12342cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 12352cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 12362cd3a2a5SAndreas Fenkart 1237b417577dSAdrian Hunter /* Flush posted write */ 1238b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12391f6b9fa4SVenkatraman S } 12404dffd7a2SAdrian Hunter 1241a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1242a45c6cb8SMadhusudhan Chikkature } 1243a45c6cb8SMadhusudhan Chikkature 124470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1245e13bb300SAdrian Hunter { 1246e13bb300SAdrian Hunter unsigned long i; 1247e13bb300SAdrian Hunter 1248e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1249e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1250e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1251e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1252e13bb300SAdrian Hunter break; 1253e13bb300SAdrian Hunter cpu_relax(); 1254e13bb300SAdrian Hunter } 1255e13bb300SAdrian Hunter } 1256e13bb300SAdrian Hunter 1257a45c6cb8SMadhusudhan Chikkature /* 1258eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1259eb250826SDavid Brownell * 1260eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1261eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1262eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1263a45c6cb8SMadhusudhan Chikkature */ 126470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1265a45c6cb8SMadhusudhan Chikkature { 1266a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1267a45c6cb8SMadhusudhan Chikkature int ret; 1268a45c6cb8SMadhusudhan Chikkature 1269a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1270fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1271cd03d9a8SRajendra Nayak if (host->dbclk) 127294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1273a45c6cb8SMadhusudhan Chikkature 1274a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1275f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1276a45c6cb8SMadhusudhan Chikkature 1277a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12782bec0893SAdrian Hunter if (!ret) 1279f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1280fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1281cd03d9a8SRajendra Nayak if (host->dbclk) 128294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12832bec0893SAdrian Hunter 1284a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1285a45c6cb8SMadhusudhan Chikkature goto err; 1286a45c6cb8SMadhusudhan Chikkature 1287a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1288a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1289a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1290eb250826SDavid Brownell 1291a45c6cb8SMadhusudhan Chikkature /* 1292a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1293a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 129470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1295a45c6cb8SMadhusudhan Chikkature * 1296eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1297eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1298eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1299eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1300eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1301eb250826SDavid Brownell * 1302eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1303eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1304eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1305a45c6cb8SMadhusudhan Chikkature */ 1306eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1307a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1308eb250826SDavid Brownell else 1309eb250826SDavid Brownell reg_val |= SDVS30; 1310a45c6cb8SMadhusudhan Chikkature 1311a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1312e13bb300SAdrian Hunter set_sd_bus_power(host); 1313a45c6cb8SMadhusudhan Chikkature 1314a45c6cb8SMadhusudhan Chikkature return 0; 1315a45c6cb8SMadhusudhan Chikkature err: 1316b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1317a45c6cb8SMadhusudhan Chikkature return ret; 1318a45c6cb8SMadhusudhan Chikkature } 1319a45c6cb8SMadhusudhan Chikkature 1320b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1321b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1322b62f6228SAdrian Hunter { 1323b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1324b62f6228SAdrian Hunter return; 1325b62f6228SAdrian Hunter 1326b62f6228SAdrian Hunter host->reqs_blocked = 0; 132780412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1328b62f6228SAdrian Hunter if (host->protect_card) { 13292cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1330b62f6228SAdrian Hunter "card is now accessible\n", 1331b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1332b62f6228SAdrian Hunter host->protect_card = 0; 1333b62f6228SAdrian Hunter } 1334b62f6228SAdrian Hunter } else { 1335b62f6228SAdrian Hunter if (!host->protect_card) { 13362cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1337b62f6228SAdrian Hunter "card is now inaccessible\n", 1338b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1339b62f6228SAdrian Hunter host->protect_card = 1; 1340b62f6228SAdrian Hunter } 1341b62f6228SAdrian Hunter } 1342b62f6228SAdrian Hunter } 1343b62f6228SAdrian Hunter 1344a45c6cb8SMadhusudhan Chikkature /* 1345cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1346cde592cbSAndreas Fenkart */ 1347cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1348cde592cbSAndreas Fenkart { 1349cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1350cde592cbSAndreas Fenkart 1351cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1352cde592cbSAndreas Fenkart 1353cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1354cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1355cde592cbSAndreas Fenkart return IRQ_HANDLED; 1356cde592cbSAndreas Fenkart } 1357cde592cbSAndreas Fenkart 1358c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13590ccd76d4SJuha Yrjola { 1360c5c98927SRussell King struct omap_hsmmc_host *host = param; 1361c5c98927SRussell King struct dma_chan *chan; 1362770d7432SAdrian Hunter struct mmc_data *data; 1363c5c98927SRussell King int req_in_progress; 1364a45c6cb8SMadhusudhan Chikkature 1365c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1366b417577dSAdrian Hunter if (host->dma_ch < 0) { 1367c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1368a45c6cb8SMadhusudhan Chikkature return; 1369b417577dSAdrian Hunter } 1370a45c6cb8SMadhusudhan Chikkature 1371770d7432SAdrian Hunter data = host->mrq->data; 1372c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13739782aff8SPer Forlin if (!data->host_cookie) 1374c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1375c5c98927SRussell King data->sg, data->sg_len, 1376b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1377b417577dSAdrian Hunter 1378b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1379a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1380c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1381b417577dSAdrian Hunter 1382b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1383b417577dSAdrian Hunter if (!req_in_progress) { 1384b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1385b417577dSAdrian Hunter 1386b417577dSAdrian Hunter host->mrq = NULL; 1387b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1388f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1389f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1390b417577dSAdrian Hunter } 1391a45c6cb8SMadhusudhan Chikkature } 1392a45c6cb8SMadhusudhan Chikkature 13939782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13949782aff8SPer Forlin struct mmc_data *data, 1395c5c98927SRussell King struct omap_hsmmc_next *next, 139626b88520SRussell King struct dma_chan *chan) 13979782aff8SPer Forlin { 13989782aff8SPer Forlin int dma_len; 13999782aff8SPer Forlin 14009782aff8SPer Forlin if (!next && data->host_cookie && 14019782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 14022cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 14039782aff8SPer Forlin " host->next_data.cookie %d\n", 14049782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 14059782aff8SPer Forlin data->host_cookie = 0; 14069782aff8SPer Forlin } 14079782aff8SPer Forlin 14089782aff8SPer Forlin /* Check if next job is already prepared */ 1409b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 141026b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 14119782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14129782aff8SPer Forlin 14139782aff8SPer Forlin } else { 14149782aff8SPer Forlin dma_len = host->next_data.dma_len; 14159782aff8SPer Forlin host->next_data.dma_len = 0; 14169782aff8SPer Forlin } 14179782aff8SPer Forlin 14189782aff8SPer Forlin 14199782aff8SPer Forlin if (dma_len == 0) 14209782aff8SPer Forlin return -EINVAL; 14219782aff8SPer Forlin 14229782aff8SPer Forlin if (next) { 14239782aff8SPer Forlin next->dma_len = dma_len; 14249782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 14259782aff8SPer Forlin } else 14269782aff8SPer Forlin host->dma_len = dma_len; 14279782aff8SPer Forlin 14289782aff8SPer Forlin return 0; 14299782aff8SPer Forlin } 14309782aff8SPer Forlin 1431a45c6cb8SMadhusudhan Chikkature /* 1432a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1433a45c6cb8SMadhusudhan Chikkature */ 14349d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 143570a3341aSDenis Karpov struct mmc_request *req) 1436a45c6cb8SMadhusudhan Chikkature { 143726b88520SRussell King struct dma_slave_config cfg; 143826b88520SRussell King struct dma_async_tx_descriptor *tx; 143926b88520SRussell King int ret = 0, i; 1440a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1441c5c98927SRussell King struct dma_chan *chan; 1442a45c6cb8SMadhusudhan Chikkature 14430ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1444a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14450ccd76d4SJuha Yrjola struct scatterlist *sgl; 14460ccd76d4SJuha Yrjola 14470ccd76d4SJuha Yrjola sgl = data->sg + i; 14480ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14490ccd76d4SJuha Yrjola return -EINVAL; 14500ccd76d4SJuha Yrjola } 14510ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14520ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14530ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14540ccd76d4SJuha Yrjola */ 14550ccd76d4SJuha Yrjola return -EINVAL; 14560ccd76d4SJuha Yrjola 1457b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1458a45c6cb8SMadhusudhan Chikkature 1459c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1460c5c98927SRussell King 1461c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1462c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1463c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1464c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1465c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1466c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1467c5c98927SRussell King 1468c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14699782aff8SPer Forlin if (ret) 14709782aff8SPer Forlin return ret; 1471a45c6cb8SMadhusudhan Chikkature 147226b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1473c5c98927SRussell King if (ret) 1474c5c98927SRussell King return ret; 1475a45c6cb8SMadhusudhan Chikkature 1476c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1477c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1478c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1479c5c98927SRussell King if (!tx) { 1480c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1481c5c98927SRussell King /* FIXME: cleanup */ 1482c5c98927SRussell King return -1; 1483c5c98927SRussell King } 1484c5c98927SRussell King 1485c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1486c5c98927SRussell King tx->callback_param = host; 1487c5c98927SRussell King 1488c5c98927SRussell King /* Does not fail */ 1489c5c98927SRussell King dmaengine_submit(tx); 1490c5c98927SRussell King 149126b88520SRussell King host->dma_ch = 1; 1492c5c98927SRussell King 1493a45c6cb8SMadhusudhan Chikkature return 0; 1494a45c6cb8SMadhusudhan Chikkature } 1495a45c6cb8SMadhusudhan Chikkature 149670a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1497e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1498e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1499a45c6cb8SMadhusudhan Chikkature { 1500a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1501a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1502a45c6cb8SMadhusudhan Chikkature 1503a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1504a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1505a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1506a45c6cb8SMadhusudhan Chikkature clkd = 1; 1507a45c6cb8SMadhusudhan Chikkature 15086e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1509e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1510e2bf08d6SAdrian Hunter timeout += timeout_clks; 1511a45c6cb8SMadhusudhan Chikkature if (timeout) { 1512a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1513a45c6cb8SMadhusudhan Chikkature dto += 1; 1514a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1515a45c6cb8SMadhusudhan Chikkature } 1516a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1517a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1518a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1519a45c6cb8SMadhusudhan Chikkature dto += 1; 1520a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1521a45c6cb8SMadhusudhan Chikkature dto -= 13; 1522a45c6cb8SMadhusudhan Chikkature else 1523a45c6cb8SMadhusudhan Chikkature dto = 0; 1524a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1525a45c6cb8SMadhusudhan Chikkature dto = 14; 1526a45c6cb8SMadhusudhan Chikkature } 1527a45c6cb8SMadhusudhan Chikkature 1528a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1529a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1530a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1531a45c6cb8SMadhusudhan Chikkature } 1532a45c6cb8SMadhusudhan Chikkature 15339d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 15349d025334SBalaji T K { 15359d025334SBalaji T K struct mmc_request *req = host->mrq; 15369d025334SBalaji T K struct dma_chan *chan; 15379d025334SBalaji T K 15389d025334SBalaji T K if (!req->data) 15399d025334SBalaji T K return; 15409d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 15419d025334SBalaji T K | (req->data->blocks << 16)); 15429d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 15439d025334SBalaji T K req->data->timeout_clks); 15449d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 15459d025334SBalaji T K dma_async_issue_pending(chan); 15469d025334SBalaji T K } 15479d025334SBalaji T K 1548a45c6cb8SMadhusudhan Chikkature /* 1549a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1550a45c6cb8SMadhusudhan Chikkature */ 1551a45c6cb8SMadhusudhan Chikkature static int 155270a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1553a45c6cb8SMadhusudhan Chikkature { 1554a45c6cb8SMadhusudhan Chikkature int ret; 1555a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1556a45c6cb8SMadhusudhan Chikkature 1557a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1558a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1559e2bf08d6SAdrian Hunter /* 1560e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1561e2bf08d6SAdrian Hunter * busy signal. 1562e2bf08d6SAdrian Hunter */ 1563e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1564e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1565a45c6cb8SMadhusudhan Chikkature return 0; 1566a45c6cb8SMadhusudhan Chikkature } 1567a45c6cb8SMadhusudhan Chikkature 1568a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15699d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1570a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1571b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1572a45c6cb8SMadhusudhan Chikkature return ret; 1573a45c6cb8SMadhusudhan Chikkature } 1574a45c6cb8SMadhusudhan Chikkature } 1575a45c6cb8SMadhusudhan Chikkature return 0; 1576a45c6cb8SMadhusudhan Chikkature } 1577a45c6cb8SMadhusudhan Chikkature 15789782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15799782aff8SPer Forlin int err) 15809782aff8SPer Forlin { 15819782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15829782aff8SPer Forlin struct mmc_data *data = mrq->data; 15839782aff8SPer Forlin 158426b88520SRussell King if (host->use_dma && data->host_cookie) { 1585c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1586c5c98927SRussell King 158726b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15889782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15899782aff8SPer Forlin data->host_cookie = 0; 15909782aff8SPer Forlin } 15919782aff8SPer Forlin } 15929782aff8SPer Forlin 15939782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15949782aff8SPer Forlin bool is_first_req) 15959782aff8SPer Forlin { 15969782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15979782aff8SPer Forlin 15989782aff8SPer Forlin if (mrq->data->host_cookie) { 15999782aff8SPer Forlin mrq->data->host_cookie = 0; 16009782aff8SPer Forlin return ; 16019782aff8SPer Forlin } 16029782aff8SPer Forlin 1603c5c98927SRussell King if (host->use_dma) { 1604c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1605c5c98927SRussell King 16069782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 160726b88520SRussell King &host->next_data, c)) 16089782aff8SPer Forlin mrq->data->host_cookie = 0; 16099782aff8SPer Forlin } 1610c5c98927SRussell King } 16119782aff8SPer Forlin 1612a45c6cb8SMadhusudhan Chikkature /* 1613a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1614a45c6cb8SMadhusudhan Chikkature */ 161570a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1616a45c6cb8SMadhusudhan Chikkature { 161770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1618a3f406f8SJarkko Lavinen int err; 1619a45c6cb8SMadhusudhan Chikkature 1620b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1621b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1622f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1623b62f6228SAdrian Hunter if (host->protect_card) { 1624b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1625b62f6228SAdrian Hunter /* 1626b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1627b62f6228SAdrian Hunter * state by resetting the command and data state 1628b62f6228SAdrian Hunter * machines. 1629b62f6228SAdrian Hunter */ 1630b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1631b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1632b62f6228SAdrian Hunter host->reqs_blocked += 1; 1633b62f6228SAdrian Hunter } 1634b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1635b62f6228SAdrian Hunter if (req->data) 1636b62f6228SAdrian Hunter req->data->error = -EBADF; 1637b417577dSAdrian Hunter req->cmd->retries = 0; 1638b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1639f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1640f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1641b62f6228SAdrian Hunter return; 1642b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1643b62f6228SAdrian Hunter host->reqs_blocked = 0; 1644a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1645a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16466e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 164770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1648a3f406f8SJarkko Lavinen if (err) { 1649a3f406f8SJarkko Lavinen req->cmd->error = err; 1650a3f406f8SJarkko Lavinen if (req->data) 1651a3f406f8SJarkko Lavinen req->data->error = err; 1652a3f406f8SJarkko Lavinen host->mrq = NULL; 1653a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1654f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1655f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1656a3f406f8SJarkko Lavinen return; 1657a3f406f8SJarkko Lavinen } 1658a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1659bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1660bf129e1cSBalaji T K return; 1661bf129e1cSBalaji T K } 1662a3f406f8SJarkko Lavinen 16639d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 166470a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1665a45c6cb8SMadhusudhan Chikkature } 1666a45c6cb8SMadhusudhan Chikkature 1667a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 166870a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1669a45c6cb8SMadhusudhan Chikkature { 167070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1671a3621465SAdrian Hunter int do_send_init_stream = 0; 1672a45c6cb8SMadhusudhan Chikkature 1673fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16745e2ea617SAdrian Hunter 1675a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1676a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1677a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1678f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1679a45c6cb8SMadhusudhan Chikkature break; 1680a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1681f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1682a45c6cb8SMadhusudhan Chikkature break; 1683a3621465SAdrian Hunter case MMC_POWER_ON: 1684a3621465SAdrian Hunter do_send_init_stream = 1; 1685a3621465SAdrian Hunter break; 1686a3621465SAdrian Hunter } 1687a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1688a45c6cb8SMadhusudhan Chikkature } 1689a45c6cb8SMadhusudhan Chikkature 1690dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1691dd498effSDenis Karpov 16923796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1693a45c6cb8SMadhusudhan Chikkature 16944621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1695eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1696eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1697eb250826SDavid Brownell */ 1698a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16992cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1700a45c6cb8SMadhusudhan Chikkature /* 1701a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1702a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1703a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1704a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1705a45c6cb8SMadhusudhan Chikkature */ 170670a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1707a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1708a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1709a45c6cb8SMadhusudhan Chikkature } 1710a45c6cb8SMadhusudhan Chikkature } 1711a45c6cb8SMadhusudhan Chikkature 17125934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1713a45c6cb8SMadhusudhan Chikkature 1714a3621465SAdrian Hunter if (do_send_init_stream) 1715a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1716a45c6cb8SMadhusudhan Chikkature 17173796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 17185e2ea617SAdrian Hunter 1719fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1720a45c6cb8SMadhusudhan Chikkature } 1721a45c6cb8SMadhusudhan Chikkature 1722a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1723a45c6cb8SMadhusudhan Chikkature { 172470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1725a45c6cb8SMadhusudhan Chikkature 1726b5cd43f0SAndreas Fenkart if (!host->card_detect) 1727a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 172880412ca8SAndreas Fenkart return host->card_detect(host->dev); 1729a45c6cb8SMadhusudhan Chikkature } 1730a45c6cb8SMadhusudhan Chikkature 17314816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17324816858cSGrazvydas Ignotas { 17334816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17344816858cSGrazvydas Ignotas 1735326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1736326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 17374816858cSGrazvydas Ignotas } 17384816858cSGrazvydas Ignotas 17392cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 17402cd3a2a5SAndreas Fenkart { 17412cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 17425a52b08bSBalaji T K u32 irq_mask, con; 17432cd3a2a5SAndreas Fenkart unsigned long flags; 17442cd3a2a5SAndreas Fenkart 17452cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17462cd3a2a5SAndreas Fenkart 17475a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17482cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17492cd3a2a5SAndreas Fenkart if (enable) { 17502cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17512cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17525a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17532cd3a2a5SAndreas Fenkart } else { 17542cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17552cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17565a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17572cd3a2a5SAndreas Fenkart } 17585a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17592cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17602cd3a2a5SAndreas Fenkart 17612cd3a2a5SAndreas Fenkart /* 17622cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17632cd3a2a5SAndreas Fenkart * but always disable immediately 17642cd3a2a5SAndreas Fenkart */ 17652cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17662cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17672cd3a2a5SAndreas Fenkart 17682cd3a2a5SAndreas Fenkart /* flush posted write */ 17692cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17702cd3a2a5SAndreas Fenkart 17712cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17722cd3a2a5SAndreas Fenkart } 17732cd3a2a5SAndreas Fenkart 17742cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17752cd3a2a5SAndreas Fenkart { 17762cd3a2a5SAndreas Fenkart int ret; 17772cd3a2a5SAndreas Fenkart 17782cd3a2a5SAndreas Fenkart /* 17792cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17802cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17812cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17822cd3a2a5SAndreas Fenkart * with functional clock disabled. 17832cd3a2a5SAndreas Fenkart */ 17842cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17852cd3a2a5SAndreas Fenkart return -ENODEV; 17862cd3a2a5SAndreas Fenkart 17875b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17882cd3a2a5SAndreas Fenkart if (ret) { 17892cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17902cd3a2a5SAndreas Fenkart goto err; 17912cd3a2a5SAndreas Fenkart } 17922cd3a2a5SAndreas Fenkart 17932cd3a2a5SAndreas Fenkart /* 17942cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17952cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17962cd3a2a5SAndreas Fenkart */ 17972cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1798455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1799455e5cd6SAndreas Fenkart if (!p) { 18002cd3a2a5SAndreas Fenkart ret = -ENODEV; 1801455e5cd6SAndreas Fenkart goto err_free_irq; 1802455e5cd6SAndreas Fenkart } 1803455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1804455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1805455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1806455e5cd6SAndreas Fenkart ret = -EINVAL; 1807455e5cd6SAndreas Fenkart goto err_free_irq; 1808455e5cd6SAndreas Fenkart } 1809455e5cd6SAndreas Fenkart 1810455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1811455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1812455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1813455e5cd6SAndreas Fenkart ret = -EINVAL; 1814455e5cd6SAndreas Fenkart goto err_free_irq; 1815455e5cd6SAndreas Fenkart } 1816455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 18172cd3a2a5SAndreas Fenkart } 18182cd3a2a5SAndreas Fenkart 18195a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 18205a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 18212cd3a2a5SAndreas Fenkart return 0; 18222cd3a2a5SAndreas Fenkart 1823455e5cd6SAndreas Fenkart err_free_irq: 18245b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 18252cd3a2a5SAndreas Fenkart err: 18262cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 18272cd3a2a5SAndreas Fenkart host->wake_irq = 0; 18282cd3a2a5SAndreas Fenkart return ret; 18292cd3a2a5SAndreas Fenkart } 18302cd3a2a5SAndreas Fenkart 183170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 18321b331e69SKim Kyuwon { 18331b331e69SKim Kyuwon u32 hctl, capa, value; 18341b331e69SKim Kyuwon 18351b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 18364621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 18371b331e69SKim Kyuwon hctl = SDVS30; 18381b331e69SKim Kyuwon capa = VS30 | VS18; 18391b331e69SKim Kyuwon } else { 18401b331e69SKim Kyuwon hctl = SDVS18; 18411b331e69SKim Kyuwon capa = VS18; 18421b331e69SKim Kyuwon } 18431b331e69SKim Kyuwon 18441b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 18451b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18461b331e69SKim Kyuwon 18471b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18481b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18491b331e69SKim Kyuwon 18501b331e69SKim Kyuwon /* Set SD bus power bit */ 1851e13bb300SAdrian Hunter set_sd_bus_power(host); 18521b331e69SKim Kyuwon } 18531b331e69SKim Kyuwon 1854afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1855afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1856afd8c29dSKuninori Morimoto { 1857afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1858afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1859afd8c29dSKuninori Morimoto return 1; 1860afd8c29dSKuninori Morimoto 1861afd8c29dSKuninori Morimoto return blk_size; 1862afd8c29dSKuninori Morimoto } 1863afd8c29dSKuninori Morimoto 1864afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18659782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18669782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 186770a3341aSDenis Karpov .request = omap_hsmmc_request, 186870a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1869dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1870a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18714816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18722cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1873dd498effSDenis Karpov }; 1874dd498effSDenis Karpov 1875d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1876d900f712SDenis Karpov 187770a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1878d900f712SDenis Karpov { 1879d900f712SDenis Karpov struct mmc_host *mmc = s->private; 188070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 188111dd62a7SDenis Karpov 1882bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1883bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1884bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1885bb0635f0SAndreas Fenkart 1886bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1887bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1888bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1889bb0635f0SAndreas Fenkart : "disabled"); 1890bb0635f0SAndreas Fenkart } 1891bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18925e2ea617SAdrian Hunter 1893fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1894bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1895d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1896d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1897bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1898bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1899d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1900d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1901d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1902d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1903d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1904d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1905d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1906d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1907d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1908d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 19095e2ea617SAdrian Hunter 1910fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1911fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1912dd498effSDenis Karpov 1913d900f712SDenis Karpov return 0; 1914d900f712SDenis Karpov } 1915d900f712SDenis Karpov 191670a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1917d900f712SDenis Karpov { 191870a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1919d900f712SDenis Karpov } 1920d900f712SDenis Karpov 1921d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 192270a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1923d900f712SDenis Karpov .read = seq_read, 1924d900f712SDenis Karpov .llseek = seq_lseek, 1925d900f712SDenis Karpov .release = single_release, 1926d900f712SDenis Karpov }; 1927d900f712SDenis Karpov 192870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1929d900f712SDenis Karpov { 1930d900f712SDenis Karpov if (mmc->debugfs_root) 1931d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1932d900f712SDenis Karpov mmc, &mmc_regs_fops); 1933d900f712SDenis Karpov } 1934d900f712SDenis Karpov 1935d900f712SDenis Karpov #else 1936d900f712SDenis Karpov 193770a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1938d900f712SDenis Karpov { 1939d900f712SDenis Karpov } 1940d900f712SDenis Karpov 1941d900f712SDenis Karpov #endif 1942d900f712SDenis Karpov 194346856a68SRajendra Nayak #ifdef CONFIG_OF 194459445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 194559445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 194659445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 194759445b10SNishanth Menon }; 194859445b10SNishanth Menon 194959445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 195059445b10SNishanth Menon .reg_offset = 0x100, 195159445b10SNishanth Menon }; 19522cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19532cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19542cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19552cd3a2a5SAndreas Fenkart }; 195646856a68SRajendra Nayak 195746856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 195846856a68SRajendra Nayak { 195946856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 196046856a68SRajendra Nayak }, 196146856a68SRajendra Nayak { 196259445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 196359445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 196459445b10SNishanth Menon }, 196559445b10SNishanth Menon { 196646856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 196746856a68SRajendra Nayak }, 196846856a68SRajendra Nayak { 196946856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 197059445b10SNishanth Menon .data = &omap4_mmc_of_data, 197146856a68SRajendra Nayak }, 19722cd3a2a5SAndreas Fenkart { 19732cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19742cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19752cd3a2a5SAndreas Fenkart }, 197646856a68SRajendra Nayak {}, 1977b6d085f6SChris Ball }; 197846856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 197946856a68SRajendra Nayak 198055143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 198146856a68SRajendra Nayak { 198255143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 198346856a68SRajendra Nayak struct device_node *np = dev->of_node; 198446856a68SRajendra Nayak 198546856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 198646856a68SRajendra Nayak if (!pdata) 198719df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 198846856a68SRajendra Nayak 198946856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 199046856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 199146856a68SRajendra Nayak 1992b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1993b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1994fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 199546856a68SRajendra Nayak 199646856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1997326119c9SAndreas Fenkart pdata->nonremovable = true; 1998326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 199946856a68SRajendra Nayak } 200046856a68SRajendra Nayak 200146856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 2002326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 200346856a68SRajendra Nayak 2004cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 2005326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 2006cd587096SHebbar, Gururaja 200746856a68SRajendra Nayak return pdata; 200846856a68SRajendra Nayak } 200946856a68SRajendra Nayak #else 201055143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 201146856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 201246856a68SRajendra Nayak { 201319df45bcSBalaji T K return ERR_PTR(-EINVAL); 201446856a68SRajendra Nayak } 201546856a68SRajendra Nayak #endif 201646856a68SRajendra Nayak 2017c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 2018a45c6cb8SMadhusudhan Chikkature { 201955143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 2020a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 202170a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 2022a45c6cb8SMadhusudhan Chikkature struct resource *res; 2023db0fefc5SAdrian Hunter int ret, irq; 202446856a68SRajendra Nayak const struct of_device_id *match; 202526b88520SRussell King dma_cap_mask_t mask; 202626b88520SRussell King unsigned tx_req, rx_req; 202759445b10SNishanth Menon const struct omap_mmc_of_data *data; 202877fae219SBalaji T K void __iomem *base; 202946856a68SRajendra Nayak 203046856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 203146856a68SRajendra Nayak if (match) { 203246856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2033dc642c28SJan Luebbe 2034dc642c28SJan Luebbe if (IS_ERR(pdata)) 2035dc642c28SJan Luebbe return PTR_ERR(pdata); 2036dc642c28SJan Luebbe 203746856a68SRajendra Nayak if (match->data) { 203859445b10SNishanth Menon data = match->data; 203959445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 204059445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 204146856a68SRajendra Nayak } 204246856a68SRajendra Nayak } 2043a45c6cb8SMadhusudhan Chikkature 2044a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2045a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2046a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2047a45c6cb8SMadhusudhan Chikkature } 2048a45c6cb8SMadhusudhan Chikkature 2049a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2050a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2051a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2052a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2053a45c6cb8SMadhusudhan Chikkature 205477fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 205577fae219SBalaji T K if (IS_ERR(base)) 205677fae219SBalaji T K return PTR_ERR(base); 2057a45c6cb8SMadhusudhan Chikkature 205870a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2059a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2060a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20611e363e3bSAndreas Fenkart goto err; 2062a45c6cb8SMadhusudhan Chikkature } 2063a45c6cb8SMadhusudhan Chikkature 2064fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2065fdb9de12SNeilBrown if (ret) 2066fdb9de12SNeilBrown goto err1; 2067fdb9de12SNeilBrown 2068a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2069a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2070a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2071a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2072a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2073a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2074a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2075fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 207677fae219SBalaji T K host->base = base + pdata->reg_offset; 20776da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20789782aff8SPer Forlin host->next_data.cookie = 1; 2079e99448ffSBalaji T K host->pbias_enabled = 0; 2080a45c6cb8SMadhusudhan Chikkature 208141afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20821e363e3bSAndreas Fenkart if (ret) 20831e363e3bSAndreas Fenkart goto err_gpio; 20841e363e3bSAndreas Fenkart 2085a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2086a45c6cb8SMadhusudhan Chikkature 20872cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20882cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20892cd3a2a5SAndreas Fenkart 209070a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2091dd498effSDenis Karpov 20926b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2093d418ed87SDaniel Mack 2094d418ed87SDaniel Mack if (pdata->max_freq > 0) 2095d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2096fdb9de12SNeilBrown else if (mmc->f_max == 0) 20976b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2098a45c6cb8SMadhusudhan Chikkature 20994dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2100a45c6cb8SMadhusudhan Chikkature 21019618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2102a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2103a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2104a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2105a45c6cb8SMadhusudhan Chikkature goto err1; 2106a45c6cb8SMadhusudhan Chikkature } 2107a45c6cb8SMadhusudhan Chikkature 21089b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 21099b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2110afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 21119b68256cSPaul Walmsley } 2112dd498effSDenis Karpov 21135b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2114fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2115fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2116fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2117fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2118a45c6cb8SMadhusudhan Chikkature 211992a3aebfSBalaji T K omap_hsmmc_context_save(host); 212092a3aebfSBalaji T K 21219618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2122a45c6cb8SMadhusudhan Chikkature /* 2123a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2124a45c6cb8SMadhusudhan Chikkature */ 2125cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2126cd03d9a8SRajendra Nayak host->dbclk = NULL; 212794c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2128cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2129cd03d9a8SRajendra Nayak host->dbclk = NULL; 21302bec0893SAdrian Hunter } 2131a45c6cb8SMadhusudhan Chikkature 21320ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21330ccd76d4SJuha Yrjola * as we want. */ 2134a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21350ccd76d4SJuha Yrjola 2136a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2137a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2138a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2139a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2140a45c6cb8SMadhusudhan Chikkature 214113189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 214293caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2143a45c6cb8SMadhusudhan Chikkature 2144326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21453a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2146a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2147a45c6cb8SMadhusudhan Chikkature 2148326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 214923d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 215023d99bb9SAdrian Hunter 2151fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 21526fdc75deSEliad Peller 215370a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2154a45c6cb8SMadhusudhan Chikkature 21554a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2156b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2157b7bf773bSBalaji T K if (!res) { 2158b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21599c17d08cSKevin Hilman ret = -ENXIO; 2160f3e2f1ddSGrazvydas Ignotas goto err_irq; 2161a45c6cb8SMadhusudhan Chikkature } 216226b88520SRussell King tx_req = res->start; 2163b7bf773bSBalaji T K 2164b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2165b7bf773bSBalaji T K if (!res) { 2166b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21679c17d08cSKevin Hilman ret = -ENXIO; 2168b7bf773bSBalaji T K goto err_irq; 2169b7bf773bSBalaji T K } 217026b88520SRussell King rx_req = res->start; 21714a29b559SSantosh Shilimkar } 2172c5c98927SRussell King 2173c5c98927SRussell King dma_cap_zero(mask); 2174c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 217526b88520SRussell King 2176d272fbf0SMatt Porter host->rx_chan = 2177d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2178d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2179d272fbf0SMatt Porter 2180c5c98927SRussell King if (!host->rx_chan) { 218126b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 218204e8c7bcSKevin Hilman ret = -ENXIO; 218326b88520SRussell King goto err_irq; 2184c5c98927SRussell King } 218526b88520SRussell King 2186d272fbf0SMatt Porter host->tx_chan = 2187d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2188d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2189d272fbf0SMatt Porter 2190c5c98927SRussell King if (!host->tx_chan) { 219126b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 219204e8c7bcSKevin Hilman ret = -ENXIO; 219326b88520SRussell King goto err_irq; 2194c5c98927SRussell King } 2195a45c6cb8SMadhusudhan Chikkature 2196a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2197e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2198a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2199a45c6cb8SMadhusudhan Chikkature if (ret) { 2200b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2201a45c6cb8SMadhusudhan Chikkature goto err_irq; 2202a45c6cb8SMadhusudhan Chikkature } 2203a45c6cb8SMadhusudhan Chikkature 2204f7f0f035SAndreas Fenkart if (omap_hsmmc_have_reg()) { 2205db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2206db0fefc5SAdrian Hunter if (ret) 2207bb09d151SAndreas Fenkart goto err_irq; 2208db0fefc5SAdrian Hunter } 2209db0fefc5SAdrian Hunter 2210326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2211a45c6cb8SMadhusudhan Chikkature 2212b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2213a45c6cb8SMadhusudhan Chikkature 22142cd3a2a5SAndreas Fenkart /* 22152cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 22162cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 22172cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 22182cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 22192cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 22202cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22212cd3a2a5SAndreas Fenkart */ 22222cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22232cd3a2a5SAndreas Fenkart if (!ret) 22242cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22252cd3a2a5SAndreas Fenkart 2226b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2227b62f6228SAdrian Hunter 2228a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2229a45c6cb8SMadhusudhan Chikkature 2230326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2231a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2232a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2233a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2234a45c6cb8SMadhusudhan Chikkature } 2235cde592cbSAndreas Fenkart if (host->get_cover_state) { 2236a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2237a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2238a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2239db0fefc5SAdrian Hunter goto err_slot_name; 2240a45c6cb8SMadhusudhan Chikkature } 2241a45c6cb8SMadhusudhan Chikkature 224270a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2243fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2244fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2245d900f712SDenis Karpov 2246a45c6cb8SMadhusudhan Chikkature return 0; 2247a45c6cb8SMadhusudhan Chikkature 2248a45c6cb8SMadhusudhan Chikkature err_slot_name: 2249a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2250a45c6cb8SMadhusudhan Chikkature err_irq: 22515b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2252c5c98927SRussell King if (host->tx_chan) 2253c5c98927SRussell King dma_release_channel(host->tx_chan); 2254c5c98927SRussell King if (host->rx_chan) 2255c5c98927SRussell King dma_release_channel(host->rx_chan); 2256d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 225737f6190dSTony Lindgren pm_runtime_disable(host->dev); 22589618195eSBalaji T K if (host->dbclk) 225994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2260a45c6cb8SMadhusudhan Chikkature err1: 22611e363e3bSAndreas Fenkart err_gpio: 2262a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2263db0fefc5SAdrian Hunter err: 2264a45c6cb8SMadhusudhan Chikkature return ret; 2265a45c6cb8SMadhusudhan Chikkature } 2266a45c6cb8SMadhusudhan Chikkature 22676e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2268a45c6cb8SMadhusudhan Chikkature { 226970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2270a45c6cb8SMadhusudhan Chikkature 2271fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2272a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2273a45c6cb8SMadhusudhan Chikkature 2274c5c98927SRussell King if (host->tx_chan) 2275c5c98927SRussell King dma_release_channel(host->tx_chan); 2276c5c98927SRussell King if (host->rx_chan) 2277c5c98927SRussell King dma_release_channel(host->rx_chan); 2278c5c98927SRussell King 2279fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2280fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22815b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22829618195eSBalaji T K if (host->dbclk) 228394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2284a45c6cb8SMadhusudhan Chikkature 22859d1f0286SBalaji T K mmc_free_host(host->mmc); 2286a45c6cb8SMadhusudhan Chikkature 2287a45c6cb8SMadhusudhan Chikkature return 0; 2288a45c6cb8SMadhusudhan Chikkature } 2289a45c6cb8SMadhusudhan Chikkature 22903d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2291a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2292a45c6cb8SMadhusudhan Chikkature { 2293927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2294927ce944SFelipe Balbi 2295927ce944SFelipe Balbi if (!host) 2296927ce944SFelipe Balbi return 0; 2297a45c6cb8SMadhusudhan Chikkature 2298fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 229931f9d463SEliad Peller 230031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 23012cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23022cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 230431f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 230531f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 230631f9d463SEliad Peller } 2307927ce944SFelipe Balbi 2308cd03d9a8SRajendra Nayak if (host->dbclk) 230994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 23103932afd5SUlf Hansson 2311fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 23123932afd5SUlf Hansson return 0; 2313a45c6cb8SMadhusudhan Chikkature } 2314a45c6cb8SMadhusudhan Chikkature 2315a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2316a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2317a45c6cb8SMadhusudhan Chikkature { 2318927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2319927ce944SFelipe Balbi 2320927ce944SFelipe Balbi if (!host) 2321927ce944SFelipe Balbi return 0; 2322a45c6cb8SMadhusudhan Chikkature 2323fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 232411dd62a7SDenis Karpov 2325cd03d9a8SRajendra Nayak if (host->dbclk) 232694c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23272bec0893SAdrian Hunter 232831f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 232970a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23301b331e69SKim Kyuwon 2331b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2332fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2333fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23343932afd5SUlf Hansson return 0; 2335a45c6cb8SMadhusudhan Chikkature } 2336a45c6cb8SMadhusudhan Chikkature #endif 2337a45c6cb8SMadhusudhan Chikkature 2338fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2339fa4aa2d4SBalaji T K { 2340fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23412cd3a2a5SAndreas Fenkart unsigned long flags; 2342f945901fSAndreas Fenkart int ret = 0; 2343fa4aa2d4SBalaji T K 2344fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2345fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2346927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2347fa4aa2d4SBalaji T K 23482cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23492cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23502cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23512cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23522cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23532cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2354f945901fSAndreas Fenkart 2355f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2356f945901fSAndreas Fenkart /* 2357f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2358f945901fSAndreas Fenkart * race condition: possible irq handler running on 2359f945901fSAndreas Fenkart * multi-core, abort 2360f945901fSAndreas Fenkart */ 2361f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23622cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2363f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2364f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2365f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2366f945901fSAndreas Fenkart ret = -EBUSY; 2367f945901fSAndreas Fenkart goto abort; 2368f945901fSAndreas Fenkart } 23692cd3a2a5SAndreas Fenkart 237097978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 237197978a44SAndreas Fenkart } else { 237297978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23732cd3a2a5SAndreas Fenkart } 237497978a44SAndreas Fenkart 2375f945901fSAndreas Fenkart abort: 23762cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2377f945901fSAndreas Fenkart return ret; 2378fa4aa2d4SBalaji T K } 2379fa4aa2d4SBalaji T K 2380fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2381fa4aa2d4SBalaji T K { 2382fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23832cd3a2a5SAndreas Fenkart unsigned long flags; 2384fa4aa2d4SBalaji T K 2385fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2386fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2387927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2388fa4aa2d4SBalaji T K 23892cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23902cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23912cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23922cd3a2a5SAndreas Fenkart 239397978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 239497978a44SAndreas Fenkart 239597978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23962cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23972cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23982cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 239997978a44SAndreas Fenkart } else { 240097978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 24012cd3a2a5SAndreas Fenkart } 24022cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2403fa4aa2d4SBalaji T K return 0; 2404fa4aa2d4SBalaji T K } 2405fa4aa2d4SBalaji T K 2406a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 24073d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2408fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2409fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2410a791daa1SKevin Hilman }; 2411a791daa1SKevin Hilman 2412a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2413efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24140433c143SBill Pemberton .remove = omap_hsmmc_remove, 2415a45c6cb8SMadhusudhan Chikkature .driver = { 2416a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2417a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 241846856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2419a45c6cb8SMadhusudhan Chikkature }, 2420a45c6cb8SMadhusudhan Chikkature }; 2421a45c6cb8SMadhusudhan Chikkature 2422b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2423a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2424a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2425a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2426a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2427