1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22d900f712SDenis Karpov #include <linux/seq_file.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3013189e78SJarkko Lavinen #include <linux/mmc/core.h> 3193caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 32a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 33a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 34db0fefc5SAdrian Hunter #include <linux/gpio.h> 35db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 36fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 37ce491cf8STony Lindgren #include <plat/dma.h> 38a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 39ce491cf8STony Lindgren #include <plat/board.h> 40ce491cf8STony Lindgren #include <plat/mmc.h> 41ce491cf8STony Lindgren #include <plat/cpu.h> 42a45c6cb8SMadhusudhan Chikkature 43a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 44a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 4511dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 46a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 61a45c6cb8SMadhusudhan Chikkature 62a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 63a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 64a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 65a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 66eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 671b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 68a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 69a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 70a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 71a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 72a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 73a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 74a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 75a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 76a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 77a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 78a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 79a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 80a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 81ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 82ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8393caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 84a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 85a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 86a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 87a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 88a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 89a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 90a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9173153010SJarkko Lavinen #define DW8 (1 << 5) 92a45c6cb8SMadhusudhan Chikkature #define CC 0x1 93a45c6cb8SMadhusudhan Chikkature #define TC 0x02 94a45c6cb8SMadhusudhan Chikkature #define OD 0x1 95a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 96a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 97a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 98a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 99a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 100a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 101a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 102a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 103a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 104a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 105a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10611dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10711dd62a7SDenis Karpov #define RESETDONE (1 << 0) 108a45c6cb8SMadhusudhan Chikkature 109a45c6cb8SMadhusudhan Chikkature /* 110a45c6cb8SMadhusudhan Chikkature * FIXME: Most likely all the data using these _DEVID defines should come 111a45c6cb8SMadhusudhan Chikkature * from the platform_data, or implemented in controller and slot specific 112a45c6cb8SMadhusudhan Chikkature * functions. 113a45c6cb8SMadhusudhan Chikkature */ 114a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC1_DEVID 0 115a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC2_DEVID 1 116f3e2f1ddSGrazvydas Ignotas #define OMAP_MMC3_DEVID 2 11782cf818dSkishore kadiyala #define OMAP_MMC4_DEVID 3 11882cf818dSkishore kadiyala #define OMAP_MMC5_DEVID 4 119a45c6cb8SMadhusudhan Chikkature 120fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 121a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1226b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1236b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1240005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 125a45c6cb8SMadhusudhan Chikkature 126a45c6cb8SMadhusudhan Chikkature /* 127a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 128a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 129a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 130a45c6cb8SMadhusudhan Chikkature */ 131a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 132a45c6cb8SMadhusudhan Chikkature 133a45c6cb8SMadhusudhan Chikkature /* 134a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 135a45c6cb8SMadhusudhan Chikkature */ 136a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 137a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 138a45c6cb8SMadhusudhan Chikkature 139a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 140a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 141a45c6cb8SMadhusudhan Chikkature 1429782aff8SPer Forlin struct omap_hsmmc_next { 1439782aff8SPer Forlin unsigned int dma_len; 1449782aff8SPer Forlin s32 cookie; 1459782aff8SPer Forlin }; 1469782aff8SPer Forlin 14770a3341aSDenis Karpov struct omap_hsmmc_host { 148a45c6cb8SMadhusudhan Chikkature struct device *dev; 149a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 150a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 151a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 152a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 153a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 154a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 155db0fefc5SAdrian Hunter /* 156db0fefc5SAdrian Hunter * vcc == configured supply 157db0fefc5SAdrian Hunter * vcc_aux == optional 158db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 159db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 160db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 161db0fefc5SAdrian Hunter */ 162db0fefc5SAdrian Hunter struct regulator *vcc; 163db0fefc5SAdrian Hunter struct regulator *vcc_aux; 164a45c6cb8SMadhusudhan Chikkature void __iomem *base; 165a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1664dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 167a45c6cb8SMadhusudhan Chikkature unsigned int id; 168a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1690ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 170a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 171a3621465SAdrian Hunter unsigned char power_mode; 172a45c6cb8SMadhusudhan Chikkature u32 *buffer; 173a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 174a45c6cb8SMadhusudhan Chikkature int suspended; 175a45c6cb8SMadhusudhan Chikkature int irq; 176a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 177f3e2f1ddSGrazvydas Ignotas int dma_line_tx, dma_line_rx; 178a45c6cb8SMadhusudhan Chikkature int slot_id; 1792bec0893SAdrian Hunter int got_dbclk; 1804a694dc9SAdrian Hunter int response_busy; 18111dd62a7SDenis Karpov int context_loss; 182dd498effSDenis Karpov int dpm_state; 183623821f7SAdrian Hunter int vdd; 184b62f6228SAdrian Hunter int protect_card; 185b62f6228SAdrian Hunter int reqs_blocked; 186db0fefc5SAdrian Hunter int use_reg; 187b417577dSAdrian Hunter int req_in_progress; 1889782aff8SPer Forlin struct omap_hsmmc_next next_data; 18911dd62a7SDenis Karpov 190a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 191a45c6cb8SMadhusudhan Chikkature }; 192a45c6cb8SMadhusudhan Chikkature 193db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 194db0fefc5SAdrian Hunter { 195db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 196db0fefc5SAdrian Hunter 197db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 198db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 199db0fefc5SAdrian Hunter } 200db0fefc5SAdrian Hunter 201db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 202db0fefc5SAdrian Hunter { 203db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 204db0fefc5SAdrian Hunter 205db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 206db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 207db0fefc5SAdrian Hunter } 208db0fefc5SAdrian Hunter 209db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 210db0fefc5SAdrian Hunter { 211db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 212db0fefc5SAdrian Hunter 213db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 214db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 215db0fefc5SAdrian Hunter } 216db0fefc5SAdrian Hunter 217db0fefc5SAdrian Hunter #ifdef CONFIG_PM 218db0fefc5SAdrian Hunter 219db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 220db0fefc5SAdrian Hunter { 221db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 222db0fefc5SAdrian Hunter 223db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 224db0fefc5SAdrian Hunter return 0; 225db0fefc5SAdrian Hunter } 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 228db0fefc5SAdrian Hunter { 229db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 230db0fefc5SAdrian Hunter 231db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 232db0fefc5SAdrian Hunter return 0; 233db0fefc5SAdrian Hunter } 234db0fefc5SAdrian Hunter 235db0fefc5SAdrian Hunter #else 236db0fefc5SAdrian Hunter 237db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 238db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 239db0fefc5SAdrian Hunter 240db0fefc5SAdrian Hunter #endif 241db0fefc5SAdrian Hunter 242b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 243b702b106SAdrian Hunter 244db0fefc5SAdrian Hunter static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 245db0fefc5SAdrian Hunter int vdd) 246db0fefc5SAdrian Hunter { 247db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 248db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 249db0fefc5SAdrian Hunter int ret; 250db0fefc5SAdrian Hunter 251db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 252db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 253db0fefc5SAdrian Hunter 254db0fefc5SAdrian Hunter if (power_on) 25599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 256db0fefc5SAdrian Hunter else 25799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 258db0fefc5SAdrian Hunter 259db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 260db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 261db0fefc5SAdrian Hunter 262db0fefc5SAdrian Hunter return ret; 263db0fefc5SAdrian Hunter } 264db0fefc5SAdrian Hunter 2657715db5aSKishore Kadiyala static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, 266db0fefc5SAdrian Hunter int vdd) 267db0fefc5SAdrian Hunter { 268db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 269db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 270db0fefc5SAdrian Hunter int ret = 0; 271db0fefc5SAdrian Hunter 272db0fefc5SAdrian Hunter /* 273db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 274db0fefc5SAdrian Hunter * voltage always-on regulator. 275db0fefc5SAdrian Hunter */ 276db0fefc5SAdrian Hunter if (!host->vcc) 277db0fefc5SAdrian Hunter return 0; 278db0fefc5SAdrian Hunter 279db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 280db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 281db0fefc5SAdrian Hunter 282db0fefc5SAdrian Hunter /* 283db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 284db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 285db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 286db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 287db0fefc5SAdrian Hunter * 288db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 289db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 290db0fefc5SAdrian Hunter * 291db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 292db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 293db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 294db0fefc5SAdrian Hunter */ 295db0fefc5SAdrian Hunter if (power_on) { 29699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 297db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 298db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 299db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 300db0fefc5SAdrian Hunter if (ret < 0) 30199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30299fc5131SLinus Walleij host->vcc, 0); 303db0fefc5SAdrian Hunter } 304db0fefc5SAdrian Hunter } else { 30599fc5131SLinus Walleij /* Shut down the rail */ 3066da20c89SAdrian Hunter if (host->vcc_aux) 307db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 30899fc5131SLinus Walleij if (!ret) { 30999fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31199fc5131SLinus Walleij host->vcc, 0); 31299fc5131SLinus Walleij } 313db0fefc5SAdrian Hunter } 314db0fefc5SAdrian Hunter 315db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 316db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 317db0fefc5SAdrian Hunter 318db0fefc5SAdrian Hunter return ret; 319db0fefc5SAdrian Hunter } 320db0fefc5SAdrian Hunter 3217715db5aSKishore Kadiyala static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, 3227715db5aSKishore Kadiyala int vdd) 3237715db5aSKishore Kadiyala { 3247715db5aSKishore Kadiyala return 0; 3257715db5aSKishore Kadiyala } 3267715db5aSKishore Kadiyala 327db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 328db0fefc5SAdrian Hunter { 329db0fefc5SAdrian Hunter struct regulator *reg; 330db0fefc5SAdrian Hunter int ret = 0; 33164be9782Skishore kadiyala int ocr_value = 0; 332db0fefc5SAdrian Hunter 333db0fefc5SAdrian Hunter switch (host->id) { 334db0fefc5SAdrian Hunter case OMAP_MMC1_DEVID: 335db0fefc5SAdrian Hunter /* On-chip level shifting via PBIAS0/PBIAS1 */ 336db0fefc5SAdrian Hunter mmc_slot(host).set_power = omap_hsmmc_1_set_power; 337db0fefc5SAdrian Hunter break; 338db0fefc5SAdrian Hunter case OMAP_MMC2_DEVID: 339db0fefc5SAdrian Hunter case OMAP_MMC3_DEVID: 3407715db5aSKishore Kadiyala case OMAP_MMC5_DEVID: 341db0fefc5SAdrian Hunter /* Off-chip level shifting, or none */ 3427715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_235_set_power; 343db0fefc5SAdrian Hunter break; 3447715db5aSKishore Kadiyala case OMAP_MMC4_DEVID: 3457715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_4_set_power; 346db0fefc5SAdrian Hunter default: 347db0fefc5SAdrian Hunter pr_err("MMC%d configuration not supported!\n", host->id); 348db0fefc5SAdrian Hunter return -EINVAL; 349db0fefc5SAdrian Hunter } 350db0fefc5SAdrian Hunter 351db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 352db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 353db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 354db0fefc5SAdrian Hunter /* 355db0fefc5SAdrian Hunter * HACK: until fixed.c regulator is usable, 356db0fefc5SAdrian Hunter * we don't require a main regulator 357db0fefc5SAdrian Hunter * for MMC2 or MMC3 358db0fefc5SAdrian Hunter */ 359db0fefc5SAdrian Hunter if (host->id == OMAP_MMC1_DEVID) { 360db0fefc5SAdrian Hunter ret = PTR_ERR(reg); 361db0fefc5SAdrian Hunter goto err; 362db0fefc5SAdrian Hunter } 363db0fefc5SAdrian Hunter } else { 364db0fefc5SAdrian Hunter host->vcc = reg; 36564be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 36664be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 36764be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 36864be9782Skishore kadiyala } else { 36964be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 37064be9782Skishore kadiyala pr_err("MMC%d ocrmask %x is not supported\n", 37164be9782Skishore kadiyala host->id, mmc_slot(host).ocr_mask); 37264be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 37364be9782Skishore kadiyala return -EINVAL; 37464be9782Skishore kadiyala } 37564be9782Skishore kadiyala } 376db0fefc5SAdrian Hunter 377db0fefc5SAdrian Hunter /* Allow an aux regulator */ 378db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 379db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 380db0fefc5SAdrian Hunter 381b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 382b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 383b1c1df7aSBalaji T K return 0; 384db0fefc5SAdrian Hunter /* 385db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 386db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 387db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 388db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 389db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 390db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 391db0fefc5SAdrian Hunter */ 392e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 393e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 394e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 395e840ce13SAdrian Hunter 396e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 397e840ce13SAdrian Hunter 1, vdd); 398e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 399e840ce13SAdrian Hunter 0, 0); 400db0fefc5SAdrian Hunter } 401db0fefc5SAdrian Hunter } 402db0fefc5SAdrian Hunter 403db0fefc5SAdrian Hunter return 0; 404db0fefc5SAdrian Hunter 405db0fefc5SAdrian Hunter err: 406db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 407db0fefc5SAdrian Hunter return ret; 408db0fefc5SAdrian Hunter } 409db0fefc5SAdrian Hunter 410db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 411db0fefc5SAdrian Hunter { 412db0fefc5SAdrian Hunter regulator_put(host->vcc); 413db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 414db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 415db0fefc5SAdrian Hunter } 416db0fefc5SAdrian Hunter 417b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 418b702b106SAdrian Hunter { 419b702b106SAdrian Hunter return 1; 420b702b106SAdrian Hunter } 421b702b106SAdrian Hunter 422b702b106SAdrian Hunter #else 423b702b106SAdrian Hunter 424b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 425b702b106SAdrian Hunter { 426b702b106SAdrian Hunter return -EINVAL; 427b702b106SAdrian Hunter } 428b702b106SAdrian Hunter 429b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 430b702b106SAdrian Hunter { 431b702b106SAdrian Hunter } 432b702b106SAdrian Hunter 433b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 434b702b106SAdrian Hunter { 435b702b106SAdrian Hunter return 0; 436b702b106SAdrian Hunter } 437b702b106SAdrian Hunter 438b702b106SAdrian Hunter #endif 439b702b106SAdrian Hunter 440b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 441b702b106SAdrian Hunter { 442b702b106SAdrian Hunter int ret; 443b702b106SAdrian Hunter 444b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 445b702b106SAdrian Hunter if (pdata->slots[0].cover) 446b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 447b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 448b702b106SAdrian Hunter else 449b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 450b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 451b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 452b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 453b702b106SAdrian Hunter if (ret) 454b702b106SAdrian Hunter return ret; 455b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 456b702b106SAdrian Hunter if (ret) 457b702b106SAdrian Hunter goto err_free_sp; 458b702b106SAdrian Hunter } else 459b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 460b702b106SAdrian Hunter 461b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 462b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 463b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 464b702b106SAdrian Hunter if (ret) 465b702b106SAdrian Hunter goto err_free_cd; 466b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 467b702b106SAdrian Hunter if (ret) 468b702b106SAdrian Hunter goto err_free_wp; 469b702b106SAdrian Hunter } else 470b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 471b702b106SAdrian Hunter 472b702b106SAdrian Hunter return 0; 473b702b106SAdrian Hunter 474b702b106SAdrian Hunter err_free_wp: 475b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 476b702b106SAdrian Hunter err_free_cd: 477b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 478b702b106SAdrian Hunter err_free_sp: 479b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 480b702b106SAdrian Hunter return ret; 481b702b106SAdrian Hunter } 482b702b106SAdrian Hunter 483b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 484b702b106SAdrian Hunter { 485b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 486b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 487b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 488b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 489b702b106SAdrian Hunter } 490b702b106SAdrian Hunter 491a45c6cb8SMadhusudhan Chikkature /* 492e0c7f99bSAndy Shevchenko * Start clock to the card 493e0c7f99bSAndy Shevchenko */ 494e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 495e0c7f99bSAndy Shevchenko { 496e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 497e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 498e0c7f99bSAndy Shevchenko } 499e0c7f99bSAndy Shevchenko 500e0c7f99bSAndy Shevchenko /* 501a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 502a45c6cb8SMadhusudhan Chikkature */ 50370a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 504a45c6cb8SMadhusudhan Chikkature { 505a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 506a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 507a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 508a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 509a45c6cb8SMadhusudhan Chikkature } 510a45c6cb8SMadhusudhan Chikkature 51193caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 51293caf8e6SAdrian Hunter struct mmc_command *cmd) 513b417577dSAdrian Hunter { 514b417577dSAdrian Hunter unsigned int irq_mask; 515b417577dSAdrian Hunter 516b417577dSAdrian Hunter if (host->use_dma) 517b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 518b417577dSAdrian Hunter else 519b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 520b417577dSAdrian Hunter 52193caf8e6SAdrian Hunter /* Disable timeout for erases */ 52293caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 52393caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 52493caf8e6SAdrian Hunter 525b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 526b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 527b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 528b417577dSAdrian Hunter } 529b417577dSAdrian Hunter 530b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 531b417577dSAdrian Hunter { 532b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 533b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 534b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 535b417577dSAdrian Hunter } 536b417577dSAdrian Hunter 537ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 538d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 539ac330f44SAndy Shevchenko { 540ac330f44SAndy Shevchenko u16 dsor = 0; 541ac330f44SAndy Shevchenko 542ac330f44SAndy Shevchenko if (ios->clock) { 543d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 544ac330f44SAndy Shevchenko if (dsor > 250) 545ac330f44SAndy Shevchenko dsor = 250; 546ac330f44SAndy Shevchenko } 547ac330f44SAndy Shevchenko 548ac330f44SAndy Shevchenko return dsor; 549ac330f44SAndy Shevchenko } 550ac330f44SAndy Shevchenko 5515934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5525934df2fSAndy Shevchenko { 5535934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5545934df2fSAndy Shevchenko unsigned long regval; 5555934df2fSAndy Shevchenko unsigned long timeout; 5565934df2fSAndy Shevchenko 5575934df2fSAndy Shevchenko dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5585934df2fSAndy Shevchenko 5595934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5605934df2fSAndy Shevchenko 5615934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5625934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 563d83b6e03SBalaji TK regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); 5645934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5655934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5665934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5675934df2fSAndy Shevchenko 5685934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5695934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5705934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5715934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5725934df2fSAndy Shevchenko cpu_relax(); 5735934df2fSAndy Shevchenko 5745934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5755934df2fSAndy Shevchenko } 5765934df2fSAndy Shevchenko 5773796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5783796fb8aSAndy Shevchenko { 5793796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5803796fb8aSAndy Shevchenko u32 con; 5813796fb8aSAndy Shevchenko 5823796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5833796fb8aSAndy Shevchenko switch (ios->bus_width) { 5843796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5853796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5863796fb8aSAndy Shevchenko break; 5873796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5883796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5893796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5903796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5913796fb8aSAndy Shevchenko break; 5923796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5933796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5943796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5953796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5963796fb8aSAndy Shevchenko break; 5973796fb8aSAndy Shevchenko } 5983796fb8aSAndy Shevchenko } 5993796fb8aSAndy Shevchenko 6003796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6013796fb8aSAndy Shevchenko { 6023796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6033796fb8aSAndy Shevchenko u32 con; 6043796fb8aSAndy Shevchenko 6053796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6063796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6073796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6083796fb8aSAndy Shevchenko else 6093796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6103796fb8aSAndy Shevchenko } 6113796fb8aSAndy Shevchenko 61211dd62a7SDenis Karpov #ifdef CONFIG_PM 61311dd62a7SDenis Karpov 61411dd62a7SDenis Karpov /* 61511dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 61611dd62a7SDenis Karpov * power state change. 61711dd62a7SDenis Karpov */ 61870a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 61911dd62a7SDenis Karpov { 62011dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 62111dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 62211dd62a7SDenis Karpov int context_loss = 0; 6233796fb8aSAndy Shevchenko u32 hctl, capa; 62411dd62a7SDenis Karpov unsigned long timeout; 62511dd62a7SDenis Karpov 62611dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 62711dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 62811dd62a7SDenis Karpov if (context_loss < 0) 62911dd62a7SDenis Karpov return 1; 63011dd62a7SDenis Karpov } 63111dd62a7SDenis Karpov 63211dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 63311dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 63411dd62a7SDenis Karpov if (host->context_loss == context_loss) 63511dd62a7SDenis Karpov return 1; 63611dd62a7SDenis Karpov 63711dd62a7SDenis Karpov /* Wait for hardware reset */ 63811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 63911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 64011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64111dd62a7SDenis Karpov ; 64211dd62a7SDenis Karpov 64311dd62a7SDenis Karpov /* Do software reset */ 64411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 64511dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 64611dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 64711dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64811dd62a7SDenis Karpov ; 64911dd62a7SDenis Karpov 65011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 65111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 65211dd62a7SDenis Karpov 653c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 65411dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 65511dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 65611dd62a7SDenis Karpov hctl = SDVS18; 65711dd62a7SDenis Karpov else 65811dd62a7SDenis Karpov hctl = SDVS30; 65911dd62a7SDenis Karpov capa = VS30 | VS18; 66011dd62a7SDenis Karpov } else { 66111dd62a7SDenis Karpov hctl = SDVS18; 66211dd62a7SDenis Karpov capa = VS18; 66311dd62a7SDenis Karpov } 66411dd62a7SDenis Karpov 66511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 66711dd62a7SDenis Karpov 66811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 66911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 67011dd62a7SDenis Karpov 67111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 67311dd62a7SDenis Karpov 67411dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 67511dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 67611dd62a7SDenis Karpov && time_before(jiffies, timeout)) 67711dd62a7SDenis Karpov ; 67811dd62a7SDenis Karpov 679b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 68011dd62a7SDenis Karpov 68111dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 68211dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 68311dd62a7SDenis Karpov goto out; 68411dd62a7SDenis Karpov 6853796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 68611dd62a7SDenis Karpov 6875934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 68811dd62a7SDenis Karpov 6893796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6903796fb8aSAndy Shevchenko 69111dd62a7SDenis Karpov out: 69211dd62a7SDenis Karpov host->context_loss = context_loss; 69311dd62a7SDenis Karpov 69411dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 69511dd62a7SDenis Karpov return 0; 69611dd62a7SDenis Karpov } 69711dd62a7SDenis Karpov 69811dd62a7SDenis Karpov /* 69911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 70011dd62a7SDenis Karpov */ 70170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70211dd62a7SDenis Karpov { 70311dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 70411dd62a7SDenis Karpov int context_loss; 70511dd62a7SDenis Karpov 70611dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 70711dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 70811dd62a7SDenis Karpov if (context_loss < 0) 70911dd62a7SDenis Karpov return; 71011dd62a7SDenis Karpov host->context_loss = context_loss; 71111dd62a7SDenis Karpov } 71211dd62a7SDenis Karpov } 71311dd62a7SDenis Karpov 71411dd62a7SDenis Karpov #else 71511dd62a7SDenis Karpov 71670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 71711dd62a7SDenis Karpov { 71811dd62a7SDenis Karpov return 0; 71911dd62a7SDenis Karpov } 72011dd62a7SDenis Karpov 72170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 72211dd62a7SDenis Karpov { 72311dd62a7SDenis Karpov } 72411dd62a7SDenis Karpov 72511dd62a7SDenis Karpov #endif 72611dd62a7SDenis Karpov 727a45c6cb8SMadhusudhan Chikkature /* 728a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 729a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 730a45c6cb8SMadhusudhan Chikkature */ 73170a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 732a45c6cb8SMadhusudhan Chikkature { 733a45c6cb8SMadhusudhan Chikkature int reg = 0; 734a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 735a45c6cb8SMadhusudhan Chikkature 736b62f6228SAdrian Hunter if (host->protect_card) 737b62f6228SAdrian Hunter return; 738b62f6228SAdrian Hunter 739a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 740b417577dSAdrian Hunter 741b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 742a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 743a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 744a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 745a45c6cb8SMadhusudhan Chikkature 746a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 747a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 748a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 749a45c6cb8SMadhusudhan Chikkature 750a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 751a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 752c653a6d4SAdrian Hunter 753c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 754c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 755c653a6d4SAdrian Hunter 756a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 757a45c6cb8SMadhusudhan Chikkature } 758a45c6cb8SMadhusudhan Chikkature 759a45c6cb8SMadhusudhan Chikkature static inline 76070a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 761a45c6cb8SMadhusudhan Chikkature { 762a45c6cb8SMadhusudhan Chikkature int r = 1; 763a45c6cb8SMadhusudhan Chikkature 764191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 765191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 766a45c6cb8SMadhusudhan Chikkature return r; 767a45c6cb8SMadhusudhan Chikkature } 768a45c6cb8SMadhusudhan Chikkature 769a45c6cb8SMadhusudhan Chikkature static ssize_t 77070a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 771a45c6cb8SMadhusudhan Chikkature char *buf) 772a45c6cb8SMadhusudhan Chikkature { 773a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 77470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 775a45c6cb8SMadhusudhan Chikkature 77670a3341aSDenis Karpov return sprintf(buf, "%s\n", 77770a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 778a45c6cb8SMadhusudhan Chikkature } 779a45c6cb8SMadhusudhan Chikkature 78070a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 781a45c6cb8SMadhusudhan Chikkature 782a45c6cb8SMadhusudhan Chikkature static ssize_t 78370a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 784a45c6cb8SMadhusudhan Chikkature char *buf) 785a45c6cb8SMadhusudhan Chikkature { 786a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 78770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 788a45c6cb8SMadhusudhan Chikkature 789191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 790a45c6cb8SMadhusudhan Chikkature } 791a45c6cb8SMadhusudhan Chikkature 79270a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 793a45c6cb8SMadhusudhan Chikkature 794a45c6cb8SMadhusudhan Chikkature /* 795a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 796a45c6cb8SMadhusudhan Chikkature */ 797a45c6cb8SMadhusudhan Chikkature static void 79870a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 799a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 800a45c6cb8SMadhusudhan Chikkature { 801a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 802a45c6cb8SMadhusudhan Chikkature 803a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 804a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 805a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 806a45c6cb8SMadhusudhan Chikkature 80793caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 808a45c6cb8SMadhusudhan Chikkature 8094a694dc9SAdrian Hunter host->response_busy = 0; 810a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 811a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 812a45c6cb8SMadhusudhan Chikkature resptype = 1; 8134a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8144a694dc9SAdrian Hunter resptype = 3; 8154a694dc9SAdrian Hunter host->response_busy = 1; 8164a694dc9SAdrian Hunter } else 817a45c6cb8SMadhusudhan Chikkature resptype = 2; 818a45c6cb8SMadhusudhan Chikkature } 819a45c6cb8SMadhusudhan Chikkature 820a45c6cb8SMadhusudhan Chikkature /* 821a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 822a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 823a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 824a45c6cb8SMadhusudhan Chikkature */ 825a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 826a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 827a45c6cb8SMadhusudhan Chikkature 828a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature if (data) { 831a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 832a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 833a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 834a45c6cb8SMadhusudhan Chikkature else 835a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 836a45c6cb8SMadhusudhan Chikkature } 837a45c6cb8SMadhusudhan Chikkature 838a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 839a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 840a45c6cb8SMadhusudhan Chikkature 841b417577dSAdrian Hunter host->req_in_progress = 1; 8424dffd7a2SAdrian Hunter 843a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 844a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 845a45c6cb8SMadhusudhan Chikkature } 846a45c6cb8SMadhusudhan Chikkature 8470ccd76d4SJuha Yrjola static int 84870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8490ccd76d4SJuha Yrjola { 8500ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8510ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8520ccd76d4SJuha Yrjola else 8530ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8540ccd76d4SJuha Yrjola } 8550ccd76d4SJuha Yrjola 856b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 857b417577dSAdrian Hunter { 858b417577dSAdrian Hunter int dma_ch; 859b417577dSAdrian Hunter 860b417577dSAdrian Hunter spin_lock(&host->irq_lock); 861b417577dSAdrian Hunter host->req_in_progress = 0; 862b417577dSAdrian Hunter dma_ch = host->dma_ch; 863b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 864b417577dSAdrian Hunter 865b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 866b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 867b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 868b417577dSAdrian Hunter return; 869b417577dSAdrian Hunter host->mrq = NULL; 870b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 871b417577dSAdrian Hunter } 872b417577dSAdrian Hunter 873a45c6cb8SMadhusudhan Chikkature /* 874a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 875a45c6cb8SMadhusudhan Chikkature */ 876a45c6cb8SMadhusudhan Chikkature static void 87770a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 878a45c6cb8SMadhusudhan Chikkature { 8794a694dc9SAdrian Hunter if (!data) { 8804a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8814a694dc9SAdrian Hunter 88223050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 88323050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 88423050103SAdrian Hunter host->response_busy) { 88523050103SAdrian Hunter host->response_busy = 0; 88623050103SAdrian Hunter return; 88723050103SAdrian Hunter } 88823050103SAdrian Hunter 889b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8904a694dc9SAdrian Hunter return; 8914a694dc9SAdrian Hunter } 8924a694dc9SAdrian Hunter 893a45c6cb8SMadhusudhan Chikkature host->data = NULL; 894a45c6cb8SMadhusudhan Chikkature 895a45c6cb8SMadhusudhan Chikkature if (!data->error) 896a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 897a45c6cb8SMadhusudhan Chikkature else 898a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 899a45c6cb8SMadhusudhan Chikkature 900a45c6cb8SMadhusudhan Chikkature if (!data->stop) { 901b417577dSAdrian Hunter omap_hsmmc_request_done(host, data->mrq); 902a45c6cb8SMadhusudhan Chikkature return; 903a45c6cb8SMadhusudhan Chikkature } 90470a3341aSDenis Karpov omap_hsmmc_start_command(host, data->stop, NULL); 905a45c6cb8SMadhusudhan Chikkature } 906a45c6cb8SMadhusudhan Chikkature 907a45c6cb8SMadhusudhan Chikkature /* 908a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 909a45c6cb8SMadhusudhan Chikkature */ 910a45c6cb8SMadhusudhan Chikkature static void 91170a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 912a45c6cb8SMadhusudhan Chikkature { 913a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 914a45c6cb8SMadhusudhan Chikkature 915a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 916a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 917a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 918a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 919a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 920a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 921a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 922a45c6cb8SMadhusudhan Chikkature } else { 923a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 924a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 925a45c6cb8SMadhusudhan Chikkature } 926a45c6cb8SMadhusudhan Chikkature } 927b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 928b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 929a45c6cb8SMadhusudhan Chikkature } 930a45c6cb8SMadhusudhan Chikkature 931a45c6cb8SMadhusudhan Chikkature /* 932a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 933a45c6cb8SMadhusudhan Chikkature */ 93470a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 935a45c6cb8SMadhusudhan Chikkature { 936b417577dSAdrian Hunter int dma_ch; 937b417577dSAdrian Hunter 93882788ff5SJarkko Lavinen host->data->error = errno; 939a45c6cb8SMadhusudhan Chikkature 940b417577dSAdrian Hunter spin_lock(&host->irq_lock); 941b417577dSAdrian Hunter dma_ch = host->dma_ch; 942b417577dSAdrian Hunter host->dma_ch = -1; 943b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 944b417577dSAdrian Hunter 945b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 946a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, 947a9120c33SPer Forlin host->data->sg_len, 94870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 949b417577dSAdrian Hunter omap_free_dma(dma_ch); 950053bf34fSPer Forlin host->data->host_cookie = 0; 951a45c6cb8SMadhusudhan Chikkature } 952a45c6cb8SMadhusudhan Chikkature host->data = NULL; 953a45c6cb8SMadhusudhan Chikkature } 954a45c6cb8SMadhusudhan Chikkature 955a45c6cb8SMadhusudhan Chikkature /* 956a45c6cb8SMadhusudhan Chikkature * Readable error output 957a45c6cb8SMadhusudhan Chikkature */ 958a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 959699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 960a45c6cb8SMadhusudhan Chikkature { 961a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 96270a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 963699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 964699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 965699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 966699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 967a45c6cb8SMadhusudhan Chikkature }; 968a45c6cb8SMadhusudhan Chikkature char res[256]; 969a45c6cb8SMadhusudhan Chikkature char *buf = res; 970a45c6cb8SMadhusudhan Chikkature int len, i; 971a45c6cb8SMadhusudhan Chikkature 972a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 973a45c6cb8SMadhusudhan Chikkature buf += len; 974a45c6cb8SMadhusudhan Chikkature 97570a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 976a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 97770a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 978a45c6cb8SMadhusudhan Chikkature buf += len; 979a45c6cb8SMadhusudhan Chikkature } 980a45c6cb8SMadhusudhan Chikkature 981a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 982a45c6cb8SMadhusudhan Chikkature } 983699b958bSAdrian Hunter #else 984699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 985699b958bSAdrian Hunter u32 status) 986699b958bSAdrian Hunter { 987699b958bSAdrian Hunter } 988a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 989a45c6cb8SMadhusudhan Chikkature 9903ebf74b1SJean Pihet /* 9913ebf74b1SJean Pihet * MMC controller internal state machines reset 9923ebf74b1SJean Pihet * 9933ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9943ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9953ebf74b1SJean Pihet * Can be called from interrupt context 9963ebf74b1SJean Pihet */ 99770a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9983ebf74b1SJean Pihet unsigned long bit) 9993ebf74b1SJean Pihet { 10003ebf74b1SJean Pihet unsigned long i = 0; 10013ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 10023ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 10033ebf74b1SJean Pihet 10043ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10053ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10063ebf74b1SJean Pihet 100707ad64b6SMadhusudhan Chikkature /* 100807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 100907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 101007ad64b6SMadhusudhan Chikkature */ 101107ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1012b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 101307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 101407ad64b6SMadhusudhan Chikkature cpu_relax(); 101507ad64b6SMadhusudhan Chikkature } 101607ad64b6SMadhusudhan Chikkature i = 0; 101707ad64b6SMadhusudhan Chikkature 10183ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10193ebf74b1SJean Pihet (i++ < limit)) 10203ebf74b1SJean Pihet cpu_relax(); 10213ebf74b1SJean Pihet 10223ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10233ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10243ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10253ebf74b1SJean Pihet __func__); 10263ebf74b1SJean Pihet } 1027a45c6cb8SMadhusudhan Chikkature 1028b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1029a45c6cb8SMadhusudhan Chikkature { 1030a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1031b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1032a45c6cb8SMadhusudhan Chikkature 1033b417577dSAdrian Hunter if (!host->req_in_progress) { 1034b417577dSAdrian Hunter do { 1035b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, status); 103600adadc1SKevin Hilman /* Flush posted write */ 1037b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1038b417577dSAdrian Hunter } while (status & INT_EN_MASK); 1039b417577dSAdrian Hunter return; 1040a45c6cb8SMadhusudhan Chikkature } 1041a45c6cb8SMadhusudhan Chikkature 1042a45c6cb8SMadhusudhan Chikkature data = host->data; 1043a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1044a45c6cb8SMadhusudhan Chikkature 1045a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 1046699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 1047a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 1048a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 1049a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 1050a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 105170a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 1052191d1f1dSDenis Karpov SRC); 1053a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 1054a45c6cb8SMadhusudhan Chikkature } else { 1055a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 1056a45c6cb8SMadhusudhan Chikkature } 1057a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1058a45c6cb8SMadhusudhan Chikkature } 10594a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10604a694dc9SAdrian Hunter if (host->data) 106170a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 106270a3341aSDenis Karpov -ETIMEDOUT); 10634a694dc9SAdrian Hunter host->response_busy = 0; 106470a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1065c232f457SJean Pihet } 1066a45c6cb8SMadhusudhan Chikkature } 1067a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 1068a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 10694a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10704a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 10714a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 10724a694dc9SAdrian Hunter 10734a694dc9SAdrian Hunter if (host->data) 107470a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 1075a45c6cb8SMadhusudhan Chikkature else 10764a694dc9SAdrian Hunter host->mrq->cmd->error = err; 10774a694dc9SAdrian Hunter host->response_busy = 0; 107870a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1079a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1080a45c6cb8SMadhusudhan Chikkature } 1081a45c6cb8SMadhusudhan Chikkature } 1082a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 1083a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1084a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 1085a45c6cb8SMadhusudhan Chikkature if (host->cmd) 1086a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1087a45c6cb8SMadhusudhan Chikkature if (host->data) 1088a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1089a45c6cb8SMadhusudhan Chikkature } 1090a45c6cb8SMadhusudhan Chikkature } 1091a45c6cb8SMadhusudhan Chikkature 1092a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 1093a45c6cb8SMadhusudhan Chikkature 1094a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 109570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 10960a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 109770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1098b417577dSAdrian Hunter } 1099a45c6cb8SMadhusudhan Chikkature 1100b417577dSAdrian Hunter /* 1101b417577dSAdrian Hunter * MMC controller IRQ handler 1102b417577dSAdrian Hunter */ 1103b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1104b417577dSAdrian Hunter { 1105b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1106b417577dSAdrian Hunter int status; 1107b417577dSAdrian Hunter 1108b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1109b417577dSAdrian Hunter do { 1110b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 1111b417577dSAdrian Hunter /* Flush posted write */ 1112b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1113b417577dSAdrian Hunter } while (status & INT_EN_MASK); 11144dffd7a2SAdrian Hunter 1115a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1116a45c6cb8SMadhusudhan Chikkature } 1117a45c6cb8SMadhusudhan Chikkature 111870a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1119e13bb300SAdrian Hunter { 1120e13bb300SAdrian Hunter unsigned long i; 1121e13bb300SAdrian Hunter 1122e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1123e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1124e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1125e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1126e13bb300SAdrian Hunter break; 1127e13bb300SAdrian Hunter cpu_relax(); 1128e13bb300SAdrian Hunter } 1129e13bb300SAdrian Hunter } 1130e13bb300SAdrian Hunter 1131a45c6cb8SMadhusudhan Chikkature /* 1132eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1133eb250826SDavid Brownell * 1134eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1135eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1136eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1137a45c6cb8SMadhusudhan Chikkature */ 113870a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1139a45c6cb8SMadhusudhan Chikkature { 1140a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1141a45c6cb8SMadhusudhan Chikkature int ret; 1142a45c6cb8SMadhusudhan Chikkature 1143a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1144fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 11452bec0893SAdrian Hunter if (host->got_dbclk) 1146a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1147a45c6cb8SMadhusudhan Chikkature 1148a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1149a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1150a45c6cb8SMadhusudhan Chikkature 1151a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11522bec0893SAdrian Hunter if (!ret) 11532bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11542bec0893SAdrian Hunter vdd); 1155fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 11562bec0893SAdrian Hunter if (host->got_dbclk) 11572bec0893SAdrian Hunter clk_enable(host->dbclk); 11582bec0893SAdrian Hunter 1159a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1160a45c6cb8SMadhusudhan Chikkature goto err; 1161a45c6cb8SMadhusudhan Chikkature 1162a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1163a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1164a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1165eb250826SDavid Brownell 1166a45c6cb8SMadhusudhan Chikkature /* 1167a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1168a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 116970a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1170a45c6cb8SMadhusudhan Chikkature * 1171eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1172eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1173eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1174eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1175eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1176eb250826SDavid Brownell * 1177eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1178eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1179eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1180a45c6cb8SMadhusudhan Chikkature */ 1181eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1182a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1183eb250826SDavid Brownell else 1184eb250826SDavid Brownell reg_val |= SDVS30; 1185a45c6cb8SMadhusudhan Chikkature 1186a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1187e13bb300SAdrian Hunter set_sd_bus_power(host); 1188a45c6cb8SMadhusudhan Chikkature 1189a45c6cb8SMadhusudhan Chikkature return 0; 1190a45c6cb8SMadhusudhan Chikkature err: 1191a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1192a45c6cb8SMadhusudhan Chikkature return ret; 1193a45c6cb8SMadhusudhan Chikkature } 1194a45c6cb8SMadhusudhan Chikkature 1195b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1196b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1197b62f6228SAdrian Hunter { 1198b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1199b62f6228SAdrian Hunter return; 1200b62f6228SAdrian Hunter 1201b62f6228SAdrian Hunter host->reqs_blocked = 0; 1202b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1203b62f6228SAdrian Hunter if (host->protect_card) { 1204a3c76eb9SGirish K S pr_info("%s: cover is closed, " 1205b62f6228SAdrian Hunter "card is now accessible\n", 1206b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1207b62f6228SAdrian Hunter host->protect_card = 0; 1208b62f6228SAdrian Hunter } 1209b62f6228SAdrian Hunter } else { 1210b62f6228SAdrian Hunter if (!host->protect_card) { 12113f8ddb03SLinus Torvalds pr_info("%s: cover is open, " 1212b62f6228SAdrian Hunter "card is now inaccessible\n", 1213b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1214b62f6228SAdrian Hunter host->protect_card = 1; 1215b62f6228SAdrian Hunter } 1216b62f6228SAdrian Hunter } 1217b62f6228SAdrian Hunter } 1218b62f6228SAdrian Hunter 1219a45c6cb8SMadhusudhan Chikkature /* 12207efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1221a45c6cb8SMadhusudhan Chikkature */ 12227efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1223a45c6cb8SMadhusudhan Chikkature { 12247efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1225249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1226a6b2240dSAdrian Hunter int carddetect; 1227249d0fa9SDavid Brownell 1228a6b2240dSAdrian Hunter if (host->suspended) 12297efab4f3SNeilBrown return IRQ_HANDLED; 1230a45c6cb8SMadhusudhan Chikkature 1231a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1232a6b2240dSAdrian Hunter 1233191d1f1dSDenis Karpov if (slot->card_detect) 1234db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1235b62f6228SAdrian Hunter else { 1236b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1237a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1238b62f6228SAdrian Hunter } 1239a6b2240dSAdrian Hunter 1240cdeebaddSMadhusudhan Chikkature if (carddetect) 1241a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1242cdeebaddSMadhusudhan Chikkature else 1243a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1244a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1245a45c6cb8SMadhusudhan Chikkature } 1246a45c6cb8SMadhusudhan Chikkature 124770a3341aSDenis Karpov static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 12480ccd76d4SJuha Yrjola struct mmc_data *data) 12490ccd76d4SJuha Yrjola { 12500ccd76d4SJuha Yrjola int sync_dev; 12510ccd76d4SJuha Yrjola 1252f3e2f1ddSGrazvydas Ignotas if (data->flags & MMC_DATA_WRITE) 1253f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_tx; 12540ccd76d4SJuha Yrjola else 1255f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_rx; 12560ccd76d4SJuha Yrjola return sync_dev; 12570ccd76d4SJuha Yrjola } 12580ccd76d4SJuha Yrjola 125970a3341aSDenis Karpov static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 12600ccd76d4SJuha Yrjola struct mmc_data *data, 12610ccd76d4SJuha Yrjola struct scatterlist *sgl) 12620ccd76d4SJuha Yrjola { 12630ccd76d4SJuha Yrjola int blksz, nblk, dma_ch; 12640ccd76d4SJuha Yrjola 12650ccd76d4SJuha Yrjola dma_ch = host->dma_ch; 12660ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) { 12670ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 12680ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 12690ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 12700ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 12710ccd76d4SJuha Yrjola } else { 12720ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 12730ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 12740ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 12750ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 12760ccd76d4SJuha Yrjola } 12770ccd76d4SJuha Yrjola 12780ccd76d4SJuha Yrjola blksz = host->data->blksz; 12790ccd76d4SJuha Yrjola nblk = sg_dma_len(sgl) / blksz; 12800ccd76d4SJuha Yrjola 12810ccd76d4SJuha Yrjola omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 12820ccd76d4SJuha Yrjola blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 128370a3341aSDenis Karpov omap_hsmmc_get_dma_sync_dev(host, data), 12840ccd76d4SJuha Yrjola !(data->flags & MMC_DATA_WRITE)); 12850ccd76d4SJuha Yrjola 12860ccd76d4SJuha Yrjola omap_start_dma(dma_ch); 12870ccd76d4SJuha Yrjola } 12880ccd76d4SJuha Yrjola 1289a45c6cb8SMadhusudhan Chikkature /* 1290a45c6cb8SMadhusudhan Chikkature * DMA call back function 1291a45c6cb8SMadhusudhan Chikkature */ 1292b417577dSAdrian Hunter static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1293a45c6cb8SMadhusudhan Chikkature { 1294b417577dSAdrian Hunter struct omap_hsmmc_host *host = cb_data; 1295770d7432SAdrian Hunter struct mmc_data *data; 1296b417577dSAdrian Hunter int dma_ch, req_in_progress; 1297a45c6cb8SMadhusudhan Chikkature 1298f3584e5eSVenkatraman S if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1299f3584e5eSVenkatraman S dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1300f3584e5eSVenkatraman S ch_status); 1301f3584e5eSVenkatraman S return; 1302f3584e5eSVenkatraman S } 1303a45c6cb8SMadhusudhan Chikkature 1304b417577dSAdrian Hunter spin_lock(&host->irq_lock); 1305b417577dSAdrian Hunter if (host->dma_ch < 0) { 1306b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1307a45c6cb8SMadhusudhan Chikkature return; 1308b417577dSAdrian Hunter } 1309a45c6cb8SMadhusudhan Chikkature 1310770d7432SAdrian Hunter data = host->mrq->data; 13110ccd76d4SJuha Yrjola host->dma_sg_idx++; 13120ccd76d4SJuha Yrjola if (host->dma_sg_idx < host->dma_len) { 13130ccd76d4SJuha Yrjola /* Fire up the next transfer. */ 1314b417577dSAdrian Hunter omap_hsmmc_config_dma_params(host, data, 1315b417577dSAdrian Hunter data->sg + host->dma_sg_idx); 1316b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 13170ccd76d4SJuha Yrjola return; 13180ccd76d4SJuha Yrjola } 13190ccd76d4SJuha Yrjola 13209782aff8SPer Forlin if (!data->host_cookie) 1321a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1322b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1323b417577dSAdrian Hunter 1324b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1325b417577dSAdrian Hunter dma_ch = host->dma_ch; 1326a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1327b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1328b417577dSAdrian Hunter 1329b417577dSAdrian Hunter omap_free_dma(dma_ch); 1330b417577dSAdrian Hunter 1331b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1332b417577dSAdrian Hunter if (!req_in_progress) { 1333b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1334b417577dSAdrian Hunter 1335b417577dSAdrian Hunter host->mrq = NULL; 1336b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1337b417577dSAdrian Hunter } 1338a45c6cb8SMadhusudhan Chikkature } 1339a45c6cb8SMadhusudhan Chikkature 13409782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13419782aff8SPer Forlin struct mmc_data *data, 13429782aff8SPer Forlin struct omap_hsmmc_next *next) 13439782aff8SPer Forlin { 13449782aff8SPer Forlin int dma_len; 13459782aff8SPer Forlin 13469782aff8SPer Forlin if (!next && data->host_cookie && 13479782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 1348a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 13499782aff8SPer Forlin " host->next_data.cookie %d\n", 13509782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13519782aff8SPer Forlin data->host_cookie = 0; 13529782aff8SPer Forlin } 13539782aff8SPer Forlin 13549782aff8SPer Forlin /* Check if next job is already prepared */ 13559782aff8SPer Forlin if (next || 13569782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 13579782aff8SPer Forlin dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 13589782aff8SPer Forlin data->sg_len, 13599782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13609782aff8SPer Forlin 13619782aff8SPer Forlin } else { 13629782aff8SPer Forlin dma_len = host->next_data.dma_len; 13639782aff8SPer Forlin host->next_data.dma_len = 0; 13649782aff8SPer Forlin } 13659782aff8SPer Forlin 13669782aff8SPer Forlin 13679782aff8SPer Forlin if (dma_len == 0) 13689782aff8SPer Forlin return -EINVAL; 13699782aff8SPer Forlin 13709782aff8SPer Forlin if (next) { 13719782aff8SPer Forlin next->dma_len = dma_len; 13729782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13739782aff8SPer Forlin } else 13749782aff8SPer Forlin host->dma_len = dma_len; 13759782aff8SPer Forlin 13769782aff8SPer Forlin return 0; 13779782aff8SPer Forlin } 13789782aff8SPer Forlin 1379a45c6cb8SMadhusudhan Chikkature /* 1380a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1381a45c6cb8SMadhusudhan Chikkature */ 138270a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 138370a3341aSDenis Karpov struct mmc_request *req) 1384a45c6cb8SMadhusudhan Chikkature { 1385b417577dSAdrian Hunter int dma_ch = 0, ret = 0, i; 1386a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1387a45c6cb8SMadhusudhan Chikkature 13880ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1389a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13900ccd76d4SJuha Yrjola struct scatterlist *sgl; 13910ccd76d4SJuha Yrjola 13920ccd76d4SJuha Yrjola sgl = data->sg + i; 13930ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13940ccd76d4SJuha Yrjola return -EINVAL; 13950ccd76d4SJuha Yrjola } 13960ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13970ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13980ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13990ccd76d4SJuha Yrjola */ 14000ccd76d4SJuha Yrjola return -EINVAL; 14010ccd76d4SJuha Yrjola 1402b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1403a45c6cb8SMadhusudhan Chikkature 140470a3341aSDenis Karpov ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 140570a3341aSDenis Karpov "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1406a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 14070ccd76d4SJuha Yrjola dev_err(mmc_dev(host->mmc), 1408a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 1409a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 1410a45c6cb8SMadhusudhan Chikkature return ret; 1411a45c6cb8SMadhusudhan Chikkature } 14129782aff8SPer Forlin ret = omap_hsmmc_pre_dma_transfer(host, data, NULL); 14139782aff8SPer Forlin if (ret) 14149782aff8SPer Forlin return ret; 1415a45c6cb8SMadhusudhan Chikkature 1416a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 14170ccd76d4SJuha Yrjola host->dma_sg_idx = 0; 1418a45c6cb8SMadhusudhan Chikkature 141970a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, data, data->sg); 1420a45c6cb8SMadhusudhan Chikkature 1421a45c6cb8SMadhusudhan Chikkature return 0; 1422a45c6cb8SMadhusudhan Chikkature } 1423a45c6cb8SMadhusudhan Chikkature 142470a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1425e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1426e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1427a45c6cb8SMadhusudhan Chikkature { 1428a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1429a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1430a45c6cb8SMadhusudhan Chikkature 1431a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1432a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1433a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1434a45c6cb8SMadhusudhan Chikkature clkd = 1; 1435a45c6cb8SMadhusudhan Chikkature 1436a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1437e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1438e2bf08d6SAdrian Hunter timeout += timeout_clks; 1439a45c6cb8SMadhusudhan Chikkature if (timeout) { 1440a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1441a45c6cb8SMadhusudhan Chikkature dto += 1; 1442a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1443a45c6cb8SMadhusudhan Chikkature } 1444a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1445a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1446a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1447a45c6cb8SMadhusudhan Chikkature dto += 1; 1448a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1449a45c6cb8SMadhusudhan Chikkature dto -= 13; 1450a45c6cb8SMadhusudhan Chikkature else 1451a45c6cb8SMadhusudhan Chikkature dto = 0; 1452a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1453a45c6cb8SMadhusudhan Chikkature dto = 14; 1454a45c6cb8SMadhusudhan Chikkature } 1455a45c6cb8SMadhusudhan Chikkature 1456a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1457a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1458a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1459a45c6cb8SMadhusudhan Chikkature } 1460a45c6cb8SMadhusudhan Chikkature 1461a45c6cb8SMadhusudhan Chikkature /* 1462a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1463a45c6cb8SMadhusudhan Chikkature */ 1464a45c6cb8SMadhusudhan Chikkature static int 146570a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1466a45c6cb8SMadhusudhan Chikkature { 1467a45c6cb8SMadhusudhan Chikkature int ret; 1468a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1469a45c6cb8SMadhusudhan Chikkature 1470a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1471a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1472e2bf08d6SAdrian Hunter /* 1473e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1474e2bf08d6SAdrian Hunter * busy signal. 1475e2bf08d6SAdrian Hunter */ 1476e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1477e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1478a45c6cb8SMadhusudhan Chikkature return 0; 1479a45c6cb8SMadhusudhan Chikkature } 1480a45c6cb8SMadhusudhan Chikkature 1481a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1482a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1483e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1484a45c6cb8SMadhusudhan Chikkature 1485a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 148670a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1487a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1488a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1489a45c6cb8SMadhusudhan Chikkature return ret; 1490a45c6cb8SMadhusudhan Chikkature } 1491a45c6cb8SMadhusudhan Chikkature } 1492a45c6cb8SMadhusudhan Chikkature return 0; 1493a45c6cb8SMadhusudhan Chikkature } 1494a45c6cb8SMadhusudhan Chikkature 14959782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14969782aff8SPer Forlin int err) 14979782aff8SPer Forlin { 14989782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14999782aff8SPer Forlin struct mmc_data *data = mrq->data; 15009782aff8SPer Forlin 15019782aff8SPer Forlin if (host->use_dma) { 1502053bf34fSPer Forlin if (data->host_cookie) 1503053bf34fSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 1504053bf34fSPer Forlin data->sg_len, 15059782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15069782aff8SPer Forlin data->host_cookie = 0; 15079782aff8SPer Forlin } 15089782aff8SPer Forlin } 15099782aff8SPer Forlin 15109782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15119782aff8SPer Forlin bool is_first_req) 15129782aff8SPer Forlin { 15139782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15149782aff8SPer Forlin 15159782aff8SPer Forlin if (mrq->data->host_cookie) { 15169782aff8SPer Forlin mrq->data->host_cookie = 0; 15179782aff8SPer Forlin return ; 15189782aff8SPer Forlin } 15199782aff8SPer Forlin 15209782aff8SPer Forlin if (host->use_dma) 15219782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 15229782aff8SPer Forlin &host->next_data)) 15239782aff8SPer Forlin mrq->data->host_cookie = 0; 15249782aff8SPer Forlin } 15259782aff8SPer Forlin 1526a45c6cb8SMadhusudhan Chikkature /* 1527a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1528a45c6cb8SMadhusudhan Chikkature */ 152970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1530a45c6cb8SMadhusudhan Chikkature { 153170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1532a3f406f8SJarkko Lavinen int err; 1533a45c6cb8SMadhusudhan Chikkature 1534b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1535b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1536b62f6228SAdrian Hunter if (host->protect_card) { 1537b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1538b62f6228SAdrian Hunter /* 1539b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1540b62f6228SAdrian Hunter * state by resetting the command and data state 1541b62f6228SAdrian Hunter * machines. 1542b62f6228SAdrian Hunter */ 1543b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1544b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1545b62f6228SAdrian Hunter host->reqs_blocked += 1; 1546b62f6228SAdrian Hunter } 1547b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1548b62f6228SAdrian Hunter if (req->data) 1549b62f6228SAdrian Hunter req->data->error = -EBADF; 1550b417577dSAdrian Hunter req->cmd->retries = 0; 1551b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1552b62f6228SAdrian Hunter return; 1553b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1554b62f6228SAdrian Hunter host->reqs_blocked = 0; 1555a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1556a45c6cb8SMadhusudhan Chikkature host->mrq = req; 155770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1558a3f406f8SJarkko Lavinen if (err) { 1559a3f406f8SJarkko Lavinen req->cmd->error = err; 1560a3f406f8SJarkko Lavinen if (req->data) 1561a3f406f8SJarkko Lavinen req->data->error = err; 1562a3f406f8SJarkko Lavinen host->mrq = NULL; 1563a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1564a3f406f8SJarkko Lavinen return; 1565a3f406f8SJarkko Lavinen } 1566a3f406f8SJarkko Lavinen 156770a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1568a45c6cb8SMadhusudhan Chikkature } 1569a45c6cb8SMadhusudhan Chikkature 1570a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 157170a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1572a45c6cb8SMadhusudhan Chikkature { 157370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1574a3621465SAdrian Hunter int do_send_init_stream = 0; 1575a45c6cb8SMadhusudhan Chikkature 1576fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15775e2ea617SAdrian Hunter 1578a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1579a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1580a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1581a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1582a3621465SAdrian Hunter 0, 0); 1583623821f7SAdrian Hunter host->vdd = 0; 1584a45c6cb8SMadhusudhan Chikkature break; 1585a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1586a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1587a3621465SAdrian Hunter 1, ios->vdd); 1588623821f7SAdrian Hunter host->vdd = ios->vdd; 1589a45c6cb8SMadhusudhan Chikkature break; 1590a3621465SAdrian Hunter case MMC_POWER_ON: 1591a3621465SAdrian Hunter do_send_init_stream = 1; 1592a3621465SAdrian Hunter break; 1593a3621465SAdrian Hunter } 1594a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1595a45c6cb8SMadhusudhan Chikkature } 1596a45c6cb8SMadhusudhan Chikkature 1597dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1598dd498effSDenis Karpov 15993796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1600a45c6cb8SMadhusudhan Chikkature 16014621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1602eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1603eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1604eb250826SDavid Brownell */ 1605a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1606a45c6cb8SMadhusudhan Chikkature (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1607a45c6cb8SMadhusudhan Chikkature /* 1608a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1609a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1610a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1611a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1612a45c6cb8SMadhusudhan Chikkature */ 161370a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1614a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1615a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1616a45c6cb8SMadhusudhan Chikkature } 1617a45c6cb8SMadhusudhan Chikkature } 1618a45c6cb8SMadhusudhan Chikkature 16195934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1620a45c6cb8SMadhusudhan Chikkature 1621a3621465SAdrian Hunter if (do_send_init_stream) 1622a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1623a45c6cb8SMadhusudhan Chikkature 16243796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16255e2ea617SAdrian Hunter 1626fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1627a45c6cb8SMadhusudhan Chikkature } 1628a45c6cb8SMadhusudhan Chikkature 1629a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1630a45c6cb8SMadhusudhan Chikkature { 163170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1632a45c6cb8SMadhusudhan Chikkature 1633191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1634a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1635db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1636a45c6cb8SMadhusudhan Chikkature } 1637a45c6cb8SMadhusudhan Chikkature 1638a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1639a45c6cb8SMadhusudhan Chikkature { 164070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1641a45c6cb8SMadhusudhan Chikkature 1642191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1643a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1644191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1645a45c6cb8SMadhusudhan Chikkature } 1646a45c6cb8SMadhusudhan Chikkature 16474816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16484816858cSGrazvydas Ignotas { 16494816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16504816858cSGrazvydas Ignotas 16514816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 16524816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 16534816858cSGrazvydas Ignotas } 16544816858cSGrazvydas Ignotas 165570a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 16561b331e69SKim Kyuwon { 16571b331e69SKim Kyuwon u32 hctl, capa, value; 16581b331e69SKim Kyuwon 16591b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 16604621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 16611b331e69SKim Kyuwon hctl = SDVS30; 16621b331e69SKim Kyuwon capa = VS30 | VS18; 16631b331e69SKim Kyuwon } else { 16641b331e69SKim Kyuwon hctl = SDVS18; 16651b331e69SKim Kyuwon capa = VS18; 16661b331e69SKim Kyuwon } 16671b331e69SKim Kyuwon 16681b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 16691b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 16701b331e69SKim Kyuwon 16711b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 16721b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 16731b331e69SKim Kyuwon 16741b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 16751b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 16761b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 16771b331e69SKim Kyuwon 16781b331e69SKim Kyuwon /* Set SD bus power bit */ 1679e13bb300SAdrian Hunter set_sd_bus_power(host); 16801b331e69SKim Kyuwon } 16811b331e69SKim Kyuwon 168270a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1683dd498effSDenis Karpov { 168470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1685dd498effSDenis Karpov 1686fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1687fa4aa2d4SBalaji T K 1688dd498effSDenis Karpov return 0; 1689dd498effSDenis Karpov } 1690dd498effSDenis Karpov 169170a3341aSDenis Karpov static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1692dd498effSDenis Karpov { 169370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1694dd498effSDenis Karpov 1695fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1696fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1697fa4aa2d4SBalaji T K 1698dd498effSDenis Karpov return 0; 1699dd498effSDenis Karpov } 1700dd498effSDenis Karpov 170170a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 170270a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 170370a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 17049782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17059782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 170670a3341aSDenis Karpov .request = omap_hsmmc_request, 170770a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1708dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1709dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 17104816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1711dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1712dd498effSDenis Karpov }; 1713dd498effSDenis Karpov 1714d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1715d900f712SDenis Karpov 171670a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1717d900f712SDenis Karpov { 1718d900f712SDenis Karpov struct mmc_host *mmc = s->private; 171970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 172011dd62a7SDenis Karpov int context_loss = 0; 172111dd62a7SDenis Karpov 172270a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 172370a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1724d900f712SDenis Karpov 17255e2ea617SAdrian Hunter seq_printf(s, "mmc%d:\n" 17265e2ea617SAdrian Hunter " enabled:\t%d\n" 1727dd498effSDenis Karpov " dpm_state:\t%d\n" 17285e2ea617SAdrian Hunter " nesting_cnt:\t%d\n" 172911dd62a7SDenis Karpov " ctx_loss:\t%d:%d\n" 17305e2ea617SAdrian Hunter "\nregs:\n", 1731dd498effSDenis Karpov mmc->index, mmc->enabled ? 1 : 0, 1732dd498effSDenis Karpov host->dpm_state, mmc->nesting_cnt, 173311dd62a7SDenis Karpov host->context_loss, context_loss); 17345e2ea617SAdrian Hunter 17357a8c2cefSBalaji T K if (host->suspended) { 1736dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1737dd498effSDenis Karpov return 0; 1738dd498effSDenis Karpov } 1739dd498effSDenis Karpov 1740fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1741d900f712SDenis Karpov 1742d900f712SDenis Karpov seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1743d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1744d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1745d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1746d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1747d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1748d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1749d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1750d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1751d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1752d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1753d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1754d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1755d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 17565e2ea617SAdrian Hunter 1757fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1758fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1759dd498effSDenis Karpov 1760d900f712SDenis Karpov return 0; 1761d900f712SDenis Karpov } 1762d900f712SDenis Karpov 176370a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1764d900f712SDenis Karpov { 176570a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1766d900f712SDenis Karpov } 1767d900f712SDenis Karpov 1768d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 176970a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1770d900f712SDenis Karpov .read = seq_read, 1771d900f712SDenis Karpov .llseek = seq_lseek, 1772d900f712SDenis Karpov .release = single_release, 1773d900f712SDenis Karpov }; 1774d900f712SDenis Karpov 177570a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1776d900f712SDenis Karpov { 1777d900f712SDenis Karpov if (mmc->debugfs_root) 1778d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1779d900f712SDenis Karpov mmc, &mmc_regs_fops); 1780d900f712SDenis Karpov } 1781d900f712SDenis Karpov 1782d900f712SDenis Karpov #else 1783d900f712SDenis Karpov 178470a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1785d900f712SDenis Karpov { 1786d900f712SDenis Karpov } 1787d900f712SDenis Karpov 1788d900f712SDenis Karpov #endif 1789d900f712SDenis Karpov 179070a3341aSDenis Karpov static int __init omap_hsmmc_probe(struct platform_device *pdev) 1791a45c6cb8SMadhusudhan Chikkature { 1792a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1793a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179470a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1795a45c6cb8SMadhusudhan Chikkature struct resource *res; 1796db0fefc5SAdrian Hunter int ret, irq; 1797a45c6cb8SMadhusudhan Chikkature 1798a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1799a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1800a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1801a45c6cb8SMadhusudhan Chikkature } 1802a45c6cb8SMadhusudhan Chikkature 1803a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1804a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1805a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1806a45c6cb8SMadhusudhan Chikkature } 1807a45c6cb8SMadhusudhan Chikkature 1808a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1809a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1810a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1811a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1812a45c6cb8SMadhusudhan Chikkature 181391a0b089Skishore kadiyala res->start += pdata->reg_offset; 181491a0b089Skishore kadiyala res->end += pdata->reg_offset; 1815984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1816a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1817a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1818a45c6cb8SMadhusudhan Chikkature 1819db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1820db0fefc5SAdrian Hunter if (ret) 1821db0fefc5SAdrian Hunter goto err; 1822db0fefc5SAdrian Hunter 182370a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1824a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1825a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1826db0fefc5SAdrian Hunter goto err_alloc; 1827a45c6cb8SMadhusudhan Chikkature } 1828a45c6cb8SMadhusudhan Chikkature 1829a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1830a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1831a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1832a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1833a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1834a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 1835a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1836a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1837a45c6cb8SMadhusudhan Chikkature host->id = pdev->id; 1838a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1839a45c6cb8SMadhusudhan Chikkature host->mapbase = res->start; 1840a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18416da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18429782aff8SPer Forlin host->next_data.cookie = 1; 1843a45c6cb8SMadhusudhan Chikkature 1844a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1845a45c6cb8SMadhusudhan Chikkature 184670a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1847dd498effSDenis Karpov 1848e0eb2424SAdrian Hunter /* 1849e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1850e0eb2424SAdrian Hunter * no off state. 1851e0eb2424SAdrian Hunter */ 1852e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1853e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1854e0eb2424SAdrian Hunter 18556b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1856d418ed87SDaniel Mack 1857d418ed87SDaniel Mack if (pdata->max_freq > 0) 1858d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1859d418ed87SDaniel Mack else 18606b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1861a45c6cb8SMadhusudhan Chikkature 18624dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1863a45c6cb8SMadhusudhan Chikkature 18646f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1865a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1866a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1867a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1868a45c6cb8SMadhusudhan Chikkature goto err1; 1869a45c6cb8SMadhusudhan Chikkature } 1870a45c6cb8SMadhusudhan Chikkature 187170a3341aSDenis Karpov omap_hsmmc_context_save(host); 187211dd62a7SDenis Karpov 18735e2ea617SAdrian Hunter mmc->caps |= MMC_CAP_DISABLE; 18749b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18759b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18769b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18779b68256cSPaul Walmsley } 1878dd498effSDenis Karpov 1879fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1880fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1881fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1882fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1883a45c6cb8SMadhusudhan Chikkature 18842bec0893SAdrian Hunter if (cpu_is_omap2430()) { 1885a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1886a45c6cb8SMadhusudhan Chikkature /* 1887a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1888a45c6cb8SMadhusudhan Chikkature */ 1889a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->dbclk)) 18902bec0893SAdrian Hunter dev_warn(mmc_dev(host->mmc), 18912bec0893SAdrian Hunter "Failed to get debounce clock\n"); 1892a45c6cb8SMadhusudhan Chikkature else 18932bec0893SAdrian Hunter host->got_dbclk = 1; 18942bec0893SAdrian Hunter 18952bec0893SAdrian Hunter if (host->got_dbclk) 1896a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1897a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 1898a45c6cb8SMadhusudhan Chikkature " clk failed\n"); 18992bec0893SAdrian Hunter } 1900a45c6cb8SMadhusudhan Chikkature 19010ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19020ccd76d4SJuha Yrjola * as we want. */ 1903a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19040ccd76d4SJuha Yrjola 1905a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1906a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1907a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1908a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1909a45c6cb8SMadhusudhan Chikkature 191013189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 191193caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1912a45c6cb8SMadhusudhan Chikkature 19133a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19143a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1915a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1916a45c6cb8SMadhusudhan Chikkature 1917191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 191823d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 191923d99bb9SAdrian Hunter 19206fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19216fdc75deSEliad Peller 192270a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1923a45c6cb8SMadhusudhan Chikkature 1924b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1925b7bf773bSBalaji T K if (!res) { 1926b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 1927f3e2f1ddSGrazvydas Ignotas goto err_irq; 1928a45c6cb8SMadhusudhan Chikkature } 1929b7bf773bSBalaji T K host->dma_line_tx = res->start; 1930b7bf773bSBalaji T K 1931b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1932b7bf773bSBalaji T K if (!res) { 1933b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 1934b7bf773bSBalaji T K goto err_irq; 1935b7bf773bSBalaji T K } 1936b7bf773bSBalaji T K host->dma_line_rx = res->start; 1937a45c6cb8SMadhusudhan Chikkature 1938a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1939d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1940a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1941a45c6cb8SMadhusudhan Chikkature if (ret) { 1942a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1943a45c6cb8SMadhusudhan Chikkature goto err_irq; 1944a45c6cb8SMadhusudhan Chikkature } 1945a45c6cb8SMadhusudhan Chikkature 1946a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1947a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 194870a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 194970a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1950a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1951a45c6cb8SMadhusudhan Chikkature } 1952a45c6cb8SMadhusudhan Chikkature } 1953db0fefc5SAdrian Hunter 1954b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1955db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1956db0fefc5SAdrian Hunter if (ret) 1957db0fefc5SAdrian Hunter goto err_reg; 1958db0fefc5SAdrian Hunter host->use_reg = 1; 1959db0fefc5SAdrian Hunter } 1960db0fefc5SAdrian Hunter 1961b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1962a45c6cb8SMadhusudhan Chikkature 1963a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1964e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19657efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19667efab4f3SNeilBrown NULL, 19677efab4f3SNeilBrown omap_hsmmc_detect, 1968d9618e9fSYong Zhang IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1969a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1970a45c6cb8SMadhusudhan Chikkature if (ret) { 1971a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1972a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1973a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1974a45c6cb8SMadhusudhan Chikkature } 197572f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 197672f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1977a45c6cb8SMadhusudhan Chikkature } 1978a45c6cb8SMadhusudhan Chikkature 1979b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1980a45c6cb8SMadhusudhan Chikkature 1981b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1982b62f6228SAdrian Hunter 1983a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1984a45c6cb8SMadhusudhan Chikkature 1985191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1986a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1987a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1988a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1989a45c6cb8SMadhusudhan Chikkature } 1990191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1991a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 1992a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 1993a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1994db0fefc5SAdrian Hunter goto err_slot_name; 1995a45c6cb8SMadhusudhan Chikkature } 1996a45c6cb8SMadhusudhan Chikkature 199770a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 1998fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1999fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2000d900f712SDenis Karpov 2001a45c6cb8SMadhusudhan Chikkature return 0; 2002a45c6cb8SMadhusudhan Chikkature 2003a45c6cb8SMadhusudhan Chikkature err_slot_name: 2004a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2005a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2006db0fefc5SAdrian Hunter err_irq_cd: 2007db0fefc5SAdrian Hunter if (host->use_reg) 2008db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2009db0fefc5SAdrian Hunter err_reg: 2010db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2011db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2012a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2013a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2014a45c6cb8SMadhusudhan Chikkature err_irq: 2015fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2016fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2017a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 20182bec0893SAdrian Hunter if (host->got_dbclk) { 2019a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2020a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2021a45c6cb8SMadhusudhan Chikkature } 2022a45c6cb8SMadhusudhan Chikkature err1: 2023a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2024db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 2025a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2026db0fefc5SAdrian Hunter err_alloc: 2027db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2028db0fefc5SAdrian Hunter err: 2029984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2030a45c6cb8SMadhusudhan Chikkature return ret; 2031a45c6cb8SMadhusudhan Chikkature } 2032a45c6cb8SMadhusudhan Chikkature 203370a3341aSDenis Karpov static int omap_hsmmc_remove(struct platform_device *pdev) 2034a45c6cb8SMadhusudhan Chikkature { 203570a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2036a45c6cb8SMadhusudhan Chikkature struct resource *res; 2037a45c6cb8SMadhusudhan Chikkature 2038a45c6cb8SMadhusudhan Chikkature if (host) { 2039fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2040a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2041db0fefc5SAdrian Hunter if (host->use_reg) 2042db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2043a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2044a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2045a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2046a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2047a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2048a45c6cb8SMadhusudhan Chikkature 2049fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2050fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2051a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 20522bec0893SAdrian Hunter if (host->got_dbclk) { 2053a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2054a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2055a45c6cb8SMadhusudhan Chikkature } 2056a45c6cb8SMadhusudhan Chikkature 2057a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2058a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2059db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2060a45c6cb8SMadhusudhan Chikkature } 2061a45c6cb8SMadhusudhan Chikkature 2062a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2063a45c6cb8SMadhusudhan Chikkature if (res) 2064984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2065a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2066a45c6cb8SMadhusudhan Chikkature 2067a45c6cb8SMadhusudhan Chikkature return 0; 2068a45c6cb8SMadhusudhan Chikkature } 2069a45c6cb8SMadhusudhan Chikkature 2070a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2071a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2072a45c6cb8SMadhusudhan Chikkature { 2073a45c6cb8SMadhusudhan Chikkature int ret = 0; 2074a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 207570a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2076a45c6cb8SMadhusudhan Chikkature 2077a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2078a45c6cb8SMadhusudhan Chikkature return 0; 2079a45c6cb8SMadhusudhan Chikkature 2080a45c6cb8SMadhusudhan Chikkature if (host) { 2081fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2082a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2083a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2084a45c6cb8SMadhusudhan Chikkature ret = host->pdata->suspend(&pdev->dev, 2085a45c6cb8SMadhusudhan Chikkature host->slot_id); 2086a6b2240dSAdrian Hunter if (ret) { 2087a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2088a45c6cb8SMadhusudhan Chikkature "Unable to handle MMC board" 2089a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2090a6b2240dSAdrian Hunter host->suspended = 0; 2091a6b2240dSAdrian Hunter return ret; 2092a45c6cb8SMadhusudhan Chikkature } 2093a6b2240dSAdrian Hunter } 20941a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2095fa4aa2d4SBalaji T K 209631f9d463SEliad Peller if (ret) { 2097a6b2240dSAdrian Hunter host->suspended = 0; 2098a6b2240dSAdrian Hunter if (host->pdata->resume) { 2099a6b2240dSAdrian Hunter ret = host->pdata->resume(&pdev->dev, 2100a6b2240dSAdrian Hunter host->slot_id); 2101a6b2240dSAdrian Hunter if (ret) 2102a6b2240dSAdrian Hunter dev_dbg(mmc_dev(host->mmc), 2103a6b2240dSAdrian Hunter "Unmask interrupt failed\n"); 2104a6b2240dSAdrian Hunter } 210531f9d463SEliad Peller goto err; 2106a6b2240dSAdrian Hunter } 210731f9d463SEliad Peller 210831f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 210931f9d463SEliad Peller omap_hsmmc_disable_irq(host); 211031f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 211131f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 211231f9d463SEliad Peller } 211331f9d463SEliad Peller if (host->got_dbclk) 211431f9d463SEliad Peller clk_disable(host->dbclk); 211531f9d463SEliad Peller 211631f9d463SEliad Peller } 211731f9d463SEliad Peller err: 2118fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2119a45c6cb8SMadhusudhan Chikkature return ret; 2120a45c6cb8SMadhusudhan Chikkature } 2121a45c6cb8SMadhusudhan Chikkature 2122a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2123a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2124a45c6cb8SMadhusudhan Chikkature { 2125a45c6cb8SMadhusudhan Chikkature int ret = 0; 2126a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 212770a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2128a45c6cb8SMadhusudhan Chikkature 2129a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2130a45c6cb8SMadhusudhan Chikkature return 0; 2131a45c6cb8SMadhusudhan Chikkature 2132a45c6cb8SMadhusudhan Chikkature if (host) { 2133fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 213411dd62a7SDenis Karpov 21352bec0893SAdrian Hunter if (host->got_dbclk) 21362bec0893SAdrian Hunter clk_enable(host->dbclk); 21372bec0893SAdrian Hunter 213831f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 213970a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21401b331e69SKim Kyuwon 2141a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2142a45c6cb8SMadhusudhan Chikkature ret = host->pdata->resume(&pdev->dev, host->slot_id); 2143a45c6cb8SMadhusudhan Chikkature if (ret) 2144a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2145a45c6cb8SMadhusudhan Chikkature "Unmask interrupt failed\n"); 2146a45c6cb8SMadhusudhan Chikkature } 2147a45c6cb8SMadhusudhan Chikkature 2148b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2149b62f6228SAdrian Hunter 2150a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2151a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2152a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2153a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2154fa4aa2d4SBalaji T K 2155fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2156fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2157a45c6cb8SMadhusudhan Chikkature } 2158a45c6cb8SMadhusudhan Chikkature 2159a45c6cb8SMadhusudhan Chikkature return ret; 2160a45c6cb8SMadhusudhan Chikkature 2161a45c6cb8SMadhusudhan Chikkature } 2162a45c6cb8SMadhusudhan Chikkature 2163a45c6cb8SMadhusudhan Chikkature #else 216470a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 216570a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2166a45c6cb8SMadhusudhan Chikkature #endif 2167a45c6cb8SMadhusudhan Chikkature 2168fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2169fa4aa2d4SBalaji T K { 2170fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2171fa4aa2d4SBalaji T K 2172fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2173fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2174fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "disabled\n"); 2175fa4aa2d4SBalaji T K 2176fa4aa2d4SBalaji T K return 0; 2177fa4aa2d4SBalaji T K } 2178fa4aa2d4SBalaji T K 2179fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2180fa4aa2d4SBalaji T K { 2181fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2182fa4aa2d4SBalaji T K 2183fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2184fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2185fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "enabled\n"); 2186fa4aa2d4SBalaji T K 2187fa4aa2d4SBalaji T K return 0; 2188fa4aa2d4SBalaji T K } 2189fa4aa2d4SBalaji T K 2190a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 219170a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 219270a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2193fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2194fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2195a791daa1SKevin Hilman }; 2196a791daa1SKevin Hilman 2197a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2198a791daa1SKevin Hilman .remove = omap_hsmmc_remove, 2199a45c6cb8SMadhusudhan Chikkature .driver = { 2200a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2201a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2202a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 2203a45c6cb8SMadhusudhan Chikkature }, 2204a45c6cb8SMadhusudhan Chikkature }; 2205a45c6cb8SMadhusudhan Chikkature 220670a3341aSDenis Karpov static int __init omap_hsmmc_init(void) 2207a45c6cb8SMadhusudhan Chikkature { 2208a45c6cb8SMadhusudhan Chikkature /* Register the MMC driver */ 22098753298aSRoger Quadros return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2210a45c6cb8SMadhusudhan Chikkature } 2211a45c6cb8SMadhusudhan Chikkature 221270a3341aSDenis Karpov static void __exit omap_hsmmc_cleanup(void) 2213a45c6cb8SMadhusudhan Chikkature { 2214a45c6cb8SMadhusudhan Chikkature /* Unregister MMC driver */ 221570a3341aSDenis Karpov platform_driver_unregister(&omap_hsmmc_driver); 2216a45c6cb8SMadhusudhan Chikkature } 2217a45c6cb8SMadhusudhan Chikkature 221870a3341aSDenis Karpov module_init(omap_hsmmc_init); 221970a3341aSDenis Karpov module_exit(omap_hsmmc_cleanup); 2220a45c6cb8SMadhusudhan Chikkature 2221a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2222a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2223a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2224a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2225