1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4568f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 46a45c6cb8SMadhusudhan Chikkature 47a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4811dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 50a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 59bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 65a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 67a45c6cb8SMadhusudhan Chikkature 68a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 69a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 70cd587096SHebbar, Gururaja #define HSS (1 << 21) 71a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 72a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 73eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 741b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 75a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 76a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 77a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 78a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 79a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 80a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 81a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 82a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 83ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 84a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 85a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 86a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 87a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 88a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 89a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 90a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 91a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 92a7e96879SVenkatraman S #define DMAE 0x1 93a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 94a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 95a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 96cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9703b5d924SBalaji T K #define DDR (1 << 19) 9873153010SJarkko Lavinen #define DW8 (1 << 5) 99a45c6cb8SMadhusudhan Chikkature #define OD 0x1 100a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 101a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 102a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 103a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 104a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10511dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 106a45c6cb8SMadhusudhan Chikkature 107a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 108a7e96879SVenkatraman S #define CC_EN (1 << 0) 109a7e96879SVenkatraman S #define TC_EN (1 << 1) 110a7e96879SVenkatraman S #define BWR_EN (1 << 4) 111a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1122cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 113a7e96879SVenkatraman S #define ERR_EN (1 << 15) 114a7e96879SVenkatraman S #define CTO_EN (1 << 16) 115a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 116a7e96879SVenkatraman S #define CEB_EN (1 << 18) 117a7e96879SVenkatraman S #define CIE_EN (1 << 19) 118a7e96879SVenkatraman S #define DTO_EN (1 << 20) 119a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 120a7e96879SVenkatraman S #define DEB_EN (1 << 22) 121a2e77152SBalaji T K #define ACE_EN (1 << 24) 122a7e96879SVenkatraman S #define CERR_EN (1 << 28) 123a7e96879SVenkatraman S #define BADA_EN (1 << 29) 124a7e96879SVenkatraman S 125a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 126a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 127a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 128a7e96879SVenkatraman S 129a2e77152SBalaji T K #define CNI (1 << 7) 130a2e77152SBalaji T K #define ACIE (1 << 4) 131a2e77152SBalaji T K #define ACEB (1 << 3) 132a2e77152SBalaji T K #define ACCE (1 << 2) 133a2e77152SBalaji T K #define ACTO (1 << 1) 134a2e77152SBalaji T K #define ACNE (1 << 0) 135a2e77152SBalaji T K 136fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1371e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1381e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1396b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1406b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1410005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 142a45c6cb8SMadhusudhan Chikkature 143e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 144e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 145e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 146e99448ffSBalaji T K 147a45c6cb8SMadhusudhan Chikkature /* 148a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 149a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 150a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 151a45c6cb8SMadhusudhan Chikkature */ 152a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 153a45c6cb8SMadhusudhan Chikkature 154a45c6cb8SMadhusudhan Chikkature /* 155a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 156a45c6cb8SMadhusudhan Chikkature */ 157a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 158a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 159a45c6cb8SMadhusudhan Chikkature 160a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 161a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 162a45c6cb8SMadhusudhan Chikkature 1639782aff8SPer Forlin struct omap_hsmmc_next { 1649782aff8SPer Forlin unsigned int dma_len; 1659782aff8SPer Forlin s32 cookie; 1669782aff8SPer Forlin }; 1679782aff8SPer Forlin 16870a3341aSDenis Karpov struct omap_hsmmc_host { 169a45c6cb8SMadhusudhan Chikkature struct device *dev; 170a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 171a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 172a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 173a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 174a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 175a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 176db0fefc5SAdrian Hunter /* 177db0fefc5SAdrian Hunter * vcc == configured supply 178db0fefc5SAdrian Hunter * vcc_aux == optional 179db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 180db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 181db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 182db0fefc5SAdrian Hunter */ 183db0fefc5SAdrian Hunter struct regulator *vcc; 184db0fefc5SAdrian Hunter struct regulator *vcc_aux; 185e99448ffSBalaji T K struct regulator *pbias; 186e99448ffSBalaji T K bool pbias_enabled; 187a45c6cb8SMadhusudhan Chikkature void __iomem *base; 188a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1894dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 190a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1910ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 192a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 193a3621465SAdrian Hunter unsigned char power_mode; 194a45c6cb8SMadhusudhan Chikkature int suspended; 1950a82e06eSTony Lindgren u32 con; 1960a82e06eSTony Lindgren u32 hctl; 1970a82e06eSTony Lindgren u32 sysctl; 1980a82e06eSTony Lindgren u32 capa; 199a45c6cb8SMadhusudhan Chikkature int irq; 2002cd3a2a5SAndreas Fenkart int wake_irq; 201a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 202c5c98927SRussell King struct dma_chan *tx_chan; 203c5c98927SRussell King struct dma_chan *rx_chan; 204a45c6cb8SMadhusudhan Chikkature int slot_id; 2054a694dc9SAdrian Hunter int response_busy; 20611dd62a7SDenis Karpov int context_loss; 207b62f6228SAdrian Hunter int protect_card; 208b62f6228SAdrian Hunter int reqs_blocked; 209db0fefc5SAdrian Hunter int use_reg; 210b417577dSAdrian Hunter int req_in_progress; 2116e3076c2SBalaji T K unsigned long clk_rate; 212a2e77152SBalaji T K unsigned int flags; 2132cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2142cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2152cd3a2a5SAndreas Fenkart #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) 2169782aff8SPer Forlin struct omap_hsmmc_next next_data; 217a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 218a45c6cb8SMadhusudhan Chikkature }; 219a45c6cb8SMadhusudhan Chikkature 22059445b10SNishanth Menon struct omap_mmc_of_data { 22159445b10SNishanth Menon u32 reg_offset; 22259445b10SNishanth Menon u8 controller_flags; 22359445b10SNishanth Menon }; 22459445b10SNishanth Menon 225bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 226bf129e1cSBalaji T K 227db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 228db0fefc5SAdrian Hunter { 2299ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2309ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 231db0fefc5SAdrian Hunter 232db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 233db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 234db0fefc5SAdrian Hunter } 235db0fefc5SAdrian Hunter 236db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 237db0fefc5SAdrian Hunter { 2389ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2399ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 240db0fefc5SAdrian Hunter 241db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 242db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 243db0fefc5SAdrian Hunter } 244db0fefc5SAdrian Hunter 245db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 246db0fefc5SAdrian Hunter { 2479ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2489ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 249db0fefc5SAdrian Hunter 250db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 251db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 252db0fefc5SAdrian Hunter } 253db0fefc5SAdrian Hunter 254db0fefc5SAdrian Hunter #ifdef CONFIG_PM 255db0fefc5SAdrian Hunter 256db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 257db0fefc5SAdrian Hunter { 2589ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2599ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 260db0fefc5SAdrian Hunter 261db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 262db0fefc5SAdrian Hunter return 0; 263db0fefc5SAdrian Hunter } 264db0fefc5SAdrian Hunter 265db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 266db0fefc5SAdrian Hunter { 2679ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2689ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 269db0fefc5SAdrian Hunter 270db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 271db0fefc5SAdrian Hunter return 0; 272db0fefc5SAdrian Hunter } 273db0fefc5SAdrian Hunter 274db0fefc5SAdrian Hunter #else 275db0fefc5SAdrian Hunter 276db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 277db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 278db0fefc5SAdrian Hunter 279db0fefc5SAdrian Hunter #endif 280db0fefc5SAdrian Hunter 281b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 282b702b106SAdrian Hunter 28369b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 284db0fefc5SAdrian Hunter int vdd) 285db0fefc5SAdrian Hunter { 286db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 287db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 288db0fefc5SAdrian Hunter int ret = 0; 289db0fefc5SAdrian Hunter 290db0fefc5SAdrian Hunter /* 291db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 292db0fefc5SAdrian Hunter * voltage always-on regulator. 293db0fefc5SAdrian Hunter */ 294db0fefc5SAdrian Hunter if (!host->vcc) 295db0fefc5SAdrian Hunter return 0; 296db0fefc5SAdrian Hunter 297db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 298db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 299db0fefc5SAdrian Hunter 300e99448ffSBalaji T K if (host->pbias) { 301e99448ffSBalaji T K if (host->pbias_enabled == 1) { 302e99448ffSBalaji T K ret = regulator_disable(host->pbias); 303e99448ffSBalaji T K if (!ret) 304e99448ffSBalaji T K host->pbias_enabled = 0; 305e99448ffSBalaji T K } 306e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 307e99448ffSBalaji T K } 308e99448ffSBalaji T K 309db0fefc5SAdrian Hunter /* 310db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 311db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 312db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 313db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 314db0fefc5SAdrian Hunter * 315db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 316db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 317db0fefc5SAdrian Hunter * 318db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 319db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 320db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 321db0fefc5SAdrian Hunter */ 322db0fefc5SAdrian Hunter if (power_on) { 323987fd49bSBalaji T K if (host->vcc) 32499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 325db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 326db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 327db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 328987fd49bSBalaji T K if (ret < 0 && host->vcc) 32999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 33099fc5131SLinus Walleij host->vcc, 0); 331db0fefc5SAdrian Hunter } 332db0fefc5SAdrian Hunter } else { 33399fc5131SLinus Walleij /* Shut down the rail */ 3346da20c89SAdrian Hunter if (host->vcc_aux) 335db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 336987fd49bSBalaji T K if (host->vcc) { 33799fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 33899fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 33999fc5131SLinus Walleij host->vcc, 0); 34099fc5131SLinus Walleij } 341db0fefc5SAdrian Hunter } 342db0fefc5SAdrian Hunter 343e99448ffSBalaji T K if (host->pbias) { 344e99448ffSBalaji T K if (vdd <= VDD_165_195) 345e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 346e99448ffSBalaji T K VDD_1V8); 347e99448ffSBalaji T K else 348e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 349e99448ffSBalaji T K VDD_3V0); 350e99448ffSBalaji T K if (ret < 0) 351e99448ffSBalaji T K goto error_set_power; 352e99448ffSBalaji T K 353e99448ffSBalaji T K if (host->pbias_enabled == 0) { 354e99448ffSBalaji T K ret = regulator_enable(host->pbias); 355e99448ffSBalaji T K if (!ret) 356e99448ffSBalaji T K host->pbias_enabled = 1; 357e99448ffSBalaji T K } 358e99448ffSBalaji T K } 359e99448ffSBalaji T K 360db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 361db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 362db0fefc5SAdrian Hunter 363e99448ffSBalaji T K error_set_power: 364db0fefc5SAdrian Hunter return ret; 365db0fefc5SAdrian Hunter } 366db0fefc5SAdrian Hunter 367db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 368db0fefc5SAdrian Hunter { 369db0fefc5SAdrian Hunter struct regulator *reg; 37064be9782Skishore kadiyala int ocr_value = 0; 371db0fefc5SAdrian Hunter 372f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 373db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 374987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 375987fd49bSBalaji T K PTR_ERR(reg)); 3761fdc90fbSNeilBrown return PTR_ERR(reg); 377db0fefc5SAdrian Hunter } else { 378db0fefc5SAdrian Hunter host->vcc = reg; 37964be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 38064be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 38164be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 38264be9782Skishore kadiyala } else { 38364be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3842cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 385e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 38664be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 38764be9782Skishore kadiyala return -EINVAL; 38864be9782Skishore kadiyala } 38964be9782Skishore kadiyala } 390987fd49bSBalaji T K } 391987fd49bSBalaji T K mmc_slot(host).set_power = omap_hsmmc_set_power; 392db0fefc5SAdrian Hunter 393db0fefc5SAdrian Hunter /* Allow an aux regulator */ 394f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 395db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 396db0fefc5SAdrian Hunter 397e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 398e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 399e99448ffSBalaji T K 400b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 401b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 402b1c1df7aSBalaji T K return 0; 403db0fefc5SAdrian Hunter /* 404987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 405987fd49bSBalaji T K * to increase usecount and then disable it. 406db0fefc5SAdrian Hunter */ 407987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 408e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 409e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 410e840ce13SAdrian Hunter 411987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 412987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 413db0fefc5SAdrian Hunter } 414db0fefc5SAdrian Hunter 415db0fefc5SAdrian Hunter return 0; 416db0fefc5SAdrian Hunter } 417db0fefc5SAdrian Hunter 418db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 419db0fefc5SAdrian Hunter { 420db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 421db0fefc5SAdrian Hunter } 422db0fefc5SAdrian Hunter 423b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 424b702b106SAdrian Hunter { 425b702b106SAdrian Hunter return 1; 426b702b106SAdrian Hunter } 427b702b106SAdrian Hunter 428b702b106SAdrian Hunter #else 429b702b106SAdrian Hunter 430b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 431b702b106SAdrian Hunter { 432b702b106SAdrian Hunter return -EINVAL; 433b702b106SAdrian Hunter } 434b702b106SAdrian Hunter 435b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 436b702b106SAdrian Hunter { 437b702b106SAdrian Hunter } 438b702b106SAdrian Hunter 439b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 440b702b106SAdrian Hunter { 441b702b106SAdrian Hunter return 0; 442b702b106SAdrian Hunter } 443b702b106SAdrian Hunter 444b702b106SAdrian Hunter #endif 445b702b106SAdrian Hunter 446b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 447b702b106SAdrian Hunter { 448b702b106SAdrian Hunter int ret; 449b702b106SAdrian Hunter 450b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 451b702b106SAdrian Hunter if (pdata->slots[0].cover) 452b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 453b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 454b702b106SAdrian Hunter else 455b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 456b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 457b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 458b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 459b702b106SAdrian Hunter if (ret) 460b702b106SAdrian Hunter return ret; 461b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 462b702b106SAdrian Hunter if (ret) 463b702b106SAdrian Hunter goto err_free_sp; 464b702b106SAdrian Hunter } else 465b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 466b702b106SAdrian Hunter 467b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 468b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 469b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 470b702b106SAdrian Hunter if (ret) 471b702b106SAdrian Hunter goto err_free_cd; 472b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 473b702b106SAdrian Hunter if (ret) 474b702b106SAdrian Hunter goto err_free_wp; 475b702b106SAdrian Hunter } else 476b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 477b702b106SAdrian Hunter 478b702b106SAdrian Hunter return 0; 479b702b106SAdrian Hunter 480b702b106SAdrian Hunter err_free_wp: 481b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 482b702b106SAdrian Hunter err_free_cd: 483b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 484b702b106SAdrian Hunter err_free_sp: 485b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 486b702b106SAdrian Hunter return ret; 487b702b106SAdrian Hunter } 488b702b106SAdrian Hunter 489b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 490b702b106SAdrian Hunter { 491b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 492b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 493b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 494b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 495b702b106SAdrian Hunter } 496b702b106SAdrian Hunter 497a45c6cb8SMadhusudhan Chikkature /* 498e0c7f99bSAndy Shevchenko * Start clock to the card 499e0c7f99bSAndy Shevchenko */ 500e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 501e0c7f99bSAndy Shevchenko { 502e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 503e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 504e0c7f99bSAndy Shevchenko } 505e0c7f99bSAndy Shevchenko 506e0c7f99bSAndy Shevchenko /* 507a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 508a45c6cb8SMadhusudhan Chikkature */ 50970a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 510a45c6cb8SMadhusudhan Chikkature { 511a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 512a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 513a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5147122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 515a45c6cb8SMadhusudhan Chikkature } 516a45c6cb8SMadhusudhan Chikkature 51793caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 51893caf8e6SAdrian Hunter struct mmc_command *cmd) 519b417577dSAdrian Hunter { 5202cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5212cd3a2a5SAndreas Fenkart unsigned long flags; 522b417577dSAdrian Hunter 523b417577dSAdrian Hunter if (host->use_dma) 5242cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 525b417577dSAdrian Hunter 52693caf8e6SAdrian Hunter /* Disable timeout for erases */ 52793caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 528a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 52993caf8e6SAdrian Hunter 5302cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 531b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 532b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5332cd3a2a5SAndreas Fenkart 5342cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5352cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5362cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 537b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5382cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 539b417577dSAdrian Hunter } 540b417577dSAdrian Hunter 541b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 542b417577dSAdrian Hunter { 5432cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5442cd3a2a5SAndreas Fenkart unsigned long flags; 5452cd3a2a5SAndreas Fenkart 5462cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5472cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5482cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5492cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5502cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5512cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 552b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5532cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 554b417577dSAdrian Hunter } 555b417577dSAdrian Hunter 556ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 557d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 558ac330f44SAndy Shevchenko { 559ac330f44SAndy Shevchenko u16 dsor = 0; 560ac330f44SAndy Shevchenko 561ac330f44SAndy Shevchenko if (ios->clock) { 562d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 563ed164182SBalaji T K if (dsor > CLKD_MAX) 564ed164182SBalaji T K dsor = CLKD_MAX; 565ac330f44SAndy Shevchenko } 566ac330f44SAndy Shevchenko 567ac330f44SAndy Shevchenko return dsor; 568ac330f44SAndy Shevchenko } 569ac330f44SAndy Shevchenko 5705934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5715934df2fSAndy Shevchenko { 5725934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5735934df2fSAndy Shevchenko unsigned long regval; 5745934df2fSAndy Shevchenko unsigned long timeout; 575cd587096SHebbar, Gururaja unsigned long clkdiv; 5765934df2fSAndy Shevchenko 5778986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5785934df2fSAndy Shevchenko 5795934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5805934df2fSAndy Shevchenko 5815934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5825934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 583cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 584cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5855934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5865934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5875934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5885934df2fSAndy Shevchenko 5895934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5905934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5915934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5925934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5935934df2fSAndy Shevchenko cpu_relax(); 5945934df2fSAndy Shevchenko 595cd587096SHebbar, Gururaja /* 596cd587096SHebbar, Gururaja * Enable High-Speed Support 597cd587096SHebbar, Gururaja * Pre-Requisites 598cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 599cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 600cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 601cd587096SHebbar, Gururaja * in capabilities register 602cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 603cd587096SHebbar, Gururaja */ 604cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 6055438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 606cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 607cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 608cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 609cd587096SHebbar, Gururaja regval |= HSPE; 610cd587096SHebbar, Gururaja else 611cd587096SHebbar, Gururaja regval &= ~HSPE; 612cd587096SHebbar, Gururaja 613cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 614cd587096SHebbar, Gururaja } 615cd587096SHebbar, Gururaja 6165934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6175934df2fSAndy Shevchenko } 6185934df2fSAndy Shevchenko 6193796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6203796fb8aSAndy Shevchenko { 6213796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6223796fb8aSAndy Shevchenko u32 con; 6233796fb8aSAndy Shevchenko 6243796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6255438ad95SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) 62603b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 62703b5d924SBalaji T K else 62803b5d924SBalaji T K con &= ~DDR; 6293796fb8aSAndy Shevchenko switch (ios->bus_width) { 6303796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6313796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6323796fb8aSAndy Shevchenko break; 6333796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6343796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6353796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6363796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6373796fb8aSAndy Shevchenko break; 6383796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6393796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6403796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6413796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6423796fb8aSAndy Shevchenko break; 6433796fb8aSAndy Shevchenko } 6443796fb8aSAndy Shevchenko } 6453796fb8aSAndy Shevchenko 6463796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6473796fb8aSAndy Shevchenko { 6483796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6493796fb8aSAndy Shevchenko u32 con; 6503796fb8aSAndy Shevchenko 6513796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6523796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6533796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6543796fb8aSAndy Shevchenko else 6553796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6563796fb8aSAndy Shevchenko } 6573796fb8aSAndy Shevchenko 65811dd62a7SDenis Karpov #ifdef CONFIG_PM 65911dd62a7SDenis Karpov 66011dd62a7SDenis Karpov /* 66111dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 66211dd62a7SDenis Karpov * power state change. 66311dd62a7SDenis Karpov */ 66470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 66511dd62a7SDenis Karpov { 66611dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6673796fb8aSAndy Shevchenko u32 hctl, capa; 66811dd62a7SDenis Karpov unsigned long timeout; 66911dd62a7SDenis Karpov 6700a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6710a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6720a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6730a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6740a82e06eSTony Lindgren return 0; 6750a82e06eSTony Lindgren 6760a82e06eSTony Lindgren host->context_loss++; 6770a82e06eSTony Lindgren 678c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 67911dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 68011dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 68111dd62a7SDenis Karpov hctl = SDVS18; 68211dd62a7SDenis Karpov else 68311dd62a7SDenis Karpov hctl = SDVS30; 68411dd62a7SDenis Karpov capa = VS30 | VS18; 68511dd62a7SDenis Karpov } else { 68611dd62a7SDenis Karpov hctl = SDVS18; 68711dd62a7SDenis Karpov capa = VS18; 68811dd62a7SDenis Karpov } 68911dd62a7SDenis Karpov 69011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 69111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 69211dd62a7SDenis Karpov 69311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 69411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 69511dd62a7SDenis Karpov 69611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 69711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 69811dd62a7SDenis Karpov 69911dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 70011dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 70111dd62a7SDenis Karpov && time_before(jiffies, timeout)) 70211dd62a7SDenis Karpov ; 70311dd62a7SDenis Karpov 7042cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7052cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7062cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 70711dd62a7SDenis Karpov 70811dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 70911dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 71011dd62a7SDenis Karpov goto out; 71111dd62a7SDenis Karpov 7123796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 71311dd62a7SDenis Karpov 7145934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 71511dd62a7SDenis Karpov 7163796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7173796fb8aSAndy Shevchenko 71811dd62a7SDenis Karpov out: 7190a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7200a82e06eSTony Lindgren host->context_loss); 72111dd62a7SDenis Karpov return 0; 72211dd62a7SDenis Karpov } 72311dd62a7SDenis Karpov 72411dd62a7SDenis Karpov /* 72511dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 72611dd62a7SDenis Karpov */ 72770a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 72811dd62a7SDenis Karpov { 7290a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7300a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7310a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7320a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 73311dd62a7SDenis Karpov } 73411dd62a7SDenis Karpov 73511dd62a7SDenis Karpov #else 73611dd62a7SDenis Karpov 73770a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 73811dd62a7SDenis Karpov { 73911dd62a7SDenis Karpov return 0; 74011dd62a7SDenis Karpov } 74111dd62a7SDenis Karpov 74270a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 74311dd62a7SDenis Karpov { 74411dd62a7SDenis Karpov } 74511dd62a7SDenis Karpov 74611dd62a7SDenis Karpov #endif 74711dd62a7SDenis Karpov 748a45c6cb8SMadhusudhan Chikkature /* 749a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 750a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 751a45c6cb8SMadhusudhan Chikkature */ 75270a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 753a45c6cb8SMadhusudhan Chikkature { 754a45c6cb8SMadhusudhan Chikkature int reg = 0; 755a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 756a45c6cb8SMadhusudhan Chikkature 757b62f6228SAdrian Hunter if (host->protect_card) 758b62f6228SAdrian Hunter return; 759b62f6228SAdrian Hunter 760a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 761b417577dSAdrian Hunter 762b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 763a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 764a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 765a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 766a45c6cb8SMadhusudhan Chikkature 767a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 768a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 769a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 770a45c6cb8SMadhusudhan Chikkature 771a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 772a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 773c653a6d4SAdrian Hunter 774c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 775c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 776c653a6d4SAdrian Hunter 777a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 778a45c6cb8SMadhusudhan Chikkature } 779a45c6cb8SMadhusudhan Chikkature 780a45c6cb8SMadhusudhan Chikkature static inline 78170a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 782a45c6cb8SMadhusudhan Chikkature { 783a45c6cb8SMadhusudhan Chikkature int r = 1; 784a45c6cb8SMadhusudhan Chikkature 785191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 786191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 787a45c6cb8SMadhusudhan Chikkature return r; 788a45c6cb8SMadhusudhan Chikkature } 789a45c6cb8SMadhusudhan Chikkature 790a45c6cb8SMadhusudhan Chikkature static ssize_t 79170a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 792a45c6cb8SMadhusudhan Chikkature char *buf) 793a45c6cb8SMadhusudhan Chikkature { 794a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 79570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 796a45c6cb8SMadhusudhan Chikkature 79770a3341aSDenis Karpov return sprintf(buf, "%s\n", 79870a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 799a45c6cb8SMadhusudhan Chikkature } 800a45c6cb8SMadhusudhan Chikkature 80170a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 802a45c6cb8SMadhusudhan Chikkature 803a45c6cb8SMadhusudhan Chikkature static ssize_t 80470a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 805a45c6cb8SMadhusudhan Chikkature char *buf) 806a45c6cb8SMadhusudhan Chikkature { 807a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 80870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 809a45c6cb8SMadhusudhan Chikkature 810191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 811a45c6cb8SMadhusudhan Chikkature } 812a45c6cb8SMadhusudhan Chikkature 81370a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 814a45c6cb8SMadhusudhan Chikkature 815a45c6cb8SMadhusudhan Chikkature /* 816a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 817a45c6cb8SMadhusudhan Chikkature */ 818a45c6cb8SMadhusudhan Chikkature static void 81970a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 820a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 821a45c6cb8SMadhusudhan Chikkature { 822a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 823a45c6cb8SMadhusudhan Chikkature 8248986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 825a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 826a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 827a45c6cb8SMadhusudhan Chikkature 82893caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 829a45c6cb8SMadhusudhan Chikkature 8304a694dc9SAdrian Hunter host->response_busy = 0; 831a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 832a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 833a45c6cb8SMadhusudhan Chikkature resptype = 1; 8344a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8354a694dc9SAdrian Hunter resptype = 3; 8364a694dc9SAdrian Hunter host->response_busy = 1; 8374a694dc9SAdrian Hunter } else 838a45c6cb8SMadhusudhan Chikkature resptype = 2; 839a45c6cb8SMadhusudhan Chikkature } 840a45c6cb8SMadhusudhan Chikkature 841a45c6cb8SMadhusudhan Chikkature /* 842a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 843a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 844a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 845a45c6cb8SMadhusudhan Chikkature */ 846a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 847a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 848a45c6cb8SMadhusudhan Chikkature 849a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 850a45c6cb8SMadhusudhan Chikkature 851a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 852a2e77152SBalaji T K host->mrq->sbc) { 853a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 854a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 855a2e77152SBalaji T K } 856a45c6cb8SMadhusudhan Chikkature if (data) { 857a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 858a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 859a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 860a45c6cb8SMadhusudhan Chikkature else 861a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 862a45c6cb8SMadhusudhan Chikkature } 863a45c6cb8SMadhusudhan Chikkature 864a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 865a7e96879SVenkatraman S cmdreg |= DMAE; 866a45c6cb8SMadhusudhan Chikkature 867b417577dSAdrian Hunter host->req_in_progress = 1; 8684dffd7a2SAdrian Hunter 869a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 870a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 871a45c6cb8SMadhusudhan Chikkature } 872a45c6cb8SMadhusudhan Chikkature 8730ccd76d4SJuha Yrjola static int 87470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8750ccd76d4SJuha Yrjola { 8760ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8770ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8780ccd76d4SJuha Yrjola else 8790ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8800ccd76d4SJuha Yrjola } 8810ccd76d4SJuha Yrjola 882c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 883c5c98927SRussell King struct mmc_data *data) 884c5c98927SRussell King { 885c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 886c5c98927SRussell King } 887c5c98927SRussell King 888b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 889b417577dSAdrian Hunter { 890b417577dSAdrian Hunter int dma_ch; 89131463b14SVenkatraman S unsigned long flags; 892b417577dSAdrian Hunter 89331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 894b417577dSAdrian Hunter host->req_in_progress = 0; 895b417577dSAdrian Hunter dma_ch = host->dma_ch; 89631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 897b417577dSAdrian Hunter 898b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 899b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 900b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 901b417577dSAdrian Hunter return; 902b417577dSAdrian Hunter host->mrq = NULL; 903b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 904b417577dSAdrian Hunter } 905b417577dSAdrian Hunter 906a45c6cb8SMadhusudhan Chikkature /* 907a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 908a45c6cb8SMadhusudhan Chikkature */ 909a45c6cb8SMadhusudhan Chikkature static void 91070a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 911a45c6cb8SMadhusudhan Chikkature { 9124a694dc9SAdrian Hunter if (!data) { 9134a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9144a694dc9SAdrian Hunter 91523050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 91623050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 91723050103SAdrian Hunter host->response_busy) { 91823050103SAdrian Hunter host->response_busy = 0; 91923050103SAdrian Hunter return; 92023050103SAdrian Hunter } 92123050103SAdrian Hunter 922b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9234a694dc9SAdrian Hunter return; 9244a694dc9SAdrian Hunter } 9254a694dc9SAdrian Hunter 926a45c6cb8SMadhusudhan Chikkature host->data = NULL; 927a45c6cb8SMadhusudhan Chikkature 928a45c6cb8SMadhusudhan Chikkature if (!data->error) 929a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 930a45c6cb8SMadhusudhan Chikkature else 931a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 932a45c6cb8SMadhusudhan Chikkature 933bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 934fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 935bf129e1cSBalaji T K else 936bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 937a45c6cb8SMadhusudhan Chikkature } 938a45c6cb8SMadhusudhan Chikkature 939a45c6cb8SMadhusudhan Chikkature /* 940a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 941a45c6cb8SMadhusudhan Chikkature */ 942a45c6cb8SMadhusudhan Chikkature static void 94370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 944a45c6cb8SMadhusudhan Chikkature { 945bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 946a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9472177fa94SBalaji T K host->cmd = NULL; 948bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 949bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 950bf129e1cSBalaji T K host->mrq->data); 951bf129e1cSBalaji T K return; 952bf129e1cSBalaji T K } 953bf129e1cSBalaji T K 9542177fa94SBalaji T K host->cmd = NULL; 9552177fa94SBalaji T K 956a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 957a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 958a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 959a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 960a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 961a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 962a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 963a45c6cb8SMadhusudhan Chikkature } else { 964a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 965a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 966a45c6cb8SMadhusudhan Chikkature } 967a45c6cb8SMadhusudhan Chikkature } 968b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 969d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 970a45c6cb8SMadhusudhan Chikkature } 971a45c6cb8SMadhusudhan Chikkature 972a45c6cb8SMadhusudhan Chikkature /* 973a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 974a45c6cb8SMadhusudhan Chikkature */ 97570a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 976a45c6cb8SMadhusudhan Chikkature { 977b417577dSAdrian Hunter int dma_ch; 97831463b14SVenkatraman S unsigned long flags; 979b417577dSAdrian Hunter 98082788ff5SJarkko Lavinen host->data->error = errno; 981a45c6cb8SMadhusudhan Chikkature 98231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 983b417577dSAdrian Hunter dma_ch = host->dma_ch; 984b417577dSAdrian Hunter host->dma_ch = -1; 98531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 986b417577dSAdrian Hunter 987b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 988c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 989c5c98927SRussell King 990c5c98927SRussell King dmaengine_terminate_all(chan); 991c5c98927SRussell King dma_unmap_sg(chan->device->dev, 992c5c98927SRussell King host->data->sg, host->data->sg_len, 99370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 994c5c98927SRussell King 995053bf34fSPer Forlin host->data->host_cookie = 0; 996a45c6cb8SMadhusudhan Chikkature } 997a45c6cb8SMadhusudhan Chikkature host->data = NULL; 998a45c6cb8SMadhusudhan Chikkature } 999a45c6cb8SMadhusudhan Chikkature 1000a45c6cb8SMadhusudhan Chikkature /* 1001a45c6cb8SMadhusudhan Chikkature * Readable error output 1002a45c6cb8SMadhusudhan Chikkature */ 1003a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1004699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1005a45c6cb8SMadhusudhan Chikkature { 1006a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 100770a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1008699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1009699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1010699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1011699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1012a45c6cb8SMadhusudhan Chikkature }; 1013a45c6cb8SMadhusudhan Chikkature char res[256]; 1014a45c6cb8SMadhusudhan Chikkature char *buf = res; 1015a45c6cb8SMadhusudhan Chikkature int len, i; 1016a45c6cb8SMadhusudhan Chikkature 1017a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1018a45c6cb8SMadhusudhan Chikkature buf += len; 1019a45c6cb8SMadhusudhan Chikkature 102070a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1021a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 102270a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1023a45c6cb8SMadhusudhan Chikkature buf += len; 1024a45c6cb8SMadhusudhan Chikkature } 1025a45c6cb8SMadhusudhan Chikkature 10268986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1027a45c6cb8SMadhusudhan Chikkature } 1028699b958bSAdrian Hunter #else 1029699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1030699b958bSAdrian Hunter u32 status) 1031699b958bSAdrian Hunter { 1032699b958bSAdrian Hunter } 1033a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1034a45c6cb8SMadhusudhan Chikkature 10353ebf74b1SJean Pihet /* 10363ebf74b1SJean Pihet * MMC controller internal state machines reset 10373ebf74b1SJean Pihet * 10383ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10393ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10403ebf74b1SJean Pihet * Can be called from interrupt context 10413ebf74b1SJean Pihet */ 104270a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10433ebf74b1SJean Pihet unsigned long bit) 10443ebf74b1SJean Pihet { 10453ebf74b1SJean Pihet unsigned long i = 0; 10461e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10473ebf74b1SJean Pihet 10483ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10493ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10503ebf74b1SJean Pihet 105107ad64b6SMadhusudhan Chikkature /* 105207ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 105307ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 105407ad64b6SMadhusudhan Chikkature */ 105507ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1056b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 105707ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10581e881786SJianpeng Ma udelay(1); 105907ad64b6SMadhusudhan Chikkature } 106007ad64b6SMadhusudhan Chikkature i = 0; 106107ad64b6SMadhusudhan Chikkature 10623ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10633ebf74b1SJean Pihet (i++ < limit)) 10641e881786SJianpeng Ma udelay(1); 10653ebf74b1SJean Pihet 10663ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10673ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10683ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10693ebf74b1SJean Pihet __func__); 10703ebf74b1SJean Pihet } 1071a45c6cb8SMadhusudhan Chikkature 107225e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 107325e1897bSBalaji T K int err, int end_cmd) 1074ae4bf788SVenkatraman S { 107525e1897bSBalaji T K if (end_cmd) { 107694d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 107725e1897bSBalaji T K if (host->cmd) 1078ae4bf788SVenkatraman S host->cmd->error = err; 107925e1897bSBalaji T K } 1080ae4bf788SVenkatraman S 1081ae4bf788SVenkatraman S if (host->data) { 1082ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1083ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1084dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1085dc7745bdSBalaji T K host->mrq->cmd->error = err; 1086ae4bf788SVenkatraman S } 1087ae4bf788SVenkatraman S 1088b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1089a45c6cb8SMadhusudhan Chikkature { 1090a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1091b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1092a2e77152SBalaji T K int error = 0; 1093a45c6cb8SMadhusudhan Chikkature 1094a45c6cb8SMadhusudhan Chikkature data = host->data; 10958986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1096a45c6cb8SMadhusudhan Chikkature 1097a7e96879SVenkatraman S if (status & ERR_EN) { 1098699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10994a694dc9SAdrian Hunter 1100a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1101a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1102a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 110325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1104a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 110525e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 110625e1897bSBalaji T K 1107a2e77152SBalaji T K if (status & ACE_EN) { 1108a2e77152SBalaji T K u32 ac12; 1109a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1110a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1111a2e77152SBalaji T K end_cmd = 1; 1112a2e77152SBalaji T K if (ac12 & ACTO) 1113a2e77152SBalaji T K error = -ETIMEDOUT; 1114a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1115a2e77152SBalaji T K error = -EILSEQ; 1116a2e77152SBalaji T K host->mrq->sbc->error = error; 1117a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1118a2e77152SBalaji T K } 1119a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1120a2e77152SBalaji T K } 1121ae4bf788SVenkatraman S if (host->data || host->response_busy) { 112225e1897bSBalaji T K end_trans = !end_cmd; 1123ae4bf788SVenkatraman S host->response_busy = 0; 1124a45c6cb8SMadhusudhan Chikkature } 1125a45c6cb8SMadhusudhan Chikkature } 1126a45c6cb8SMadhusudhan Chikkature 11277472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1128a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 112970a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1130a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 113170a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1132b417577dSAdrian Hunter } 1133a45c6cb8SMadhusudhan Chikkature 1134b417577dSAdrian Hunter /* 1135b417577dSAdrian Hunter * MMC controller IRQ handler 1136b417577dSAdrian Hunter */ 1137b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1138b417577dSAdrian Hunter { 1139b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1140b417577dSAdrian Hunter int status; 1141b417577dSAdrian Hunter 1142b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11432cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11442cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1145b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11461f6b9fa4SVenkatraman S 11472cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11482cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11492cd3a2a5SAndreas Fenkart 1150b417577dSAdrian Hunter /* Flush posted write */ 1151b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11521f6b9fa4SVenkatraman S } 11534dffd7a2SAdrian Hunter 1154a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1155a45c6cb8SMadhusudhan Chikkature } 1156a45c6cb8SMadhusudhan Chikkature 11572cd3a2a5SAndreas Fenkart static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) 11582cd3a2a5SAndreas Fenkart { 11592cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 11602cd3a2a5SAndreas Fenkart 11612cd3a2a5SAndreas Fenkart /* cirq is level triggered, disable to avoid infinite loop */ 11622cd3a2a5SAndreas Fenkart spin_lock(&host->irq_lock); 11632cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 11642cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 11652cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 11662cd3a2a5SAndreas Fenkart } 11672cd3a2a5SAndreas Fenkart spin_unlock(&host->irq_lock); 11682cd3a2a5SAndreas Fenkart pm_request_resume(host->dev); /* no use counter */ 11692cd3a2a5SAndreas Fenkart 11702cd3a2a5SAndreas Fenkart return IRQ_HANDLED; 11712cd3a2a5SAndreas Fenkart } 11722cd3a2a5SAndreas Fenkart 117370a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1174e13bb300SAdrian Hunter { 1175e13bb300SAdrian Hunter unsigned long i; 1176e13bb300SAdrian Hunter 1177e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1178e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1179e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1180e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1181e13bb300SAdrian Hunter break; 1182e13bb300SAdrian Hunter cpu_relax(); 1183e13bb300SAdrian Hunter } 1184e13bb300SAdrian Hunter } 1185e13bb300SAdrian Hunter 1186a45c6cb8SMadhusudhan Chikkature /* 1187eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1188eb250826SDavid Brownell * 1189eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1190eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1191eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1192a45c6cb8SMadhusudhan Chikkature */ 119370a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1194a45c6cb8SMadhusudhan Chikkature { 1195a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1196a45c6cb8SMadhusudhan Chikkature int ret; 1197a45c6cb8SMadhusudhan Chikkature 1198a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1199fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1200cd03d9a8SRajendra Nayak if (host->dbclk) 120194c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1202a45c6cb8SMadhusudhan Chikkature 1203a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1204a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1205a45c6cb8SMadhusudhan Chikkature 1206a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12072bec0893SAdrian Hunter if (!ret) 12082bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 12092bec0893SAdrian Hunter vdd); 1210fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1211cd03d9a8SRajendra Nayak if (host->dbclk) 121294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12132bec0893SAdrian Hunter 1214a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1215a45c6cb8SMadhusudhan Chikkature goto err; 1216a45c6cb8SMadhusudhan Chikkature 1217a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1218a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1219a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1220eb250826SDavid Brownell 1221a45c6cb8SMadhusudhan Chikkature /* 1222a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1223a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 122470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1225a45c6cb8SMadhusudhan Chikkature * 1226eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1227eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1228eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1229eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1230eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1231eb250826SDavid Brownell * 1232eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1233eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1234eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1235a45c6cb8SMadhusudhan Chikkature */ 1236eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1237a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1238eb250826SDavid Brownell else 1239eb250826SDavid Brownell reg_val |= SDVS30; 1240a45c6cb8SMadhusudhan Chikkature 1241a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1242e13bb300SAdrian Hunter set_sd_bus_power(host); 1243a45c6cb8SMadhusudhan Chikkature 1244a45c6cb8SMadhusudhan Chikkature return 0; 1245a45c6cb8SMadhusudhan Chikkature err: 1246b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1247a45c6cb8SMadhusudhan Chikkature return ret; 1248a45c6cb8SMadhusudhan Chikkature } 1249a45c6cb8SMadhusudhan Chikkature 1250b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1251b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1252b62f6228SAdrian Hunter { 1253b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1254b62f6228SAdrian Hunter return; 1255b62f6228SAdrian Hunter 1256b62f6228SAdrian Hunter host->reqs_blocked = 0; 1257b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1258b62f6228SAdrian Hunter if (host->protect_card) { 12592cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1260b62f6228SAdrian Hunter "card is now accessible\n", 1261b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1262b62f6228SAdrian Hunter host->protect_card = 0; 1263b62f6228SAdrian Hunter } 1264b62f6228SAdrian Hunter } else { 1265b62f6228SAdrian Hunter if (!host->protect_card) { 12662cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1267b62f6228SAdrian Hunter "card is now inaccessible\n", 1268b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1269b62f6228SAdrian Hunter host->protect_card = 1; 1270b62f6228SAdrian Hunter } 1271b62f6228SAdrian Hunter } 1272b62f6228SAdrian Hunter } 1273b62f6228SAdrian Hunter 1274a45c6cb8SMadhusudhan Chikkature /* 12757efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1276a45c6cb8SMadhusudhan Chikkature */ 12777efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1278a45c6cb8SMadhusudhan Chikkature { 12797efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1280249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1281a6b2240dSAdrian Hunter int carddetect; 1282249d0fa9SDavid Brownell 1283a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1284a6b2240dSAdrian Hunter 1285191d1f1dSDenis Karpov if (slot->card_detect) 1286db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1287b62f6228SAdrian Hunter else { 1288b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1289a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1290b62f6228SAdrian Hunter } 1291a6b2240dSAdrian Hunter 1292cdeebaddSMadhusudhan Chikkature if (carddetect) 1293a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1294cdeebaddSMadhusudhan Chikkature else 1295a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1296a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1297a45c6cb8SMadhusudhan Chikkature } 1298a45c6cb8SMadhusudhan Chikkature 1299c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13000ccd76d4SJuha Yrjola { 1301c5c98927SRussell King struct omap_hsmmc_host *host = param; 1302c5c98927SRussell King struct dma_chan *chan; 1303770d7432SAdrian Hunter struct mmc_data *data; 1304c5c98927SRussell King int req_in_progress; 1305a45c6cb8SMadhusudhan Chikkature 1306c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1307b417577dSAdrian Hunter if (host->dma_ch < 0) { 1308c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1309a45c6cb8SMadhusudhan Chikkature return; 1310b417577dSAdrian Hunter } 1311a45c6cb8SMadhusudhan Chikkature 1312770d7432SAdrian Hunter data = host->mrq->data; 1313c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13149782aff8SPer Forlin if (!data->host_cookie) 1315c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1316c5c98927SRussell King data->sg, data->sg_len, 1317b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1318b417577dSAdrian Hunter 1319b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1320a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1321c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1322b417577dSAdrian Hunter 1323b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1324b417577dSAdrian Hunter if (!req_in_progress) { 1325b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1326b417577dSAdrian Hunter 1327b417577dSAdrian Hunter host->mrq = NULL; 1328b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1329b417577dSAdrian Hunter } 1330a45c6cb8SMadhusudhan Chikkature } 1331a45c6cb8SMadhusudhan Chikkature 13329782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13339782aff8SPer Forlin struct mmc_data *data, 1334c5c98927SRussell King struct omap_hsmmc_next *next, 133526b88520SRussell King struct dma_chan *chan) 13369782aff8SPer Forlin { 13379782aff8SPer Forlin int dma_len; 13389782aff8SPer Forlin 13399782aff8SPer Forlin if (!next && data->host_cookie && 13409782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13412cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13429782aff8SPer Forlin " host->next_data.cookie %d\n", 13439782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13449782aff8SPer Forlin data->host_cookie = 0; 13459782aff8SPer Forlin } 13469782aff8SPer Forlin 13479782aff8SPer Forlin /* Check if next job is already prepared */ 1348b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 134926b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13509782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13519782aff8SPer Forlin 13529782aff8SPer Forlin } else { 13539782aff8SPer Forlin dma_len = host->next_data.dma_len; 13549782aff8SPer Forlin host->next_data.dma_len = 0; 13559782aff8SPer Forlin } 13569782aff8SPer Forlin 13579782aff8SPer Forlin 13589782aff8SPer Forlin if (dma_len == 0) 13599782aff8SPer Forlin return -EINVAL; 13609782aff8SPer Forlin 13619782aff8SPer Forlin if (next) { 13629782aff8SPer Forlin next->dma_len = dma_len; 13639782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13649782aff8SPer Forlin } else 13659782aff8SPer Forlin host->dma_len = dma_len; 13669782aff8SPer Forlin 13679782aff8SPer Forlin return 0; 13689782aff8SPer Forlin } 13699782aff8SPer Forlin 1370a45c6cb8SMadhusudhan Chikkature /* 1371a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1372a45c6cb8SMadhusudhan Chikkature */ 13739d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 137470a3341aSDenis Karpov struct mmc_request *req) 1375a45c6cb8SMadhusudhan Chikkature { 137626b88520SRussell King struct dma_slave_config cfg; 137726b88520SRussell King struct dma_async_tx_descriptor *tx; 137826b88520SRussell King int ret = 0, i; 1379a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1380c5c98927SRussell King struct dma_chan *chan; 1381a45c6cb8SMadhusudhan Chikkature 13820ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1383a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13840ccd76d4SJuha Yrjola struct scatterlist *sgl; 13850ccd76d4SJuha Yrjola 13860ccd76d4SJuha Yrjola sgl = data->sg + i; 13870ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13880ccd76d4SJuha Yrjola return -EINVAL; 13890ccd76d4SJuha Yrjola } 13900ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13910ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13920ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13930ccd76d4SJuha Yrjola */ 13940ccd76d4SJuha Yrjola return -EINVAL; 13950ccd76d4SJuha Yrjola 1396b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1397a45c6cb8SMadhusudhan Chikkature 1398c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1399c5c98927SRussell King 1400c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1401c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1402c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1403c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1404c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1405c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1406c5c98927SRussell King 1407c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14089782aff8SPer Forlin if (ret) 14099782aff8SPer Forlin return ret; 1410a45c6cb8SMadhusudhan Chikkature 141126b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1412c5c98927SRussell King if (ret) 1413c5c98927SRussell King return ret; 1414a45c6cb8SMadhusudhan Chikkature 1415c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1416c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1417c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1418c5c98927SRussell King if (!tx) { 1419c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1420c5c98927SRussell King /* FIXME: cleanup */ 1421c5c98927SRussell King return -1; 1422c5c98927SRussell King } 1423c5c98927SRussell King 1424c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1425c5c98927SRussell King tx->callback_param = host; 1426c5c98927SRussell King 1427c5c98927SRussell King /* Does not fail */ 1428c5c98927SRussell King dmaengine_submit(tx); 1429c5c98927SRussell King 143026b88520SRussell King host->dma_ch = 1; 1431c5c98927SRussell King 1432a45c6cb8SMadhusudhan Chikkature return 0; 1433a45c6cb8SMadhusudhan Chikkature } 1434a45c6cb8SMadhusudhan Chikkature 143570a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1436e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1437e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1438a45c6cb8SMadhusudhan Chikkature { 1439a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1440a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1441a45c6cb8SMadhusudhan Chikkature 1442a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1443a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1444a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1445a45c6cb8SMadhusudhan Chikkature clkd = 1; 1446a45c6cb8SMadhusudhan Chikkature 14476e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1448e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1449e2bf08d6SAdrian Hunter timeout += timeout_clks; 1450a45c6cb8SMadhusudhan Chikkature if (timeout) { 1451a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1452a45c6cb8SMadhusudhan Chikkature dto += 1; 1453a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1454a45c6cb8SMadhusudhan Chikkature } 1455a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1456a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1457a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1458a45c6cb8SMadhusudhan Chikkature dto += 1; 1459a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1460a45c6cb8SMadhusudhan Chikkature dto -= 13; 1461a45c6cb8SMadhusudhan Chikkature else 1462a45c6cb8SMadhusudhan Chikkature dto = 0; 1463a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1464a45c6cb8SMadhusudhan Chikkature dto = 14; 1465a45c6cb8SMadhusudhan Chikkature } 1466a45c6cb8SMadhusudhan Chikkature 1467a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1468a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1469a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1470a45c6cb8SMadhusudhan Chikkature } 1471a45c6cb8SMadhusudhan Chikkature 14729d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14739d025334SBalaji T K { 14749d025334SBalaji T K struct mmc_request *req = host->mrq; 14759d025334SBalaji T K struct dma_chan *chan; 14769d025334SBalaji T K 14779d025334SBalaji T K if (!req->data) 14789d025334SBalaji T K return; 14799d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14809d025334SBalaji T K | (req->data->blocks << 16)); 14819d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14829d025334SBalaji T K req->data->timeout_clks); 14839d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14849d025334SBalaji T K dma_async_issue_pending(chan); 14859d025334SBalaji T K } 14869d025334SBalaji T K 1487a45c6cb8SMadhusudhan Chikkature /* 1488a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1489a45c6cb8SMadhusudhan Chikkature */ 1490a45c6cb8SMadhusudhan Chikkature static int 149170a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1492a45c6cb8SMadhusudhan Chikkature { 1493a45c6cb8SMadhusudhan Chikkature int ret; 1494a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1495a45c6cb8SMadhusudhan Chikkature 1496a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1497a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1498e2bf08d6SAdrian Hunter /* 1499e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1500e2bf08d6SAdrian Hunter * busy signal. 1501e2bf08d6SAdrian Hunter */ 1502e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1503e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1504a45c6cb8SMadhusudhan Chikkature return 0; 1505a45c6cb8SMadhusudhan Chikkature } 1506a45c6cb8SMadhusudhan Chikkature 1507a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15089d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1509a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1510b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1511a45c6cb8SMadhusudhan Chikkature return ret; 1512a45c6cb8SMadhusudhan Chikkature } 1513a45c6cb8SMadhusudhan Chikkature } 1514a45c6cb8SMadhusudhan Chikkature return 0; 1515a45c6cb8SMadhusudhan Chikkature } 1516a45c6cb8SMadhusudhan Chikkature 15179782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15189782aff8SPer Forlin int err) 15199782aff8SPer Forlin { 15209782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15219782aff8SPer Forlin struct mmc_data *data = mrq->data; 15229782aff8SPer Forlin 152326b88520SRussell King if (host->use_dma && data->host_cookie) { 1524c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1525c5c98927SRussell King 152626b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15279782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15289782aff8SPer Forlin data->host_cookie = 0; 15299782aff8SPer Forlin } 15309782aff8SPer Forlin } 15319782aff8SPer Forlin 15329782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15339782aff8SPer Forlin bool is_first_req) 15349782aff8SPer Forlin { 15359782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15369782aff8SPer Forlin 15379782aff8SPer Forlin if (mrq->data->host_cookie) { 15389782aff8SPer Forlin mrq->data->host_cookie = 0; 15399782aff8SPer Forlin return ; 15409782aff8SPer Forlin } 15419782aff8SPer Forlin 1542c5c98927SRussell King if (host->use_dma) { 1543c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1544c5c98927SRussell King 15459782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 154626b88520SRussell King &host->next_data, c)) 15479782aff8SPer Forlin mrq->data->host_cookie = 0; 15489782aff8SPer Forlin } 1549c5c98927SRussell King } 15509782aff8SPer Forlin 1551a45c6cb8SMadhusudhan Chikkature /* 1552a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1553a45c6cb8SMadhusudhan Chikkature */ 155470a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1555a45c6cb8SMadhusudhan Chikkature { 155670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1557a3f406f8SJarkko Lavinen int err; 1558a45c6cb8SMadhusudhan Chikkature 1559b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1560b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1561b62f6228SAdrian Hunter if (host->protect_card) { 1562b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1563b62f6228SAdrian Hunter /* 1564b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1565b62f6228SAdrian Hunter * state by resetting the command and data state 1566b62f6228SAdrian Hunter * machines. 1567b62f6228SAdrian Hunter */ 1568b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1569b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1570b62f6228SAdrian Hunter host->reqs_blocked += 1; 1571b62f6228SAdrian Hunter } 1572b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1573b62f6228SAdrian Hunter if (req->data) 1574b62f6228SAdrian Hunter req->data->error = -EBADF; 1575b417577dSAdrian Hunter req->cmd->retries = 0; 1576b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1577b62f6228SAdrian Hunter return; 1578b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1579b62f6228SAdrian Hunter host->reqs_blocked = 0; 1580a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1581a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15826e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 158370a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1584a3f406f8SJarkko Lavinen if (err) { 1585a3f406f8SJarkko Lavinen req->cmd->error = err; 1586a3f406f8SJarkko Lavinen if (req->data) 1587a3f406f8SJarkko Lavinen req->data->error = err; 1588a3f406f8SJarkko Lavinen host->mrq = NULL; 1589a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1590a3f406f8SJarkko Lavinen return; 1591a3f406f8SJarkko Lavinen } 1592a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1593bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1594bf129e1cSBalaji T K return; 1595bf129e1cSBalaji T K } 1596a3f406f8SJarkko Lavinen 15979d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 159870a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1599a45c6cb8SMadhusudhan Chikkature } 1600a45c6cb8SMadhusudhan Chikkature 1601a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 160270a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1603a45c6cb8SMadhusudhan Chikkature { 160470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1605a3621465SAdrian Hunter int do_send_init_stream = 0; 1606a45c6cb8SMadhusudhan Chikkature 1607fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16085e2ea617SAdrian Hunter 1609a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1610a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1611a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1612a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1613a3621465SAdrian Hunter 0, 0); 1614a45c6cb8SMadhusudhan Chikkature break; 1615a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1616a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1617a3621465SAdrian Hunter 1, ios->vdd); 1618a45c6cb8SMadhusudhan Chikkature break; 1619a3621465SAdrian Hunter case MMC_POWER_ON: 1620a3621465SAdrian Hunter do_send_init_stream = 1; 1621a3621465SAdrian Hunter break; 1622a3621465SAdrian Hunter } 1623a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1624a45c6cb8SMadhusudhan Chikkature } 1625a45c6cb8SMadhusudhan Chikkature 1626dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1627dd498effSDenis Karpov 16283796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1629a45c6cb8SMadhusudhan Chikkature 16304621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1631eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1632eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1633eb250826SDavid Brownell */ 1634a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16352cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1636a45c6cb8SMadhusudhan Chikkature /* 1637a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1638a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1639a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1640a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1641a45c6cb8SMadhusudhan Chikkature */ 164270a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1643a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1644a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1645a45c6cb8SMadhusudhan Chikkature } 1646a45c6cb8SMadhusudhan Chikkature } 1647a45c6cb8SMadhusudhan Chikkature 16485934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1649a45c6cb8SMadhusudhan Chikkature 1650a3621465SAdrian Hunter if (do_send_init_stream) 1651a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1652a45c6cb8SMadhusudhan Chikkature 16533796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16545e2ea617SAdrian Hunter 1655fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1656a45c6cb8SMadhusudhan Chikkature } 1657a45c6cb8SMadhusudhan Chikkature 1658a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1659a45c6cb8SMadhusudhan Chikkature { 166070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1661a45c6cb8SMadhusudhan Chikkature 1662191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1663a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1664db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1665a45c6cb8SMadhusudhan Chikkature } 1666a45c6cb8SMadhusudhan Chikkature 1667a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1668a45c6cb8SMadhusudhan Chikkature { 166970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1670a45c6cb8SMadhusudhan Chikkature 1671191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1672a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1673191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1674a45c6cb8SMadhusudhan Chikkature } 1675a45c6cb8SMadhusudhan Chikkature 16764816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16774816858cSGrazvydas Ignotas { 16784816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16794816858cSGrazvydas Ignotas 16804816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 16814816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 16824816858cSGrazvydas Ignotas } 16834816858cSGrazvydas Ignotas 16842cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16852cd3a2a5SAndreas Fenkart { 16862cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16872cd3a2a5SAndreas Fenkart u32 irq_mask; 16882cd3a2a5SAndreas Fenkart unsigned long flags; 16892cd3a2a5SAndreas Fenkart 16902cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16912cd3a2a5SAndreas Fenkart 16922cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16932cd3a2a5SAndreas Fenkart if (enable) { 16942cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16952cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16962cd3a2a5SAndreas Fenkart } else { 16972cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16982cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16992cd3a2a5SAndreas Fenkart } 17002cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17012cd3a2a5SAndreas Fenkart 17022cd3a2a5SAndreas Fenkart /* 17032cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17042cd3a2a5SAndreas Fenkart * but always disable immediately 17052cd3a2a5SAndreas Fenkart */ 17062cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17072cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17082cd3a2a5SAndreas Fenkart 17092cd3a2a5SAndreas Fenkart /* flush posted write */ 17102cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17112cd3a2a5SAndreas Fenkart 17122cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17132cd3a2a5SAndreas Fenkart } 17142cd3a2a5SAndreas Fenkart 17152cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17162cd3a2a5SAndreas Fenkart { 17172cd3a2a5SAndreas Fenkart struct mmc_host *mmc = host->mmc; 17182cd3a2a5SAndreas Fenkart int ret; 17192cd3a2a5SAndreas Fenkart 17202cd3a2a5SAndreas Fenkart /* 17212cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17222cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17232cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17242cd3a2a5SAndreas Fenkart * with functional clock disabled. 17252cd3a2a5SAndreas Fenkart */ 17262cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17272cd3a2a5SAndreas Fenkart return -ENODEV; 17282cd3a2a5SAndreas Fenkart 17292cd3a2a5SAndreas Fenkart /* Prevent auto-enabling of IRQ */ 17302cd3a2a5SAndreas Fenkart irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); 17312cd3a2a5SAndreas Fenkart ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, 17322cd3a2a5SAndreas Fenkart IRQF_TRIGGER_LOW | IRQF_ONESHOT, 17332cd3a2a5SAndreas Fenkart mmc_hostname(mmc), host); 17342cd3a2a5SAndreas Fenkart if (ret) { 17352cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17362cd3a2a5SAndreas Fenkart goto err; 17372cd3a2a5SAndreas Fenkart } 17382cd3a2a5SAndreas Fenkart 17392cd3a2a5SAndreas Fenkart /* 17402cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17412cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17422cd3a2a5SAndreas Fenkart */ 17432cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 17442cd3a2a5SAndreas Fenkart ret = -ENODEV; 17452cd3a2a5SAndreas Fenkart devm_free_irq(host->dev, host->wake_irq, host); 17462cd3a2a5SAndreas Fenkart goto err; 17472cd3a2a5SAndreas Fenkart } 17482cd3a2a5SAndreas Fenkart 17492cd3a2a5SAndreas Fenkart return 0; 17502cd3a2a5SAndreas Fenkart 17512cd3a2a5SAndreas Fenkart err: 17522cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17532cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17542cd3a2a5SAndreas Fenkart return ret; 17552cd3a2a5SAndreas Fenkart } 17562cd3a2a5SAndreas Fenkart 175770a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17581b331e69SKim Kyuwon { 17591b331e69SKim Kyuwon u32 hctl, capa, value; 17601b331e69SKim Kyuwon 17611b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17624621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17631b331e69SKim Kyuwon hctl = SDVS30; 17641b331e69SKim Kyuwon capa = VS30 | VS18; 17651b331e69SKim Kyuwon } else { 17661b331e69SKim Kyuwon hctl = SDVS18; 17671b331e69SKim Kyuwon capa = VS18; 17681b331e69SKim Kyuwon } 17691b331e69SKim Kyuwon 17701b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17711b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17721b331e69SKim Kyuwon 17731b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17741b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17751b331e69SKim Kyuwon 17761b331e69SKim Kyuwon /* Set SD bus power bit */ 1777e13bb300SAdrian Hunter set_sd_bus_power(host); 17781b331e69SKim Kyuwon } 17791b331e69SKim Kyuwon 178070a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1781dd498effSDenis Karpov { 178270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1783dd498effSDenis Karpov 1784fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1785fa4aa2d4SBalaji T K 1786dd498effSDenis Karpov return 0; 1787dd498effSDenis Karpov } 1788dd498effSDenis Karpov 1789907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1790dd498effSDenis Karpov { 179170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1792dd498effSDenis Karpov 1793fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1794fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1795fa4aa2d4SBalaji T K 1796dd498effSDenis Karpov return 0; 1797dd498effSDenis Karpov } 1798dd498effSDenis Karpov 179970a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 180070a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 180170a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 18029782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18039782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 180470a3341aSDenis Karpov .request = omap_hsmmc_request, 180570a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1806dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1807dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 18084816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18092cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1810dd498effSDenis Karpov }; 1811dd498effSDenis Karpov 1812d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1813d900f712SDenis Karpov 181470a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1815d900f712SDenis Karpov { 1816d900f712SDenis Karpov struct mmc_host *mmc = s->private; 181770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 181811dd62a7SDenis Karpov 1819bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1820bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1821bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1822bb0635f0SAndreas Fenkart 1823bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1824bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1825bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1826bb0635f0SAndreas Fenkart : "disabled"); 1827bb0635f0SAndreas Fenkart } 1828bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18295e2ea617SAdrian Hunter 1830fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1831bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1832d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1833d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1834bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1835bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1836d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1837d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1838d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1839d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1840d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1841d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1842d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1843d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1844d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1845d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18465e2ea617SAdrian Hunter 1847fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1848fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1849dd498effSDenis Karpov 1850d900f712SDenis Karpov return 0; 1851d900f712SDenis Karpov } 1852d900f712SDenis Karpov 185370a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1854d900f712SDenis Karpov { 185570a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1856d900f712SDenis Karpov } 1857d900f712SDenis Karpov 1858d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 185970a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1860d900f712SDenis Karpov .read = seq_read, 1861d900f712SDenis Karpov .llseek = seq_lseek, 1862d900f712SDenis Karpov .release = single_release, 1863d900f712SDenis Karpov }; 1864d900f712SDenis Karpov 186570a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1866d900f712SDenis Karpov { 1867d900f712SDenis Karpov if (mmc->debugfs_root) 1868d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1869d900f712SDenis Karpov mmc, &mmc_regs_fops); 1870d900f712SDenis Karpov } 1871d900f712SDenis Karpov 1872d900f712SDenis Karpov #else 1873d900f712SDenis Karpov 187470a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1875d900f712SDenis Karpov { 1876d900f712SDenis Karpov } 1877d900f712SDenis Karpov 1878d900f712SDenis Karpov #endif 1879d900f712SDenis Karpov 188046856a68SRajendra Nayak #ifdef CONFIG_OF 188159445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 188259445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 188359445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 188459445b10SNishanth Menon }; 188559445b10SNishanth Menon 188659445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 188759445b10SNishanth Menon .reg_offset = 0x100, 188859445b10SNishanth Menon }; 18892cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18902cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18912cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18922cd3a2a5SAndreas Fenkart }; 189346856a68SRajendra Nayak 189446856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 189546856a68SRajendra Nayak { 189646856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 189746856a68SRajendra Nayak }, 189846856a68SRajendra Nayak { 189959445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 190059445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 190159445b10SNishanth Menon }, 190259445b10SNishanth Menon { 190346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 190446856a68SRajendra Nayak }, 190546856a68SRajendra Nayak { 190646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 190759445b10SNishanth Menon .data = &omap4_mmc_of_data, 190846856a68SRajendra Nayak }, 19092cd3a2a5SAndreas Fenkart { 19102cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19112cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19122cd3a2a5SAndreas Fenkart }, 191346856a68SRajendra Nayak {}, 1914b6d085f6SChris Ball }; 191546856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 191646856a68SRajendra Nayak 191746856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 191846856a68SRajendra Nayak { 191946856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 192046856a68SRajendra Nayak struct device_node *np = dev->of_node; 1921d8714e87SDaniel Mack u32 bus_width, max_freq; 1922dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1923dc642c28SJan Luebbe 1924dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1925dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1926dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1927dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 192846856a68SRajendra Nayak 192946856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 193046856a68SRajendra Nayak if (!pdata) 193119df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 193246856a68SRajendra Nayak 193346856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 193446856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 193546856a68SRajendra Nayak 193646856a68SRajendra Nayak /* This driver only supports 1 slot */ 193746856a68SRajendra Nayak pdata->nr_slots = 1; 1938dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1939dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 194046856a68SRajendra Nayak 194146856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 194246856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 194346856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 194446856a68SRajendra Nayak } 19457f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 194646856a68SRajendra Nayak if (bus_width == 4) 194746856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 194846856a68SRajendra Nayak else if (bus_width == 8) 194946856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 195046856a68SRajendra Nayak 195146856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 195246856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 195346856a68SRajendra Nayak 1954d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1955d8714e87SDaniel Mack pdata->max_freq = max_freq; 1956d8714e87SDaniel Mack 1957cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1958cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1959cd587096SHebbar, Gururaja 1960c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 1961c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; 1962c9ae64dbSDaniel Mack 1963c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1964c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1965c9ae64dbSDaniel Mack 196646856a68SRajendra Nayak return pdata; 196746856a68SRajendra Nayak } 196846856a68SRajendra Nayak #else 196946856a68SRajendra Nayak static inline struct omap_mmc_platform_data 197046856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 197146856a68SRajendra Nayak { 197219df45bcSBalaji T K return ERR_PTR(-EINVAL); 197346856a68SRajendra Nayak } 197446856a68SRajendra Nayak #endif 197546856a68SRajendra Nayak 1976c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1977a45c6cb8SMadhusudhan Chikkature { 1978a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1979a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 198070a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1981a45c6cb8SMadhusudhan Chikkature struct resource *res; 1982db0fefc5SAdrian Hunter int ret, irq; 198346856a68SRajendra Nayak const struct of_device_id *match; 198426b88520SRussell King dma_cap_mask_t mask; 198526b88520SRussell King unsigned tx_req, rx_req; 198646b76035SDaniel Mack struct pinctrl *pinctrl; 198759445b10SNishanth Menon const struct omap_mmc_of_data *data; 198877fae219SBalaji T K void __iomem *base; 198946856a68SRajendra Nayak 199046856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 199146856a68SRajendra Nayak if (match) { 199246856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1993dc642c28SJan Luebbe 1994dc642c28SJan Luebbe if (IS_ERR(pdata)) 1995dc642c28SJan Luebbe return PTR_ERR(pdata); 1996dc642c28SJan Luebbe 199746856a68SRajendra Nayak if (match->data) { 199859445b10SNishanth Menon data = match->data; 199959445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 200059445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 200146856a68SRajendra Nayak } 200246856a68SRajendra Nayak } 2003a45c6cb8SMadhusudhan Chikkature 2004a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2005a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2006a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2007a45c6cb8SMadhusudhan Chikkature } 2008a45c6cb8SMadhusudhan Chikkature 2009a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 2010a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 2011a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2012a45c6cb8SMadhusudhan Chikkature } 2013a45c6cb8SMadhusudhan Chikkature 2014a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2015a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2016a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2017a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2018a45c6cb8SMadhusudhan Chikkature 201977fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 202077fae219SBalaji T K if (IS_ERR(base)) 202177fae219SBalaji T K return PTR_ERR(base); 2022a45c6cb8SMadhusudhan Chikkature 2023db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 2024db0fefc5SAdrian Hunter if (ret) 2025db0fefc5SAdrian Hunter goto err; 2026db0fefc5SAdrian Hunter 202770a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2028a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2029a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 2030db0fefc5SAdrian Hunter goto err_alloc; 2031a45c6cb8SMadhusudhan Chikkature } 2032a45c6cb8SMadhusudhan Chikkature 2033a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2034a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2035a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2036a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2037a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2038a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2039a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2040a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 2041fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 204277fae219SBalaji T K host->base = base + pdata->reg_offset; 20436da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20449782aff8SPer Forlin host->next_data.cookie = 1; 2045e99448ffSBalaji T K host->pbias_enabled = 0; 2046a45c6cb8SMadhusudhan Chikkature 2047a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2048a45c6cb8SMadhusudhan Chikkature 20492cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20502cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20512cd3a2a5SAndreas Fenkart 205270a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2053dd498effSDenis Karpov 20546b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2055d418ed87SDaniel Mack 2056d418ed87SDaniel Mack if (pdata->max_freq > 0) 2057d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2058d418ed87SDaniel Mack else 20596b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2060a45c6cb8SMadhusudhan Chikkature 20614dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2062a45c6cb8SMadhusudhan Chikkature 20639618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2064a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2065a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2066a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2067a45c6cb8SMadhusudhan Chikkature goto err1; 2068a45c6cb8SMadhusudhan Chikkature } 2069a45c6cb8SMadhusudhan Chikkature 20709b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20719b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 20729b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 20739b68256cSPaul Walmsley } 2074dd498effSDenis Karpov 2075fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2076fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2077fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2078fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2079a45c6cb8SMadhusudhan Chikkature 208092a3aebfSBalaji T K omap_hsmmc_context_save(host); 208192a3aebfSBalaji T K 20829618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2083a45c6cb8SMadhusudhan Chikkature /* 2084a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2085a45c6cb8SMadhusudhan Chikkature */ 2086cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2087cd03d9a8SRajendra Nayak host->dbclk = NULL; 208894c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2089cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2090cd03d9a8SRajendra Nayak host->dbclk = NULL; 20912bec0893SAdrian Hunter } 2092a45c6cb8SMadhusudhan Chikkature 20930ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20940ccd76d4SJuha Yrjola * as we want. */ 2095a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20960ccd76d4SJuha Yrjola 2097a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2098a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2099a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2100a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2101a45c6cb8SMadhusudhan Chikkature 210213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 210393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2104a45c6cb8SMadhusudhan Chikkature 21053a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 21063a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2107a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2108a45c6cb8SMadhusudhan Chikkature 2109191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 211023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 211123d99bb9SAdrian Hunter 21126fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 21136fdc75deSEliad Peller 211470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2115a45c6cb8SMadhusudhan Chikkature 21164a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2117b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2118b7bf773bSBalaji T K if (!res) { 2119b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21209c17d08cSKevin Hilman ret = -ENXIO; 2121f3e2f1ddSGrazvydas Ignotas goto err_irq; 2122a45c6cb8SMadhusudhan Chikkature } 212326b88520SRussell King tx_req = res->start; 2124b7bf773bSBalaji T K 2125b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2126b7bf773bSBalaji T K if (!res) { 2127b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21289c17d08cSKevin Hilman ret = -ENXIO; 2129b7bf773bSBalaji T K goto err_irq; 2130b7bf773bSBalaji T K } 213126b88520SRussell King rx_req = res->start; 21324a29b559SSantosh Shilimkar } 2133c5c98927SRussell King 2134c5c98927SRussell King dma_cap_zero(mask); 2135c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 213626b88520SRussell King 2137d272fbf0SMatt Porter host->rx_chan = 2138d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2139d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2140d272fbf0SMatt Porter 2141c5c98927SRussell King if (!host->rx_chan) { 214226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 214304e8c7bcSKevin Hilman ret = -ENXIO; 214426b88520SRussell King goto err_irq; 2145c5c98927SRussell King } 214626b88520SRussell King 2147d272fbf0SMatt Porter host->tx_chan = 2148d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2149d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2150d272fbf0SMatt Porter 2151c5c98927SRussell King if (!host->tx_chan) { 215226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 215304e8c7bcSKevin Hilman ret = -ENXIO; 215426b88520SRussell King goto err_irq; 2155c5c98927SRussell King } 2156a45c6cb8SMadhusudhan Chikkature 2157a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2158e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2159a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2160a45c6cb8SMadhusudhan Chikkature if (ret) { 2161b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2162a45c6cb8SMadhusudhan Chikkature goto err_irq; 2163a45c6cb8SMadhusudhan Chikkature } 2164a45c6cb8SMadhusudhan Chikkature 2165a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 2166a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 2167b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 216870a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 2169e1538ed7SBalaji T K goto err_irq; 2170a45c6cb8SMadhusudhan Chikkature } 2171a45c6cb8SMadhusudhan Chikkature } 2172db0fefc5SAdrian Hunter 2173b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2174db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2175db0fefc5SAdrian Hunter if (ret) 2176db0fefc5SAdrian Hunter goto err_reg; 2177db0fefc5SAdrian Hunter host->use_reg = 1; 2178db0fefc5SAdrian Hunter } 2179db0fefc5SAdrian Hunter 2180b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 2181a45c6cb8SMadhusudhan Chikkature 2182a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2183e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 21849fa0e05eSBalaji T K ret = devm_request_threaded_irq(&pdev->dev, 21859fa0e05eSBalaji T K mmc_slot(host).card_detect_irq, 21869fa0e05eSBalaji T K NULL, omap_hsmmc_detect, 2187db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2188a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2189a45c6cb8SMadhusudhan Chikkature if (ret) { 2190b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 2191a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2192a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2193a45c6cb8SMadhusudhan Chikkature } 219472f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 219572f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2196a45c6cb8SMadhusudhan Chikkature } 2197a45c6cb8SMadhusudhan Chikkature 2198b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2199a45c6cb8SMadhusudhan Chikkature 220046b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 220146b76035SDaniel Mack if (IS_ERR(pinctrl)) 220246b76035SDaniel Mack dev_warn(&pdev->dev, 220346b76035SDaniel Mack "pins are not configured from the driver\n"); 220446b76035SDaniel Mack 22052cd3a2a5SAndreas Fenkart /* 22062cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 22072cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 22082cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 22092cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 22102cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 22112cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22122cd3a2a5SAndreas Fenkart */ 22132cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22142cd3a2a5SAndreas Fenkart if (!ret) 22152cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22162cd3a2a5SAndreas Fenkart 2217b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2218b62f6228SAdrian Hunter 2219a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2220a45c6cb8SMadhusudhan Chikkature 2221191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2222a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2223a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2224a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2225a45c6cb8SMadhusudhan Chikkature } 2226191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2227a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2228a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2229a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2230db0fefc5SAdrian Hunter goto err_slot_name; 2231a45c6cb8SMadhusudhan Chikkature } 2232a45c6cb8SMadhusudhan Chikkature 223370a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2234fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2235fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2236d900f712SDenis Karpov 2237a45c6cb8SMadhusudhan Chikkature return 0; 2238a45c6cb8SMadhusudhan Chikkature 2239a45c6cb8SMadhusudhan Chikkature err_slot_name: 2240a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2241db0fefc5SAdrian Hunter err_irq_cd: 2242db0fefc5SAdrian Hunter if (host->use_reg) 2243db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2244db0fefc5SAdrian Hunter err_reg: 2245db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2246db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2247a45c6cb8SMadhusudhan Chikkature err_irq: 2248c5c98927SRussell King if (host->tx_chan) 2249c5c98927SRussell King dma_release_channel(host->tx_chan); 2250c5c98927SRussell King if (host->rx_chan) 2251c5c98927SRussell King dma_release_channel(host->rx_chan); 2252d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 225337f6190dSTony Lindgren pm_runtime_disable(host->dev); 22549618195eSBalaji T K if (host->dbclk) 225594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2256a45c6cb8SMadhusudhan Chikkature err1: 2257a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2258db0fefc5SAdrian Hunter err_alloc: 2259db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2260db0fefc5SAdrian Hunter err: 2261a45c6cb8SMadhusudhan Chikkature return ret; 2262a45c6cb8SMadhusudhan Chikkature } 2263a45c6cb8SMadhusudhan Chikkature 22646e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2265a45c6cb8SMadhusudhan Chikkature { 226670a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2267a45c6cb8SMadhusudhan Chikkature 2268fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2269a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2270db0fefc5SAdrian Hunter if (host->use_reg) 2271db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2272a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2273a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2274a45c6cb8SMadhusudhan Chikkature 2275c5c98927SRussell King if (host->tx_chan) 2276c5c98927SRussell King dma_release_channel(host->tx_chan); 2277c5c98927SRussell King if (host->rx_chan) 2278c5c98927SRussell King dma_release_channel(host->rx_chan); 2279c5c98927SRussell King 2280fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2281fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22829618195eSBalaji T K if (host->dbclk) 228394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2284a45c6cb8SMadhusudhan Chikkature 22859ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 22869d1f0286SBalaji T K mmc_free_host(host->mmc); 2287a45c6cb8SMadhusudhan Chikkature 2288a45c6cb8SMadhusudhan Chikkature return 0; 2289a45c6cb8SMadhusudhan Chikkature } 2290a45c6cb8SMadhusudhan Chikkature 2291a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2292a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2293a48ce884SFelipe Balbi { 2294a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2295a48ce884SFelipe Balbi 2296a48ce884SFelipe Balbi if (host->pdata->suspend) 2297a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2298a48ce884SFelipe Balbi 2299a48ce884SFelipe Balbi return 0; 2300a48ce884SFelipe Balbi } 2301a48ce884SFelipe Balbi 2302a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2303a48ce884SFelipe Balbi { 2304a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2305a48ce884SFelipe Balbi 2306a48ce884SFelipe Balbi if (host->pdata->resume) 2307a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2308a48ce884SFelipe Balbi 2309a48ce884SFelipe Balbi } 2310a48ce884SFelipe Balbi 2311a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2312a45c6cb8SMadhusudhan Chikkature { 2313927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2314927ce944SFelipe Balbi 2315927ce944SFelipe Balbi if (!host) 2316927ce944SFelipe Balbi return 0; 2317a45c6cb8SMadhusudhan Chikkature 2318fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 231931f9d463SEliad Peller 232031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 23212cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23222cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23232cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 232431f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 232531f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 232631f9d463SEliad Peller } 2327927ce944SFelipe Balbi 23282cd3a2a5SAndreas Fenkart /* do not wake up due to sdio irq */ 23292cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23302cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23312cd3a2a5SAndreas Fenkart disable_irq(host->wake_irq); 23322cd3a2a5SAndreas Fenkart 2333cd03d9a8SRajendra Nayak if (host->dbclk) 233494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 23353932afd5SUlf Hansson 2336fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 23373932afd5SUlf Hansson return 0; 2338a45c6cb8SMadhusudhan Chikkature } 2339a45c6cb8SMadhusudhan Chikkature 2340a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2341a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2342a45c6cb8SMadhusudhan Chikkature { 2343927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2344927ce944SFelipe Balbi 2345927ce944SFelipe Balbi if (!host) 2346927ce944SFelipe Balbi return 0; 2347a45c6cb8SMadhusudhan Chikkature 2348fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 234911dd62a7SDenis Karpov 2350cd03d9a8SRajendra Nayak if (host->dbclk) 235194c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23522bec0893SAdrian Hunter 235331f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 235470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23551b331e69SKim Kyuwon 2356b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2357b62f6228SAdrian Hunter 23582cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23592cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23602cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23612cd3a2a5SAndreas Fenkart 2362fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2363fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23643932afd5SUlf Hansson return 0; 2365a45c6cb8SMadhusudhan Chikkature } 2366a45c6cb8SMadhusudhan Chikkature 2367a45c6cb8SMadhusudhan Chikkature #else 2368a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2369a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 237070a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 237170a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2372a45c6cb8SMadhusudhan Chikkature #endif 2373a45c6cb8SMadhusudhan Chikkature 2374fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2375fa4aa2d4SBalaji T K { 2376fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23772cd3a2a5SAndreas Fenkart unsigned long flags; 2378fa4aa2d4SBalaji T K 2379fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2380fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2381927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2382fa4aa2d4SBalaji T K 23832cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23842cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23852cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23862cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23872cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23882cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23892cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23902cd3a2a5SAndreas Fenkart 23912cd3a2a5SAndreas Fenkart WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); 23922cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23932cd3a2a5SAndreas Fenkart host->flags |= HSMMC_WAKE_IRQ_ENABLED; 23942cd3a2a5SAndreas Fenkart } 23952cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2396fa4aa2d4SBalaji T K return 0; 2397fa4aa2d4SBalaji T K } 2398fa4aa2d4SBalaji T K 2399fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2400fa4aa2d4SBalaji T K { 2401fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 24022cd3a2a5SAndreas Fenkart unsigned long flags; 2403fa4aa2d4SBalaji T K 2404fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2405fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2406927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2407fa4aa2d4SBalaji T K 24082cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 24092cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 24102cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 24112cd3a2a5SAndreas Fenkart /* sdio irq flag can't change while in runtime suspend */ 24122cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 24132cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 24142cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 24152cd3a2a5SAndreas Fenkart } 24162cd3a2a5SAndreas Fenkart 24172cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 24182cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 24192cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 24202cd3a2a5SAndreas Fenkart } 24212cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2422fa4aa2d4SBalaji T K return 0; 2423fa4aa2d4SBalaji T K } 2424fa4aa2d4SBalaji T K 2425a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 242670a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 242770a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2428a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2429a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2430fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2431fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2432a791daa1SKevin Hilman }; 2433a791daa1SKevin Hilman 2434a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2435efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24360433c143SBill Pemberton .remove = omap_hsmmc_remove, 2437a45c6cb8SMadhusudhan Chikkature .driver = { 2438a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2439a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2440a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 244146856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2442a45c6cb8SMadhusudhan Chikkature }, 2443a45c6cb8SMadhusudhan Chikkature }; 2444a45c6cb8SMadhusudhan Chikkature 2445b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2446a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2447a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2448a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2449a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2450