1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3046856a68SRajendra Nayak #include <linux/of.h> 3146856a68SRajendra Nayak #include <linux/of_gpio.h> 3246856a68SRajendra Nayak #include <linux/of_device.h> 333451c067SRussell King #include <linux/omap-dma.h> 34a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3513189e78SJarkko Lavinen #include <linux/mmc/core.h> 3693caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 37a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 38db0fefc5SAdrian Hunter #include <linux/gpio.h> 39db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 40fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 41a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 42ce491cf8STony Lindgren #include <plat/board.h> 43ce491cf8STony Lindgren #include <plat/mmc.h> 44ce491cf8STony Lindgren #include <plat/cpu.h> 45a45c6cb8SMadhusudhan Chikkature 46a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4711dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 63a45c6cb8SMadhusudhan Chikkature 64a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 65a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 79a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 80a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 81a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 82a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 83ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 84ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8593caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 86a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 87a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 88a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 89a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 90a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 91a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 92a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9303b5d924SBalaji T K #define DDR (1 << 19) 9473153010SJarkko Lavinen #define DW8 (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define CC 0x1 96a45c6cb8SMadhusudhan Chikkature #define TC 0x02 97a45c6cb8SMadhusudhan Chikkature #define OD 0x1 98a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 99a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 100a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 101a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 102a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 103a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 11011dd62a7SDenis Karpov #define RESETDONE (1 << 0) 111a45c6cb8SMadhusudhan Chikkature 112fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 113a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1146b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1156b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1160005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 117a45c6cb8SMadhusudhan Chikkature 118a45c6cb8SMadhusudhan Chikkature /* 119a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 120a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 121a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 122a45c6cb8SMadhusudhan Chikkature */ 123a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 124a45c6cb8SMadhusudhan Chikkature 125a45c6cb8SMadhusudhan Chikkature /* 126a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 127a45c6cb8SMadhusudhan Chikkature */ 128a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 129a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 130a45c6cb8SMadhusudhan Chikkature 131a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 132a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 133a45c6cb8SMadhusudhan Chikkature 1349782aff8SPer Forlin struct omap_hsmmc_next { 1359782aff8SPer Forlin unsigned int dma_len; 1369782aff8SPer Forlin s32 cookie; 1379782aff8SPer Forlin }; 1389782aff8SPer Forlin 13970a3341aSDenis Karpov struct omap_hsmmc_host { 140a45c6cb8SMadhusudhan Chikkature struct device *dev; 141a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 142a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 143a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 144a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 145a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 146a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 147db0fefc5SAdrian Hunter /* 148db0fefc5SAdrian Hunter * vcc == configured supply 149db0fefc5SAdrian Hunter * vcc_aux == optional 150db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 151db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 152db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 153db0fefc5SAdrian Hunter */ 154db0fefc5SAdrian Hunter struct regulator *vcc; 155db0fefc5SAdrian Hunter struct regulator *vcc_aux; 156a45c6cb8SMadhusudhan Chikkature void __iomem *base; 157a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1584dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 159a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1600ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 161a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 162a3621465SAdrian Hunter unsigned char power_mode; 163a45c6cb8SMadhusudhan Chikkature int suspended; 164a45c6cb8SMadhusudhan Chikkature int irq; 165a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 166c5c98927SRussell King struct dma_chan *tx_chan; 167c5c98927SRussell King struct dma_chan *rx_chan; 168a45c6cb8SMadhusudhan Chikkature int slot_id; 1694a694dc9SAdrian Hunter int response_busy; 17011dd62a7SDenis Karpov int context_loss; 171b62f6228SAdrian Hunter int protect_card; 172b62f6228SAdrian Hunter int reqs_blocked; 173db0fefc5SAdrian Hunter int use_reg; 174b417577dSAdrian Hunter int req_in_progress; 1759782aff8SPer Forlin struct omap_hsmmc_next next_data; 17611dd62a7SDenis Karpov 177a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 178a45c6cb8SMadhusudhan Chikkature }; 179a45c6cb8SMadhusudhan Chikkature 180db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 181db0fefc5SAdrian Hunter { 182db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 183db0fefc5SAdrian Hunter 184db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 185db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 186db0fefc5SAdrian Hunter } 187db0fefc5SAdrian Hunter 188db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 189db0fefc5SAdrian Hunter { 190db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 191db0fefc5SAdrian Hunter 192db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 193db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 194db0fefc5SAdrian Hunter } 195db0fefc5SAdrian Hunter 196db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 197db0fefc5SAdrian Hunter { 198db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 199db0fefc5SAdrian Hunter 200db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 201db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 202db0fefc5SAdrian Hunter } 203db0fefc5SAdrian Hunter 204db0fefc5SAdrian Hunter #ifdef CONFIG_PM 205db0fefc5SAdrian Hunter 206db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 207db0fefc5SAdrian Hunter { 208db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 209db0fefc5SAdrian Hunter 210db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 211db0fefc5SAdrian Hunter return 0; 212db0fefc5SAdrian Hunter } 213db0fefc5SAdrian Hunter 214db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 215db0fefc5SAdrian Hunter { 216db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 217db0fefc5SAdrian Hunter 218db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 219db0fefc5SAdrian Hunter return 0; 220db0fefc5SAdrian Hunter } 221db0fefc5SAdrian Hunter 222db0fefc5SAdrian Hunter #else 223db0fefc5SAdrian Hunter 224db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 225db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter #endif 228db0fefc5SAdrian Hunter 229b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 230b702b106SAdrian Hunter 23169b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 232db0fefc5SAdrian Hunter int vdd) 233db0fefc5SAdrian Hunter { 234db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 235db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 236db0fefc5SAdrian Hunter int ret = 0; 237db0fefc5SAdrian Hunter 238db0fefc5SAdrian Hunter /* 239db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 240db0fefc5SAdrian Hunter * voltage always-on regulator. 241db0fefc5SAdrian Hunter */ 242db0fefc5SAdrian Hunter if (!host->vcc) 243db0fefc5SAdrian Hunter return 0; 2441f84b71bSRajendra Nayak /* 2451f84b71bSRajendra Nayak * With DT, never turn OFF the regulator. This is because 2461f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2471f84b71bSRajendra Nayak * booting with Device tree 2481f84b71bSRajendra Nayak */ 2494d048f91SRajendra Nayak if (dev->of_node && !vdd) 2501f84b71bSRajendra Nayak return 0; 251db0fefc5SAdrian Hunter 252db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 253db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 254db0fefc5SAdrian Hunter 255db0fefc5SAdrian Hunter /* 256db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 257db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 258db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 259db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 260db0fefc5SAdrian Hunter * 261db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 262db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 263db0fefc5SAdrian Hunter * 264db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 265db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 266db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 267db0fefc5SAdrian Hunter */ 268db0fefc5SAdrian Hunter if (power_on) { 26999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 270db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 271db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 272db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 273db0fefc5SAdrian Hunter if (ret < 0) 27499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 27599fc5131SLinus Walleij host->vcc, 0); 276db0fefc5SAdrian Hunter } 277db0fefc5SAdrian Hunter } else { 27899fc5131SLinus Walleij /* Shut down the rail */ 2796da20c89SAdrian Hunter if (host->vcc_aux) 280db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 28199fc5131SLinus Walleij if (!ret) { 28299fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 28399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 28499fc5131SLinus Walleij host->vcc, 0); 28599fc5131SLinus Walleij } 286db0fefc5SAdrian Hunter } 287db0fefc5SAdrian Hunter 288db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 289db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 290db0fefc5SAdrian Hunter 291db0fefc5SAdrian Hunter return ret; 292db0fefc5SAdrian Hunter } 293db0fefc5SAdrian Hunter 294db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 295db0fefc5SAdrian Hunter { 296db0fefc5SAdrian Hunter struct regulator *reg; 29764be9782Skishore kadiyala int ocr_value = 0; 298db0fefc5SAdrian Hunter 299db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 300db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 301db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 3021fdc90fbSNeilBrown return PTR_ERR(reg); 303db0fefc5SAdrian Hunter } else { 3041fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 305db0fefc5SAdrian Hunter host->vcc = reg; 30664be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 30764be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 30864be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 30964be9782Skishore kadiyala } else { 31064be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3112cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 312e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 31364be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 31464be9782Skishore kadiyala return -EINVAL; 31564be9782Skishore kadiyala } 31664be9782Skishore kadiyala } 317db0fefc5SAdrian Hunter 318db0fefc5SAdrian Hunter /* Allow an aux regulator */ 319db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 320db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 321db0fefc5SAdrian Hunter 322b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 323b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 324b1c1df7aSBalaji T K return 0; 325db0fefc5SAdrian Hunter /* 326db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 327db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 328db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 329db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 330db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 331db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 332db0fefc5SAdrian Hunter */ 333e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 334e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 335e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 336e840ce13SAdrian Hunter 337e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 338e840ce13SAdrian Hunter 1, vdd); 339e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 340e840ce13SAdrian Hunter 0, 0); 341db0fefc5SAdrian Hunter } 342db0fefc5SAdrian Hunter } 343db0fefc5SAdrian Hunter 344db0fefc5SAdrian Hunter return 0; 345db0fefc5SAdrian Hunter } 346db0fefc5SAdrian Hunter 347db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 348db0fefc5SAdrian Hunter { 349db0fefc5SAdrian Hunter regulator_put(host->vcc); 350db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 351db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 352db0fefc5SAdrian Hunter } 353db0fefc5SAdrian Hunter 354b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 355b702b106SAdrian Hunter { 356b702b106SAdrian Hunter return 1; 357b702b106SAdrian Hunter } 358b702b106SAdrian Hunter 359b702b106SAdrian Hunter #else 360b702b106SAdrian Hunter 361b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 362b702b106SAdrian Hunter { 363b702b106SAdrian Hunter return -EINVAL; 364b702b106SAdrian Hunter } 365b702b106SAdrian Hunter 366b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 367b702b106SAdrian Hunter { 368b702b106SAdrian Hunter } 369b702b106SAdrian Hunter 370b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 371b702b106SAdrian Hunter { 372b702b106SAdrian Hunter return 0; 373b702b106SAdrian Hunter } 374b702b106SAdrian Hunter 375b702b106SAdrian Hunter #endif 376b702b106SAdrian Hunter 377b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 378b702b106SAdrian Hunter { 379b702b106SAdrian Hunter int ret; 380b702b106SAdrian Hunter 381b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 382b702b106SAdrian Hunter if (pdata->slots[0].cover) 383b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 384b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 385b702b106SAdrian Hunter else 386b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 387b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 388b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 389b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 390b702b106SAdrian Hunter if (ret) 391b702b106SAdrian Hunter return ret; 392b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 393b702b106SAdrian Hunter if (ret) 394b702b106SAdrian Hunter goto err_free_sp; 395b702b106SAdrian Hunter } else 396b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 397b702b106SAdrian Hunter 398b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 399b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 400b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 401b702b106SAdrian Hunter if (ret) 402b702b106SAdrian Hunter goto err_free_cd; 403b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 404b702b106SAdrian Hunter if (ret) 405b702b106SAdrian Hunter goto err_free_wp; 406b702b106SAdrian Hunter } else 407b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 408b702b106SAdrian Hunter 409b702b106SAdrian Hunter return 0; 410b702b106SAdrian Hunter 411b702b106SAdrian Hunter err_free_wp: 412b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 413b702b106SAdrian Hunter err_free_cd: 414b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 415b702b106SAdrian Hunter err_free_sp: 416b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 417b702b106SAdrian Hunter return ret; 418b702b106SAdrian Hunter } 419b702b106SAdrian Hunter 420b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 421b702b106SAdrian Hunter { 422b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 423b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 424b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 425b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 426b702b106SAdrian Hunter } 427b702b106SAdrian Hunter 428a45c6cb8SMadhusudhan Chikkature /* 429e0c7f99bSAndy Shevchenko * Start clock to the card 430e0c7f99bSAndy Shevchenko */ 431e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 432e0c7f99bSAndy Shevchenko { 433e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 434e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 435e0c7f99bSAndy Shevchenko } 436e0c7f99bSAndy Shevchenko 437e0c7f99bSAndy Shevchenko /* 438a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 439a45c6cb8SMadhusudhan Chikkature */ 44070a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 441a45c6cb8SMadhusudhan Chikkature { 442a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 443a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 444a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 445a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 446a45c6cb8SMadhusudhan Chikkature } 447a45c6cb8SMadhusudhan Chikkature 44893caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 44993caf8e6SAdrian Hunter struct mmc_command *cmd) 450b417577dSAdrian Hunter { 451b417577dSAdrian Hunter unsigned int irq_mask; 452b417577dSAdrian Hunter 453b417577dSAdrian Hunter if (host->use_dma) 454b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 455b417577dSAdrian Hunter else 456b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 457b417577dSAdrian Hunter 45893caf8e6SAdrian Hunter /* Disable timeout for erases */ 45993caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 46093caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 46193caf8e6SAdrian Hunter 462b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 463b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 464b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 465b417577dSAdrian Hunter } 466b417577dSAdrian Hunter 467b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 468b417577dSAdrian Hunter { 469b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 470b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 471b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 472b417577dSAdrian Hunter } 473b417577dSAdrian Hunter 474ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 475d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 476ac330f44SAndy Shevchenko { 477ac330f44SAndy Shevchenko u16 dsor = 0; 478ac330f44SAndy Shevchenko 479ac330f44SAndy Shevchenko if (ios->clock) { 480d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 481ac330f44SAndy Shevchenko if (dsor > 250) 482ac330f44SAndy Shevchenko dsor = 250; 483ac330f44SAndy Shevchenko } 484ac330f44SAndy Shevchenko 485ac330f44SAndy Shevchenko return dsor; 486ac330f44SAndy Shevchenko } 487ac330f44SAndy Shevchenko 4885934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 4895934df2fSAndy Shevchenko { 4905934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 4915934df2fSAndy Shevchenko unsigned long regval; 4925934df2fSAndy Shevchenko unsigned long timeout; 4935934df2fSAndy Shevchenko 4948986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 4955934df2fSAndy Shevchenko 4965934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 4975934df2fSAndy Shevchenko 4985934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 4995934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 500d83b6e03SBalaji TK regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); 5015934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5025934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5035934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5045934df2fSAndy Shevchenko 5055934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5065934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5075934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5085934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5095934df2fSAndy Shevchenko cpu_relax(); 5105934df2fSAndy Shevchenko 5115934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5125934df2fSAndy Shevchenko } 5135934df2fSAndy Shevchenko 5143796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5153796fb8aSAndy Shevchenko { 5163796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5173796fb8aSAndy Shevchenko u32 con; 5183796fb8aSAndy Shevchenko 5193796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 52003b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 52103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 52203b5d924SBalaji T K else 52303b5d924SBalaji T K con &= ~DDR; 5243796fb8aSAndy Shevchenko switch (ios->bus_width) { 5253796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5263796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5273796fb8aSAndy Shevchenko break; 5283796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5293796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5303796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5313796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5323796fb8aSAndy Shevchenko break; 5333796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5343796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5353796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5363796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5373796fb8aSAndy Shevchenko break; 5383796fb8aSAndy Shevchenko } 5393796fb8aSAndy Shevchenko } 5403796fb8aSAndy Shevchenko 5413796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5423796fb8aSAndy Shevchenko { 5433796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5443796fb8aSAndy Shevchenko u32 con; 5453796fb8aSAndy Shevchenko 5463796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5473796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5483796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5493796fb8aSAndy Shevchenko else 5503796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5513796fb8aSAndy Shevchenko } 5523796fb8aSAndy Shevchenko 55311dd62a7SDenis Karpov #ifdef CONFIG_PM 55411dd62a7SDenis Karpov 55511dd62a7SDenis Karpov /* 55611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 55711dd62a7SDenis Karpov * power state change. 55811dd62a7SDenis Karpov */ 55970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 56011dd62a7SDenis Karpov { 56111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 56211dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 56311dd62a7SDenis Karpov int context_loss = 0; 5643796fb8aSAndy Shevchenko u32 hctl, capa; 56511dd62a7SDenis Karpov unsigned long timeout; 56611dd62a7SDenis Karpov 56711dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 56811dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 56911dd62a7SDenis Karpov if (context_loss < 0) 57011dd62a7SDenis Karpov return 1; 57111dd62a7SDenis Karpov } 57211dd62a7SDenis Karpov 57311dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 57411dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 57511dd62a7SDenis Karpov if (host->context_loss == context_loss) 57611dd62a7SDenis Karpov return 1; 57711dd62a7SDenis Karpov 5786c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 5796c31b215SVenkatraman S return 1; 58011dd62a7SDenis Karpov 581c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 58211dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 58311dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 58411dd62a7SDenis Karpov hctl = SDVS18; 58511dd62a7SDenis Karpov else 58611dd62a7SDenis Karpov hctl = SDVS30; 58711dd62a7SDenis Karpov capa = VS30 | VS18; 58811dd62a7SDenis Karpov } else { 58911dd62a7SDenis Karpov hctl = SDVS18; 59011dd62a7SDenis Karpov capa = VS18; 59111dd62a7SDenis Karpov } 59211dd62a7SDenis Karpov 59311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 59411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 59511dd62a7SDenis Karpov 59611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 59711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 59811dd62a7SDenis Karpov 59911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 60011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 60111dd62a7SDenis Karpov 60211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 60311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 60411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 60511dd62a7SDenis Karpov ; 60611dd62a7SDenis Karpov 607b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 60811dd62a7SDenis Karpov 60911dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 61011dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 61111dd62a7SDenis Karpov goto out; 61211dd62a7SDenis Karpov 6133796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 61411dd62a7SDenis Karpov 6155934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 61611dd62a7SDenis Karpov 6173796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6183796fb8aSAndy Shevchenko 61911dd62a7SDenis Karpov out: 62011dd62a7SDenis Karpov host->context_loss = context_loss; 62111dd62a7SDenis Karpov 62211dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 62311dd62a7SDenis Karpov return 0; 62411dd62a7SDenis Karpov } 62511dd62a7SDenis Karpov 62611dd62a7SDenis Karpov /* 62711dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 62811dd62a7SDenis Karpov */ 62970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 63011dd62a7SDenis Karpov { 63111dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 63211dd62a7SDenis Karpov int context_loss; 63311dd62a7SDenis Karpov 63411dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 63511dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 63611dd62a7SDenis Karpov if (context_loss < 0) 63711dd62a7SDenis Karpov return; 63811dd62a7SDenis Karpov host->context_loss = context_loss; 63911dd62a7SDenis Karpov } 64011dd62a7SDenis Karpov } 64111dd62a7SDenis Karpov 64211dd62a7SDenis Karpov #else 64311dd62a7SDenis Karpov 64470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 64511dd62a7SDenis Karpov { 64611dd62a7SDenis Karpov return 0; 64711dd62a7SDenis Karpov } 64811dd62a7SDenis Karpov 64970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 65011dd62a7SDenis Karpov { 65111dd62a7SDenis Karpov } 65211dd62a7SDenis Karpov 65311dd62a7SDenis Karpov #endif 65411dd62a7SDenis Karpov 655a45c6cb8SMadhusudhan Chikkature /* 656a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 657a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 658a45c6cb8SMadhusudhan Chikkature */ 65970a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 660a45c6cb8SMadhusudhan Chikkature { 661a45c6cb8SMadhusudhan Chikkature int reg = 0; 662a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 663a45c6cb8SMadhusudhan Chikkature 664b62f6228SAdrian Hunter if (host->protect_card) 665b62f6228SAdrian Hunter return; 666b62f6228SAdrian Hunter 667a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 668b417577dSAdrian Hunter 669b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 670a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 671a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 672a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 673a45c6cb8SMadhusudhan Chikkature 674a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 675a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 676a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 677a45c6cb8SMadhusudhan Chikkature 678a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 679a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 680c653a6d4SAdrian Hunter 681c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 682c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 683c653a6d4SAdrian Hunter 684a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 685a45c6cb8SMadhusudhan Chikkature } 686a45c6cb8SMadhusudhan Chikkature 687a45c6cb8SMadhusudhan Chikkature static inline 68870a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 689a45c6cb8SMadhusudhan Chikkature { 690a45c6cb8SMadhusudhan Chikkature int r = 1; 691a45c6cb8SMadhusudhan Chikkature 692191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 693191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 694a45c6cb8SMadhusudhan Chikkature return r; 695a45c6cb8SMadhusudhan Chikkature } 696a45c6cb8SMadhusudhan Chikkature 697a45c6cb8SMadhusudhan Chikkature static ssize_t 69870a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 699a45c6cb8SMadhusudhan Chikkature char *buf) 700a45c6cb8SMadhusudhan Chikkature { 701a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 70270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 703a45c6cb8SMadhusudhan Chikkature 70470a3341aSDenis Karpov return sprintf(buf, "%s\n", 70570a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 706a45c6cb8SMadhusudhan Chikkature } 707a45c6cb8SMadhusudhan Chikkature 70870a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 709a45c6cb8SMadhusudhan Chikkature 710a45c6cb8SMadhusudhan Chikkature static ssize_t 71170a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 712a45c6cb8SMadhusudhan Chikkature char *buf) 713a45c6cb8SMadhusudhan Chikkature { 714a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 71570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 716a45c6cb8SMadhusudhan Chikkature 717191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 718a45c6cb8SMadhusudhan Chikkature } 719a45c6cb8SMadhusudhan Chikkature 72070a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 721a45c6cb8SMadhusudhan Chikkature 722a45c6cb8SMadhusudhan Chikkature /* 723a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 724a45c6cb8SMadhusudhan Chikkature */ 725a45c6cb8SMadhusudhan Chikkature static void 72670a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 727a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 728a45c6cb8SMadhusudhan Chikkature { 729a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 730a45c6cb8SMadhusudhan Chikkature 7318986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 732a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 733a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 734a45c6cb8SMadhusudhan Chikkature 73593caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 736a45c6cb8SMadhusudhan Chikkature 7374a694dc9SAdrian Hunter host->response_busy = 0; 738a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 739a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 740a45c6cb8SMadhusudhan Chikkature resptype = 1; 7414a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7424a694dc9SAdrian Hunter resptype = 3; 7434a694dc9SAdrian Hunter host->response_busy = 1; 7444a694dc9SAdrian Hunter } else 745a45c6cb8SMadhusudhan Chikkature resptype = 2; 746a45c6cb8SMadhusudhan Chikkature } 747a45c6cb8SMadhusudhan Chikkature 748a45c6cb8SMadhusudhan Chikkature /* 749a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 750a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 751a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 752a45c6cb8SMadhusudhan Chikkature */ 753a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 754a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 755a45c6cb8SMadhusudhan Chikkature 756a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 757a45c6cb8SMadhusudhan Chikkature 758a45c6cb8SMadhusudhan Chikkature if (data) { 759a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 760a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 761a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 762a45c6cb8SMadhusudhan Chikkature else 763a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 764a45c6cb8SMadhusudhan Chikkature } 765a45c6cb8SMadhusudhan Chikkature 766a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 767a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 768a45c6cb8SMadhusudhan Chikkature 769b417577dSAdrian Hunter host->req_in_progress = 1; 7704dffd7a2SAdrian Hunter 771a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 772a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 773a45c6cb8SMadhusudhan Chikkature } 774a45c6cb8SMadhusudhan Chikkature 7750ccd76d4SJuha Yrjola static int 77670a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 7770ccd76d4SJuha Yrjola { 7780ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 7790ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 7800ccd76d4SJuha Yrjola else 7810ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 7820ccd76d4SJuha Yrjola } 7830ccd76d4SJuha Yrjola 784c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 785c5c98927SRussell King struct mmc_data *data) 786c5c98927SRussell King { 787c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 788c5c98927SRussell King } 789c5c98927SRussell King 790b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 791b417577dSAdrian Hunter { 792b417577dSAdrian Hunter int dma_ch; 79331463b14SVenkatraman S unsigned long flags; 794b417577dSAdrian Hunter 79531463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 796b417577dSAdrian Hunter host->req_in_progress = 0; 797b417577dSAdrian Hunter dma_ch = host->dma_ch; 79831463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 799b417577dSAdrian Hunter 800b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 801b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 802b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 803b417577dSAdrian Hunter return; 804b417577dSAdrian Hunter host->mrq = NULL; 805b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 806b417577dSAdrian Hunter } 807b417577dSAdrian Hunter 808a45c6cb8SMadhusudhan Chikkature /* 809a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 810a45c6cb8SMadhusudhan Chikkature */ 811a45c6cb8SMadhusudhan Chikkature static void 81270a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 813a45c6cb8SMadhusudhan Chikkature { 8144a694dc9SAdrian Hunter if (!data) { 8154a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8164a694dc9SAdrian Hunter 81723050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 81823050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 81923050103SAdrian Hunter host->response_busy) { 82023050103SAdrian Hunter host->response_busy = 0; 82123050103SAdrian Hunter return; 82223050103SAdrian Hunter } 82323050103SAdrian Hunter 824b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8254a694dc9SAdrian Hunter return; 8264a694dc9SAdrian Hunter } 8274a694dc9SAdrian Hunter 828a45c6cb8SMadhusudhan Chikkature host->data = NULL; 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature if (!data->error) 831a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 832a45c6cb8SMadhusudhan Chikkature else 833a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 834a45c6cb8SMadhusudhan Chikkature 835fe852273SMing Lei if (!data->stop) { 836dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 837fe852273SMing Lei return; 838dba3c29eSBalaji T K } 839fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 840a45c6cb8SMadhusudhan Chikkature } 841a45c6cb8SMadhusudhan Chikkature 842a45c6cb8SMadhusudhan Chikkature /* 843a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 844a45c6cb8SMadhusudhan Chikkature */ 845a45c6cb8SMadhusudhan Chikkature static void 84670a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 847a45c6cb8SMadhusudhan Chikkature { 848a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 849a45c6cb8SMadhusudhan Chikkature 850a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 851a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 852a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 853a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 854a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 855a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 856a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 857a45c6cb8SMadhusudhan Chikkature } else { 858a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 859a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 860a45c6cb8SMadhusudhan Chikkature } 861a45c6cb8SMadhusudhan Chikkature } 862b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 863b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 864a45c6cb8SMadhusudhan Chikkature } 865a45c6cb8SMadhusudhan Chikkature 866a45c6cb8SMadhusudhan Chikkature /* 867a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 868a45c6cb8SMadhusudhan Chikkature */ 86970a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 870a45c6cb8SMadhusudhan Chikkature { 871b417577dSAdrian Hunter int dma_ch; 87231463b14SVenkatraman S unsigned long flags; 873b417577dSAdrian Hunter 87482788ff5SJarkko Lavinen host->data->error = errno; 875a45c6cb8SMadhusudhan Chikkature 87631463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 877b417577dSAdrian Hunter dma_ch = host->dma_ch; 878b417577dSAdrian Hunter host->dma_ch = -1; 87931463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 880b417577dSAdrian Hunter 881b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 882c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 883c5c98927SRussell King 884c5c98927SRussell King dmaengine_terminate_all(chan); 885c5c98927SRussell King dma_unmap_sg(chan->device->dev, 886c5c98927SRussell King host->data->sg, host->data->sg_len, 88770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 888c5c98927SRussell King 889053bf34fSPer Forlin host->data->host_cookie = 0; 890a45c6cb8SMadhusudhan Chikkature } 891a45c6cb8SMadhusudhan Chikkature host->data = NULL; 892a45c6cb8SMadhusudhan Chikkature } 893a45c6cb8SMadhusudhan Chikkature 894a45c6cb8SMadhusudhan Chikkature /* 895a45c6cb8SMadhusudhan Chikkature * Readable error output 896a45c6cb8SMadhusudhan Chikkature */ 897a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 898699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 899a45c6cb8SMadhusudhan Chikkature { 900a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 90170a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 902699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 903699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 904699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 905699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 906a45c6cb8SMadhusudhan Chikkature }; 907a45c6cb8SMadhusudhan Chikkature char res[256]; 908a45c6cb8SMadhusudhan Chikkature char *buf = res; 909a45c6cb8SMadhusudhan Chikkature int len, i; 910a45c6cb8SMadhusudhan Chikkature 911a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 912a45c6cb8SMadhusudhan Chikkature buf += len; 913a45c6cb8SMadhusudhan Chikkature 91470a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 915a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 91670a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 917a45c6cb8SMadhusudhan Chikkature buf += len; 918a45c6cb8SMadhusudhan Chikkature } 919a45c6cb8SMadhusudhan Chikkature 9208986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 921a45c6cb8SMadhusudhan Chikkature } 922699b958bSAdrian Hunter #else 923699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 924699b958bSAdrian Hunter u32 status) 925699b958bSAdrian Hunter { 926699b958bSAdrian Hunter } 927a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 928a45c6cb8SMadhusudhan Chikkature 9293ebf74b1SJean Pihet /* 9303ebf74b1SJean Pihet * MMC controller internal state machines reset 9313ebf74b1SJean Pihet * 9323ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9333ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9343ebf74b1SJean Pihet * Can be called from interrupt context 9353ebf74b1SJean Pihet */ 93670a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9373ebf74b1SJean Pihet unsigned long bit) 9383ebf74b1SJean Pihet { 9393ebf74b1SJean Pihet unsigned long i = 0; 9403ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 9413ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 9423ebf74b1SJean Pihet 9433ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9443ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9453ebf74b1SJean Pihet 94607ad64b6SMadhusudhan Chikkature /* 94707ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 94807ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 94907ad64b6SMadhusudhan Chikkature */ 95007ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 951b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 95207ad64b6SMadhusudhan Chikkature && (i++ < limit)) 95307ad64b6SMadhusudhan Chikkature cpu_relax(); 95407ad64b6SMadhusudhan Chikkature } 95507ad64b6SMadhusudhan Chikkature i = 0; 95607ad64b6SMadhusudhan Chikkature 9573ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9583ebf74b1SJean Pihet (i++ < limit)) 9593ebf74b1SJean Pihet cpu_relax(); 9603ebf74b1SJean Pihet 9613ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9623ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9633ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 9643ebf74b1SJean Pihet __func__); 9653ebf74b1SJean Pihet } 966a45c6cb8SMadhusudhan Chikkature 967ae4bf788SVenkatraman S static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err) 968ae4bf788SVenkatraman S { 969ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRC); 970ae4bf788SVenkatraman S host->cmd->error = err; 971ae4bf788SVenkatraman S 972ae4bf788SVenkatraman S if (host->data) { 973ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 974ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 975ae4bf788SVenkatraman S } 976ae4bf788SVenkatraman S 977ae4bf788SVenkatraman S } 978ae4bf788SVenkatraman S 979b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 980a45c6cb8SMadhusudhan Chikkature { 981a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 982b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 983a45c6cb8SMadhusudhan Chikkature 984a45c6cb8SMadhusudhan Chikkature data = host->data; 9858986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 986a45c6cb8SMadhusudhan Chikkature 987a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 988699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 989ae4bf788SVenkatraman S if (status & (CMD_TIMEOUT | DATA_TIMEOUT)) 990ae4bf788SVenkatraman S hsmmc_command_incomplete(host, -ETIMEDOUT); 991ae4bf788SVenkatraman S else if (status & (CMD_CRC | DATA_CRC)) 992ae4bf788SVenkatraman S hsmmc_command_incomplete(host, -EILSEQ); 9934a694dc9SAdrian Hunter 994a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 995ae4bf788SVenkatraman S if (host->data || host->response_busy) { 996a45c6cb8SMadhusudhan Chikkature end_trans = 1; 997ae4bf788SVenkatraman S host->response_busy = 0; 998a45c6cb8SMadhusudhan Chikkature } 999a45c6cb8SMadhusudhan Chikkature } 1000a45c6cb8SMadhusudhan Chikkature 1001a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 100270a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 10030a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 100470a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1005b417577dSAdrian Hunter } 1006a45c6cb8SMadhusudhan Chikkature 1007b417577dSAdrian Hunter /* 1008b417577dSAdrian Hunter * MMC controller IRQ handler 1009b417577dSAdrian Hunter */ 1010b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1011b417577dSAdrian Hunter { 1012b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1013b417577dSAdrian Hunter int status; 1014b417577dSAdrian Hunter 1015b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10161f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1017b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10181f6b9fa4SVenkatraman S 1019b417577dSAdrian Hunter /* Flush posted write */ 10201f6b9fa4SVenkatraman S OMAP_HSMMC_WRITE(host->base, STAT, status); 1021b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10221f6b9fa4SVenkatraman S } 10234dffd7a2SAdrian Hunter 1024a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1025a45c6cb8SMadhusudhan Chikkature } 1026a45c6cb8SMadhusudhan Chikkature 102770a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1028e13bb300SAdrian Hunter { 1029e13bb300SAdrian Hunter unsigned long i; 1030e13bb300SAdrian Hunter 1031e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1032e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1033e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1034e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1035e13bb300SAdrian Hunter break; 1036e13bb300SAdrian Hunter cpu_relax(); 1037e13bb300SAdrian Hunter } 1038e13bb300SAdrian Hunter } 1039e13bb300SAdrian Hunter 1040a45c6cb8SMadhusudhan Chikkature /* 1041eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1042eb250826SDavid Brownell * 1043eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1044eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1045eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1046a45c6cb8SMadhusudhan Chikkature */ 104770a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1048a45c6cb8SMadhusudhan Chikkature { 1049a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1050a45c6cb8SMadhusudhan Chikkature int ret; 1051a45c6cb8SMadhusudhan Chikkature 1052a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1053fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1054cd03d9a8SRajendra Nayak if (host->dbclk) 105594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1056a45c6cb8SMadhusudhan Chikkature 1057a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1058a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1059a45c6cb8SMadhusudhan Chikkature 1060a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 10612bec0893SAdrian Hunter if (!ret) 10622bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 10632bec0893SAdrian Hunter vdd); 1064fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1065cd03d9a8SRajendra Nayak if (host->dbclk) 106694c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 10672bec0893SAdrian Hunter 1068a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1069a45c6cb8SMadhusudhan Chikkature goto err; 1070a45c6cb8SMadhusudhan Chikkature 1071a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1072a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1073a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1074eb250826SDavid Brownell 1075a45c6cb8SMadhusudhan Chikkature /* 1076a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1077a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 107870a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1079a45c6cb8SMadhusudhan Chikkature * 1080eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1081eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1082eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1083eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1084eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1085eb250826SDavid Brownell * 1086eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1087eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1088eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1089a45c6cb8SMadhusudhan Chikkature */ 1090eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1091a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1092eb250826SDavid Brownell else 1093eb250826SDavid Brownell reg_val |= SDVS30; 1094a45c6cb8SMadhusudhan Chikkature 1095a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1096e13bb300SAdrian Hunter set_sd_bus_power(host); 1097a45c6cb8SMadhusudhan Chikkature 1098a45c6cb8SMadhusudhan Chikkature return 0; 1099a45c6cb8SMadhusudhan Chikkature err: 1100a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1101a45c6cb8SMadhusudhan Chikkature return ret; 1102a45c6cb8SMadhusudhan Chikkature } 1103a45c6cb8SMadhusudhan Chikkature 1104b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1105b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1106b62f6228SAdrian Hunter { 1107b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1108b62f6228SAdrian Hunter return; 1109b62f6228SAdrian Hunter 1110b62f6228SAdrian Hunter host->reqs_blocked = 0; 1111b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1112b62f6228SAdrian Hunter if (host->protect_card) { 11132cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1114b62f6228SAdrian Hunter "card is now accessible\n", 1115b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1116b62f6228SAdrian Hunter host->protect_card = 0; 1117b62f6228SAdrian Hunter } 1118b62f6228SAdrian Hunter } else { 1119b62f6228SAdrian Hunter if (!host->protect_card) { 11202cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1121b62f6228SAdrian Hunter "card is now inaccessible\n", 1122b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1123b62f6228SAdrian Hunter host->protect_card = 1; 1124b62f6228SAdrian Hunter } 1125b62f6228SAdrian Hunter } 1126b62f6228SAdrian Hunter } 1127b62f6228SAdrian Hunter 1128a45c6cb8SMadhusudhan Chikkature /* 11297efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1130a45c6cb8SMadhusudhan Chikkature */ 11317efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1132a45c6cb8SMadhusudhan Chikkature { 11337efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1134249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1135a6b2240dSAdrian Hunter int carddetect; 1136249d0fa9SDavid Brownell 1137a6b2240dSAdrian Hunter if (host->suspended) 11387efab4f3SNeilBrown return IRQ_HANDLED; 1139a45c6cb8SMadhusudhan Chikkature 1140a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1141a6b2240dSAdrian Hunter 1142191d1f1dSDenis Karpov if (slot->card_detect) 1143db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1144b62f6228SAdrian Hunter else { 1145b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1146a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1147b62f6228SAdrian Hunter } 1148a6b2240dSAdrian Hunter 1149cdeebaddSMadhusudhan Chikkature if (carddetect) 1150a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1151cdeebaddSMadhusudhan Chikkature else 1152a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1153a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1154a45c6cb8SMadhusudhan Chikkature } 1155a45c6cb8SMadhusudhan Chikkature 1156c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11570ccd76d4SJuha Yrjola { 1158c5c98927SRussell King struct omap_hsmmc_host *host = param; 1159c5c98927SRussell King struct dma_chan *chan; 1160770d7432SAdrian Hunter struct mmc_data *data; 1161c5c98927SRussell King int req_in_progress; 1162a45c6cb8SMadhusudhan Chikkature 1163c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1164b417577dSAdrian Hunter if (host->dma_ch < 0) { 1165c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1166a45c6cb8SMadhusudhan Chikkature return; 1167b417577dSAdrian Hunter } 1168a45c6cb8SMadhusudhan Chikkature 1169770d7432SAdrian Hunter data = host->mrq->data; 1170c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 11719782aff8SPer Forlin if (!data->host_cookie) 1172c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1173c5c98927SRussell King data->sg, data->sg_len, 1174b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1175b417577dSAdrian Hunter 1176b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1177a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1178c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1179b417577dSAdrian Hunter 1180b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1181b417577dSAdrian Hunter if (!req_in_progress) { 1182b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1183b417577dSAdrian Hunter 1184b417577dSAdrian Hunter host->mrq = NULL; 1185b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1186b417577dSAdrian Hunter } 1187a45c6cb8SMadhusudhan Chikkature } 1188a45c6cb8SMadhusudhan Chikkature 11899782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 11909782aff8SPer Forlin struct mmc_data *data, 1191c5c98927SRussell King struct omap_hsmmc_next *next, 119226b88520SRussell King struct dma_chan *chan) 11939782aff8SPer Forlin { 11949782aff8SPer Forlin int dma_len; 11959782aff8SPer Forlin 11969782aff8SPer Forlin if (!next && data->host_cookie && 11979782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 11982cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 11999782aff8SPer Forlin " host->next_data.cookie %d\n", 12009782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12019782aff8SPer Forlin data->host_cookie = 0; 12029782aff8SPer Forlin } 12039782aff8SPer Forlin 12049782aff8SPer Forlin /* Check if next job is already prepared */ 12059782aff8SPer Forlin if (next || 12069782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 120726b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12089782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12099782aff8SPer Forlin 12109782aff8SPer Forlin } else { 12119782aff8SPer Forlin dma_len = host->next_data.dma_len; 12129782aff8SPer Forlin host->next_data.dma_len = 0; 12139782aff8SPer Forlin } 12149782aff8SPer Forlin 12159782aff8SPer Forlin 12169782aff8SPer Forlin if (dma_len == 0) 12179782aff8SPer Forlin return -EINVAL; 12189782aff8SPer Forlin 12199782aff8SPer Forlin if (next) { 12209782aff8SPer Forlin next->dma_len = dma_len; 12219782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12229782aff8SPer Forlin } else 12239782aff8SPer Forlin host->dma_len = dma_len; 12249782aff8SPer Forlin 12259782aff8SPer Forlin return 0; 12269782aff8SPer Forlin } 12279782aff8SPer Forlin 1228a45c6cb8SMadhusudhan Chikkature /* 1229a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1230a45c6cb8SMadhusudhan Chikkature */ 123170a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 123270a3341aSDenis Karpov struct mmc_request *req) 1233a45c6cb8SMadhusudhan Chikkature { 123426b88520SRussell King struct dma_slave_config cfg; 123526b88520SRussell King struct dma_async_tx_descriptor *tx; 123626b88520SRussell King int ret = 0, i; 1237a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1238c5c98927SRussell King struct dma_chan *chan; 1239a45c6cb8SMadhusudhan Chikkature 12400ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1241a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12420ccd76d4SJuha Yrjola struct scatterlist *sgl; 12430ccd76d4SJuha Yrjola 12440ccd76d4SJuha Yrjola sgl = data->sg + i; 12450ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12460ccd76d4SJuha Yrjola return -EINVAL; 12470ccd76d4SJuha Yrjola } 12480ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12490ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12500ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12510ccd76d4SJuha Yrjola */ 12520ccd76d4SJuha Yrjola return -EINVAL; 12530ccd76d4SJuha Yrjola 1254b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1255a45c6cb8SMadhusudhan Chikkature 1256c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1257c5c98927SRussell King 1258c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1259c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1260c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1261c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1262c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1263c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1264c5c98927SRussell King 1265c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 12669782aff8SPer Forlin if (ret) 12679782aff8SPer Forlin return ret; 1268a45c6cb8SMadhusudhan Chikkature 126926b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1270c5c98927SRussell King if (ret) 1271c5c98927SRussell King return ret; 1272a45c6cb8SMadhusudhan Chikkature 1273c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1274c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1275c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1276c5c98927SRussell King if (!tx) { 1277c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1278c5c98927SRussell King /* FIXME: cleanup */ 1279c5c98927SRussell King return -1; 1280c5c98927SRussell King } 1281c5c98927SRussell King 1282c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1283c5c98927SRussell King tx->callback_param = host; 1284c5c98927SRussell King 1285c5c98927SRussell King /* Does not fail */ 1286c5c98927SRussell King dmaengine_submit(tx); 1287c5c98927SRussell King 128826b88520SRussell King host->dma_ch = 1; 1289c5c98927SRussell King 1290c5c98927SRussell King dma_async_issue_pending(chan); 1291a45c6cb8SMadhusudhan Chikkature 1292a45c6cb8SMadhusudhan Chikkature return 0; 1293a45c6cb8SMadhusudhan Chikkature } 1294a45c6cb8SMadhusudhan Chikkature 129570a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1296e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1297e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1298a45c6cb8SMadhusudhan Chikkature { 1299a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1300a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1301a45c6cb8SMadhusudhan Chikkature 1302a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1303a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1304a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1305a45c6cb8SMadhusudhan Chikkature clkd = 1; 1306a45c6cb8SMadhusudhan Chikkature 1307a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1308e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1309e2bf08d6SAdrian Hunter timeout += timeout_clks; 1310a45c6cb8SMadhusudhan Chikkature if (timeout) { 1311a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1312a45c6cb8SMadhusudhan Chikkature dto += 1; 1313a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1314a45c6cb8SMadhusudhan Chikkature } 1315a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1316a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1317a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1318a45c6cb8SMadhusudhan Chikkature dto += 1; 1319a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1320a45c6cb8SMadhusudhan Chikkature dto -= 13; 1321a45c6cb8SMadhusudhan Chikkature else 1322a45c6cb8SMadhusudhan Chikkature dto = 0; 1323a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1324a45c6cb8SMadhusudhan Chikkature dto = 14; 1325a45c6cb8SMadhusudhan Chikkature } 1326a45c6cb8SMadhusudhan Chikkature 1327a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1328a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1329a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1330a45c6cb8SMadhusudhan Chikkature } 1331a45c6cb8SMadhusudhan Chikkature 1332a45c6cb8SMadhusudhan Chikkature /* 1333a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1334a45c6cb8SMadhusudhan Chikkature */ 1335a45c6cb8SMadhusudhan Chikkature static int 133670a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1337a45c6cb8SMadhusudhan Chikkature { 1338a45c6cb8SMadhusudhan Chikkature int ret; 1339a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1340a45c6cb8SMadhusudhan Chikkature 1341a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1342a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1343e2bf08d6SAdrian Hunter /* 1344e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1345e2bf08d6SAdrian Hunter * busy signal. 1346e2bf08d6SAdrian Hunter */ 1347e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1348e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1349a45c6cb8SMadhusudhan Chikkature return 0; 1350a45c6cb8SMadhusudhan Chikkature } 1351a45c6cb8SMadhusudhan Chikkature 1352a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1353a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1354e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1355a45c6cb8SMadhusudhan Chikkature 1356a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 135770a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1358a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1359a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1360a45c6cb8SMadhusudhan Chikkature return ret; 1361a45c6cb8SMadhusudhan Chikkature } 1362a45c6cb8SMadhusudhan Chikkature } 1363a45c6cb8SMadhusudhan Chikkature return 0; 1364a45c6cb8SMadhusudhan Chikkature } 1365a45c6cb8SMadhusudhan Chikkature 13669782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 13679782aff8SPer Forlin int err) 13689782aff8SPer Forlin { 13699782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 13709782aff8SPer Forlin struct mmc_data *data = mrq->data; 13719782aff8SPer Forlin 137226b88520SRussell King if (host->use_dma && data->host_cookie) { 1373c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1374c5c98927SRussell King 137526b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 13769782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13779782aff8SPer Forlin data->host_cookie = 0; 13789782aff8SPer Forlin } 13799782aff8SPer Forlin } 13809782aff8SPer Forlin 13819782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 13829782aff8SPer Forlin bool is_first_req) 13839782aff8SPer Forlin { 13849782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 13859782aff8SPer Forlin 13869782aff8SPer Forlin if (mrq->data->host_cookie) { 13879782aff8SPer Forlin mrq->data->host_cookie = 0; 13889782aff8SPer Forlin return ; 13899782aff8SPer Forlin } 13909782aff8SPer Forlin 1391c5c98927SRussell King if (host->use_dma) { 1392c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1393c5c98927SRussell King 13949782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 139526b88520SRussell King &host->next_data, c)) 13969782aff8SPer Forlin mrq->data->host_cookie = 0; 13979782aff8SPer Forlin } 1398c5c98927SRussell King } 13999782aff8SPer Forlin 1400a45c6cb8SMadhusudhan Chikkature /* 1401a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1402a45c6cb8SMadhusudhan Chikkature */ 140370a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1404a45c6cb8SMadhusudhan Chikkature { 140570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1406a3f406f8SJarkko Lavinen int err; 1407a45c6cb8SMadhusudhan Chikkature 1408b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1409b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1410b62f6228SAdrian Hunter if (host->protect_card) { 1411b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1412b62f6228SAdrian Hunter /* 1413b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1414b62f6228SAdrian Hunter * state by resetting the command and data state 1415b62f6228SAdrian Hunter * machines. 1416b62f6228SAdrian Hunter */ 1417b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1418b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1419b62f6228SAdrian Hunter host->reqs_blocked += 1; 1420b62f6228SAdrian Hunter } 1421b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1422b62f6228SAdrian Hunter if (req->data) 1423b62f6228SAdrian Hunter req->data->error = -EBADF; 1424b417577dSAdrian Hunter req->cmd->retries = 0; 1425b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1426b62f6228SAdrian Hunter return; 1427b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1428b62f6228SAdrian Hunter host->reqs_blocked = 0; 1429a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1430a45c6cb8SMadhusudhan Chikkature host->mrq = req; 143170a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1432a3f406f8SJarkko Lavinen if (err) { 1433a3f406f8SJarkko Lavinen req->cmd->error = err; 1434a3f406f8SJarkko Lavinen if (req->data) 1435a3f406f8SJarkko Lavinen req->data->error = err; 1436a3f406f8SJarkko Lavinen host->mrq = NULL; 1437a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1438a3f406f8SJarkko Lavinen return; 1439a3f406f8SJarkko Lavinen } 1440a3f406f8SJarkko Lavinen 144170a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1442a45c6cb8SMadhusudhan Chikkature } 1443a45c6cb8SMadhusudhan Chikkature 1444a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 144570a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1446a45c6cb8SMadhusudhan Chikkature { 144770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1448a3621465SAdrian Hunter int do_send_init_stream = 0; 1449a45c6cb8SMadhusudhan Chikkature 1450fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14515e2ea617SAdrian Hunter 1452a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1453a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1454a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1455a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1456a3621465SAdrian Hunter 0, 0); 1457a45c6cb8SMadhusudhan Chikkature break; 1458a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1459a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1460a3621465SAdrian Hunter 1, ios->vdd); 1461a45c6cb8SMadhusudhan Chikkature break; 1462a3621465SAdrian Hunter case MMC_POWER_ON: 1463a3621465SAdrian Hunter do_send_init_stream = 1; 1464a3621465SAdrian Hunter break; 1465a3621465SAdrian Hunter } 1466a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1467a45c6cb8SMadhusudhan Chikkature } 1468a45c6cb8SMadhusudhan Chikkature 1469dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1470dd498effSDenis Karpov 14713796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1472a45c6cb8SMadhusudhan Chikkature 14734621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1474eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1475eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1476eb250826SDavid Brownell */ 1477a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 14781f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 14791f84b71bSRajendra Nayak /* 14801f84b71bSRajendra Nayak * With pbias cell programming missing, this 14811f84b71bSRajendra Nayak * can't be allowed when booting with device 14821f84b71bSRajendra Nayak * tree. 14831f84b71bSRajendra Nayak */ 14844d048f91SRajendra Nayak !host->dev->of_node) { 1485a45c6cb8SMadhusudhan Chikkature /* 1486a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1487a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1488a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1489a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1490a45c6cb8SMadhusudhan Chikkature */ 149170a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1492a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1493a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1494a45c6cb8SMadhusudhan Chikkature } 1495a45c6cb8SMadhusudhan Chikkature } 1496a45c6cb8SMadhusudhan Chikkature 14975934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1498a45c6cb8SMadhusudhan Chikkature 1499a3621465SAdrian Hunter if (do_send_init_stream) 1500a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1501a45c6cb8SMadhusudhan Chikkature 15023796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15035e2ea617SAdrian Hunter 1504fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1505a45c6cb8SMadhusudhan Chikkature } 1506a45c6cb8SMadhusudhan Chikkature 1507a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1508a45c6cb8SMadhusudhan Chikkature { 150970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1510a45c6cb8SMadhusudhan Chikkature 1511191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1512a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1513db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1514a45c6cb8SMadhusudhan Chikkature } 1515a45c6cb8SMadhusudhan Chikkature 1516a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1517a45c6cb8SMadhusudhan Chikkature { 151870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1519a45c6cb8SMadhusudhan Chikkature 1520191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1521a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1522191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1523a45c6cb8SMadhusudhan Chikkature } 1524a45c6cb8SMadhusudhan Chikkature 15254816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15264816858cSGrazvydas Ignotas { 15274816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15284816858cSGrazvydas Ignotas 15294816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15304816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15314816858cSGrazvydas Ignotas } 15324816858cSGrazvydas Ignotas 153370a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15341b331e69SKim Kyuwon { 15351b331e69SKim Kyuwon u32 hctl, capa, value; 15361b331e69SKim Kyuwon 15371b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15384621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15391b331e69SKim Kyuwon hctl = SDVS30; 15401b331e69SKim Kyuwon capa = VS30 | VS18; 15411b331e69SKim Kyuwon } else { 15421b331e69SKim Kyuwon hctl = SDVS18; 15431b331e69SKim Kyuwon capa = VS18; 15441b331e69SKim Kyuwon } 15451b331e69SKim Kyuwon 15461b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15471b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15481b331e69SKim Kyuwon 15491b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15501b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15511b331e69SKim Kyuwon 15521b331e69SKim Kyuwon /* Set SD bus power bit */ 1553e13bb300SAdrian Hunter set_sd_bus_power(host); 15541b331e69SKim Kyuwon } 15551b331e69SKim Kyuwon 155670a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1557dd498effSDenis Karpov { 155870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1559dd498effSDenis Karpov 1560fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1561fa4aa2d4SBalaji T K 1562dd498effSDenis Karpov return 0; 1563dd498effSDenis Karpov } 1564dd498effSDenis Karpov 1565907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1566dd498effSDenis Karpov { 156770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1568dd498effSDenis Karpov 1569fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1570fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1571fa4aa2d4SBalaji T K 1572dd498effSDenis Karpov return 0; 1573dd498effSDenis Karpov } 1574dd498effSDenis Karpov 157570a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 157670a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 157770a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 15789782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 15799782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 158070a3341aSDenis Karpov .request = omap_hsmmc_request, 158170a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1582dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1583dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 15844816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1585dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1586dd498effSDenis Karpov }; 1587dd498effSDenis Karpov 1588d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1589d900f712SDenis Karpov 159070a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1591d900f712SDenis Karpov { 1592d900f712SDenis Karpov struct mmc_host *mmc = s->private; 159370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 159411dd62a7SDenis Karpov int context_loss = 0; 159511dd62a7SDenis Karpov 159670a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 159770a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1598d900f712SDenis Karpov 1599907d2e7cSAdrian Hunter seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", 1600907d2e7cSAdrian Hunter mmc->index, host->context_loss, context_loss); 16015e2ea617SAdrian Hunter 16027a8c2cefSBalaji T K if (host->suspended) { 1603dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1604dd498effSDenis Karpov return 0; 1605dd498effSDenis Karpov } 1606dd498effSDenis Karpov 1607fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1608d900f712SDenis Karpov 1609d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1610d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1611d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1612d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1613d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1614d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1615d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1616d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1617d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1618d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1619d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1620d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16215e2ea617SAdrian Hunter 1622fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1623fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1624dd498effSDenis Karpov 1625d900f712SDenis Karpov return 0; 1626d900f712SDenis Karpov } 1627d900f712SDenis Karpov 162870a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1629d900f712SDenis Karpov { 163070a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1631d900f712SDenis Karpov } 1632d900f712SDenis Karpov 1633d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 163470a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1635d900f712SDenis Karpov .read = seq_read, 1636d900f712SDenis Karpov .llseek = seq_lseek, 1637d900f712SDenis Karpov .release = single_release, 1638d900f712SDenis Karpov }; 1639d900f712SDenis Karpov 164070a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1641d900f712SDenis Karpov { 1642d900f712SDenis Karpov if (mmc->debugfs_root) 1643d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1644d900f712SDenis Karpov mmc, &mmc_regs_fops); 1645d900f712SDenis Karpov } 1646d900f712SDenis Karpov 1647d900f712SDenis Karpov #else 1648d900f712SDenis Karpov 164970a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1650d900f712SDenis Karpov { 1651d900f712SDenis Karpov } 1652d900f712SDenis Karpov 1653d900f712SDenis Karpov #endif 1654d900f712SDenis Karpov 165546856a68SRajendra Nayak #ifdef CONFIG_OF 165646856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 165746856a68SRajendra Nayak 165846856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 165946856a68SRajendra Nayak { 166046856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 166146856a68SRajendra Nayak }, 166246856a68SRajendra Nayak { 166346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 166446856a68SRajendra Nayak }, 166546856a68SRajendra Nayak { 166646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 166746856a68SRajendra Nayak .data = &omap4_reg_offset, 166846856a68SRajendra Nayak }, 166946856a68SRajendra Nayak {}, 1670b6d085f6SChris Ball }; 167146856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 167246856a68SRajendra Nayak 167346856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 167446856a68SRajendra Nayak { 167546856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 167646856a68SRajendra Nayak struct device_node *np = dev->of_node; 167746856a68SRajendra Nayak u32 bus_width; 167846856a68SRajendra Nayak 167946856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 168046856a68SRajendra Nayak if (!pdata) 168146856a68SRajendra Nayak return NULL; /* out of memory */ 168246856a68SRajendra Nayak 168346856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 168446856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 168546856a68SRajendra Nayak 168646856a68SRajendra Nayak /* This driver only supports 1 slot */ 168746856a68SRajendra Nayak pdata->nr_slots = 1; 168846856a68SRajendra Nayak pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0); 168946856a68SRajendra Nayak pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 169046856a68SRajendra Nayak 169146856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 169246856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 169346856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 169446856a68SRajendra Nayak } 16957f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 169646856a68SRajendra Nayak if (bus_width == 4) 169746856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 169846856a68SRajendra Nayak else if (bus_width == 8) 169946856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 170046856a68SRajendra Nayak 170146856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 170246856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 170346856a68SRajendra Nayak 170446856a68SRajendra Nayak return pdata; 170546856a68SRajendra Nayak } 170646856a68SRajendra Nayak #else 170746856a68SRajendra Nayak static inline struct omap_mmc_platform_data 170846856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 170946856a68SRajendra Nayak { 171046856a68SRajendra Nayak return NULL; 171146856a68SRajendra Nayak } 171246856a68SRajendra Nayak #endif 171346856a68SRajendra Nayak 1714efa25fd3SFelipe Balbi static int __devinit omap_hsmmc_probe(struct platform_device *pdev) 1715a45c6cb8SMadhusudhan Chikkature { 1716a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1717a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 171870a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1719a45c6cb8SMadhusudhan Chikkature struct resource *res; 1720db0fefc5SAdrian Hunter int ret, irq; 172146856a68SRajendra Nayak const struct of_device_id *match; 172226b88520SRussell King dma_cap_mask_t mask; 172326b88520SRussell King unsigned tx_req, rx_req; 172446856a68SRajendra Nayak 172546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 172646856a68SRajendra Nayak if (match) { 172746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 172846856a68SRajendra Nayak if (match->data) { 172946856a68SRajendra Nayak u16 *offsetp = match->data; 173046856a68SRajendra Nayak pdata->reg_offset = *offsetp; 173146856a68SRajendra Nayak } 173246856a68SRajendra Nayak } 1733a45c6cb8SMadhusudhan Chikkature 1734a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1735a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1736a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1737a45c6cb8SMadhusudhan Chikkature } 1738a45c6cb8SMadhusudhan Chikkature 1739a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1740a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1741a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1742a45c6cb8SMadhusudhan Chikkature } 1743a45c6cb8SMadhusudhan Chikkature 1744a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1745a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1746a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1747a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1748a45c6cb8SMadhusudhan Chikkature 1749984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1750a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1751a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1752a45c6cb8SMadhusudhan Chikkature 1753db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1754db0fefc5SAdrian Hunter if (ret) 1755db0fefc5SAdrian Hunter goto err; 1756db0fefc5SAdrian Hunter 175770a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1758a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1759a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1760db0fefc5SAdrian Hunter goto err_alloc; 1761a45c6cb8SMadhusudhan Chikkature } 1762a45c6cb8SMadhusudhan Chikkature 1763a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1764a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1765a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1766a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1767a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1768a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1769a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1770a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1771fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1772a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 17736da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 17749782aff8SPer Forlin host->next_data.cookie = 1; 1775a45c6cb8SMadhusudhan Chikkature 1776a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1777a45c6cb8SMadhusudhan Chikkature 177870a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1779dd498effSDenis Karpov 1780e0eb2424SAdrian Hunter /* 1781e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1782e0eb2424SAdrian Hunter * no off state. 1783e0eb2424SAdrian Hunter */ 1784e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1785e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1786e0eb2424SAdrian Hunter 17876b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1788d418ed87SDaniel Mack 1789d418ed87SDaniel Mack if (pdata->max_freq > 0) 1790d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1791d418ed87SDaniel Mack else 17926b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1793a45c6cb8SMadhusudhan Chikkature 17944dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1795a45c6cb8SMadhusudhan Chikkature 17966f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1797a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1798a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1799a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1800a45c6cb8SMadhusudhan Chikkature goto err1; 1801a45c6cb8SMadhusudhan Chikkature } 1802a45c6cb8SMadhusudhan Chikkature 18039b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18049b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18059b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18069b68256cSPaul Walmsley } 1807dd498effSDenis Karpov 1808fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1809fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1810fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1811fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1812a45c6cb8SMadhusudhan Chikkature 181392a3aebfSBalaji T K omap_hsmmc_context_save(host); 181492a3aebfSBalaji T K 1815a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1816a45c6cb8SMadhusudhan Chikkature /* 1817a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1818a45c6cb8SMadhusudhan Chikkature */ 1819cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1820cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n"); 1821cd03d9a8SRajendra Nayak host->dbclk = NULL; 182294c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1823cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1824cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1825cd03d9a8SRajendra Nayak host->dbclk = NULL; 18262bec0893SAdrian Hunter } 1827a45c6cb8SMadhusudhan Chikkature 18280ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18290ccd76d4SJuha Yrjola * as we want. */ 1830a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18310ccd76d4SJuha Yrjola 1832a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1833a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1834a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1835a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1836a45c6cb8SMadhusudhan Chikkature 183713189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 183893caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1839a45c6cb8SMadhusudhan Chikkature 18403a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 18413a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1842a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1843a45c6cb8SMadhusudhan Chikkature 1844191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 184523d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 184623d99bb9SAdrian Hunter 18476fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 18486fdc75deSEliad Peller 184970a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1850a45c6cb8SMadhusudhan Chikkature 1851b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1852b7bf773bSBalaji T K if (!res) { 1853b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 18549c17d08cSKevin Hilman ret = -ENXIO; 1855f3e2f1ddSGrazvydas Ignotas goto err_irq; 1856a45c6cb8SMadhusudhan Chikkature } 185726b88520SRussell King tx_req = res->start; 1858b7bf773bSBalaji T K 1859b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1860b7bf773bSBalaji T K if (!res) { 1861b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 18629c17d08cSKevin Hilman ret = -ENXIO; 1863b7bf773bSBalaji T K goto err_irq; 1864b7bf773bSBalaji T K } 186526b88520SRussell King rx_req = res->start; 1866c5c98927SRussell King 1867c5c98927SRussell King dma_cap_zero(mask); 1868c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 186926b88520SRussell King 187026b88520SRussell King host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req); 1871c5c98927SRussell King if (!host->rx_chan) { 187226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 187304e8c7bcSKevin Hilman ret = -ENXIO; 187426b88520SRussell King goto err_irq; 1875c5c98927SRussell King } 187626b88520SRussell King 187726b88520SRussell King host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req); 1878c5c98927SRussell King if (!host->tx_chan) { 187926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 188004e8c7bcSKevin Hilman ret = -ENXIO; 188126b88520SRussell King goto err_irq; 1882c5c98927SRussell King } 1883a45c6cb8SMadhusudhan Chikkature 1884a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1885d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1886a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1887a45c6cb8SMadhusudhan Chikkature if (ret) { 1888a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1889a45c6cb8SMadhusudhan Chikkature goto err_irq; 1890a45c6cb8SMadhusudhan Chikkature } 1891a45c6cb8SMadhusudhan Chikkature 1892a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1893a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 189470a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 189570a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1896a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1897a45c6cb8SMadhusudhan Chikkature } 1898a45c6cb8SMadhusudhan Chikkature } 1899db0fefc5SAdrian Hunter 1900b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1901db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1902db0fefc5SAdrian Hunter if (ret) 1903db0fefc5SAdrian Hunter goto err_reg; 1904db0fefc5SAdrian Hunter host->use_reg = 1; 1905db0fefc5SAdrian Hunter } 1906db0fefc5SAdrian Hunter 1907b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1908a45c6cb8SMadhusudhan Chikkature 1909a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1910e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19117efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19127efab4f3SNeilBrown NULL, 19137efab4f3SNeilBrown omap_hsmmc_detect, 1914db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1915a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1916a45c6cb8SMadhusudhan Chikkature if (ret) { 1917a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1918a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1919a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1920a45c6cb8SMadhusudhan Chikkature } 192172f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 192272f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1923a45c6cb8SMadhusudhan Chikkature } 1924a45c6cb8SMadhusudhan Chikkature 1925b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1926a45c6cb8SMadhusudhan Chikkature 1927b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1928b62f6228SAdrian Hunter 1929a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1930a45c6cb8SMadhusudhan Chikkature 1931191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1932a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1933a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1934a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1935a45c6cb8SMadhusudhan Chikkature } 1936191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1937a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 1938a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 1939a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1940db0fefc5SAdrian Hunter goto err_slot_name; 1941a45c6cb8SMadhusudhan Chikkature } 1942a45c6cb8SMadhusudhan Chikkature 194370a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 1944fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1945fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1946d900f712SDenis Karpov 1947a45c6cb8SMadhusudhan Chikkature return 0; 1948a45c6cb8SMadhusudhan Chikkature 1949a45c6cb8SMadhusudhan Chikkature err_slot_name: 1950a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 1951a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1952db0fefc5SAdrian Hunter err_irq_cd: 1953db0fefc5SAdrian Hunter if (host->use_reg) 1954db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 1955db0fefc5SAdrian Hunter err_reg: 1956db0fefc5SAdrian Hunter if (host->pdata->cleanup) 1957db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 1958a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 1959a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1960a45c6cb8SMadhusudhan Chikkature err_irq: 1961c5c98927SRussell King if (host->tx_chan) 1962c5c98927SRussell King dma_release_channel(host->tx_chan); 1963c5c98927SRussell King if (host->rx_chan) 1964c5c98927SRussell King dma_release_channel(host->rx_chan); 1965d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 196637f6190dSTony Lindgren pm_runtime_disable(host->dev); 1967a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1968cd03d9a8SRajendra Nayak if (host->dbclk) { 196994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1970a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1971a45c6cb8SMadhusudhan Chikkature } 1972a45c6cb8SMadhusudhan Chikkature err1: 1973a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1974db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 1975a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 1976db0fefc5SAdrian Hunter err_alloc: 1977db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 1978db0fefc5SAdrian Hunter err: 197948b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 198048b332f9SRussell King if (res) 1981984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 1982a45c6cb8SMadhusudhan Chikkature return ret; 1983a45c6cb8SMadhusudhan Chikkature } 1984a45c6cb8SMadhusudhan Chikkature 1985efa25fd3SFelipe Balbi static int __devexit omap_hsmmc_remove(struct platform_device *pdev) 1986a45c6cb8SMadhusudhan Chikkature { 198770a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 1988a45c6cb8SMadhusudhan Chikkature struct resource *res; 1989a45c6cb8SMadhusudhan Chikkature 1990fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1991a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 1992db0fefc5SAdrian Hunter if (host->use_reg) 1993db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 1994a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 1995a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 1996a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1997a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 1998a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1999a45c6cb8SMadhusudhan Chikkature 2000c5c98927SRussell King if (host->tx_chan) 2001c5c98927SRussell King dma_release_channel(host->tx_chan); 2002c5c98927SRussell King if (host->rx_chan) 2003c5c98927SRussell King dma_release_channel(host->rx_chan); 2004c5c98927SRussell King 2005fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2006fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2007a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2008cd03d9a8SRajendra Nayak if (host->dbclk) { 200994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2010a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2011a45c6cb8SMadhusudhan Chikkature } 2012a45c6cb8SMadhusudhan Chikkature 2013a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2014a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2015db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2016a45c6cb8SMadhusudhan Chikkature 2017a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2018a45c6cb8SMadhusudhan Chikkature if (res) 2019984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2020a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2021a45c6cb8SMadhusudhan Chikkature 2022a45c6cb8SMadhusudhan Chikkature return 0; 2023a45c6cb8SMadhusudhan Chikkature } 2024a45c6cb8SMadhusudhan Chikkature 2025a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2026a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2027a45c6cb8SMadhusudhan Chikkature { 2028a45c6cb8SMadhusudhan Chikkature int ret = 0; 2029927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2030927ce944SFelipe Balbi 2031927ce944SFelipe Balbi if (!host) 2032927ce944SFelipe Balbi return 0; 2033a45c6cb8SMadhusudhan Chikkature 2034a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2035a45c6cb8SMadhusudhan Chikkature return 0; 2036a45c6cb8SMadhusudhan Chikkature 2037fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2038a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2039a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2040927ce944SFelipe Balbi ret = host->pdata->suspend(dev, host->slot_id); 2041a6b2240dSAdrian Hunter if (ret) { 2042927ce944SFelipe Balbi dev_dbg(dev, "Unable to handle MMC board" 2043a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2044a6b2240dSAdrian Hunter host->suspended = 0; 2045a6b2240dSAdrian Hunter return ret; 2046a45c6cb8SMadhusudhan Chikkature } 2047a6b2240dSAdrian Hunter } 20481a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2049fa4aa2d4SBalaji T K 205031f9d463SEliad Peller if (ret) { 2051a6b2240dSAdrian Hunter host->suspended = 0; 2052a6b2240dSAdrian Hunter if (host->pdata->resume) { 2053927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2054a6b2240dSAdrian Hunter if (ret) 2055927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2056a6b2240dSAdrian Hunter } 205731f9d463SEliad Peller goto err; 2058a6b2240dSAdrian Hunter } 205931f9d463SEliad Peller 206031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 206131f9d463SEliad Peller omap_hsmmc_disable_irq(host); 206231f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 206331f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 206431f9d463SEliad Peller } 2065927ce944SFelipe Balbi 2066cd03d9a8SRajendra Nayak if (host->dbclk) 206794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 206831f9d463SEliad Peller err: 2069fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2070a45c6cb8SMadhusudhan Chikkature return ret; 2071a45c6cb8SMadhusudhan Chikkature } 2072a45c6cb8SMadhusudhan Chikkature 2073a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2074a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2075a45c6cb8SMadhusudhan Chikkature { 2076a45c6cb8SMadhusudhan Chikkature int ret = 0; 2077927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2078927ce944SFelipe Balbi 2079927ce944SFelipe Balbi if (!host) 2080927ce944SFelipe Balbi return 0; 2081a45c6cb8SMadhusudhan Chikkature 2082a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2083a45c6cb8SMadhusudhan Chikkature return 0; 2084a45c6cb8SMadhusudhan Chikkature 2085fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 208611dd62a7SDenis Karpov 2087cd03d9a8SRajendra Nayak if (host->dbclk) 208894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 20892bec0893SAdrian Hunter 209031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 209170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 20921b331e69SKim Kyuwon 2093a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2094927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2095a45c6cb8SMadhusudhan Chikkature if (ret) 2096927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2097a45c6cb8SMadhusudhan Chikkature } 2098a45c6cb8SMadhusudhan Chikkature 2099b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2100b62f6228SAdrian Hunter 2101a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2102a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2103a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2104a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2105fa4aa2d4SBalaji T K 2106fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2107fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2108a45c6cb8SMadhusudhan Chikkature 2109a45c6cb8SMadhusudhan Chikkature return ret; 2110a45c6cb8SMadhusudhan Chikkature 2111a45c6cb8SMadhusudhan Chikkature } 2112a45c6cb8SMadhusudhan Chikkature 2113a45c6cb8SMadhusudhan Chikkature #else 211470a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 211570a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2116a45c6cb8SMadhusudhan Chikkature #endif 2117a45c6cb8SMadhusudhan Chikkature 2118fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2119fa4aa2d4SBalaji T K { 2120fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2121fa4aa2d4SBalaji T K 2122fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2123fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2124927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2125fa4aa2d4SBalaji T K 2126fa4aa2d4SBalaji T K return 0; 2127fa4aa2d4SBalaji T K } 2128fa4aa2d4SBalaji T K 2129fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2130fa4aa2d4SBalaji T K { 2131fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2132fa4aa2d4SBalaji T K 2133fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2134fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2135927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2136fa4aa2d4SBalaji T K 2137fa4aa2d4SBalaji T K return 0; 2138fa4aa2d4SBalaji T K } 2139fa4aa2d4SBalaji T K 2140a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 214170a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 214270a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2143fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2144fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2145a791daa1SKevin Hilman }; 2146a791daa1SKevin Hilman 2147a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2148efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 2149efa25fd3SFelipe Balbi .remove = __devexit_p(omap_hsmmc_remove), 2150a45c6cb8SMadhusudhan Chikkature .driver = { 2151a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2152a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2153a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 215446856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2155a45c6cb8SMadhusudhan Chikkature }, 2156a45c6cb8SMadhusudhan Chikkature }; 2157a45c6cb8SMadhusudhan Chikkature 2158b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2159a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2160a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2161a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2162a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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