1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 3246856a68SRajendra Nayak #include <linux/of_gpio.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 343451c067SRussell King #include <linux/omap-dma.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 39db0fefc5SAdrian Hunter #include <linux/gpio.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4368f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 44a45c6cb8SMadhusudhan Chikkature 45a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65cd587096SHebbar, Gururaja #define HSS (1 << 21) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 79a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 80a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 81a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 82a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 83a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 84a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 85a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 86a7e96879SVenkatraman S #define DMAE 0x1 87a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 88a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 89a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 90cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9103b5d924SBalaji T K #define DDR (1 << 19) 9273153010SJarkko Lavinen #define DW8 (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define OD 0x1 94a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 95a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 96a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 97a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 98a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 100a45c6cb8SMadhusudhan Chikkature 101a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 102a7e96879SVenkatraman S #define CC_EN (1 << 0) 103a7e96879SVenkatraman S #define TC_EN (1 << 1) 104a7e96879SVenkatraman S #define BWR_EN (1 << 4) 105a7e96879SVenkatraman S #define BRR_EN (1 << 5) 106a7e96879SVenkatraman S #define ERR_EN (1 << 15) 107a7e96879SVenkatraman S #define CTO_EN (1 << 16) 108a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 109a7e96879SVenkatraman S #define CEB_EN (1 << 18) 110a7e96879SVenkatraman S #define CIE_EN (1 << 19) 111a7e96879SVenkatraman S #define DTO_EN (1 << 20) 112a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 113a7e96879SVenkatraman S #define DEB_EN (1 << 22) 114a7e96879SVenkatraman S #define CERR_EN (1 << 28) 115a7e96879SVenkatraman S #define BADA_EN (1 << 29) 116a7e96879SVenkatraman S 117a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 118a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 119a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 120a7e96879SVenkatraman S 121fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1221e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1231e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1246b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1256b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1260005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 127a45c6cb8SMadhusudhan Chikkature 128e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 129e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 130e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 131e99448ffSBalaji T K 132a45c6cb8SMadhusudhan Chikkature /* 133a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 134a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 135a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 136a45c6cb8SMadhusudhan Chikkature */ 137a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 138a45c6cb8SMadhusudhan Chikkature 139a45c6cb8SMadhusudhan Chikkature /* 140a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 141a45c6cb8SMadhusudhan Chikkature */ 142a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 143a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 144a45c6cb8SMadhusudhan Chikkature 145a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 146a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 147a45c6cb8SMadhusudhan Chikkature 1489782aff8SPer Forlin struct omap_hsmmc_next { 1499782aff8SPer Forlin unsigned int dma_len; 1509782aff8SPer Forlin s32 cookie; 1519782aff8SPer Forlin }; 1529782aff8SPer Forlin 15370a3341aSDenis Karpov struct omap_hsmmc_host { 154a45c6cb8SMadhusudhan Chikkature struct device *dev; 155a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 156a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 157a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 158a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 159a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 160a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 161db0fefc5SAdrian Hunter /* 162db0fefc5SAdrian Hunter * vcc == configured supply 163db0fefc5SAdrian Hunter * vcc_aux == optional 164db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 165db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 166db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 167db0fefc5SAdrian Hunter */ 168db0fefc5SAdrian Hunter struct regulator *vcc; 169db0fefc5SAdrian Hunter struct regulator *vcc_aux; 170e99448ffSBalaji T K struct regulator *pbias; 171e99448ffSBalaji T K bool pbias_enabled; 172a45c6cb8SMadhusudhan Chikkature void __iomem *base; 173a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1744dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 175a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1760ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 177a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 178a3621465SAdrian Hunter unsigned char power_mode; 179a45c6cb8SMadhusudhan Chikkature int suspended; 1800a82e06eSTony Lindgren u32 con; 1810a82e06eSTony Lindgren u32 hctl; 1820a82e06eSTony Lindgren u32 sysctl; 1830a82e06eSTony Lindgren u32 capa; 184a45c6cb8SMadhusudhan Chikkature int irq; 185a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 186c5c98927SRussell King struct dma_chan *tx_chan; 187c5c98927SRussell King struct dma_chan *rx_chan; 188a45c6cb8SMadhusudhan Chikkature int slot_id; 1894a694dc9SAdrian Hunter int response_busy; 19011dd62a7SDenis Karpov int context_loss; 191b62f6228SAdrian Hunter int protect_card; 192b62f6228SAdrian Hunter int reqs_blocked; 193db0fefc5SAdrian Hunter int use_reg; 194b417577dSAdrian Hunter int req_in_progress; 1956e3076c2SBalaji T K unsigned long clk_rate; 1969782aff8SPer Forlin struct omap_hsmmc_next next_data; 197a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 198a45c6cb8SMadhusudhan Chikkature }; 199a45c6cb8SMadhusudhan Chikkature 20059445b10SNishanth Menon struct omap_mmc_of_data { 20159445b10SNishanth Menon u32 reg_offset; 20259445b10SNishanth Menon u8 controller_flags; 20359445b10SNishanth Menon }; 20459445b10SNishanth Menon 205db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 206db0fefc5SAdrian Hunter { 2079ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2089ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 209db0fefc5SAdrian Hunter 210db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 211db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 212db0fefc5SAdrian Hunter } 213db0fefc5SAdrian Hunter 214db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 215db0fefc5SAdrian Hunter { 2169ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2179ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 218db0fefc5SAdrian Hunter 219db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 220db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 221db0fefc5SAdrian Hunter } 222db0fefc5SAdrian Hunter 223db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 224db0fefc5SAdrian Hunter { 2259ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2269ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 227db0fefc5SAdrian Hunter 228db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 229db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 230db0fefc5SAdrian Hunter } 231db0fefc5SAdrian Hunter 232db0fefc5SAdrian Hunter #ifdef CONFIG_PM 233db0fefc5SAdrian Hunter 234db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 235db0fefc5SAdrian Hunter { 2369ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2379ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 238db0fefc5SAdrian Hunter 239db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 240db0fefc5SAdrian Hunter return 0; 241db0fefc5SAdrian Hunter } 242db0fefc5SAdrian Hunter 243db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 244db0fefc5SAdrian Hunter { 2459ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2469ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 247db0fefc5SAdrian Hunter 248db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 249db0fefc5SAdrian Hunter return 0; 250db0fefc5SAdrian Hunter } 251db0fefc5SAdrian Hunter 252db0fefc5SAdrian Hunter #else 253db0fefc5SAdrian Hunter 254db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 255db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 256db0fefc5SAdrian Hunter 257db0fefc5SAdrian Hunter #endif 258db0fefc5SAdrian Hunter 259b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 260b702b106SAdrian Hunter 26169b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 262db0fefc5SAdrian Hunter int vdd) 263db0fefc5SAdrian Hunter { 264db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 265db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 266db0fefc5SAdrian Hunter int ret = 0; 267db0fefc5SAdrian Hunter 268db0fefc5SAdrian Hunter /* 269db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 270db0fefc5SAdrian Hunter * voltage always-on regulator. 271db0fefc5SAdrian Hunter */ 272db0fefc5SAdrian Hunter if (!host->vcc) 273db0fefc5SAdrian Hunter return 0; 274db0fefc5SAdrian Hunter 275db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 276db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 277db0fefc5SAdrian Hunter 278e99448ffSBalaji T K if (host->pbias) { 279e99448ffSBalaji T K if (host->pbias_enabled == 1) { 280e99448ffSBalaji T K ret = regulator_disable(host->pbias); 281e99448ffSBalaji T K if (!ret) 282e99448ffSBalaji T K host->pbias_enabled = 0; 283e99448ffSBalaji T K } 284e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 285e99448ffSBalaji T K } 286e99448ffSBalaji T K 287db0fefc5SAdrian Hunter /* 288db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 289db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 290db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 291db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 292db0fefc5SAdrian Hunter * 293db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 294db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 295db0fefc5SAdrian Hunter * 296db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 297db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 298db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 299db0fefc5SAdrian Hunter */ 300db0fefc5SAdrian Hunter if (power_on) { 301987fd49bSBalaji T K if (host->vcc) 30299fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 303db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 304db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 305db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 306987fd49bSBalaji T K if (ret < 0 && host->vcc) 30799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30899fc5131SLinus Walleij host->vcc, 0); 309db0fefc5SAdrian Hunter } 310db0fefc5SAdrian Hunter } else { 31199fc5131SLinus Walleij /* Shut down the rail */ 3126da20c89SAdrian Hunter if (host->vcc_aux) 313db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 314987fd49bSBalaji T K if (host->vcc) { 31599fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31799fc5131SLinus Walleij host->vcc, 0); 31899fc5131SLinus Walleij } 319db0fefc5SAdrian Hunter } 320db0fefc5SAdrian Hunter 321e99448ffSBalaji T K if (host->pbias) { 322e99448ffSBalaji T K if (vdd <= VDD_165_195) 323e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 324e99448ffSBalaji T K VDD_1V8); 325e99448ffSBalaji T K else 326e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 327e99448ffSBalaji T K VDD_3V0); 328e99448ffSBalaji T K if (ret < 0) 329e99448ffSBalaji T K goto error_set_power; 330e99448ffSBalaji T K 331e99448ffSBalaji T K if (host->pbias_enabled == 0) { 332e99448ffSBalaji T K ret = regulator_enable(host->pbias); 333e99448ffSBalaji T K if (!ret) 334e99448ffSBalaji T K host->pbias_enabled = 1; 335e99448ffSBalaji T K } 336e99448ffSBalaji T K } 337e99448ffSBalaji T K 338db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 339db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 340db0fefc5SAdrian Hunter 341e99448ffSBalaji T K error_set_power: 342db0fefc5SAdrian Hunter return ret; 343db0fefc5SAdrian Hunter } 344db0fefc5SAdrian Hunter 345db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 346db0fefc5SAdrian Hunter { 347db0fefc5SAdrian Hunter struct regulator *reg; 34864be9782Skishore kadiyala int ocr_value = 0; 349db0fefc5SAdrian Hunter 350f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 351db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 352987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 353987fd49bSBalaji T K PTR_ERR(reg)); 3541fdc90fbSNeilBrown return PTR_ERR(reg); 355db0fefc5SAdrian Hunter } else { 356db0fefc5SAdrian Hunter host->vcc = reg; 35764be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 35864be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 35964be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 36064be9782Skishore kadiyala } else { 36164be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3622cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 363e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 36464be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 36564be9782Skishore kadiyala return -EINVAL; 36664be9782Skishore kadiyala } 36764be9782Skishore kadiyala } 368987fd49bSBalaji T K } 369987fd49bSBalaji T K mmc_slot(host).set_power = omap_hsmmc_set_power; 370db0fefc5SAdrian Hunter 371db0fefc5SAdrian Hunter /* Allow an aux regulator */ 372f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 373db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 374db0fefc5SAdrian Hunter 375e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 376e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 377e99448ffSBalaji T K 378b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 379b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 380b1c1df7aSBalaji T K return 0; 381db0fefc5SAdrian Hunter /* 382987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 383987fd49bSBalaji T K * to increase usecount and then disable it. 384db0fefc5SAdrian Hunter */ 385987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 386e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 387e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 388e840ce13SAdrian Hunter 389987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 390987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 391db0fefc5SAdrian Hunter } 392db0fefc5SAdrian Hunter 393db0fefc5SAdrian Hunter return 0; 394db0fefc5SAdrian Hunter } 395db0fefc5SAdrian Hunter 396db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 397db0fefc5SAdrian Hunter { 398db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 399db0fefc5SAdrian Hunter } 400db0fefc5SAdrian Hunter 401b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 402b702b106SAdrian Hunter { 403b702b106SAdrian Hunter return 1; 404b702b106SAdrian Hunter } 405b702b106SAdrian Hunter 406b702b106SAdrian Hunter #else 407b702b106SAdrian Hunter 408b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 409b702b106SAdrian Hunter { 410b702b106SAdrian Hunter return -EINVAL; 411b702b106SAdrian Hunter } 412b702b106SAdrian Hunter 413b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 414b702b106SAdrian Hunter { 415b702b106SAdrian Hunter } 416b702b106SAdrian Hunter 417b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 418b702b106SAdrian Hunter { 419b702b106SAdrian Hunter return 0; 420b702b106SAdrian Hunter } 421b702b106SAdrian Hunter 422b702b106SAdrian Hunter #endif 423b702b106SAdrian Hunter 424b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 425b702b106SAdrian Hunter { 426b702b106SAdrian Hunter int ret; 427b702b106SAdrian Hunter 428b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 429b702b106SAdrian Hunter if (pdata->slots[0].cover) 430b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 431b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 432b702b106SAdrian Hunter else 433b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 434b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 435b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 436b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 437b702b106SAdrian Hunter if (ret) 438b702b106SAdrian Hunter return ret; 439b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 440b702b106SAdrian Hunter if (ret) 441b702b106SAdrian Hunter goto err_free_sp; 442b702b106SAdrian Hunter } else 443b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 444b702b106SAdrian Hunter 445b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 446b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 447b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 448b702b106SAdrian Hunter if (ret) 449b702b106SAdrian Hunter goto err_free_cd; 450b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 451b702b106SAdrian Hunter if (ret) 452b702b106SAdrian Hunter goto err_free_wp; 453b702b106SAdrian Hunter } else 454b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 455b702b106SAdrian Hunter 456b702b106SAdrian Hunter return 0; 457b702b106SAdrian Hunter 458b702b106SAdrian Hunter err_free_wp: 459b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 460b702b106SAdrian Hunter err_free_cd: 461b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 462b702b106SAdrian Hunter err_free_sp: 463b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 464b702b106SAdrian Hunter return ret; 465b702b106SAdrian Hunter } 466b702b106SAdrian Hunter 467b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 468b702b106SAdrian Hunter { 469b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 470b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 471b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 472b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 473b702b106SAdrian Hunter } 474b702b106SAdrian Hunter 475a45c6cb8SMadhusudhan Chikkature /* 476e0c7f99bSAndy Shevchenko * Start clock to the card 477e0c7f99bSAndy Shevchenko */ 478e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 479e0c7f99bSAndy Shevchenko { 480e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 481e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 482e0c7f99bSAndy Shevchenko } 483e0c7f99bSAndy Shevchenko 484e0c7f99bSAndy Shevchenko /* 485a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 486a45c6cb8SMadhusudhan Chikkature */ 48770a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 488a45c6cb8SMadhusudhan Chikkature { 489a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 490a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 491a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4927122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 493a45c6cb8SMadhusudhan Chikkature } 494a45c6cb8SMadhusudhan Chikkature 49593caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 49693caf8e6SAdrian Hunter struct mmc_command *cmd) 497b417577dSAdrian Hunter { 498b417577dSAdrian Hunter unsigned int irq_mask; 499b417577dSAdrian Hunter 500b417577dSAdrian Hunter if (host->use_dma) 501a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 502b417577dSAdrian Hunter else 503b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 504b417577dSAdrian Hunter 50593caf8e6SAdrian Hunter /* Disable timeout for erases */ 50693caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 507a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 50893caf8e6SAdrian Hunter 509b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 510b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 511b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 512b417577dSAdrian Hunter } 513b417577dSAdrian Hunter 514b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 515b417577dSAdrian Hunter { 516b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 517b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 518b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 519b417577dSAdrian Hunter } 520b417577dSAdrian Hunter 521ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 522d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 523ac330f44SAndy Shevchenko { 524ac330f44SAndy Shevchenko u16 dsor = 0; 525ac330f44SAndy Shevchenko 526ac330f44SAndy Shevchenko if (ios->clock) { 527d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 528ed164182SBalaji T K if (dsor > CLKD_MAX) 529ed164182SBalaji T K dsor = CLKD_MAX; 530ac330f44SAndy Shevchenko } 531ac330f44SAndy Shevchenko 532ac330f44SAndy Shevchenko return dsor; 533ac330f44SAndy Shevchenko } 534ac330f44SAndy Shevchenko 5355934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5365934df2fSAndy Shevchenko { 5375934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5385934df2fSAndy Shevchenko unsigned long regval; 5395934df2fSAndy Shevchenko unsigned long timeout; 540cd587096SHebbar, Gururaja unsigned long clkdiv; 5415934df2fSAndy Shevchenko 5428986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5435934df2fSAndy Shevchenko 5445934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5455934df2fSAndy Shevchenko 5465934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5475934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 548cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 549cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5505934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5515934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5525934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5535934df2fSAndy Shevchenko 5545934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5555934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5565934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5575934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5585934df2fSAndy Shevchenko cpu_relax(); 5595934df2fSAndy Shevchenko 560cd587096SHebbar, Gururaja /* 561cd587096SHebbar, Gururaja * Enable High-Speed Support 562cd587096SHebbar, Gururaja * Pre-Requisites 563cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 564cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 565cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 566cd587096SHebbar, Gururaja * in capabilities register 567cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 568cd587096SHebbar, Gururaja */ 569cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 570cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 571cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 572cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 573cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 574cd587096SHebbar, Gururaja regval |= HSPE; 575cd587096SHebbar, Gururaja else 576cd587096SHebbar, Gururaja regval &= ~HSPE; 577cd587096SHebbar, Gururaja 578cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 579cd587096SHebbar, Gururaja } 580cd587096SHebbar, Gururaja 5815934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5825934df2fSAndy Shevchenko } 5835934df2fSAndy Shevchenko 5843796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5853796fb8aSAndy Shevchenko { 5863796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5873796fb8aSAndy Shevchenko u32 con; 5883796fb8aSAndy Shevchenko 5893796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 59003b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 59103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 59203b5d924SBalaji T K else 59303b5d924SBalaji T K con &= ~DDR; 5943796fb8aSAndy Shevchenko switch (ios->bus_width) { 5953796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5973796fb8aSAndy Shevchenko break; 5983796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5993796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6003796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6013796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6023796fb8aSAndy Shevchenko break; 6033796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6043796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6053796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6063796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6073796fb8aSAndy Shevchenko break; 6083796fb8aSAndy Shevchenko } 6093796fb8aSAndy Shevchenko } 6103796fb8aSAndy Shevchenko 6113796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6123796fb8aSAndy Shevchenko { 6133796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6143796fb8aSAndy Shevchenko u32 con; 6153796fb8aSAndy Shevchenko 6163796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6173796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6183796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6193796fb8aSAndy Shevchenko else 6203796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6213796fb8aSAndy Shevchenko } 6223796fb8aSAndy Shevchenko 62311dd62a7SDenis Karpov #ifdef CONFIG_PM 62411dd62a7SDenis Karpov 62511dd62a7SDenis Karpov /* 62611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 62711dd62a7SDenis Karpov * power state change. 62811dd62a7SDenis Karpov */ 62970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 63011dd62a7SDenis Karpov { 63111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6323796fb8aSAndy Shevchenko u32 hctl, capa; 63311dd62a7SDenis Karpov unsigned long timeout; 63411dd62a7SDenis Karpov 6350a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6360a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6370a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6380a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6390a82e06eSTony Lindgren return 0; 6400a82e06eSTony Lindgren 6410a82e06eSTony Lindgren host->context_loss++; 6420a82e06eSTony Lindgren 643c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 64411dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 64511dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 64611dd62a7SDenis Karpov hctl = SDVS18; 64711dd62a7SDenis Karpov else 64811dd62a7SDenis Karpov hctl = SDVS30; 64911dd62a7SDenis Karpov capa = VS30 | VS18; 65011dd62a7SDenis Karpov } else { 65111dd62a7SDenis Karpov hctl = SDVS18; 65211dd62a7SDenis Karpov capa = VS18; 65311dd62a7SDenis Karpov } 65411dd62a7SDenis Karpov 65511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 65611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 65711dd62a7SDenis Karpov 65811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 65911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 66011dd62a7SDenis Karpov 66111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 66311dd62a7SDenis Karpov 66411dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 66511dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 66611dd62a7SDenis Karpov && time_before(jiffies, timeout)) 66711dd62a7SDenis Karpov ; 66811dd62a7SDenis Karpov 669b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 67011dd62a7SDenis Karpov 67111dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 67211dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 67311dd62a7SDenis Karpov goto out; 67411dd62a7SDenis Karpov 6753796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 67611dd62a7SDenis Karpov 6775934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 67811dd62a7SDenis Karpov 6793796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6803796fb8aSAndy Shevchenko 68111dd62a7SDenis Karpov out: 6820a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6830a82e06eSTony Lindgren host->context_loss); 68411dd62a7SDenis Karpov return 0; 68511dd62a7SDenis Karpov } 68611dd62a7SDenis Karpov 68711dd62a7SDenis Karpov /* 68811dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 68911dd62a7SDenis Karpov */ 69070a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 69111dd62a7SDenis Karpov { 6920a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6930a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6940a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6950a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 69611dd62a7SDenis Karpov } 69711dd62a7SDenis Karpov 69811dd62a7SDenis Karpov #else 69911dd62a7SDenis Karpov 70070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70111dd62a7SDenis Karpov { 70211dd62a7SDenis Karpov return 0; 70311dd62a7SDenis Karpov } 70411dd62a7SDenis Karpov 70570a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70611dd62a7SDenis Karpov { 70711dd62a7SDenis Karpov } 70811dd62a7SDenis Karpov 70911dd62a7SDenis Karpov #endif 71011dd62a7SDenis Karpov 711a45c6cb8SMadhusudhan Chikkature /* 712a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 713a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 714a45c6cb8SMadhusudhan Chikkature */ 71570a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 716a45c6cb8SMadhusudhan Chikkature { 717a45c6cb8SMadhusudhan Chikkature int reg = 0; 718a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 719a45c6cb8SMadhusudhan Chikkature 720b62f6228SAdrian Hunter if (host->protect_card) 721b62f6228SAdrian Hunter return; 722b62f6228SAdrian Hunter 723a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 724b417577dSAdrian Hunter 725b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 726a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 727a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 728a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 729a45c6cb8SMadhusudhan Chikkature 730a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 731a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 732a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 733a45c6cb8SMadhusudhan Chikkature 734a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 735a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 736c653a6d4SAdrian Hunter 737c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 738c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 739c653a6d4SAdrian Hunter 740a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 741a45c6cb8SMadhusudhan Chikkature } 742a45c6cb8SMadhusudhan Chikkature 743a45c6cb8SMadhusudhan Chikkature static inline 74470a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 745a45c6cb8SMadhusudhan Chikkature { 746a45c6cb8SMadhusudhan Chikkature int r = 1; 747a45c6cb8SMadhusudhan Chikkature 748191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 749191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 750a45c6cb8SMadhusudhan Chikkature return r; 751a45c6cb8SMadhusudhan Chikkature } 752a45c6cb8SMadhusudhan Chikkature 753a45c6cb8SMadhusudhan Chikkature static ssize_t 75470a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 755a45c6cb8SMadhusudhan Chikkature char *buf) 756a45c6cb8SMadhusudhan Chikkature { 757a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 75870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 759a45c6cb8SMadhusudhan Chikkature 76070a3341aSDenis Karpov return sprintf(buf, "%s\n", 76170a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 762a45c6cb8SMadhusudhan Chikkature } 763a45c6cb8SMadhusudhan Chikkature 76470a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 765a45c6cb8SMadhusudhan Chikkature 766a45c6cb8SMadhusudhan Chikkature static ssize_t 76770a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 768a45c6cb8SMadhusudhan Chikkature char *buf) 769a45c6cb8SMadhusudhan Chikkature { 770a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 77170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 772a45c6cb8SMadhusudhan Chikkature 773191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 774a45c6cb8SMadhusudhan Chikkature } 775a45c6cb8SMadhusudhan Chikkature 77670a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 777a45c6cb8SMadhusudhan Chikkature 778a45c6cb8SMadhusudhan Chikkature /* 779a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 780a45c6cb8SMadhusudhan Chikkature */ 781a45c6cb8SMadhusudhan Chikkature static void 78270a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 783a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 784a45c6cb8SMadhusudhan Chikkature { 785a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 786a45c6cb8SMadhusudhan Chikkature 7878986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 788a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 789a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 790a45c6cb8SMadhusudhan Chikkature 79193caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 792a45c6cb8SMadhusudhan Chikkature 7934a694dc9SAdrian Hunter host->response_busy = 0; 794a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 795a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 796a45c6cb8SMadhusudhan Chikkature resptype = 1; 7974a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7984a694dc9SAdrian Hunter resptype = 3; 7994a694dc9SAdrian Hunter host->response_busy = 1; 8004a694dc9SAdrian Hunter } else 801a45c6cb8SMadhusudhan Chikkature resptype = 2; 802a45c6cb8SMadhusudhan Chikkature } 803a45c6cb8SMadhusudhan Chikkature 804a45c6cb8SMadhusudhan Chikkature /* 805a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 806a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 807a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 808a45c6cb8SMadhusudhan Chikkature */ 809a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 810a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 811a45c6cb8SMadhusudhan Chikkature 812a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 813a45c6cb8SMadhusudhan Chikkature 814a45c6cb8SMadhusudhan Chikkature if (data) { 815a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 816a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 817a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 818a45c6cb8SMadhusudhan Chikkature else 819a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 820a45c6cb8SMadhusudhan Chikkature } 821a45c6cb8SMadhusudhan Chikkature 822a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 823a7e96879SVenkatraman S cmdreg |= DMAE; 824a45c6cb8SMadhusudhan Chikkature 825b417577dSAdrian Hunter host->req_in_progress = 1; 8264dffd7a2SAdrian Hunter 827a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 828a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 829a45c6cb8SMadhusudhan Chikkature } 830a45c6cb8SMadhusudhan Chikkature 8310ccd76d4SJuha Yrjola static int 83270a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8330ccd76d4SJuha Yrjola { 8340ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8350ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8360ccd76d4SJuha Yrjola else 8370ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8380ccd76d4SJuha Yrjola } 8390ccd76d4SJuha Yrjola 840c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 841c5c98927SRussell King struct mmc_data *data) 842c5c98927SRussell King { 843c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 844c5c98927SRussell King } 845c5c98927SRussell King 846b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 847b417577dSAdrian Hunter { 848b417577dSAdrian Hunter int dma_ch; 84931463b14SVenkatraman S unsigned long flags; 850b417577dSAdrian Hunter 85131463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 852b417577dSAdrian Hunter host->req_in_progress = 0; 853b417577dSAdrian Hunter dma_ch = host->dma_ch; 85431463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 855b417577dSAdrian Hunter 856b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 857b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 858b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 859b417577dSAdrian Hunter return; 860b417577dSAdrian Hunter host->mrq = NULL; 861b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 862b417577dSAdrian Hunter } 863b417577dSAdrian Hunter 864a45c6cb8SMadhusudhan Chikkature /* 865a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 866a45c6cb8SMadhusudhan Chikkature */ 867a45c6cb8SMadhusudhan Chikkature static void 86870a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 869a45c6cb8SMadhusudhan Chikkature { 8704a694dc9SAdrian Hunter if (!data) { 8714a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8724a694dc9SAdrian Hunter 87323050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 87423050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 87523050103SAdrian Hunter host->response_busy) { 87623050103SAdrian Hunter host->response_busy = 0; 87723050103SAdrian Hunter return; 87823050103SAdrian Hunter } 87923050103SAdrian Hunter 880b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8814a694dc9SAdrian Hunter return; 8824a694dc9SAdrian Hunter } 8834a694dc9SAdrian Hunter 884a45c6cb8SMadhusudhan Chikkature host->data = NULL; 885a45c6cb8SMadhusudhan Chikkature 886a45c6cb8SMadhusudhan Chikkature if (!data->error) 887a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 888a45c6cb8SMadhusudhan Chikkature else 889a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 890a45c6cb8SMadhusudhan Chikkature 891fe852273SMing Lei if (!data->stop) { 892dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 893fe852273SMing Lei return; 894dba3c29eSBalaji T K } 895fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 896a45c6cb8SMadhusudhan Chikkature } 897a45c6cb8SMadhusudhan Chikkature 898a45c6cb8SMadhusudhan Chikkature /* 899a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 900a45c6cb8SMadhusudhan Chikkature */ 901a45c6cb8SMadhusudhan Chikkature static void 90270a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 903a45c6cb8SMadhusudhan Chikkature { 904a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 905a45c6cb8SMadhusudhan Chikkature 906a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 907a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 908a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 909a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 910a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 911a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 912a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 913a45c6cb8SMadhusudhan Chikkature } else { 914a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 915a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 916a45c6cb8SMadhusudhan Chikkature } 917a45c6cb8SMadhusudhan Chikkature } 918b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 919d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 920a45c6cb8SMadhusudhan Chikkature } 921a45c6cb8SMadhusudhan Chikkature 922a45c6cb8SMadhusudhan Chikkature /* 923a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 924a45c6cb8SMadhusudhan Chikkature */ 92570a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 926a45c6cb8SMadhusudhan Chikkature { 927b417577dSAdrian Hunter int dma_ch; 92831463b14SVenkatraman S unsigned long flags; 929b417577dSAdrian Hunter 93082788ff5SJarkko Lavinen host->data->error = errno; 931a45c6cb8SMadhusudhan Chikkature 93231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 933b417577dSAdrian Hunter dma_ch = host->dma_ch; 934b417577dSAdrian Hunter host->dma_ch = -1; 93531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 936b417577dSAdrian Hunter 937b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 938c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 939c5c98927SRussell King 940c5c98927SRussell King dmaengine_terminate_all(chan); 941c5c98927SRussell King dma_unmap_sg(chan->device->dev, 942c5c98927SRussell King host->data->sg, host->data->sg_len, 94370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 944c5c98927SRussell King 945053bf34fSPer Forlin host->data->host_cookie = 0; 946a45c6cb8SMadhusudhan Chikkature } 947a45c6cb8SMadhusudhan Chikkature host->data = NULL; 948a45c6cb8SMadhusudhan Chikkature } 949a45c6cb8SMadhusudhan Chikkature 950a45c6cb8SMadhusudhan Chikkature /* 951a45c6cb8SMadhusudhan Chikkature * Readable error output 952a45c6cb8SMadhusudhan Chikkature */ 953a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 954699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 955a45c6cb8SMadhusudhan Chikkature { 956a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 95770a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 958699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 959699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 960699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 961699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 962a45c6cb8SMadhusudhan Chikkature }; 963a45c6cb8SMadhusudhan Chikkature char res[256]; 964a45c6cb8SMadhusudhan Chikkature char *buf = res; 965a45c6cb8SMadhusudhan Chikkature int len, i; 966a45c6cb8SMadhusudhan Chikkature 967a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 968a45c6cb8SMadhusudhan Chikkature buf += len; 969a45c6cb8SMadhusudhan Chikkature 97070a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 971a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 97270a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 973a45c6cb8SMadhusudhan Chikkature buf += len; 974a45c6cb8SMadhusudhan Chikkature } 975a45c6cb8SMadhusudhan Chikkature 9768986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 977a45c6cb8SMadhusudhan Chikkature } 978699b958bSAdrian Hunter #else 979699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 980699b958bSAdrian Hunter u32 status) 981699b958bSAdrian Hunter { 982699b958bSAdrian Hunter } 983a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 984a45c6cb8SMadhusudhan Chikkature 9853ebf74b1SJean Pihet /* 9863ebf74b1SJean Pihet * MMC controller internal state machines reset 9873ebf74b1SJean Pihet * 9883ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9893ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9903ebf74b1SJean Pihet * Can be called from interrupt context 9913ebf74b1SJean Pihet */ 99270a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9933ebf74b1SJean Pihet unsigned long bit) 9943ebf74b1SJean Pihet { 9953ebf74b1SJean Pihet unsigned long i = 0; 9961e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 9973ebf74b1SJean Pihet 9983ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9993ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10003ebf74b1SJean Pihet 100107ad64b6SMadhusudhan Chikkature /* 100207ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 100307ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 100407ad64b6SMadhusudhan Chikkature */ 100507ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1006b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 100707ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10081e881786SJianpeng Ma udelay(1); 100907ad64b6SMadhusudhan Chikkature } 101007ad64b6SMadhusudhan Chikkature i = 0; 101107ad64b6SMadhusudhan Chikkature 10123ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10133ebf74b1SJean Pihet (i++ < limit)) 10141e881786SJianpeng Ma udelay(1); 10153ebf74b1SJean Pihet 10163ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10173ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10183ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10193ebf74b1SJean Pihet __func__); 10203ebf74b1SJean Pihet } 1021a45c6cb8SMadhusudhan Chikkature 102225e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 102325e1897bSBalaji T K int err, int end_cmd) 1024ae4bf788SVenkatraman S { 102525e1897bSBalaji T K if (end_cmd) { 102694d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 102725e1897bSBalaji T K if (host->cmd) 1028ae4bf788SVenkatraman S host->cmd->error = err; 102925e1897bSBalaji T K } 1030ae4bf788SVenkatraman S 1031ae4bf788SVenkatraman S if (host->data) { 1032ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1033ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1034dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1035dc7745bdSBalaji T K host->mrq->cmd->error = err; 1036ae4bf788SVenkatraman S } 1037ae4bf788SVenkatraman S 1038b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1039a45c6cb8SMadhusudhan Chikkature { 1040a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1041b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1042a45c6cb8SMadhusudhan Chikkature 1043a45c6cb8SMadhusudhan Chikkature data = host->data; 10448986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1045a45c6cb8SMadhusudhan Chikkature 1046a7e96879SVenkatraman S if (status & ERR_EN) { 1047699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10484a694dc9SAdrian Hunter 1049a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1050a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1051a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 105225e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1053a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 105425e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 105525e1897bSBalaji T K 1056ae4bf788SVenkatraman S if (host->data || host->response_busy) { 105725e1897bSBalaji T K end_trans = !end_cmd; 1058ae4bf788SVenkatraman S host->response_busy = 0; 1059a45c6cb8SMadhusudhan Chikkature } 1060a45c6cb8SMadhusudhan Chikkature } 1061a45c6cb8SMadhusudhan Chikkature 10627472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1063a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 106470a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1065a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 106670a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1067b417577dSAdrian Hunter } 1068a45c6cb8SMadhusudhan Chikkature 1069b417577dSAdrian Hunter /* 1070b417577dSAdrian Hunter * MMC controller IRQ handler 1071b417577dSAdrian Hunter */ 1072b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1073b417577dSAdrian Hunter { 1074b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1075b417577dSAdrian Hunter int status; 1076b417577dSAdrian Hunter 1077b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10781f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1079b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10801f6b9fa4SVenkatraman S 1081b417577dSAdrian Hunter /* Flush posted write */ 1082b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10831f6b9fa4SVenkatraman S } 10844dffd7a2SAdrian Hunter 1085a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1086a45c6cb8SMadhusudhan Chikkature } 1087a45c6cb8SMadhusudhan Chikkature 108870a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1089e13bb300SAdrian Hunter { 1090e13bb300SAdrian Hunter unsigned long i; 1091e13bb300SAdrian Hunter 1092e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1093e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1094e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1095e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1096e13bb300SAdrian Hunter break; 1097e13bb300SAdrian Hunter cpu_relax(); 1098e13bb300SAdrian Hunter } 1099e13bb300SAdrian Hunter } 1100e13bb300SAdrian Hunter 1101a45c6cb8SMadhusudhan Chikkature /* 1102eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1103eb250826SDavid Brownell * 1104eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1105eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1106eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1107a45c6cb8SMadhusudhan Chikkature */ 110870a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1109a45c6cb8SMadhusudhan Chikkature { 1110a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1111a45c6cb8SMadhusudhan Chikkature int ret; 1112a45c6cb8SMadhusudhan Chikkature 1113a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1114fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1115cd03d9a8SRajendra Nayak if (host->dbclk) 111694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1117a45c6cb8SMadhusudhan Chikkature 1118a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1119a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1120a45c6cb8SMadhusudhan Chikkature 1121a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11222bec0893SAdrian Hunter if (!ret) 11232bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11242bec0893SAdrian Hunter vdd); 1125fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1126cd03d9a8SRajendra Nayak if (host->dbclk) 112794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11282bec0893SAdrian Hunter 1129a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1130a45c6cb8SMadhusudhan Chikkature goto err; 1131a45c6cb8SMadhusudhan Chikkature 1132a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1133a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1134a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1135eb250826SDavid Brownell 1136a45c6cb8SMadhusudhan Chikkature /* 1137a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1138a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 113970a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1140a45c6cb8SMadhusudhan Chikkature * 1141eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1142eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1143eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1144eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1145eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1146eb250826SDavid Brownell * 1147eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1148eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1149eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1150a45c6cb8SMadhusudhan Chikkature */ 1151eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1152a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1153eb250826SDavid Brownell else 1154eb250826SDavid Brownell reg_val |= SDVS30; 1155a45c6cb8SMadhusudhan Chikkature 1156a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1157e13bb300SAdrian Hunter set_sd_bus_power(host); 1158a45c6cb8SMadhusudhan Chikkature 1159a45c6cb8SMadhusudhan Chikkature return 0; 1160a45c6cb8SMadhusudhan Chikkature err: 1161b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1162a45c6cb8SMadhusudhan Chikkature return ret; 1163a45c6cb8SMadhusudhan Chikkature } 1164a45c6cb8SMadhusudhan Chikkature 1165b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1166b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1167b62f6228SAdrian Hunter { 1168b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1169b62f6228SAdrian Hunter return; 1170b62f6228SAdrian Hunter 1171b62f6228SAdrian Hunter host->reqs_blocked = 0; 1172b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1173b62f6228SAdrian Hunter if (host->protect_card) { 11742cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1175b62f6228SAdrian Hunter "card is now accessible\n", 1176b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1177b62f6228SAdrian Hunter host->protect_card = 0; 1178b62f6228SAdrian Hunter } 1179b62f6228SAdrian Hunter } else { 1180b62f6228SAdrian Hunter if (!host->protect_card) { 11812cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1182b62f6228SAdrian Hunter "card is now inaccessible\n", 1183b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1184b62f6228SAdrian Hunter host->protect_card = 1; 1185b62f6228SAdrian Hunter } 1186b62f6228SAdrian Hunter } 1187b62f6228SAdrian Hunter } 1188b62f6228SAdrian Hunter 1189a45c6cb8SMadhusudhan Chikkature /* 11907efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1191a45c6cb8SMadhusudhan Chikkature */ 11927efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1193a45c6cb8SMadhusudhan Chikkature { 11947efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1195249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1196a6b2240dSAdrian Hunter int carddetect; 1197249d0fa9SDavid Brownell 1198a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1199a6b2240dSAdrian Hunter 1200191d1f1dSDenis Karpov if (slot->card_detect) 1201db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1202b62f6228SAdrian Hunter else { 1203b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1204a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1205b62f6228SAdrian Hunter } 1206a6b2240dSAdrian Hunter 1207cdeebaddSMadhusudhan Chikkature if (carddetect) 1208a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1209cdeebaddSMadhusudhan Chikkature else 1210a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1211a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1212a45c6cb8SMadhusudhan Chikkature } 1213a45c6cb8SMadhusudhan Chikkature 1214c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12150ccd76d4SJuha Yrjola { 1216c5c98927SRussell King struct omap_hsmmc_host *host = param; 1217c5c98927SRussell King struct dma_chan *chan; 1218770d7432SAdrian Hunter struct mmc_data *data; 1219c5c98927SRussell King int req_in_progress; 1220a45c6cb8SMadhusudhan Chikkature 1221c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1222b417577dSAdrian Hunter if (host->dma_ch < 0) { 1223c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1224a45c6cb8SMadhusudhan Chikkature return; 1225b417577dSAdrian Hunter } 1226a45c6cb8SMadhusudhan Chikkature 1227770d7432SAdrian Hunter data = host->mrq->data; 1228c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12299782aff8SPer Forlin if (!data->host_cookie) 1230c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1231c5c98927SRussell King data->sg, data->sg_len, 1232b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1233b417577dSAdrian Hunter 1234b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1235a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1236c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1237b417577dSAdrian Hunter 1238b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1239b417577dSAdrian Hunter if (!req_in_progress) { 1240b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1241b417577dSAdrian Hunter 1242b417577dSAdrian Hunter host->mrq = NULL; 1243b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1244b417577dSAdrian Hunter } 1245a45c6cb8SMadhusudhan Chikkature } 1246a45c6cb8SMadhusudhan Chikkature 12479782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12489782aff8SPer Forlin struct mmc_data *data, 1249c5c98927SRussell King struct omap_hsmmc_next *next, 125026b88520SRussell King struct dma_chan *chan) 12519782aff8SPer Forlin { 12529782aff8SPer Forlin int dma_len; 12539782aff8SPer Forlin 12549782aff8SPer Forlin if (!next && data->host_cookie && 12559782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12562cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12579782aff8SPer Forlin " host->next_data.cookie %d\n", 12589782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12599782aff8SPer Forlin data->host_cookie = 0; 12609782aff8SPer Forlin } 12619782aff8SPer Forlin 12629782aff8SPer Forlin /* Check if next job is already prepared */ 1263b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 126426b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12659782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12669782aff8SPer Forlin 12679782aff8SPer Forlin } else { 12689782aff8SPer Forlin dma_len = host->next_data.dma_len; 12699782aff8SPer Forlin host->next_data.dma_len = 0; 12709782aff8SPer Forlin } 12719782aff8SPer Forlin 12729782aff8SPer Forlin 12739782aff8SPer Forlin if (dma_len == 0) 12749782aff8SPer Forlin return -EINVAL; 12759782aff8SPer Forlin 12769782aff8SPer Forlin if (next) { 12779782aff8SPer Forlin next->dma_len = dma_len; 12789782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12799782aff8SPer Forlin } else 12809782aff8SPer Forlin host->dma_len = dma_len; 12819782aff8SPer Forlin 12829782aff8SPer Forlin return 0; 12839782aff8SPer Forlin } 12849782aff8SPer Forlin 1285a45c6cb8SMadhusudhan Chikkature /* 1286a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1287a45c6cb8SMadhusudhan Chikkature */ 12889d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 128970a3341aSDenis Karpov struct mmc_request *req) 1290a45c6cb8SMadhusudhan Chikkature { 129126b88520SRussell King struct dma_slave_config cfg; 129226b88520SRussell King struct dma_async_tx_descriptor *tx; 129326b88520SRussell King int ret = 0, i; 1294a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1295c5c98927SRussell King struct dma_chan *chan; 1296a45c6cb8SMadhusudhan Chikkature 12970ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1298a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12990ccd76d4SJuha Yrjola struct scatterlist *sgl; 13000ccd76d4SJuha Yrjola 13010ccd76d4SJuha Yrjola sgl = data->sg + i; 13020ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13030ccd76d4SJuha Yrjola return -EINVAL; 13040ccd76d4SJuha Yrjola } 13050ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13060ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13070ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13080ccd76d4SJuha Yrjola */ 13090ccd76d4SJuha Yrjola return -EINVAL; 13100ccd76d4SJuha Yrjola 1311b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1312a45c6cb8SMadhusudhan Chikkature 1313c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1314c5c98927SRussell King 1315c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1316c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1317c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1318c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1319c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1320c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1321c5c98927SRussell King 1322c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13239782aff8SPer Forlin if (ret) 13249782aff8SPer Forlin return ret; 1325a45c6cb8SMadhusudhan Chikkature 132626b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1327c5c98927SRussell King if (ret) 1328c5c98927SRussell King return ret; 1329a45c6cb8SMadhusudhan Chikkature 1330c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1331c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1332c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1333c5c98927SRussell King if (!tx) { 1334c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1335c5c98927SRussell King /* FIXME: cleanup */ 1336c5c98927SRussell King return -1; 1337c5c98927SRussell King } 1338c5c98927SRussell King 1339c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1340c5c98927SRussell King tx->callback_param = host; 1341c5c98927SRussell King 1342c5c98927SRussell King /* Does not fail */ 1343c5c98927SRussell King dmaengine_submit(tx); 1344c5c98927SRussell King 134526b88520SRussell King host->dma_ch = 1; 1346c5c98927SRussell King 1347a45c6cb8SMadhusudhan Chikkature return 0; 1348a45c6cb8SMadhusudhan Chikkature } 1349a45c6cb8SMadhusudhan Chikkature 135070a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1351e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1352e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1353a45c6cb8SMadhusudhan Chikkature { 1354a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1355a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1356a45c6cb8SMadhusudhan Chikkature 1357a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1358a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1359a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1360a45c6cb8SMadhusudhan Chikkature clkd = 1; 1361a45c6cb8SMadhusudhan Chikkature 13626e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1363e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1364e2bf08d6SAdrian Hunter timeout += timeout_clks; 1365a45c6cb8SMadhusudhan Chikkature if (timeout) { 1366a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1367a45c6cb8SMadhusudhan Chikkature dto += 1; 1368a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1369a45c6cb8SMadhusudhan Chikkature } 1370a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1371a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1372a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1373a45c6cb8SMadhusudhan Chikkature dto += 1; 1374a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1375a45c6cb8SMadhusudhan Chikkature dto -= 13; 1376a45c6cb8SMadhusudhan Chikkature else 1377a45c6cb8SMadhusudhan Chikkature dto = 0; 1378a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1379a45c6cb8SMadhusudhan Chikkature dto = 14; 1380a45c6cb8SMadhusudhan Chikkature } 1381a45c6cb8SMadhusudhan Chikkature 1382a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1383a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1384a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1385a45c6cb8SMadhusudhan Chikkature } 1386a45c6cb8SMadhusudhan Chikkature 13879d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 13889d025334SBalaji T K { 13899d025334SBalaji T K struct mmc_request *req = host->mrq; 13909d025334SBalaji T K struct dma_chan *chan; 13919d025334SBalaji T K 13929d025334SBalaji T K if (!req->data) 13939d025334SBalaji T K return; 13949d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 13959d025334SBalaji T K | (req->data->blocks << 16)); 13969d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 13979d025334SBalaji T K req->data->timeout_clks); 13989d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 13999d025334SBalaji T K dma_async_issue_pending(chan); 14009d025334SBalaji T K } 14019d025334SBalaji T K 1402a45c6cb8SMadhusudhan Chikkature /* 1403a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1404a45c6cb8SMadhusudhan Chikkature */ 1405a45c6cb8SMadhusudhan Chikkature static int 140670a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1407a45c6cb8SMadhusudhan Chikkature { 1408a45c6cb8SMadhusudhan Chikkature int ret; 1409a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1410a45c6cb8SMadhusudhan Chikkature 1411a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1412a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1413e2bf08d6SAdrian Hunter /* 1414e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1415e2bf08d6SAdrian Hunter * busy signal. 1416e2bf08d6SAdrian Hunter */ 1417e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1418e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1419a45c6cb8SMadhusudhan Chikkature return 0; 1420a45c6cb8SMadhusudhan Chikkature } 1421a45c6cb8SMadhusudhan Chikkature 1422a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 14239d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1424a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1425b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1426a45c6cb8SMadhusudhan Chikkature return ret; 1427a45c6cb8SMadhusudhan Chikkature } 1428a45c6cb8SMadhusudhan Chikkature } 1429a45c6cb8SMadhusudhan Chikkature return 0; 1430a45c6cb8SMadhusudhan Chikkature } 1431a45c6cb8SMadhusudhan Chikkature 14329782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14339782aff8SPer Forlin int err) 14349782aff8SPer Forlin { 14359782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14369782aff8SPer Forlin struct mmc_data *data = mrq->data; 14379782aff8SPer Forlin 143826b88520SRussell King if (host->use_dma && data->host_cookie) { 1439c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1440c5c98927SRussell King 144126b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14429782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14439782aff8SPer Forlin data->host_cookie = 0; 14449782aff8SPer Forlin } 14459782aff8SPer Forlin } 14469782aff8SPer Forlin 14479782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14489782aff8SPer Forlin bool is_first_req) 14499782aff8SPer Forlin { 14509782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14519782aff8SPer Forlin 14529782aff8SPer Forlin if (mrq->data->host_cookie) { 14539782aff8SPer Forlin mrq->data->host_cookie = 0; 14549782aff8SPer Forlin return ; 14559782aff8SPer Forlin } 14569782aff8SPer Forlin 1457c5c98927SRussell King if (host->use_dma) { 1458c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1459c5c98927SRussell King 14609782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 146126b88520SRussell King &host->next_data, c)) 14629782aff8SPer Forlin mrq->data->host_cookie = 0; 14639782aff8SPer Forlin } 1464c5c98927SRussell King } 14659782aff8SPer Forlin 1466a45c6cb8SMadhusudhan Chikkature /* 1467a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1468a45c6cb8SMadhusudhan Chikkature */ 146970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1470a45c6cb8SMadhusudhan Chikkature { 147170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1472a3f406f8SJarkko Lavinen int err; 1473a45c6cb8SMadhusudhan Chikkature 1474b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1475b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1476b62f6228SAdrian Hunter if (host->protect_card) { 1477b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1478b62f6228SAdrian Hunter /* 1479b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1480b62f6228SAdrian Hunter * state by resetting the command and data state 1481b62f6228SAdrian Hunter * machines. 1482b62f6228SAdrian Hunter */ 1483b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1484b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1485b62f6228SAdrian Hunter host->reqs_blocked += 1; 1486b62f6228SAdrian Hunter } 1487b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1488b62f6228SAdrian Hunter if (req->data) 1489b62f6228SAdrian Hunter req->data->error = -EBADF; 1490b417577dSAdrian Hunter req->cmd->retries = 0; 1491b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1492b62f6228SAdrian Hunter return; 1493b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1494b62f6228SAdrian Hunter host->reqs_blocked = 0; 1495a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1496a45c6cb8SMadhusudhan Chikkature host->mrq = req; 14976e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 149870a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1499a3f406f8SJarkko Lavinen if (err) { 1500a3f406f8SJarkko Lavinen req->cmd->error = err; 1501a3f406f8SJarkko Lavinen if (req->data) 1502a3f406f8SJarkko Lavinen req->data->error = err; 1503a3f406f8SJarkko Lavinen host->mrq = NULL; 1504a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1505a3f406f8SJarkko Lavinen return; 1506a3f406f8SJarkko Lavinen } 1507a3f406f8SJarkko Lavinen 15089d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 150970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1510a45c6cb8SMadhusudhan Chikkature } 1511a45c6cb8SMadhusudhan Chikkature 1512a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 151370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1514a45c6cb8SMadhusudhan Chikkature { 151570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1516a3621465SAdrian Hunter int do_send_init_stream = 0; 1517a45c6cb8SMadhusudhan Chikkature 1518fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15195e2ea617SAdrian Hunter 1520a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1521a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1522a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1523a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1524a3621465SAdrian Hunter 0, 0); 1525a45c6cb8SMadhusudhan Chikkature break; 1526a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1527a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1528a3621465SAdrian Hunter 1, ios->vdd); 1529a45c6cb8SMadhusudhan Chikkature break; 1530a3621465SAdrian Hunter case MMC_POWER_ON: 1531a3621465SAdrian Hunter do_send_init_stream = 1; 1532a3621465SAdrian Hunter break; 1533a3621465SAdrian Hunter } 1534a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1535a45c6cb8SMadhusudhan Chikkature } 1536a45c6cb8SMadhusudhan Chikkature 1537dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1538dd498effSDenis Karpov 15393796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1540a45c6cb8SMadhusudhan Chikkature 15414621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1542eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1543eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1544eb250826SDavid Brownell */ 1545a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15462cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1547a45c6cb8SMadhusudhan Chikkature /* 1548a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1549a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1550a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1551a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1552a45c6cb8SMadhusudhan Chikkature */ 155370a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1554a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1555a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1556a45c6cb8SMadhusudhan Chikkature } 1557a45c6cb8SMadhusudhan Chikkature } 1558a45c6cb8SMadhusudhan Chikkature 15595934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1560a45c6cb8SMadhusudhan Chikkature 1561a3621465SAdrian Hunter if (do_send_init_stream) 1562a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1563a45c6cb8SMadhusudhan Chikkature 15643796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15655e2ea617SAdrian Hunter 1566fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1567a45c6cb8SMadhusudhan Chikkature } 1568a45c6cb8SMadhusudhan Chikkature 1569a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1570a45c6cb8SMadhusudhan Chikkature { 157170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1572a45c6cb8SMadhusudhan Chikkature 1573191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1574a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1575db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1576a45c6cb8SMadhusudhan Chikkature } 1577a45c6cb8SMadhusudhan Chikkature 1578a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1579a45c6cb8SMadhusudhan Chikkature { 158070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1581a45c6cb8SMadhusudhan Chikkature 1582191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1583a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1584191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1585a45c6cb8SMadhusudhan Chikkature } 1586a45c6cb8SMadhusudhan Chikkature 15874816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15884816858cSGrazvydas Ignotas { 15894816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15904816858cSGrazvydas Ignotas 15914816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15924816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15934816858cSGrazvydas Ignotas } 15944816858cSGrazvydas Ignotas 159570a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15961b331e69SKim Kyuwon { 15971b331e69SKim Kyuwon u32 hctl, capa, value; 15981b331e69SKim Kyuwon 15991b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 16004621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 16011b331e69SKim Kyuwon hctl = SDVS30; 16021b331e69SKim Kyuwon capa = VS30 | VS18; 16031b331e69SKim Kyuwon } else { 16041b331e69SKim Kyuwon hctl = SDVS18; 16051b331e69SKim Kyuwon capa = VS18; 16061b331e69SKim Kyuwon } 16071b331e69SKim Kyuwon 16081b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 16091b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 16101b331e69SKim Kyuwon 16111b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 16121b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 16131b331e69SKim Kyuwon 16141b331e69SKim Kyuwon /* Set SD bus power bit */ 1615e13bb300SAdrian Hunter set_sd_bus_power(host); 16161b331e69SKim Kyuwon } 16171b331e69SKim Kyuwon 161870a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1619dd498effSDenis Karpov { 162070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1621dd498effSDenis Karpov 1622fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1623fa4aa2d4SBalaji T K 1624dd498effSDenis Karpov return 0; 1625dd498effSDenis Karpov } 1626dd498effSDenis Karpov 1627907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1628dd498effSDenis Karpov { 162970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1630dd498effSDenis Karpov 1631fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1632fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1633fa4aa2d4SBalaji T K 1634dd498effSDenis Karpov return 0; 1635dd498effSDenis Karpov } 1636dd498effSDenis Karpov 163770a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 163870a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 163970a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16409782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16419782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 164270a3341aSDenis Karpov .request = omap_hsmmc_request, 164370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1644dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1645dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16464816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1647dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1648dd498effSDenis Karpov }; 1649dd498effSDenis Karpov 1650d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1651d900f712SDenis Karpov 165270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1653d900f712SDenis Karpov { 1654d900f712SDenis Karpov struct mmc_host *mmc = s->private; 165570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 165611dd62a7SDenis Karpov 16570a82e06eSTony Lindgren seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 16580a82e06eSTony Lindgren mmc->index, host->context_loss); 16595e2ea617SAdrian Hunter 1660fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1661d900f712SDenis Karpov 1662d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1663d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1664d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1665d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1666d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1667d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1668d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1669d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1670d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1671d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1672d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1673d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16745e2ea617SAdrian Hunter 1675fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1676fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1677dd498effSDenis Karpov 1678d900f712SDenis Karpov return 0; 1679d900f712SDenis Karpov } 1680d900f712SDenis Karpov 168170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1682d900f712SDenis Karpov { 168370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1684d900f712SDenis Karpov } 1685d900f712SDenis Karpov 1686d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 168770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1688d900f712SDenis Karpov .read = seq_read, 1689d900f712SDenis Karpov .llseek = seq_lseek, 1690d900f712SDenis Karpov .release = single_release, 1691d900f712SDenis Karpov }; 1692d900f712SDenis Karpov 169370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1694d900f712SDenis Karpov { 1695d900f712SDenis Karpov if (mmc->debugfs_root) 1696d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1697d900f712SDenis Karpov mmc, &mmc_regs_fops); 1698d900f712SDenis Karpov } 1699d900f712SDenis Karpov 1700d900f712SDenis Karpov #else 1701d900f712SDenis Karpov 170270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1703d900f712SDenis Karpov { 1704d900f712SDenis Karpov } 1705d900f712SDenis Karpov 1706d900f712SDenis Karpov #endif 1707d900f712SDenis Karpov 170846856a68SRajendra Nayak #ifdef CONFIG_OF 170959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 171059445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 171159445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 171259445b10SNishanth Menon }; 171359445b10SNishanth Menon 171459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 171559445b10SNishanth Menon .reg_offset = 0x100, 171659445b10SNishanth Menon }; 171746856a68SRajendra Nayak 171846856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 171946856a68SRajendra Nayak { 172046856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 172146856a68SRajendra Nayak }, 172246856a68SRajendra Nayak { 172359445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 172459445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 172559445b10SNishanth Menon }, 172659445b10SNishanth Menon { 172746856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 172846856a68SRajendra Nayak }, 172946856a68SRajendra Nayak { 173046856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 173159445b10SNishanth Menon .data = &omap4_mmc_of_data, 173246856a68SRajendra Nayak }, 173346856a68SRajendra Nayak {}, 1734b6d085f6SChris Ball }; 173546856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 173646856a68SRajendra Nayak 173746856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 173846856a68SRajendra Nayak { 173946856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 174046856a68SRajendra Nayak struct device_node *np = dev->of_node; 1741d8714e87SDaniel Mack u32 bus_width, max_freq; 1742dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1743dc642c28SJan Luebbe 1744dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1745dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1746dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1747dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 174846856a68SRajendra Nayak 174946856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 175046856a68SRajendra Nayak if (!pdata) 175119df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 175246856a68SRajendra Nayak 175346856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 175446856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 175546856a68SRajendra Nayak 175646856a68SRajendra Nayak /* This driver only supports 1 slot */ 175746856a68SRajendra Nayak pdata->nr_slots = 1; 1758dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1759dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 176046856a68SRajendra Nayak 176146856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 176246856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 176346856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 176446856a68SRajendra Nayak } 17657f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 176646856a68SRajendra Nayak if (bus_width == 4) 176746856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 176846856a68SRajendra Nayak else if (bus_width == 8) 176946856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 177046856a68SRajendra Nayak 177146856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 177246856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 177346856a68SRajendra Nayak 1774d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1775d8714e87SDaniel Mack pdata->max_freq = max_freq; 1776d8714e87SDaniel Mack 1777cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1778cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1779cd587096SHebbar, Gururaja 1780c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 1781c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; 1782c9ae64dbSDaniel Mack 1783c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1784c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1785c9ae64dbSDaniel Mack 178646856a68SRajendra Nayak return pdata; 178746856a68SRajendra Nayak } 178846856a68SRajendra Nayak #else 178946856a68SRajendra Nayak static inline struct omap_mmc_platform_data 179046856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 179146856a68SRajendra Nayak { 179219df45bcSBalaji T K return ERR_PTR(-EINVAL); 179346856a68SRajendra Nayak } 179446856a68SRajendra Nayak #endif 179546856a68SRajendra Nayak 1796c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1797a45c6cb8SMadhusudhan Chikkature { 1798a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1799a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 180070a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1801a45c6cb8SMadhusudhan Chikkature struct resource *res; 1802db0fefc5SAdrian Hunter int ret, irq; 180346856a68SRajendra Nayak const struct of_device_id *match; 180426b88520SRussell King dma_cap_mask_t mask; 180526b88520SRussell King unsigned tx_req, rx_req; 180646b76035SDaniel Mack struct pinctrl *pinctrl; 180759445b10SNishanth Menon const struct omap_mmc_of_data *data; 180846856a68SRajendra Nayak 180946856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 181046856a68SRajendra Nayak if (match) { 181146856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1812dc642c28SJan Luebbe 1813dc642c28SJan Luebbe if (IS_ERR(pdata)) 1814dc642c28SJan Luebbe return PTR_ERR(pdata); 1815dc642c28SJan Luebbe 181646856a68SRajendra Nayak if (match->data) { 181759445b10SNishanth Menon data = match->data; 181859445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 181959445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 182046856a68SRajendra Nayak } 182146856a68SRajendra Nayak } 1822a45c6cb8SMadhusudhan Chikkature 1823a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1824a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1825a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1826a45c6cb8SMadhusudhan Chikkature } 1827a45c6cb8SMadhusudhan Chikkature 1828a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1829a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1830a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1831a45c6cb8SMadhusudhan Chikkature } 1832a45c6cb8SMadhusudhan Chikkature 1833a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1834a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1835a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1836a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1837a45c6cb8SMadhusudhan Chikkature 1838984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1839a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1840a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1841a45c6cb8SMadhusudhan Chikkature 1842db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1843db0fefc5SAdrian Hunter if (ret) 1844db0fefc5SAdrian Hunter goto err; 1845db0fefc5SAdrian Hunter 184670a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1847a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1848a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1849db0fefc5SAdrian Hunter goto err_alloc; 1850a45c6cb8SMadhusudhan Chikkature } 1851a45c6cb8SMadhusudhan Chikkature 1852a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1853a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1854a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1855a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1856a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1857a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1858a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1859a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1860fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1861a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18626da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18639782aff8SPer Forlin host->next_data.cookie = 1; 1864e99448ffSBalaji T K host->pbias_enabled = 0; 1865a45c6cb8SMadhusudhan Chikkature 1866a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1867a45c6cb8SMadhusudhan Chikkature 186870a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1869dd498effSDenis Karpov 18706b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1871d418ed87SDaniel Mack 1872d418ed87SDaniel Mack if (pdata->max_freq > 0) 1873d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1874d418ed87SDaniel Mack else 18756b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1876a45c6cb8SMadhusudhan Chikkature 18774dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1878a45c6cb8SMadhusudhan Chikkature 18796f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1880a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1881a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1882a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1883a45c6cb8SMadhusudhan Chikkature goto err1; 1884a45c6cb8SMadhusudhan Chikkature } 1885a45c6cb8SMadhusudhan Chikkature 18869b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18879b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18889b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18899b68256cSPaul Walmsley } 1890dd498effSDenis Karpov 1891fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1892fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1893fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1894fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1895a45c6cb8SMadhusudhan Chikkature 189692a3aebfSBalaji T K omap_hsmmc_context_save(host); 189792a3aebfSBalaji T K 1898a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1899a45c6cb8SMadhusudhan Chikkature /* 1900a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1901a45c6cb8SMadhusudhan Chikkature */ 1902cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1903cd03d9a8SRajendra Nayak host->dbclk = NULL; 190494c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1905cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1906cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1907cd03d9a8SRajendra Nayak host->dbclk = NULL; 19082bec0893SAdrian Hunter } 1909a45c6cb8SMadhusudhan Chikkature 19100ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19110ccd76d4SJuha Yrjola * as we want. */ 1912a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19130ccd76d4SJuha Yrjola 1914a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1915a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1916a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1917a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1918a45c6cb8SMadhusudhan Chikkature 191913189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 192093caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1921a45c6cb8SMadhusudhan Chikkature 19223a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19233a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1924a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1925a45c6cb8SMadhusudhan Chikkature 1926191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 192723d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 192823d99bb9SAdrian Hunter 19296fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19306fdc75deSEliad Peller 193170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1932a45c6cb8SMadhusudhan Chikkature 19334a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 1934b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1935b7bf773bSBalaji T K if (!res) { 1936b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19379c17d08cSKevin Hilman ret = -ENXIO; 1938f3e2f1ddSGrazvydas Ignotas goto err_irq; 1939a45c6cb8SMadhusudhan Chikkature } 194026b88520SRussell King tx_req = res->start; 1941b7bf773bSBalaji T K 1942b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1943b7bf773bSBalaji T K if (!res) { 1944b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19459c17d08cSKevin Hilman ret = -ENXIO; 1946b7bf773bSBalaji T K goto err_irq; 1947b7bf773bSBalaji T K } 194826b88520SRussell King rx_req = res->start; 19494a29b559SSantosh Shilimkar } 1950c5c98927SRussell King 1951c5c98927SRussell King dma_cap_zero(mask); 1952c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 195326b88520SRussell King 1954d272fbf0SMatt Porter host->rx_chan = 1955d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1956d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1957d272fbf0SMatt Porter 1958c5c98927SRussell King if (!host->rx_chan) { 195926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 196004e8c7bcSKevin Hilman ret = -ENXIO; 196126b88520SRussell King goto err_irq; 1962c5c98927SRussell King } 196326b88520SRussell King 1964d272fbf0SMatt Porter host->tx_chan = 1965d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1966d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1967d272fbf0SMatt Porter 1968c5c98927SRussell King if (!host->tx_chan) { 196926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 197004e8c7bcSKevin Hilman ret = -ENXIO; 197126b88520SRussell King goto err_irq; 1972c5c98927SRussell King } 1973a45c6cb8SMadhusudhan Chikkature 1974a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1975d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1976a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1977a45c6cb8SMadhusudhan Chikkature if (ret) { 1978b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1979a45c6cb8SMadhusudhan Chikkature goto err_irq; 1980a45c6cb8SMadhusudhan Chikkature } 1981a45c6cb8SMadhusudhan Chikkature 1982a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1983a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1984b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 198570a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1986a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1987a45c6cb8SMadhusudhan Chikkature } 1988a45c6cb8SMadhusudhan Chikkature } 1989db0fefc5SAdrian Hunter 1990b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1991db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1992db0fefc5SAdrian Hunter if (ret) 1993db0fefc5SAdrian Hunter goto err_reg; 1994db0fefc5SAdrian Hunter host->use_reg = 1; 1995db0fefc5SAdrian Hunter } 1996db0fefc5SAdrian Hunter 1997b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1998a45c6cb8SMadhusudhan Chikkature 1999a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2000e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 20017efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 20027efab4f3SNeilBrown NULL, 20037efab4f3SNeilBrown omap_hsmmc_detect, 2004db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2005a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2006a45c6cb8SMadhusudhan Chikkature if (ret) { 2007b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 2008a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2009a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2010a45c6cb8SMadhusudhan Chikkature } 201172f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 201272f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2013a45c6cb8SMadhusudhan Chikkature } 2014a45c6cb8SMadhusudhan Chikkature 2015b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2016a45c6cb8SMadhusudhan Chikkature 201746b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 201846b76035SDaniel Mack if (IS_ERR(pinctrl)) 201946b76035SDaniel Mack dev_warn(&pdev->dev, 202046b76035SDaniel Mack "pins are not configured from the driver\n"); 202146b76035SDaniel Mack 2022b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2023b62f6228SAdrian Hunter 2024a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2025a45c6cb8SMadhusudhan Chikkature 2026191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2027a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2028a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2029a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2030a45c6cb8SMadhusudhan Chikkature } 2031191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2032a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2033a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2034a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2035db0fefc5SAdrian Hunter goto err_slot_name; 2036a45c6cb8SMadhusudhan Chikkature } 2037a45c6cb8SMadhusudhan Chikkature 203870a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2039fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2040fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2041d900f712SDenis Karpov 2042a45c6cb8SMadhusudhan Chikkature return 0; 2043a45c6cb8SMadhusudhan Chikkature 2044a45c6cb8SMadhusudhan Chikkature err_slot_name: 2045a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2046a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2047db0fefc5SAdrian Hunter err_irq_cd: 2048db0fefc5SAdrian Hunter if (host->use_reg) 2049db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2050db0fefc5SAdrian Hunter err_reg: 2051db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2052db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2053a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2054a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2055a45c6cb8SMadhusudhan Chikkature err_irq: 2056c5c98927SRussell King if (host->tx_chan) 2057c5c98927SRussell King dma_release_channel(host->tx_chan); 2058c5c98927SRussell King if (host->rx_chan) 2059c5c98927SRussell King dma_release_channel(host->rx_chan); 2060d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 206137f6190dSTony Lindgren pm_runtime_disable(host->dev); 2062a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2063cd03d9a8SRajendra Nayak if (host->dbclk) { 206494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2065a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2066a45c6cb8SMadhusudhan Chikkature } 2067a45c6cb8SMadhusudhan Chikkature err1: 2068a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2069a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2070db0fefc5SAdrian Hunter err_alloc: 2071db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2072db0fefc5SAdrian Hunter err: 207348b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 207448b332f9SRussell King if (res) 2075984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2076a45c6cb8SMadhusudhan Chikkature return ret; 2077a45c6cb8SMadhusudhan Chikkature } 2078a45c6cb8SMadhusudhan Chikkature 20796e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2080a45c6cb8SMadhusudhan Chikkature { 208170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2082a45c6cb8SMadhusudhan Chikkature struct resource *res; 2083a45c6cb8SMadhusudhan Chikkature 2084fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2085a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2086db0fefc5SAdrian Hunter if (host->use_reg) 2087db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2088a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2089a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2090a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2091a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2092a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2093a45c6cb8SMadhusudhan Chikkature 2094c5c98927SRussell King if (host->tx_chan) 2095c5c98927SRussell King dma_release_channel(host->tx_chan); 2096c5c98927SRussell King if (host->rx_chan) 2097c5c98927SRussell King dma_release_channel(host->rx_chan); 2098c5c98927SRussell King 2099fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2100fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2101a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2102cd03d9a8SRajendra Nayak if (host->dbclk) { 210394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2104a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2105a45c6cb8SMadhusudhan Chikkature } 2106a45c6cb8SMadhusudhan Chikkature 21079ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2108a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 21099d1f0286SBalaji T K mmc_free_host(host->mmc); 2110a45c6cb8SMadhusudhan Chikkature 2111a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2112a45c6cb8SMadhusudhan Chikkature if (res) 2113984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2114a45c6cb8SMadhusudhan Chikkature 2115a45c6cb8SMadhusudhan Chikkature return 0; 2116a45c6cb8SMadhusudhan Chikkature } 2117a45c6cb8SMadhusudhan Chikkature 2118a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2119a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2120a48ce884SFelipe Balbi { 2121a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2122a48ce884SFelipe Balbi 2123a48ce884SFelipe Balbi if (host->pdata->suspend) 2124a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2125a48ce884SFelipe Balbi 2126a48ce884SFelipe Balbi return 0; 2127a48ce884SFelipe Balbi } 2128a48ce884SFelipe Balbi 2129a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2130a48ce884SFelipe Balbi { 2131a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2132a48ce884SFelipe Balbi 2133a48ce884SFelipe Balbi if (host->pdata->resume) 2134a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2135a48ce884SFelipe Balbi 2136a48ce884SFelipe Balbi } 2137a48ce884SFelipe Balbi 2138a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2139a45c6cb8SMadhusudhan Chikkature { 2140927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2141927ce944SFelipe Balbi 2142927ce944SFelipe Balbi if (!host) 2143927ce944SFelipe Balbi return 0; 2144a45c6cb8SMadhusudhan Chikkature 2145fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 214631f9d463SEliad Peller 214731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 214831f9d463SEliad Peller omap_hsmmc_disable_irq(host); 214931f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 215031f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 215131f9d463SEliad Peller } 2152927ce944SFelipe Balbi 2153cd03d9a8SRajendra Nayak if (host->dbclk) 215494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 21553932afd5SUlf Hansson 2156fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 21573932afd5SUlf Hansson return 0; 2158a45c6cb8SMadhusudhan Chikkature } 2159a45c6cb8SMadhusudhan Chikkature 2160a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2161a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2162a45c6cb8SMadhusudhan Chikkature { 2163927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2164927ce944SFelipe Balbi 2165927ce944SFelipe Balbi if (!host) 2166927ce944SFelipe Balbi return 0; 2167a45c6cb8SMadhusudhan Chikkature 2168fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 216911dd62a7SDenis Karpov 2170cd03d9a8SRajendra Nayak if (host->dbclk) 217194c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21722bec0893SAdrian Hunter 217331f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 217470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21751b331e69SKim Kyuwon 2176b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2177b62f6228SAdrian Hunter 2178fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2179fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 21803932afd5SUlf Hansson return 0; 2181a45c6cb8SMadhusudhan Chikkature } 2182a45c6cb8SMadhusudhan Chikkature 2183a45c6cb8SMadhusudhan Chikkature #else 2184a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2185a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 218670a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 218770a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2188a45c6cb8SMadhusudhan Chikkature #endif 2189a45c6cb8SMadhusudhan Chikkature 2190fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2191fa4aa2d4SBalaji T K { 2192fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2193fa4aa2d4SBalaji T K 2194fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2195fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2196927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2197fa4aa2d4SBalaji T K 2198fa4aa2d4SBalaji T K return 0; 2199fa4aa2d4SBalaji T K } 2200fa4aa2d4SBalaji T K 2201fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2202fa4aa2d4SBalaji T K { 2203fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2204fa4aa2d4SBalaji T K 2205fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2206fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2207927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2208fa4aa2d4SBalaji T K 2209fa4aa2d4SBalaji T K return 0; 2210fa4aa2d4SBalaji T K } 2211fa4aa2d4SBalaji T K 2212a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 221370a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 221470a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2215a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2216a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2217fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2218fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2219a791daa1SKevin Hilman }; 2220a791daa1SKevin Hilman 2221a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2222efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22230433c143SBill Pemberton .remove = omap_hsmmc_remove, 2224a45c6cb8SMadhusudhan Chikkature .driver = { 2225a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2226a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2227a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 222846856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2229a45c6cb8SMadhusudhan Chikkature }, 2230a45c6cb8SMadhusudhan Chikkature }; 2231a45c6cb8SMadhusudhan Chikkature 2232b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2233a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2234a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2235a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2236a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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