1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4555143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 46a45c6cb8SMadhusudhan Chikkature 47a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4811dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 50a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 59bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 65a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 67a45c6cb8SMadhusudhan Chikkature 68a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 69a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 70cd587096SHebbar, Gururaja #define HSS (1 << 21) 71a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 72a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 73eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 741b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 75a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 76a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 77a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 78a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 79a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 80a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 81a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 82a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 83ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 84a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 85a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 86a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 87a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 88a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 89a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 90a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 91a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 92a7e96879SVenkatraman S #define DMAE 0x1 93a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 94a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 95a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 96cd587096SHebbar, Gururaja #define HSPE (1 << 2) 975a52b08bSBalaji T K #define IWE (1 << 24) 9803b5d924SBalaji T K #define DDR (1 << 19) 995a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1005a52b08bSBalaji T K #define CTPL (1 << 11) 10173153010SJarkko Lavinen #define DW8 (1 << 5) 102a45c6cb8SMadhusudhan Chikkature #define OD 0x1 103a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 104a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 105a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 106a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 107a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10811dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 109a45c6cb8SMadhusudhan Chikkature 110f945901fSAndreas Fenkart /* PSTATE */ 111f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 112f945901fSAndreas Fenkart 113a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 114a7e96879SVenkatraman S #define CC_EN (1 << 0) 115a7e96879SVenkatraman S #define TC_EN (1 << 1) 116a7e96879SVenkatraman S #define BWR_EN (1 << 4) 117a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1182cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 119a7e96879SVenkatraman S #define ERR_EN (1 << 15) 120a7e96879SVenkatraman S #define CTO_EN (1 << 16) 121a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 122a7e96879SVenkatraman S #define CEB_EN (1 << 18) 123a7e96879SVenkatraman S #define CIE_EN (1 << 19) 124a7e96879SVenkatraman S #define DTO_EN (1 << 20) 125a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 126a7e96879SVenkatraman S #define DEB_EN (1 << 22) 127a2e77152SBalaji T K #define ACE_EN (1 << 24) 128a7e96879SVenkatraman S #define CERR_EN (1 << 28) 129a7e96879SVenkatraman S #define BADA_EN (1 << 29) 130a7e96879SVenkatraman S 131a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 132a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 133a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 134a7e96879SVenkatraman S 135a2e77152SBalaji T K #define CNI (1 << 7) 136a2e77152SBalaji T K #define ACIE (1 << 4) 137a2e77152SBalaji T K #define ACEB (1 << 3) 138a2e77152SBalaji T K #define ACCE (1 << 2) 139a2e77152SBalaji T K #define ACTO (1 << 1) 140a2e77152SBalaji T K #define ACNE (1 << 0) 141a2e77152SBalaji T K 142fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1431e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1441e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1456b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1466b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1470005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 148a45c6cb8SMadhusudhan Chikkature 149e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 150e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 151e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 152e99448ffSBalaji T K 153a45c6cb8SMadhusudhan Chikkature /* 154a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 155a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 156a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 157a45c6cb8SMadhusudhan Chikkature */ 158326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 159a45c6cb8SMadhusudhan Chikkature 160a45c6cb8SMadhusudhan Chikkature /* 161a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 162a45c6cb8SMadhusudhan Chikkature */ 163a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 164a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 165a45c6cb8SMadhusudhan Chikkature 166a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 167a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 168a45c6cb8SMadhusudhan Chikkature 1699782aff8SPer Forlin struct omap_hsmmc_next { 1709782aff8SPer Forlin unsigned int dma_len; 1719782aff8SPer Forlin s32 cookie; 1729782aff8SPer Forlin }; 1739782aff8SPer Forlin 17470a3341aSDenis Karpov struct omap_hsmmc_host { 175a45c6cb8SMadhusudhan Chikkature struct device *dev; 176a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 177a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 178a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 179a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 180a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 181a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 182db0fefc5SAdrian Hunter /* 183db0fefc5SAdrian Hunter * vcc == configured supply 184db0fefc5SAdrian Hunter * vcc_aux == optional 185db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 186db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 187db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 188db0fefc5SAdrian Hunter */ 189db0fefc5SAdrian Hunter struct regulator *vcc; 190db0fefc5SAdrian Hunter struct regulator *vcc_aux; 191e99448ffSBalaji T K struct regulator *pbias; 192e99448ffSBalaji T K bool pbias_enabled; 193a45c6cb8SMadhusudhan Chikkature void __iomem *base; 194a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1954dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 196a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1970ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 198a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 199a3621465SAdrian Hunter unsigned char power_mode; 200a45c6cb8SMadhusudhan Chikkature int suspended; 2010a82e06eSTony Lindgren u32 con; 2020a82e06eSTony Lindgren u32 hctl; 2030a82e06eSTony Lindgren u32 sysctl; 2040a82e06eSTony Lindgren u32 capa; 205a45c6cb8SMadhusudhan Chikkature int irq; 2062cd3a2a5SAndreas Fenkart int wake_irq; 207a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 208c5c98927SRussell King struct dma_chan *tx_chan; 209c5c98927SRussell King struct dma_chan *rx_chan; 2104a694dc9SAdrian Hunter int response_busy; 21111dd62a7SDenis Karpov int context_loss; 212b62f6228SAdrian Hunter int protect_card; 213b62f6228SAdrian Hunter int reqs_blocked; 214db0fefc5SAdrian Hunter int use_reg; 215b417577dSAdrian Hunter int req_in_progress; 2166e3076c2SBalaji T K unsigned long clk_rate; 217a2e77152SBalaji T K unsigned int flags; 2182cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2192cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2202cd3a2a5SAndreas Fenkart #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) 2219782aff8SPer Forlin struct omap_hsmmc_next next_data; 22255143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 223b5cd43f0SAndreas Fenkart 224b5cd43f0SAndreas Fenkart /* To handle board related suspend/resume functionality for MMC */ 22580412ca8SAndreas Fenkart int (*suspend)(struct device *dev); 22680412ca8SAndreas Fenkart int (*resume)(struct device *dev); 227b5cd43f0SAndreas Fenkart 228b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 229b5cd43f0SAndreas Fenkart * 230b5cd43f0SAndreas Fenkart * possible return values: 231b5cd43f0SAndreas Fenkart * 0 - closed 232b5cd43f0SAndreas Fenkart * 1 - open 233b5cd43f0SAndreas Fenkart */ 23480412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 235b5cd43f0SAndreas Fenkart 236b5cd43f0SAndreas Fenkart /* Card detection IRQs */ 237b5cd43f0SAndreas Fenkart int card_detect_irq; 238b5cd43f0SAndreas Fenkart 23980412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 24080412ca8SAndreas Fenkart int (*get_ro)(struct device *dev); 241b5cd43f0SAndreas Fenkart 242a45c6cb8SMadhusudhan Chikkature }; 243a45c6cb8SMadhusudhan Chikkature 24459445b10SNishanth Menon struct omap_mmc_of_data { 24559445b10SNishanth Menon u32 reg_offset; 24659445b10SNishanth Menon u8 controller_flags; 24759445b10SNishanth Menon }; 24859445b10SNishanth Menon 249bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 250bf129e1cSBalaji T K 25180412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 252db0fefc5SAdrian Hunter { 2539ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 25455143438SAndreas Fenkart struct omap_hsmmc_platform_data *mmc = host->pdata; 255db0fefc5SAdrian Hunter 256db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 257326119c9SAndreas Fenkart return !gpio_get_value_cansleep(mmc->switch_pin); 258db0fefc5SAdrian Hunter } 259db0fefc5SAdrian Hunter 26080412ca8SAndreas Fenkart static int omap_hsmmc_get_wp(struct device *dev) 261db0fefc5SAdrian Hunter { 2629ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 26355143438SAndreas Fenkart struct omap_hsmmc_platform_data *mmc = host->pdata; 264db0fefc5SAdrian Hunter 265db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 266326119c9SAndreas Fenkart return gpio_get_value_cansleep(mmc->gpio_wp); 267db0fefc5SAdrian Hunter } 268db0fefc5SAdrian Hunter 26980412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 270db0fefc5SAdrian Hunter { 2719ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 27255143438SAndreas Fenkart struct omap_hsmmc_platform_data *mmc = host->pdata; 273db0fefc5SAdrian Hunter 274db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 275326119c9SAndreas Fenkart return !gpio_get_value_cansleep(mmc->switch_pin); 276db0fefc5SAdrian Hunter } 277db0fefc5SAdrian Hunter 278db0fefc5SAdrian Hunter #ifdef CONFIG_PM 279db0fefc5SAdrian Hunter 28080412ca8SAndreas Fenkart static int omap_hsmmc_suspend_cdirq(struct device *dev) 281db0fefc5SAdrian Hunter { 2829ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 283db0fefc5SAdrian Hunter 284b5cd43f0SAndreas Fenkart disable_irq(host->card_detect_irq); 285db0fefc5SAdrian Hunter return 0; 286db0fefc5SAdrian Hunter } 287db0fefc5SAdrian Hunter 28880412ca8SAndreas Fenkart static int omap_hsmmc_resume_cdirq(struct device *dev) 289db0fefc5SAdrian Hunter { 2909ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 291db0fefc5SAdrian Hunter 292b5cd43f0SAndreas Fenkart enable_irq(host->card_detect_irq); 293db0fefc5SAdrian Hunter return 0; 294db0fefc5SAdrian Hunter } 295db0fefc5SAdrian Hunter 296db0fefc5SAdrian Hunter #else 297db0fefc5SAdrian Hunter 298db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 299db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 300db0fefc5SAdrian Hunter 301db0fefc5SAdrian Hunter #endif 302db0fefc5SAdrian Hunter 303b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 304b702b106SAdrian Hunter 30580412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 306db0fefc5SAdrian Hunter { 307db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 308db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 309db0fefc5SAdrian Hunter int ret = 0; 310db0fefc5SAdrian Hunter 311db0fefc5SAdrian Hunter /* 312db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 313db0fefc5SAdrian Hunter * voltage always-on regulator. 314db0fefc5SAdrian Hunter */ 315db0fefc5SAdrian Hunter if (!host->vcc) 316db0fefc5SAdrian Hunter return 0; 317db0fefc5SAdrian Hunter 318326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 31980412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 320db0fefc5SAdrian Hunter 321e99448ffSBalaji T K if (host->pbias) { 322e99448ffSBalaji T K if (host->pbias_enabled == 1) { 323e99448ffSBalaji T K ret = regulator_disable(host->pbias); 324e99448ffSBalaji T K if (!ret) 325e99448ffSBalaji T K host->pbias_enabled = 0; 326e99448ffSBalaji T K } 327e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 328e99448ffSBalaji T K } 329e99448ffSBalaji T K 330db0fefc5SAdrian Hunter /* 331db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 332db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 333db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 334db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 335db0fefc5SAdrian Hunter * 336db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 337db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 338db0fefc5SAdrian Hunter * 339db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 340db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 341db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 342db0fefc5SAdrian Hunter */ 343db0fefc5SAdrian Hunter if (power_on) { 344987fd49bSBalaji T K if (host->vcc) 34599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 346db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 347db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 348db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 349987fd49bSBalaji T K if (ret < 0 && host->vcc) 35099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 35199fc5131SLinus Walleij host->vcc, 0); 352db0fefc5SAdrian Hunter } 353db0fefc5SAdrian Hunter } else { 35499fc5131SLinus Walleij /* Shut down the rail */ 3556da20c89SAdrian Hunter if (host->vcc_aux) 356db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 357987fd49bSBalaji T K if (host->vcc) { 35899fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 35999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 36099fc5131SLinus Walleij host->vcc, 0); 36199fc5131SLinus Walleij } 362db0fefc5SAdrian Hunter } 363db0fefc5SAdrian Hunter 364e99448ffSBalaji T K if (host->pbias) { 365e99448ffSBalaji T K if (vdd <= VDD_165_195) 366e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 367e99448ffSBalaji T K VDD_1V8); 368e99448ffSBalaji T K else 369e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 370e99448ffSBalaji T K VDD_3V0); 371e99448ffSBalaji T K if (ret < 0) 372e99448ffSBalaji T K goto error_set_power; 373e99448ffSBalaji T K 374e99448ffSBalaji T K if (host->pbias_enabled == 0) { 375e99448ffSBalaji T K ret = regulator_enable(host->pbias); 376e99448ffSBalaji T K if (!ret) 377e99448ffSBalaji T K host->pbias_enabled = 1; 378e99448ffSBalaji T K } 379e99448ffSBalaji T K } 380e99448ffSBalaji T K 381326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 38280412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 383db0fefc5SAdrian Hunter 384e99448ffSBalaji T K error_set_power: 385db0fefc5SAdrian Hunter return ret; 386db0fefc5SAdrian Hunter } 387db0fefc5SAdrian Hunter 388db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 389db0fefc5SAdrian Hunter { 390db0fefc5SAdrian Hunter struct regulator *reg; 39164be9782Skishore kadiyala int ocr_value = 0; 392db0fefc5SAdrian Hunter 393f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 394db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 395987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 396987fd49bSBalaji T K PTR_ERR(reg)); 3971fdc90fbSNeilBrown return PTR_ERR(reg); 398db0fefc5SAdrian Hunter } else { 399db0fefc5SAdrian Hunter host->vcc = reg; 40064be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 401326119c9SAndreas Fenkart if (!mmc_pdata(host)->ocr_mask) { 402326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 40364be9782Skishore kadiyala } else { 404326119c9SAndreas Fenkart if (!(mmc_pdata(host)->ocr_mask & ocr_value)) { 4052cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 406326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask); 407326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = 0; 40864be9782Skishore kadiyala return -EINVAL; 40964be9782Skishore kadiyala } 41064be9782Skishore kadiyala } 411987fd49bSBalaji T K } 412326119c9SAndreas Fenkart mmc_pdata(host)->set_power = omap_hsmmc_set_power; 413db0fefc5SAdrian Hunter 414db0fefc5SAdrian Hunter /* Allow an aux regulator */ 415f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 416db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 417db0fefc5SAdrian Hunter 418e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 419e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 420e99448ffSBalaji T K 421b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 422326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 423b1c1df7aSBalaji T K return 0; 424db0fefc5SAdrian Hunter /* 425987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 426987fd49bSBalaji T K * to increase usecount and then disable it. 427db0fefc5SAdrian Hunter */ 428987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 429e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 430326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 431e840ce13SAdrian Hunter 43280412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, vdd); 43380412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 434db0fefc5SAdrian Hunter } 435db0fefc5SAdrian Hunter 436db0fefc5SAdrian Hunter return 0; 437db0fefc5SAdrian Hunter } 438db0fefc5SAdrian Hunter 439db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 440db0fefc5SAdrian Hunter { 441326119c9SAndreas Fenkart mmc_pdata(host)->set_power = NULL; 442db0fefc5SAdrian Hunter } 443db0fefc5SAdrian Hunter 444b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 445b702b106SAdrian Hunter { 446b702b106SAdrian Hunter return 1; 447b702b106SAdrian Hunter } 448b702b106SAdrian Hunter 449b702b106SAdrian Hunter #else 450b702b106SAdrian Hunter 451b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 452b702b106SAdrian Hunter { 453b702b106SAdrian Hunter return -EINVAL; 454b702b106SAdrian Hunter } 455b702b106SAdrian Hunter 456b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 457b702b106SAdrian Hunter { 458b702b106SAdrian Hunter } 459b702b106SAdrian Hunter 460b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 461b702b106SAdrian Hunter { 462b702b106SAdrian Hunter return 0; 463b702b106SAdrian Hunter } 464b702b106SAdrian Hunter 465b702b106SAdrian Hunter #endif 466b702b106SAdrian Hunter 4671e363e3bSAndreas Fenkart static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host, 4681e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 469b702b106SAdrian Hunter { 470b702b106SAdrian Hunter int ret; 471b702b106SAdrian Hunter 472326119c9SAndreas Fenkart if (gpio_is_valid(pdata->switch_pin)) { 473326119c9SAndreas Fenkart if (pdata->cover) 474b5cd43f0SAndreas Fenkart host->get_cover_state = 475b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 476b702b106SAdrian Hunter else 477b5cd43f0SAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 478b5cd43f0SAndreas Fenkart host->card_detect_irq = 479326119c9SAndreas Fenkart gpio_to_irq(pdata->switch_pin); 480326119c9SAndreas Fenkart ret = gpio_request(pdata->switch_pin, "mmc_cd"); 481b702b106SAdrian Hunter if (ret) 482b702b106SAdrian Hunter return ret; 483326119c9SAndreas Fenkart ret = gpio_direction_input(pdata->switch_pin); 484b702b106SAdrian Hunter if (ret) 485b702b106SAdrian Hunter goto err_free_sp; 486326119c9SAndreas Fenkart } else { 487326119c9SAndreas Fenkart pdata->switch_pin = -EINVAL; 488326119c9SAndreas Fenkart } 489b702b106SAdrian Hunter 490326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 491b5cd43f0SAndreas Fenkart host->get_ro = omap_hsmmc_get_wp; 492326119c9SAndreas Fenkart ret = gpio_request(pdata->gpio_wp, "mmc_wp"); 493b702b106SAdrian Hunter if (ret) 494b702b106SAdrian Hunter goto err_free_cd; 495326119c9SAndreas Fenkart ret = gpio_direction_input(pdata->gpio_wp); 496b702b106SAdrian Hunter if (ret) 497b702b106SAdrian Hunter goto err_free_wp; 498326119c9SAndreas Fenkart } else { 499326119c9SAndreas Fenkart pdata->gpio_wp = -EINVAL; 500326119c9SAndreas Fenkart } 501b702b106SAdrian Hunter 502b702b106SAdrian Hunter return 0; 503b702b106SAdrian Hunter 504b702b106SAdrian Hunter err_free_wp: 505326119c9SAndreas Fenkart gpio_free(pdata->gpio_wp); 506b702b106SAdrian Hunter err_free_cd: 507326119c9SAndreas Fenkart if (gpio_is_valid(pdata->switch_pin)) 508b702b106SAdrian Hunter err_free_sp: 509326119c9SAndreas Fenkart gpio_free(pdata->switch_pin); 510b702b106SAdrian Hunter return ret; 511b702b106SAdrian Hunter } 512b702b106SAdrian Hunter 5131e363e3bSAndreas Fenkart static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host, 5141e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 515b702b106SAdrian Hunter { 516326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) 517326119c9SAndreas Fenkart gpio_free(pdata->gpio_wp); 518326119c9SAndreas Fenkart if (gpio_is_valid(pdata->switch_pin)) 519326119c9SAndreas Fenkart gpio_free(pdata->switch_pin); 520b702b106SAdrian Hunter } 521b702b106SAdrian Hunter 522a45c6cb8SMadhusudhan Chikkature /* 523e0c7f99bSAndy Shevchenko * Start clock to the card 524e0c7f99bSAndy Shevchenko */ 525e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 526e0c7f99bSAndy Shevchenko { 527e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 528e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 529e0c7f99bSAndy Shevchenko } 530e0c7f99bSAndy Shevchenko 531e0c7f99bSAndy Shevchenko /* 532a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 533a45c6cb8SMadhusudhan Chikkature */ 53470a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 535a45c6cb8SMadhusudhan Chikkature { 536a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 537a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 538a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5397122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 540a45c6cb8SMadhusudhan Chikkature } 541a45c6cb8SMadhusudhan Chikkature 54293caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 54393caf8e6SAdrian Hunter struct mmc_command *cmd) 544b417577dSAdrian Hunter { 5452cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5462cd3a2a5SAndreas Fenkart unsigned long flags; 547b417577dSAdrian Hunter 548b417577dSAdrian Hunter if (host->use_dma) 5492cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 550b417577dSAdrian Hunter 55193caf8e6SAdrian Hunter /* Disable timeout for erases */ 55293caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 553a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 55493caf8e6SAdrian Hunter 5552cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 556b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 557b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5582cd3a2a5SAndreas Fenkart 5592cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5602cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5612cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 562b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5632cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 564b417577dSAdrian Hunter } 565b417577dSAdrian Hunter 566b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 567b417577dSAdrian Hunter { 5682cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5692cd3a2a5SAndreas Fenkart unsigned long flags; 5702cd3a2a5SAndreas Fenkart 5712cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5722cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5732cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5742cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5752cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5762cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 577b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5782cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 579b417577dSAdrian Hunter } 580b417577dSAdrian Hunter 581ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 582d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 583ac330f44SAndy Shevchenko { 584ac330f44SAndy Shevchenko u16 dsor = 0; 585ac330f44SAndy Shevchenko 586ac330f44SAndy Shevchenko if (ios->clock) { 587d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 588ed164182SBalaji T K if (dsor > CLKD_MAX) 589ed164182SBalaji T K dsor = CLKD_MAX; 590ac330f44SAndy Shevchenko } 591ac330f44SAndy Shevchenko 592ac330f44SAndy Shevchenko return dsor; 593ac330f44SAndy Shevchenko } 594ac330f44SAndy Shevchenko 5955934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5965934df2fSAndy Shevchenko { 5975934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5985934df2fSAndy Shevchenko unsigned long regval; 5995934df2fSAndy Shevchenko unsigned long timeout; 600cd587096SHebbar, Gururaja unsigned long clkdiv; 6015934df2fSAndy Shevchenko 6028986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6035934df2fSAndy Shevchenko 6045934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6055934df2fSAndy Shevchenko 6065934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6075934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 608cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 609cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6105934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6115934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6125934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6135934df2fSAndy Shevchenko 6145934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6155934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6165934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6175934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6185934df2fSAndy Shevchenko cpu_relax(); 6195934df2fSAndy Shevchenko 620cd587096SHebbar, Gururaja /* 621cd587096SHebbar, Gururaja * Enable High-Speed Support 622cd587096SHebbar, Gururaja * Pre-Requisites 623cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 624cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 625cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 626cd587096SHebbar, Gururaja * in capabilities register 627cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 628cd587096SHebbar, Gururaja */ 629326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6305438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 631cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 632cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 633cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 634cd587096SHebbar, Gururaja regval |= HSPE; 635cd587096SHebbar, Gururaja else 636cd587096SHebbar, Gururaja regval &= ~HSPE; 637cd587096SHebbar, Gururaja 638cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 639cd587096SHebbar, Gururaja } 640cd587096SHebbar, Gururaja 6415934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6425934df2fSAndy Shevchenko } 6435934df2fSAndy Shevchenko 6443796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6453796fb8aSAndy Shevchenko { 6463796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6473796fb8aSAndy Shevchenko u32 con; 6483796fb8aSAndy Shevchenko 6493796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6505438ad95SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) 65103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 65203b5d924SBalaji T K else 65303b5d924SBalaji T K con &= ~DDR; 6543796fb8aSAndy Shevchenko switch (ios->bus_width) { 6553796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6563796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6573796fb8aSAndy Shevchenko break; 6583796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6593796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6603796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6613796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6623796fb8aSAndy Shevchenko break; 6633796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6643796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6653796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6663796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6673796fb8aSAndy Shevchenko break; 6683796fb8aSAndy Shevchenko } 6693796fb8aSAndy Shevchenko } 6703796fb8aSAndy Shevchenko 6713796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6723796fb8aSAndy Shevchenko { 6733796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6743796fb8aSAndy Shevchenko u32 con; 6753796fb8aSAndy Shevchenko 6763796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6773796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6783796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6793796fb8aSAndy Shevchenko else 6803796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6813796fb8aSAndy Shevchenko } 6823796fb8aSAndy Shevchenko 68311dd62a7SDenis Karpov #ifdef CONFIG_PM 68411dd62a7SDenis Karpov 68511dd62a7SDenis Karpov /* 68611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 68711dd62a7SDenis Karpov * power state change. 68811dd62a7SDenis Karpov */ 68970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 69011dd62a7SDenis Karpov { 69111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6923796fb8aSAndy Shevchenko u32 hctl, capa; 69311dd62a7SDenis Karpov unsigned long timeout; 69411dd62a7SDenis Karpov 6950a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6960a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6970a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6980a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6990a82e06eSTony Lindgren return 0; 7000a82e06eSTony Lindgren 7010a82e06eSTony Lindgren host->context_loss++; 7020a82e06eSTony Lindgren 703c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 70411dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 70511dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 70611dd62a7SDenis Karpov hctl = SDVS18; 70711dd62a7SDenis Karpov else 70811dd62a7SDenis Karpov hctl = SDVS30; 70911dd62a7SDenis Karpov capa = VS30 | VS18; 71011dd62a7SDenis Karpov } else { 71111dd62a7SDenis Karpov hctl = SDVS18; 71211dd62a7SDenis Karpov capa = VS18; 71311dd62a7SDenis Karpov } 71411dd62a7SDenis Karpov 7155a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7165a52b08bSBalaji T K hctl |= IWE; 7175a52b08bSBalaji T K 71811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 71911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 72011dd62a7SDenis Karpov 72111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 72211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 72311dd62a7SDenis Karpov 72411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 72511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 72611dd62a7SDenis Karpov 72711dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 72811dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 72911dd62a7SDenis Karpov && time_before(jiffies, timeout)) 73011dd62a7SDenis Karpov ; 73111dd62a7SDenis Karpov 7322cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7332cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7342cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 73511dd62a7SDenis Karpov 73611dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 73711dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 73811dd62a7SDenis Karpov goto out; 73911dd62a7SDenis Karpov 7403796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 74111dd62a7SDenis Karpov 7425934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 74311dd62a7SDenis Karpov 7443796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7453796fb8aSAndy Shevchenko 74611dd62a7SDenis Karpov out: 7470a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7480a82e06eSTony Lindgren host->context_loss); 74911dd62a7SDenis Karpov return 0; 75011dd62a7SDenis Karpov } 75111dd62a7SDenis Karpov 75211dd62a7SDenis Karpov /* 75311dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 75411dd62a7SDenis Karpov */ 75570a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 75611dd62a7SDenis Karpov { 7570a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7580a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7590a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7600a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 76111dd62a7SDenis Karpov } 76211dd62a7SDenis Karpov 76311dd62a7SDenis Karpov #else 76411dd62a7SDenis Karpov 76570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 76611dd62a7SDenis Karpov { 76711dd62a7SDenis Karpov return 0; 76811dd62a7SDenis Karpov } 76911dd62a7SDenis Karpov 77070a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 77111dd62a7SDenis Karpov { 77211dd62a7SDenis Karpov } 77311dd62a7SDenis Karpov 77411dd62a7SDenis Karpov #endif 77511dd62a7SDenis Karpov 776a45c6cb8SMadhusudhan Chikkature /* 777a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 778a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 779a45c6cb8SMadhusudhan Chikkature */ 78070a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 781a45c6cb8SMadhusudhan Chikkature { 782a45c6cb8SMadhusudhan Chikkature int reg = 0; 783a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 784a45c6cb8SMadhusudhan Chikkature 785b62f6228SAdrian Hunter if (host->protect_card) 786b62f6228SAdrian Hunter return; 787b62f6228SAdrian Hunter 788a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 789b417577dSAdrian Hunter 790b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 791a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 792a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 793a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 794a45c6cb8SMadhusudhan Chikkature 795a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 796a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 797a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 798a45c6cb8SMadhusudhan Chikkature 799a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 800a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 801c653a6d4SAdrian Hunter 802c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 803c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 804c653a6d4SAdrian Hunter 805a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 806a45c6cb8SMadhusudhan Chikkature } 807a45c6cb8SMadhusudhan Chikkature 808a45c6cb8SMadhusudhan Chikkature static inline 80970a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 810a45c6cb8SMadhusudhan Chikkature { 811a45c6cb8SMadhusudhan Chikkature int r = 1; 812a45c6cb8SMadhusudhan Chikkature 813b5cd43f0SAndreas Fenkart if (host->get_cover_state) 81480412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 815a45c6cb8SMadhusudhan Chikkature return r; 816a45c6cb8SMadhusudhan Chikkature } 817a45c6cb8SMadhusudhan Chikkature 818a45c6cb8SMadhusudhan Chikkature static ssize_t 81970a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 820a45c6cb8SMadhusudhan Chikkature char *buf) 821a45c6cb8SMadhusudhan Chikkature { 822a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 82370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 824a45c6cb8SMadhusudhan Chikkature 82570a3341aSDenis Karpov return sprintf(buf, "%s\n", 82670a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 827a45c6cb8SMadhusudhan Chikkature } 828a45c6cb8SMadhusudhan Chikkature 82970a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 830a45c6cb8SMadhusudhan Chikkature 831a45c6cb8SMadhusudhan Chikkature static ssize_t 83270a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 833a45c6cb8SMadhusudhan Chikkature char *buf) 834a45c6cb8SMadhusudhan Chikkature { 835a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 83670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 837a45c6cb8SMadhusudhan Chikkature 838326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 839a45c6cb8SMadhusudhan Chikkature } 840a45c6cb8SMadhusudhan Chikkature 84170a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 842a45c6cb8SMadhusudhan Chikkature 843a45c6cb8SMadhusudhan Chikkature /* 844a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 845a45c6cb8SMadhusudhan Chikkature */ 846a45c6cb8SMadhusudhan Chikkature static void 84770a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 848a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 849a45c6cb8SMadhusudhan Chikkature { 850a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 851a45c6cb8SMadhusudhan Chikkature 8528986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 853a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 854a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 855a45c6cb8SMadhusudhan Chikkature 85693caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 857a45c6cb8SMadhusudhan Chikkature 8584a694dc9SAdrian Hunter host->response_busy = 0; 859a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 860a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 861a45c6cb8SMadhusudhan Chikkature resptype = 1; 8624a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8634a694dc9SAdrian Hunter resptype = 3; 8644a694dc9SAdrian Hunter host->response_busy = 1; 8654a694dc9SAdrian Hunter } else 866a45c6cb8SMadhusudhan Chikkature resptype = 2; 867a45c6cb8SMadhusudhan Chikkature } 868a45c6cb8SMadhusudhan Chikkature 869a45c6cb8SMadhusudhan Chikkature /* 870a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 871a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 872a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 873a45c6cb8SMadhusudhan Chikkature */ 874a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 875a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 876a45c6cb8SMadhusudhan Chikkature 877a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 878a45c6cb8SMadhusudhan Chikkature 879a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 880a2e77152SBalaji T K host->mrq->sbc) { 881a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 882a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 883a2e77152SBalaji T K } 884a45c6cb8SMadhusudhan Chikkature if (data) { 885a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 886a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 887a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 888a45c6cb8SMadhusudhan Chikkature else 889a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 890a45c6cb8SMadhusudhan Chikkature } 891a45c6cb8SMadhusudhan Chikkature 892a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 893a7e96879SVenkatraman S cmdreg |= DMAE; 894a45c6cb8SMadhusudhan Chikkature 895b417577dSAdrian Hunter host->req_in_progress = 1; 8964dffd7a2SAdrian Hunter 897a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 898a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 899a45c6cb8SMadhusudhan Chikkature } 900a45c6cb8SMadhusudhan Chikkature 9010ccd76d4SJuha Yrjola static int 90270a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9030ccd76d4SJuha Yrjola { 9040ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9050ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9060ccd76d4SJuha Yrjola else 9070ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9080ccd76d4SJuha Yrjola } 9090ccd76d4SJuha Yrjola 910c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 911c5c98927SRussell King struct mmc_data *data) 912c5c98927SRussell King { 913c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 914c5c98927SRussell King } 915c5c98927SRussell King 916b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 917b417577dSAdrian Hunter { 918b417577dSAdrian Hunter int dma_ch; 91931463b14SVenkatraman S unsigned long flags; 920b417577dSAdrian Hunter 92131463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 922b417577dSAdrian Hunter host->req_in_progress = 0; 923b417577dSAdrian Hunter dma_ch = host->dma_ch; 92431463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 925b417577dSAdrian Hunter 926b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 927b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 928b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 929b417577dSAdrian Hunter return; 930b417577dSAdrian Hunter host->mrq = NULL; 931b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 932b417577dSAdrian Hunter } 933b417577dSAdrian Hunter 934a45c6cb8SMadhusudhan Chikkature /* 935a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 936a45c6cb8SMadhusudhan Chikkature */ 937a45c6cb8SMadhusudhan Chikkature static void 93870a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 939a45c6cb8SMadhusudhan Chikkature { 9404a694dc9SAdrian Hunter if (!data) { 9414a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9424a694dc9SAdrian Hunter 94323050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 94423050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 94523050103SAdrian Hunter host->response_busy) { 94623050103SAdrian Hunter host->response_busy = 0; 94723050103SAdrian Hunter return; 94823050103SAdrian Hunter } 94923050103SAdrian Hunter 950b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9514a694dc9SAdrian Hunter return; 9524a694dc9SAdrian Hunter } 9534a694dc9SAdrian Hunter 954a45c6cb8SMadhusudhan Chikkature host->data = NULL; 955a45c6cb8SMadhusudhan Chikkature 956a45c6cb8SMadhusudhan Chikkature if (!data->error) 957a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 958a45c6cb8SMadhusudhan Chikkature else 959a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 960a45c6cb8SMadhusudhan Chikkature 961bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 962fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 963bf129e1cSBalaji T K else 964bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 965a45c6cb8SMadhusudhan Chikkature } 966a45c6cb8SMadhusudhan Chikkature 967a45c6cb8SMadhusudhan Chikkature /* 968a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 969a45c6cb8SMadhusudhan Chikkature */ 970a45c6cb8SMadhusudhan Chikkature static void 97170a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 972a45c6cb8SMadhusudhan Chikkature { 973bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 974a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9752177fa94SBalaji T K host->cmd = NULL; 976bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 977bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 978bf129e1cSBalaji T K host->mrq->data); 979bf129e1cSBalaji T K return; 980bf129e1cSBalaji T K } 981bf129e1cSBalaji T K 9822177fa94SBalaji T K host->cmd = NULL; 9832177fa94SBalaji T K 984a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 985a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 986a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 987a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 988a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 989a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 990a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 991a45c6cb8SMadhusudhan Chikkature } else { 992a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 993a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 994a45c6cb8SMadhusudhan Chikkature } 995a45c6cb8SMadhusudhan Chikkature } 996b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 997d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 998a45c6cb8SMadhusudhan Chikkature } 999a45c6cb8SMadhusudhan Chikkature 1000a45c6cb8SMadhusudhan Chikkature /* 1001a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1002a45c6cb8SMadhusudhan Chikkature */ 100370a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1004a45c6cb8SMadhusudhan Chikkature { 1005b417577dSAdrian Hunter int dma_ch; 100631463b14SVenkatraman S unsigned long flags; 1007b417577dSAdrian Hunter 100882788ff5SJarkko Lavinen host->data->error = errno; 1009a45c6cb8SMadhusudhan Chikkature 101031463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1011b417577dSAdrian Hunter dma_ch = host->dma_ch; 1012b417577dSAdrian Hunter host->dma_ch = -1; 101331463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1014b417577dSAdrian Hunter 1015b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1016c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1017c5c98927SRussell King 1018c5c98927SRussell King dmaengine_terminate_all(chan); 1019c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1020c5c98927SRussell King host->data->sg, host->data->sg_len, 102170a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1022c5c98927SRussell King 1023053bf34fSPer Forlin host->data->host_cookie = 0; 1024a45c6cb8SMadhusudhan Chikkature } 1025a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1026a45c6cb8SMadhusudhan Chikkature } 1027a45c6cb8SMadhusudhan Chikkature 1028a45c6cb8SMadhusudhan Chikkature /* 1029a45c6cb8SMadhusudhan Chikkature * Readable error output 1030a45c6cb8SMadhusudhan Chikkature */ 1031a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1032699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1033a45c6cb8SMadhusudhan Chikkature { 1034a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 103570a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1036699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1037699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1038699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1039699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1040a45c6cb8SMadhusudhan Chikkature }; 1041a45c6cb8SMadhusudhan Chikkature char res[256]; 1042a45c6cb8SMadhusudhan Chikkature char *buf = res; 1043a45c6cb8SMadhusudhan Chikkature int len, i; 1044a45c6cb8SMadhusudhan Chikkature 1045a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1046a45c6cb8SMadhusudhan Chikkature buf += len; 1047a45c6cb8SMadhusudhan Chikkature 104870a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1049a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 105070a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1051a45c6cb8SMadhusudhan Chikkature buf += len; 1052a45c6cb8SMadhusudhan Chikkature } 1053a45c6cb8SMadhusudhan Chikkature 10548986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1055a45c6cb8SMadhusudhan Chikkature } 1056699b958bSAdrian Hunter #else 1057699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1058699b958bSAdrian Hunter u32 status) 1059699b958bSAdrian Hunter { 1060699b958bSAdrian Hunter } 1061a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1062a45c6cb8SMadhusudhan Chikkature 10633ebf74b1SJean Pihet /* 10643ebf74b1SJean Pihet * MMC controller internal state machines reset 10653ebf74b1SJean Pihet * 10663ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10673ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10683ebf74b1SJean Pihet * Can be called from interrupt context 10693ebf74b1SJean Pihet */ 107070a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10713ebf74b1SJean Pihet unsigned long bit) 10723ebf74b1SJean Pihet { 10733ebf74b1SJean Pihet unsigned long i = 0; 10741e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10753ebf74b1SJean Pihet 10763ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10773ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10783ebf74b1SJean Pihet 107907ad64b6SMadhusudhan Chikkature /* 108007ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 108107ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 108207ad64b6SMadhusudhan Chikkature */ 1083326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1084b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 108507ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10861e881786SJianpeng Ma udelay(1); 108707ad64b6SMadhusudhan Chikkature } 108807ad64b6SMadhusudhan Chikkature i = 0; 108907ad64b6SMadhusudhan Chikkature 10903ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10913ebf74b1SJean Pihet (i++ < limit)) 10921e881786SJianpeng Ma udelay(1); 10933ebf74b1SJean Pihet 10943ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10953ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10963ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10973ebf74b1SJean Pihet __func__); 10983ebf74b1SJean Pihet } 1099a45c6cb8SMadhusudhan Chikkature 110025e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 110125e1897bSBalaji T K int err, int end_cmd) 1102ae4bf788SVenkatraman S { 110325e1897bSBalaji T K if (end_cmd) { 110494d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 110525e1897bSBalaji T K if (host->cmd) 1106ae4bf788SVenkatraman S host->cmd->error = err; 110725e1897bSBalaji T K } 1108ae4bf788SVenkatraman S 1109ae4bf788SVenkatraman S if (host->data) { 1110ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1111ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1112dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1113dc7745bdSBalaji T K host->mrq->cmd->error = err; 1114ae4bf788SVenkatraman S } 1115ae4bf788SVenkatraman S 1116b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1117a45c6cb8SMadhusudhan Chikkature { 1118a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1119b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1120a2e77152SBalaji T K int error = 0; 1121a45c6cb8SMadhusudhan Chikkature 1122a45c6cb8SMadhusudhan Chikkature data = host->data; 11238986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1124a45c6cb8SMadhusudhan Chikkature 1125a7e96879SVenkatraman S if (status & ERR_EN) { 1126699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11274a694dc9SAdrian Hunter 1128a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1129a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1130a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 113125e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1132a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 113325e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 113425e1897bSBalaji T K 1135a2e77152SBalaji T K if (status & ACE_EN) { 1136a2e77152SBalaji T K u32 ac12; 1137a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1138a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1139a2e77152SBalaji T K end_cmd = 1; 1140a2e77152SBalaji T K if (ac12 & ACTO) 1141a2e77152SBalaji T K error = -ETIMEDOUT; 1142a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1143a2e77152SBalaji T K error = -EILSEQ; 1144a2e77152SBalaji T K host->mrq->sbc->error = error; 1145a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1146a2e77152SBalaji T K } 1147a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1148a2e77152SBalaji T K } 1149ae4bf788SVenkatraman S if (host->data || host->response_busy) { 115025e1897bSBalaji T K end_trans = !end_cmd; 1151ae4bf788SVenkatraman S host->response_busy = 0; 1152a45c6cb8SMadhusudhan Chikkature } 1153a45c6cb8SMadhusudhan Chikkature } 1154a45c6cb8SMadhusudhan Chikkature 11557472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1156a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 115770a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1158a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 115970a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1160b417577dSAdrian Hunter } 1161a45c6cb8SMadhusudhan Chikkature 1162b417577dSAdrian Hunter /* 1163b417577dSAdrian Hunter * MMC controller IRQ handler 1164b417577dSAdrian Hunter */ 1165b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1166b417577dSAdrian Hunter { 1167b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1168b417577dSAdrian Hunter int status; 1169b417577dSAdrian Hunter 1170b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11712cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11722cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1173b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11741f6b9fa4SVenkatraman S 11752cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11762cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11772cd3a2a5SAndreas Fenkart 1178b417577dSAdrian Hunter /* Flush posted write */ 1179b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11801f6b9fa4SVenkatraman S } 11814dffd7a2SAdrian Hunter 1182a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1183a45c6cb8SMadhusudhan Chikkature } 1184a45c6cb8SMadhusudhan Chikkature 11852cd3a2a5SAndreas Fenkart static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) 11862cd3a2a5SAndreas Fenkart { 11872cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 11882cd3a2a5SAndreas Fenkart 11892cd3a2a5SAndreas Fenkart /* cirq is level triggered, disable to avoid infinite loop */ 11902cd3a2a5SAndreas Fenkart spin_lock(&host->irq_lock); 11912cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 11922cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 11932cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 11942cd3a2a5SAndreas Fenkart } 11952cd3a2a5SAndreas Fenkart spin_unlock(&host->irq_lock); 11962cd3a2a5SAndreas Fenkart pm_request_resume(host->dev); /* no use counter */ 11972cd3a2a5SAndreas Fenkart 11982cd3a2a5SAndreas Fenkart return IRQ_HANDLED; 11992cd3a2a5SAndreas Fenkart } 12002cd3a2a5SAndreas Fenkart 120170a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1202e13bb300SAdrian Hunter { 1203e13bb300SAdrian Hunter unsigned long i; 1204e13bb300SAdrian Hunter 1205e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1206e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1207e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1208e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1209e13bb300SAdrian Hunter break; 1210e13bb300SAdrian Hunter cpu_relax(); 1211e13bb300SAdrian Hunter } 1212e13bb300SAdrian Hunter } 1213e13bb300SAdrian Hunter 1214a45c6cb8SMadhusudhan Chikkature /* 1215eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1216eb250826SDavid Brownell * 1217eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1218eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1219eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1220a45c6cb8SMadhusudhan Chikkature */ 122170a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1222a45c6cb8SMadhusudhan Chikkature { 1223a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1224a45c6cb8SMadhusudhan Chikkature int ret; 1225a45c6cb8SMadhusudhan Chikkature 1226a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1227fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1228cd03d9a8SRajendra Nayak if (host->dbclk) 122994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1230a45c6cb8SMadhusudhan Chikkature 1231a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 123280412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 0, 0); 1233a45c6cb8SMadhusudhan Chikkature 1234a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12352bec0893SAdrian Hunter if (!ret) 123680412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 1, vdd); 1237fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1238cd03d9a8SRajendra Nayak if (host->dbclk) 123994c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12402bec0893SAdrian Hunter 1241a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1242a45c6cb8SMadhusudhan Chikkature goto err; 1243a45c6cb8SMadhusudhan Chikkature 1244a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1245a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1246a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1247eb250826SDavid Brownell 1248a45c6cb8SMadhusudhan Chikkature /* 1249a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1250a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 125170a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1252a45c6cb8SMadhusudhan Chikkature * 1253eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1254eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1255eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1256eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1257eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1258eb250826SDavid Brownell * 1259eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1260eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1261eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1262a45c6cb8SMadhusudhan Chikkature */ 1263eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1264a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1265eb250826SDavid Brownell else 1266eb250826SDavid Brownell reg_val |= SDVS30; 1267a45c6cb8SMadhusudhan Chikkature 1268a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1269e13bb300SAdrian Hunter set_sd_bus_power(host); 1270a45c6cb8SMadhusudhan Chikkature 1271a45c6cb8SMadhusudhan Chikkature return 0; 1272a45c6cb8SMadhusudhan Chikkature err: 1273b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1274a45c6cb8SMadhusudhan Chikkature return ret; 1275a45c6cb8SMadhusudhan Chikkature } 1276a45c6cb8SMadhusudhan Chikkature 1277b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1278b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1279b62f6228SAdrian Hunter { 1280b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1281b62f6228SAdrian Hunter return; 1282b62f6228SAdrian Hunter 1283b62f6228SAdrian Hunter host->reqs_blocked = 0; 128480412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1285b62f6228SAdrian Hunter if (host->protect_card) { 12862cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1287b62f6228SAdrian Hunter "card is now accessible\n", 1288b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1289b62f6228SAdrian Hunter host->protect_card = 0; 1290b62f6228SAdrian Hunter } 1291b62f6228SAdrian Hunter } else { 1292b62f6228SAdrian Hunter if (!host->protect_card) { 12932cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1294b62f6228SAdrian Hunter "card is now inaccessible\n", 1295b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1296b62f6228SAdrian Hunter host->protect_card = 1; 1297b62f6228SAdrian Hunter } 1298b62f6228SAdrian Hunter } 1299b62f6228SAdrian Hunter } 1300b62f6228SAdrian Hunter 1301a45c6cb8SMadhusudhan Chikkature /* 13027efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1303a45c6cb8SMadhusudhan Chikkature */ 13047efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1305a45c6cb8SMadhusudhan Chikkature { 13067efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1307a6b2240dSAdrian Hunter int carddetect; 1308249d0fa9SDavid Brownell 1309a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1310a6b2240dSAdrian Hunter 1311b5cd43f0SAndreas Fenkart if (host->card_detect) 131280412ca8SAndreas Fenkart carddetect = host->card_detect(host->dev); 1313b62f6228SAdrian Hunter else { 1314b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1315a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1316b62f6228SAdrian Hunter } 1317a6b2240dSAdrian Hunter 1318cdeebaddSMadhusudhan Chikkature if (carddetect) 1319a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1320cdeebaddSMadhusudhan Chikkature else 1321a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1322a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1323a45c6cb8SMadhusudhan Chikkature } 1324a45c6cb8SMadhusudhan Chikkature 1325c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13260ccd76d4SJuha Yrjola { 1327c5c98927SRussell King struct omap_hsmmc_host *host = param; 1328c5c98927SRussell King struct dma_chan *chan; 1329770d7432SAdrian Hunter struct mmc_data *data; 1330c5c98927SRussell King int req_in_progress; 1331a45c6cb8SMadhusudhan Chikkature 1332c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1333b417577dSAdrian Hunter if (host->dma_ch < 0) { 1334c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1335a45c6cb8SMadhusudhan Chikkature return; 1336b417577dSAdrian Hunter } 1337a45c6cb8SMadhusudhan Chikkature 1338770d7432SAdrian Hunter data = host->mrq->data; 1339c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13409782aff8SPer Forlin if (!data->host_cookie) 1341c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1342c5c98927SRussell King data->sg, data->sg_len, 1343b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1344b417577dSAdrian Hunter 1345b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1346a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1347c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1348b417577dSAdrian Hunter 1349b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1350b417577dSAdrian Hunter if (!req_in_progress) { 1351b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1352b417577dSAdrian Hunter 1353b417577dSAdrian Hunter host->mrq = NULL; 1354b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1355b417577dSAdrian Hunter } 1356a45c6cb8SMadhusudhan Chikkature } 1357a45c6cb8SMadhusudhan Chikkature 13589782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13599782aff8SPer Forlin struct mmc_data *data, 1360c5c98927SRussell King struct omap_hsmmc_next *next, 136126b88520SRussell King struct dma_chan *chan) 13629782aff8SPer Forlin { 13639782aff8SPer Forlin int dma_len; 13649782aff8SPer Forlin 13659782aff8SPer Forlin if (!next && data->host_cookie && 13669782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13672cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13689782aff8SPer Forlin " host->next_data.cookie %d\n", 13699782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13709782aff8SPer Forlin data->host_cookie = 0; 13719782aff8SPer Forlin } 13729782aff8SPer Forlin 13739782aff8SPer Forlin /* Check if next job is already prepared */ 1374b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 137526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13769782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13779782aff8SPer Forlin 13789782aff8SPer Forlin } else { 13799782aff8SPer Forlin dma_len = host->next_data.dma_len; 13809782aff8SPer Forlin host->next_data.dma_len = 0; 13819782aff8SPer Forlin } 13829782aff8SPer Forlin 13839782aff8SPer Forlin 13849782aff8SPer Forlin if (dma_len == 0) 13859782aff8SPer Forlin return -EINVAL; 13869782aff8SPer Forlin 13879782aff8SPer Forlin if (next) { 13889782aff8SPer Forlin next->dma_len = dma_len; 13899782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13909782aff8SPer Forlin } else 13919782aff8SPer Forlin host->dma_len = dma_len; 13929782aff8SPer Forlin 13939782aff8SPer Forlin return 0; 13949782aff8SPer Forlin } 13959782aff8SPer Forlin 1396a45c6cb8SMadhusudhan Chikkature /* 1397a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1398a45c6cb8SMadhusudhan Chikkature */ 13999d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 140070a3341aSDenis Karpov struct mmc_request *req) 1401a45c6cb8SMadhusudhan Chikkature { 140226b88520SRussell King struct dma_slave_config cfg; 140326b88520SRussell King struct dma_async_tx_descriptor *tx; 140426b88520SRussell King int ret = 0, i; 1405a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1406c5c98927SRussell King struct dma_chan *chan; 1407a45c6cb8SMadhusudhan Chikkature 14080ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1409a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14100ccd76d4SJuha Yrjola struct scatterlist *sgl; 14110ccd76d4SJuha Yrjola 14120ccd76d4SJuha Yrjola sgl = data->sg + i; 14130ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14140ccd76d4SJuha Yrjola return -EINVAL; 14150ccd76d4SJuha Yrjola } 14160ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14170ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14180ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14190ccd76d4SJuha Yrjola */ 14200ccd76d4SJuha Yrjola return -EINVAL; 14210ccd76d4SJuha Yrjola 1422b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1423a45c6cb8SMadhusudhan Chikkature 1424c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1425c5c98927SRussell King 1426c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1427c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1428c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1429c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1430c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1431c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1432c5c98927SRussell King 1433c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14349782aff8SPer Forlin if (ret) 14359782aff8SPer Forlin return ret; 1436a45c6cb8SMadhusudhan Chikkature 143726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1438c5c98927SRussell King if (ret) 1439c5c98927SRussell King return ret; 1440a45c6cb8SMadhusudhan Chikkature 1441c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1442c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1443c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1444c5c98927SRussell King if (!tx) { 1445c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1446c5c98927SRussell King /* FIXME: cleanup */ 1447c5c98927SRussell King return -1; 1448c5c98927SRussell King } 1449c5c98927SRussell King 1450c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1451c5c98927SRussell King tx->callback_param = host; 1452c5c98927SRussell King 1453c5c98927SRussell King /* Does not fail */ 1454c5c98927SRussell King dmaengine_submit(tx); 1455c5c98927SRussell King 145626b88520SRussell King host->dma_ch = 1; 1457c5c98927SRussell King 1458a45c6cb8SMadhusudhan Chikkature return 0; 1459a45c6cb8SMadhusudhan Chikkature } 1460a45c6cb8SMadhusudhan Chikkature 146170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1462e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1463e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1464a45c6cb8SMadhusudhan Chikkature { 1465a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1466a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1467a45c6cb8SMadhusudhan Chikkature 1468a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1469a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1470a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1471a45c6cb8SMadhusudhan Chikkature clkd = 1; 1472a45c6cb8SMadhusudhan Chikkature 14736e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1474e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1475e2bf08d6SAdrian Hunter timeout += timeout_clks; 1476a45c6cb8SMadhusudhan Chikkature if (timeout) { 1477a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1478a45c6cb8SMadhusudhan Chikkature dto += 1; 1479a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1480a45c6cb8SMadhusudhan Chikkature } 1481a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1482a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1483a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1484a45c6cb8SMadhusudhan Chikkature dto += 1; 1485a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1486a45c6cb8SMadhusudhan Chikkature dto -= 13; 1487a45c6cb8SMadhusudhan Chikkature else 1488a45c6cb8SMadhusudhan Chikkature dto = 0; 1489a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1490a45c6cb8SMadhusudhan Chikkature dto = 14; 1491a45c6cb8SMadhusudhan Chikkature } 1492a45c6cb8SMadhusudhan Chikkature 1493a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1494a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1495a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1496a45c6cb8SMadhusudhan Chikkature } 1497a45c6cb8SMadhusudhan Chikkature 14989d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14999d025334SBalaji T K { 15009d025334SBalaji T K struct mmc_request *req = host->mrq; 15019d025334SBalaji T K struct dma_chan *chan; 15029d025334SBalaji T K 15039d025334SBalaji T K if (!req->data) 15049d025334SBalaji T K return; 15059d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 15069d025334SBalaji T K | (req->data->blocks << 16)); 15079d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 15089d025334SBalaji T K req->data->timeout_clks); 15099d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 15109d025334SBalaji T K dma_async_issue_pending(chan); 15119d025334SBalaji T K } 15129d025334SBalaji T K 1513a45c6cb8SMadhusudhan Chikkature /* 1514a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1515a45c6cb8SMadhusudhan Chikkature */ 1516a45c6cb8SMadhusudhan Chikkature static int 151770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1518a45c6cb8SMadhusudhan Chikkature { 1519a45c6cb8SMadhusudhan Chikkature int ret; 1520a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1521a45c6cb8SMadhusudhan Chikkature 1522a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1523a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1524e2bf08d6SAdrian Hunter /* 1525e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1526e2bf08d6SAdrian Hunter * busy signal. 1527e2bf08d6SAdrian Hunter */ 1528e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1529e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1530a45c6cb8SMadhusudhan Chikkature return 0; 1531a45c6cb8SMadhusudhan Chikkature } 1532a45c6cb8SMadhusudhan Chikkature 1533a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15349d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1535a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1536b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1537a45c6cb8SMadhusudhan Chikkature return ret; 1538a45c6cb8SMadhusudhan Chikkature } 1539a45c6cb8SMadhusudhan Chikkature } 1540a45c6cb8SMadhusudhan Chikkature return 0; 1541a45c6cb8SMadhusudhan Chikkature } 1542a45c6cb8SMadhusudhan Chikkature 15439782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15449782aff8SPer Forlin int err) 15459782aff8SPer Forlin { 15469782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15479782aff8SPer Forlin struct mmc_data *data = mrq->data; 15489782aff8SPer Forlin 154926b88520SRussell King if (host->use_dma && data->host_cookie) { 1550c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1551c5c98927SRussell King 155226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15539782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15549782aff8SPer Forlin data->host_cookie = 0; 15559782aff8SPer Forlin } 15569782aff8SPer Forlin } 15579782aff8SPer Forlin 15589782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15599782aff8SPer Forlin bool is_first_req) 15609782aff8SPer Forlin { 15619782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15629782aff8SPer Forlin 15639782aff8SPer Forlin if (mrq->data->host_cookie) { 15649782aff8SPer Forlin mrq->data->host_cookie = 0; 15659782aff8SPer Forlin return ; 15669782aff8SPer Forlin } 15679782aff8SPer Forlin 1568c5c98927SRussell King if (host->use_dma) { 1569c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1570c5c98927SRussell King 15719782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 157226b88520SRussell King &host->next_data, c)) 15739782aff8SPer Forlin mrq->data->host_cookie = 0; 15749782aff8SPer Forlin } 1575c5c98927SRussell King } 15769782aff8SPer Forlin 1577a45c6cb8SMadhusudhan Chikkature /* 1578a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1579a45c6cb8SMadhusudhan Chikkature */ 158070a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1581a45c6cb8SMadhusudhan Chikkature { 158270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1583a3f406f8SJarkko Lavinen int err; 1584a45c6cb8SMadhusudhan Chikkature 1585b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1586b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1587b62f6228SAdrian Hunter if (host->protect_card) { 1588b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1589b62f6228SAdrian Hunter /* 1590b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1591b62f6228SAdrian Hunter * state by resetting the command and data state 1592b62f6228SAdrian Hunter * machines. 1593b62f6228SAdrian Hunter */ 1594b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1595b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1596b62f6228SAdrian Hunter host->reqs_blocked += 1; 1597b62f6228SAdrian Hunter } 1598b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1599b62f6228SAdrian Hunter if (req->data) 1600b62f6228SAdrian Hunter req->data->error = -EBADF; 1601b417577dSAdrian Hunter req->cmd->retries = 0; 1602b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1603b62f6228SAdrian Hunter return; 1604b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1605b62f6228SAdrian Hunter host->reqs_blocked = 0; 1606a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1607a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16086e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 160970a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1610a3f406f8SJarkko Lavinen if (err) { 1611a3f406f8SJarkko Lavinen req->cmd->error = err; 1612a3f406f8SJarkko Lavinen if (req->data) 1613a3f406f8SJarkko Lavinen req->data->error = err; 1614a3f406f8SJarkko Lavinen host->mrq = NULL; 1615a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1616a3f406f8SJarkko Lavinen return; 1617a3f406f8SJarkko Lavinen } 1618a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1619bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1620bf129e1cSBalaji T K return; 1621bf129e1cSBalaji T K } 1622a3f406f8SJarkko Lavinen 16239d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 162470a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1625a45c6cb8SMadhusudhan Chikkature } 1626a45c6cb8SMadhusudhan Chikkature 1627a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 162870a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1629a45c6cb8SMadhusudhan Chikkature { 163070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1631a3621465SAdrian Hunter int do_send_init_stream = 0; 1632a45c6cb8SMadhusudhan Chikkature 1633fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16345e2ea617SAdrian Hunter 1635a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1636a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1637a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 163880412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 1639a45c6cb8SMadhusudhan Chikkature break; 1640a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 164180412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, ios->vdd); 1642a45c6cb8SMadhusudhan Chikkature break; 1643a3621465SAdrian Hunter case MMC_POWER_ON: 1644a3621465SAdrian Hunter do_send_init_stream = 1; 1645a3621465SAdrian Hunter break; 1646a3621465SAdrian Hunter } 1647a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1648a45c6cb8SMadhusudhan Chikkature } 1649a45c6cb8SMadhusudhan Chikkature 1650dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1651dd498effSDenis Karpov 16523796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1653a45c6cb8SMadhusudhan Chikkature 16544621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1655eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1656eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1657eb250826SDavid Brownell */ 1658a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16592cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1660a45c6cb8SMadhusudhan Chikkature /* 1661a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1662a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1663a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1664a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1665a45c6cb8SMadhusudhan Chikkature */ 166670a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1667a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1668a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1669a45c6cb8SMadhusudhan Chikkature } 1670a45c6cb8SMadhusudhan Chikkature } 1671a45c6cb8SMadhusudhan Chikkature 16725934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1673a45c6cb8SMadhusudhan Chikkature 1674a3621465SAdrian Hunter if (do_send_init_stream) 1675a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1676a45c6cb8SMadhusudhan Chikkature 16773796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16785e2ea617SAdrian Hunter 1679fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1680a45c6cb8SMadhusudhan Chikkature } 1681a45c6cb8SMadhusudhan Chikkature 1682a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1683a45c6cb8SMadhusudhan Chikkature { 168470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1685a45c6cb8SMadhusudhan Chikkature 1686b5cd43f0SAndreas Fenkart if (!host->card_detect) 1687a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 168880412ca8SAndreas Fenkart return host->card_detect(host->dev); 1689a45c6cb8SMadhusudhan Chikkature } 1690a45c6cb8SMadhusudhan Chikkature 1691a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1692a45c6cb8SMadhusudhan Chikkature { 169370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1694a45c6cb8SMadhusudhan Chikkature 1695b5cd43f0SAndreas Fenkart if (!host->get_ro) 1696a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 169780412ca8SAndreas Fenkart return host->get_ro(host->dev); 1698a45c6cb8SMadhusudhan Chikkature } 1699a45c6cb8SMadhusudhan Chikkature 17004816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17014816858cSGrazvydas Ignotas { 17024816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17034816858cSGrazvydas Ignotas 1704326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1705326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 17064816858cSGrazvydas Ignotas } 17074816858cSGrazvydas Ignotas 17082cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 17092cd3a2a5SAndreas Fenkart { 17102cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 17115a52b08bSBalaji T K u32 irq_mask, con; 17122cd3a2a5SAndreas Fenkart unsigned long flags; 17132cd3a2a5SAndreas Fenkart 17142cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17152cd3a2a5SAndreas Fenkart 17165a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17172cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17182cd3a2a5SAndreas Fenkart if (enable) { 17192cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17202cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17215a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17222cd3a2a5SAndreas Fenkart } else { 17232cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17242cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17255a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17262cd3a2a5SAndreas Fenkart } 17275a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17282cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17292cd3a2a5SAndreas Fenkart 17302cd3a2a5SAndreas Fenkart /* 17312cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17322cd3a2a5SAndreas Fenkart * but always disable immediately 17332cd3a2a5SAndreas Fenkart */ 17342cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17352cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17362cd3a2a5SAndreas Fenkart 17372cd3a2a5SAndreas Fenkart /* flush posted write */ 17382cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17392cd3a2a5SAndreas Fenkart 17402cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17412cd3a2a5SAndreas Fenkart } 17422cd3a2a5SAndreas Fenkart 17432cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17442cd3a2a5SAndreas Fenkart { 17452cd3a2a5SAndreas Fenkart struct mmc_host *mmc = host->mmc; 17462cd3a2a5SAndreas Fenkart int ret; 17472cd3a2a5SAndreas Fenkart 17482cd3a2a5SAndreas Fenkart /* 17492cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17502cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17512cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17522cd3a2a5SAndreas Fenkart * with functional clock disabled. 17532cd3a2a5SAndreas Fenkart */ 17542cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17552cd3a2a5SAndreas Fenkart return -ENODEV; 17562cd3a2a5SAndreas Fenkart 17572cd3a2a5SAndreas Fenkart /* Prevent auto-enabling of IRQ */ 17582cd3a2a5SAndreas Fenkart irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); 17592cd3a2a5SAndreas Fenkart ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, 17602cd3a2a5SAndreas Fenkart IRQF_TRIGGER_LOW | IRQF_ONESHOT, 17612cd3a2a5SAndreas Fenkart mmc_hostname(mmc), host); 17622cd3a2a5SAndreas Fenkart if (ret) { 17632cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17642cd3a2a5SAndreas Fenkart goto err; 17652cd3a2a5SAndreas Fenkart } 17662cd3a2a5SAndreas Fenkart 17672cd3a2a5SAndreas Fenkart /* 17682cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17692cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17702cd3a2a5SAndreas Fenkart */ 17712cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1772455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1773455e5cd6SAndreas Fenkart if (!p) { 17742cd3a2a5SAndreas Fenkart ret = -ENODEV; 1775455e5cd6SAndreas Fenkart goto err_free_irq; 1776455e5cd6SAndreas Fenkart } 1777455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1778455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1779455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1780455e5cd6SAndreas Fenkart ret = -EINVAL; 1781455e5cd6SAndreas Fenkart goto err_free_irq; 1782455e5cd6SAndreas Fenkart } 1783455e5cd6SAndreas Fenkart 1784455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1785455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1786455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1787455e5cd6SAndreas Fenkart ret = -EINVAL; 1788455e5cd6SAndreas Fenkart goto err_free_irq; 1789455e5cd6SAndreas Fenkart } 1790455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17912cd3a2a5SAndreas Fenkart } 17922cd3a2a5SAndreas Fenkart 17935a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17945a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17952cd3a2a5SAndreas Fenkart return 0; 17962cd3a2a5SAndreas Fenkart 1797455e5cd6SAndreas Fenkart err_free_irq: 1798455e5cd6SAndreas Fenkart devm_free_irq(host->dev, host->wake_irq, host); 17992cd3a2a5SAndreas Fenkart err: 18002cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 18012cd3a2a5SAndreas Fenkart host->wake_irq = 0; 18022cd3a2a5SAndreas Fenkart return ret; 18032cd3a2a5SAndreas Fenkart } 18042cd3a2a5SAndreas Fenkart 180570a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 18061b331e69SKim Kyuwon { 18071b331e69SKim Kyuwon u32 hctl, capa, value; 18081b331e69SKim Kyuwon 18091b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 18104621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 18111b331e69SKim Kyuwon hctl = SDVS30; 18121b331e69SKim Kyuwon capa = VS30 | VS18; 18131b331e69SKim Kyuwon } else { 18141b331e69SKim Kyuwon hctl = SDVS18; 18151b331e69SKim Kyuwon capa = VS18; 18161b331e69SKim Kyuwon } 18171b331e69SKim Kyuwon 18181b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 18191b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18201b331e69SKim Kyuwon 18211b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18221b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18231b331e69SKim Kyuwon 18241b331e69SKim Kyuwon /* Set SD bus power bit */ 1825e13bb300SAdrian Hunter set_sd_bus_power(host); 18261b331e69SKim Kyuwon } 18271b331e69SKim Kyuwon 182870a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1829dd498effSDenis Karpov { 183070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1831dd498effSDenis Karpov 1832fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1833fa4aa2d4SBalaji T K 1834dd498effSDenis Karpov return 0; 1835dd498effSDenis Karpov } 1836dd498effSDenis Karpov 1837907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1838dd498effSDenis Karpov { 183970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1840dd498effSDenis Karpov 1841fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1842fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1843fa4aa2d4SBalaji T K 1844dd498effSDenis Karpov return 0; 1845dd498effSDenis Karpov } 1846dd498effSDenis Karpov 1847afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1848afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1849afd8c29dSKuninori Morimoto { 1850afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1851afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1852afd8c29dSKuninori Morimoto return 1; 1853afd8c29dSKuninori Morimoto 1854afd8c29dSKuninori Morimoto return blk_size; 1855afd8c29dSKuninori Morimoto } 1856afd8c29dSKuninori Morimoto 1857afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 185870a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 185970a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 18609782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18619782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 186270a3341aSDenis Karpov .request = omap_hsmmc_request, 186370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1864dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1865dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 18664816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18672cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1868dd498effSDenis Karpov }; 1869dd498effSDenis Karpov 1870d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1871d900f712SDenis Karpov 187270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1873d900f712SDenis Karpov { 1874d900f712SDenis Karpov struct mmc_host *mmc = s->private; 187570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 187611dd62a7SDenis Karpov 1877bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1878bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1879bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1880bb0635f0SAndreas Fenkart 1881bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1882bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1883bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1884bb0635f0SAndreas Fenkart : "disabled"); 1885bb0635f0SAndreas Fenkart } 1886bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18875e2ea617SAdrian Hunter 1888fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1889bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1890d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1891d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1892bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1893bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1894d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1895d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1896d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1897d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1898d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1899d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1900d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1901d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1902d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1903d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 19045e2ea617SAdrian Hunter 1905fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1906fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1907dd498effSDenis Karpov 1908d900f712SDenis Karpov return 0; 1909d900f712SDenis Karpov } 1910d900f712SDenis Karpov 191170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1912d900f712SDenis Karpov { 191370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1914d900f712SDenis Karpov } 1915d900f712SDenis Karpov 1916d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 191770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1918d900f712SDenis Karpov .read = seq_read, 1919d900f712SDenis Karpov .llseek = seq_lseek, 1920d900f712SDenis Karpov .release = single_release, 1921d900f712SDenis Karpov }; 1922d900f712SDenis Karpov 192370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1924d900f712SDenis Karpov { 1925d900f712SDenis Karpov if (mmc->debugfs_root) 1926d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1927d900f712SDenis Karpov mmc, &mmc_regs_fops); 1928d900f712SDenis Karpov } 1929d900f712SDenis Karpov 1930d900f712SDenis Karpov #else 1931d900f712SDenis Karpov 193270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1933d900f712SDenis Karpov { 1934d900f712SDenis Karpov } 1935d900f712SDenis Karpov 1936d900f712SDenis Karpov #endif 1937d900f712SDenis Karpov 193846856a68SRajendra Nayak #ifdef CONFIG_OF 193959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 194059445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 194159445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 194259445b10SNishanth Menon }; 194359445b10SNishanth Menon 194459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 194559445b10SNishanth Menon .reg_offset = 0x100, 194659445b10SNishanth Menon }; 19472cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19482cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19492cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19502cd3a2a5SAndreas Fenkart }; 195146856a68SRajendra Nayak 195246856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 195346856a68SRajendra Nayak { 195446856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 195546856a68SRajendra Nayak }, 195646856a68SRajendra Nayak { 195759445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 195859445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 195959445b10SNishanth Menon }, 196059445b10SNishanth Menon { 196146856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 196246856a68SRajendra Nayak }, 196346856a68SRajendra Nayak { 196446856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 196559445b10SNishanth Menon .data = &omap4_mmc_of_data, 196646856a68SRajendra Nayak }, 19672cd3a2a5SAndreas Fenkart { 19682cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19692cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19702cd3a2a5SAndreas Fenkart }, 197146856a68SRajendra Nayak {}, 1972b6d085f6SChris Ball }; 197346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 197446856a68SRajendra Nayak 197555143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 197646856a68SRajendra Nayak { 197755143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 197846856a68SRajendra Nayak struct device_node *np = dev->of_node; 1979d8714e87SDaniel Mack u32 bus_width, max_freq; 1980dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1981dc642c28SJan Luebbe 1982dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1983dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1984dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1985dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 198646856a68SRajendra Nayak 198746856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 198846856a68SRajendra Nayak if (!pdata) 198919df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 199046856a68SRajendra Nayak 199146856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 199246856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 199346856a68SRajendra Nayak 1994326119c9SAndreas Fenkart pdata->switch_pin = cd_gpio; 1995326119c9SAndreas Fenkart pdata->gpio_wp = wp_gpio; 199646856a68SRajendra Nayak 199746856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1998326119c9SAndreas Fenkart pdata->nonremovable = true; 1999326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 200046856a68SRajendra Nayak } 20017f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 200246856a68SRajendra Nayak if (bus_width == 4) 2003326119c9SAndreas Fenkart pdata->caps |= MMC_CAP_4_BIT_DATA; 200446856a68SRajendra Nayak else if (bus_width == 8) 2005326119c9SAndreas Fenkart pdata->caps |= MMC_CAP_8_BIT_DATA; 200646856a68SRajendra Nayak 200746856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 2008326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 200946856a68SRajendra Nayak 2010d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 2011d8714e87SDaniel Mack pdata->max_freq = max_freq; 2012d8714e87SDaniel Mack 2013cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 2014326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 2015cd587096SHebbar, Gururaja 2016c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 2017326119c9SAndreas Fenkart pdata->pm_caps |= MMC_PM_KEEP_POWER; 2018c9ae64dbSDaniel Mack 2019c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 2020326119c9SAndreas Fenkart pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2021c9ae64dbSDaniel Mack 202246856a68SRajendra Nayak return pdata; 202346856a68SRajendra Nayak } 202446856a68SRajendra Nayak #else 202555143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 202646856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 202746856a68SRajendra Nayak { 202819df45bcSBalaji T K return ERR_PTR(-EINVAL); 202946856a68SRajendra Nayak } 203046856a68SRajendra Nayak #endif 203146856a68SRajendra Nayak 2032c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 2033a45c6cb8SMadhusudhan Chikkature { 203455143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 2035a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 203670a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 2037a45c6cb8SMadhusudhan Chikkature struct resource *res; 2038db0fefc5SAdrian Hunter int ret, irq; 203946856a68SRajendra Nayak const struct of_device_id *match; 204026b88520SRussell King dma_cap_mask_t mask; 204126b88520SRussell King unsigned tx_req, rx_req; 204259445b10SNishanth Menon const struct omap_mmc_of_data *data; 204377fae219SBalaji T K void __iomem *base; 204446856a68SRajendra Nayak 204546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 204646856a68SRajendra Nayak if (match) { 204746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2048dc642c28SJan Luebbe 2049dc642c28SJan Luebbe if (IS_ERR(pdata)) 2050dc642c28SJan Luebbe return PTR_ERR(pdata); 2051dc642c28SJan Luebbe 205246856a68SRajendra Nayak if (match->data) { 205359445b10SNishanth Menon data = match->data; 205459445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 205559445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 205646856a68SRajendra Nayak } 205746856a68SRajendra Nayak } 2058a45c6cb8SMadhusudhan Chikkature 2059a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2060a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2061a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2062a45c6cb8SMadhusudhan Chikkature } 2063a45c6cb8SMadhusudhan Chikkature 2064a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2065a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2066a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2067a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2068a45c6cb8SMadhusudhan Chikkature 206977fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 207077fae219SBalaji T K if (IS_ERR(base)) 207177fae219SBalaji T K return PTR_ERR(base); 2072a45c6cb8SMadhusudhan Chikkature 207370a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2074a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2075a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20761e363e3bSAndreas Fenkart goto err; 2077a45c6cb8SMadhusudhan Chikkature } 2078a45c6cb8SMadhusudhan Chikkature 2079a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2080a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2081a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2082a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2083a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2084a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2085a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2086fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 208777fae219SBalaji T K host->base = base + pdata->reg_offset; 20886da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20899782aff8SPer Forlin host->next_data.cookie = 1; 2090e99448ffSBalaji T K host->pbias_enabled = 0; 2091a45c6cb8SMadhusudhan Chikkature 20921e363e3bSAndreas Fenkart ret = omap_hsmmc_gpio_init(host, pdata); 20931e363e3bSAndreas Fenkart if (ret) 20941e363e3bSAndreas Fenkart goto err_gpio; 20951e363e3bSAndreas Fenkart 2096a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2097a45c6cb8SMadhusudhan Chikkature 20982cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20992cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 21002cd3a2a5SAndreas Fenkart 210170a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2102dd498effSDenis Karpov 21036b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2104d418ed87SDaniel Mack 2105d418ed87SDaniel Mack if (pdata->max_freq > 0) 2106d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2107d418ed87SDaniel Mack else 21086b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2109a45c6cb8SMadhusudhan Chikkature 21104dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2111a45c6cb8SMadhusudhan Chikkature 21129618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2113a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2114a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2115a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2116a45c6cb8SMadhusudhan Chikkature goto err1; 2117a45c6cb8SMadhusudhan Chikkature } 2118a45c6cb8SMadhusudhan Chikkature 21199b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 21209b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2121afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 21229b68256cSPaul Walmsley } 2123dd498effSDenis Karpov 2124fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2125fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2126fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2127fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2128a45c6cb8SMadhusudhan Chikkature 212992a3aebfSBalaji T K omap_hsmmc_context_save(host); 213092a3aebfSBalaji T K 21319618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2132a45c6cb8SMadhusudhan Chikkature /* 2133a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2134a45c6cb8SMadhusudhan Chikkature */ 2135cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2136cd03d9a8SRajendra Nayak host->dbclk = NULL; 213794c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2138cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2139cd03d9a8SRajendra Nayak host->dbclk = NULL; 21402bec0893SAdrian Hunter } 2141a45c6cb8SMadhusudhan Chikkature 21420ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21430ccd76d4SJuha Yrjola * as we want. */ 2144a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21450ccd76d4SJuha Yrjola 2146a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2147a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2148a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2149a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2150a45c6cb8SMadhusudhan Chikkature 215113189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 215293caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2153a45c6cb8SMadhusudhan Chikkature 2154326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21553a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2156a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2157a45c6cb8SMadhusudhan Chikkature 2158326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 215923d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 216023d99bb9SAdrian Hunter 2161326119c9SAndreas Fenkart mmc->pm_caps = mmc_pdata(host)->pm_caps; 21626fdc75deSEliad Peller 216370a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2164a45c6cb8SMadhusudhan Chikkature 21654a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2166b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2167b7bf773bSBalaji T K if (!res) { 2168b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21699c17d08cSKevin Hilman ret = -ENXIO; 2170f3e2f1ddSGrazvydas Ignotas goto err_irq; 2171a45c6cb8SMadhusudhan Chikkature } 217226b88520SRussell King tx_req = res->start; 2173b7bf773bSBalaji T K 2174b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2175b7bf773bSBalaji T K if (!res) { 2176b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21779c17d08cSKevin Hilman ret = -ENXIO; 2178b7bf773bSBalaji T K goto err_irq; 2179b7bf773bSBalaji T K } 218026b88520SRussell King rx_req = res->start; 21814a29b559SSantosh Shilimkar } 2182c5c98927SRussell King 2183c5c98927SRussell King dma_cap_zero(mask); 2184c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 218526b88520SRussell King 2186d272fbf0SMatt Porter host->rx_chan = 2187d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2188d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2189d272fbf0SMatt Porter 2190c5c98927SRussell King if (!host->rx_chan) { 219126b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 219204e8c7bcSKevin Hilman ret = -ENXIO; 219326b88520SRussell King goto err_irq; 2194c5c98927SRussell King } 219526b88520SRussell King 2196d272fbf0SMatt Porter host->tx_chan = 2197d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2198d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2199d272fbf0SMatt Porter 2200c5c98927SRussell King if (!host->tx_chan) { 220126b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 220204e8c7bcSKevin Hilman ret = -ENXIO; 220326b88520SRussell King goto err_irq; 2204c5c98927SRussell King } 2205a45c6cb8SMadhusudhan Chikkature 2206a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2207e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2208a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2209a45c6cb8SMadhusudhan Chikkature if (ret) { 2210b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2211a45c6cb8SMadhusudhan Chikkature goto err_irq; 2212a45c6cb8SMadhusudhan Chikkature } 2213a45c6cb8SMadhusudhan Chikkature 2214326119c9SAndreas Fenkart if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) { 2215db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2216db0fefc5SAdrian Hunter if (ret) 2217bb09d151SAndreas Fenkart goto err_irq; 2218db0fefc5SAdrian Hunter host->use_reg = 1; 2219db0fefc5SAdrian Hunter } 2220db0fefc5SAdrian Hunter 2221326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2222a45c6cb8SMadhusudhan Chikkature 2223a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2224b5cd43f0SAndreas Fenkart if (host->card_detect_irq) { 22259fa0e05eSBalaji T K ret = devm_request_threaded_irq(&pdev->dev, 2226b5cd43f0SAndreas Fenkart host->card_detect_irq, 22279fa0e05eSBalaji T K NULL, omap_hsmmc_detect, 2228db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2229a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2230a45c6cb8SMadhusudhan Chikkature if (ret) { 2231b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 2232a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2233a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2234a45c6cb8SMadhusudhan Chikkature } 2235b5cd43f0SAndreas Fenkart host->suspend = omap_hsmmc_suspend_cdirq; 2236b5cd43f0SAndreas Fenkart host->resume = omap_hsmmc_resume_cdirq; 2237a45c6cb8SMadhusudhan Chikkature } 2238a45c6cb8SMadhusudhan Chikkature 2239b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2240a45c6cb8SMadhusudhan Chikkature 22412cd3a2a5SAndreas Fenkart /* 22422cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 22432cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 22442cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 22452cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 22462cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 22472cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22482cd3a2a5SAndreas Fenkart */ 22492cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22502cd3a2a5SAndreas Fenkart if (!ret) 22512cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22522cd3a2a5SAndreas Fenkart 2253b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2254b62f6228SAdrian Hunter 2255a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2256a45c6cb8SMadhusudhan Chikkature 2257326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2258a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2259a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2260a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2261a45c6cb8SMadhusudhan Chikkature } 2262b5cd43f0SAndreas Fenkart if (host->card_detect_irq && host->get_cover_state) { 2263a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2264a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2265a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2266db0fefc5SAdrian Hunter goto err_slot_name; 2267a45c6cb8SMadhusudhan Chikkature } 2268a45c6cb8SMadhusudhan Chikkature 226970a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2270fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2271fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2272d900f712SDenis Karpov 2273a45c6cb8SMadhusudhan Chikkature return 0; 2274a45c6cb8SMadhusudhan Chikkature 2275a45c6cb8SMadhusudhan Chikkature err_slot_name: 2276a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2277db0fefc5SAdrian Hunter err_irq_cd: 2278db0fefc5SAdrian Hunter if (host->use_reg) 2279db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2280a45c6cb8SMadhusudhan Chikkature err_irq: 2281c5c98927SRussell King if (host->tx_chan) 2282c5c98927SRussell King dma_release_channel(host->tx_chan); 2283c5c98927SRussell King if (host->rx_chan) 2284c5c98927SRussell King dma_release_channel(host->rx_chan); 2285d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 228637f6190dSTony Lindgren pm_runtime_disable(host->dev); 22879618195eSBalaji T K if (host->dbclk) 228894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2289a45c6cb8SMadhusudhan Chikkature err1: 22901e363e3bSAndreas Fenkart omap_hsmmc_gpio_free(host, pdata); 22911e363e3bSAndreas Fenkart err_gpio: 2292a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2293db0fefc5SAdrian Hunter err: 2294a45c6cb8SMadhusudhan Chikkature return ret; 2295a45c6cb8SMadhusudhan Chikkature } 2296a45c6cb8SMadhusudhan Chikkature 22976e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2298a45c6cb8SMadhusudhan Chikkature { 229970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2300a45c6cb8SMadhusudhan Chikkature 2301fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2302a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2303db0fefc5SAdrian Hunter if (host->use_reg) 2304db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2305a45c6cb8SMadhusudhan Chikkature 2306c5c98927SRussell King if (host->tx_chan) 2307c5c98927SRussell King dma_release_channel(host->tx_chan); 2308c5c98927SRussell King if (host->rx_chan) 2309c5c98927SRussell King dma_release_channel(host->rx_chan); 2310c5c98927SRussell King 2311fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2312fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 23139618195eSBalaji T K if (host->dbclk) 231494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2315a45c6cb8SMadhusudhan Chikkature 23161e363e3bSAndreas Fenkart omap_hsmmc_gpio_free(host, host->pdata); 23179d1f0286SBalaji T K mmc_free_host(host->mmc); 2318a45c6cb8SMadhusudhan Chikkature 2319a45c6cb8SMadhusudhan Chikkature return 0; 2320a45c6cb8SMadhusudhan Chikkature } 2321a45c6cb8SMadhusudhan Chikkature 2322a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2323a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2324a48ce884SFelipe Balbi { 2325a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2326a48ce884SFelipe Balbi 2327b5cd43f0SAndreas Fenkart if (host->suspend) 232880412ca8SAndreas Fenkart return host->suspend(dev); 2329a48ce884SFelipe Balbi 2330a48ce884SFelipe Balbi return 0; 2331a48ce884SFelipe Balbi } 2332a48ce884SFelipe Balbi 2333a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2334a48ce884SFelipe Balbi { 2335a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2336a48ce884SFelipe Balbi 2337b5cd43f0SAndreas Fenkart if (host->resume) 233880412ca8SAndreas Fenkart host->resume(dev); 2339a48ce884SFelipe Balbi 2340a48ce884SFelipe Balbi } 2341a48ce884SFelipe Balbi 2342a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2343a45c6cb8SMadhusudhan Chikkature { 2344927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2345927ce944SFelipe Balbi 2346927ce944SFelipe Balbi if (!host) 2347927ce944SFelipe Balbi return 0; 2348a45c6cb8SMadhusudhan Chikkature 2349fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 235031f9d463SEliad Peller 235131f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 23522cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23532cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23542cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 235531f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 235631f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 235731f9d463SEliad Peller } 2358927ce944SFelipe Balbi 23592cd3a2a5SAndreas Fenkart /* do not wake up due to sdio irq */ 23602cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23612cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23622cd3a2a5SAndreas Fenkart disable_irq(host->wake_irq); 23632cd3a2a5SAndreas Fenkart 2364cd03d9a8SRajendra Nayak if (host->dbclk) 236594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 23663932afd5SUlf Hansson 2367fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 23683932afd5SUlf Hansson return 0; 2369a45c6cb8SMadhusudhan Chikkature } 2370a45c6cb8SMadhusudhan Chikkature 2371a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2372a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2373a45c6cb8SMadhusudhan Chikkature { 2374927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2375927ce944SFelipe Balbi 2376927ce944SFelipe Balbi if (!host) 2377927ce944SFelipe Balbi return 0; 2378a45c6cb8SMadhusudhan Chikkature 2379fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 238011dd62a7SDenis Karpov 2381cd03d9a8SRajendra Nayak if (host->dbclk) 238294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23832bec0893SAdrian Hunter 238431f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 238570a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23861b331e69SKim Kyuwon 2387b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2388b62f6228SAdrian Hunter 23892cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23902cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23912cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23922cd3a2a5SAndreas Fenkart 2393fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2394fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23953932afd5SUlf Hansson return 0; 2396a45c6cb8SMadhusudhan Chikkature } 2397a45c6cb8SMadhusudhan Chikkature 2398a45c6cb8SMadhusudhan Chikkature #else 2399a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2400a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 240170a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 240270a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2403a45c6cb8SMadhusudhan Chikkature #endif 2404a45c6cb8SMadhusudhan Chikkature 2405fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2406fa4aa2d4SBalaji T K { 2407fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 24082cd3a2a5SAndreas Fenkart unsigned long flags; 2409f945901fSAndreas Fenkart int ret = 0; 2410fa4aa2d4SBalaji T K 2411fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2412fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2413927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2414fa4aa2d4SBalaji T K 24152cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 24162cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 24172cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 24182cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 24192cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 24202cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2421f945901fSAndreas Fenkart 2422f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2423f945901fSAndreas Fenkart /* 2424f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2425f945901fSAndreas Fenkart * race condition: possible irq handler running on 2426f945901fSAndreas Fenkart * multi-core, abort 2427f945901fSAndreas Fenkart */ 2428f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 24292cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2430f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2431f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2432f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2433f945901fSAndreas Fenkart ret = -EBUSY; 2434f945901fSAndreas Fenkart goto abort; 2435f945901fSAndreas Fenkart } 24362cd3a2a5SAndreas Fenkart 243797978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 243897978a44SAndreas Fenkart 24392cd3a2a5SAndreas Fenkart WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); 24402cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 24412cd3a2a5SAndreas Fenkart host->flags |= HSMMC_WAKE_IRQ_ENABLED; 244297978a44SAndreas Fenkart } else { 244397978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 24442cd3a2a5SAndreas Fenkart } 244597978a44SAndreas Fenkart 2446f945901fSAndreas Fenkart abort: 24472cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2448f945901fSAndreas Fenkart return ret; 2449fa4aa2d4SBalaji T K } 2450fa4aa2d4SBalaji T K 2451fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2452fa4aa2d4SBalaji T K { 2453fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 24542cd3a2a5SAndreas Fenkart unsigned long flags; 2455fa4aa2d4SBalaji T K 2456fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2457fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2458927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2459fa4aa2d4SBalaji T K 24602cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 24612cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 24622cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 24632cd3a2a5SAndreas Fenkart /* sdio irq flag can't change while in runtime suspend */ 24642cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 24652cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 24662cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 24672cd3a2a5SAndreas Fenkart } 24682cd3a2a5SAndreas Fenkart 246997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 247097978a44SAndreas Fenkart 247197978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 24722cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 24732cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 24742cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 247597978a44SAndreas Fenkart } else { 247697978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 24772cd3a2a5SAndreas Fenkart } 24782cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2479fa4aa2d4SBalaji T K return 0; 2480fa4aa2d4SBalaji T K } 2481fa4aa2d4SBalaji T K 2482a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 248370a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 248470a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2485a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2486a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2487fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2488fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2489a791daa1SKevin Hilman }; 2490a791daa1SKevin Hilman 2491a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2492efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24930433c143SBill Pemberton .remove = omap_hsmmc_remove, 2494a45c6cb8SMadhusudhan Chikkature .driver = { 2495a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2496a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 249746856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2498a45c6cb8SMadhusudhan Chikkature }, 2499a45c6cb8SMadhusudhan Chikkature }; 2500a45c6cb8SMadhusudhan Chikkature 2501b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2502a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2503a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2504a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2505a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2506