1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184db0fefc5SAdrian Hunter /* 185db0fefc5SAdrian Hunter * vcc == configured supply 186db0fefc5SAdrian Hunter * vcc_aux == optional 187db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 188db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 189db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 190db0fefc5SAdrian Hunter */ 191db0fefc5SAdrian Hunter struct regulator *vcc; 192db0fefc5SAdrian Hunter struct regulator *vcc_aux; 193e99448ffSBalaji T K struct regulator *pbias; 194e99448ffSBalaji T K bool pbias_enabled; 195a45c6cb8SMadhusudhan Chikkature void __iomem *base; 196a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1974dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 198a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1990ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 200a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 201a3621465SAdrian Hunter unsigned char power_mode; 202a45c6cb8SMadhusudhan Chikkature int suspended; 2030a82e06eSTony Lindgren u32 con; 2040a82e06eSTony Lindgren u32 hctl; 2050a82e06eSTony Lindgren u32 sysctl; 2060a82e06eSTony Lindgren u32 capa; 207a45c6cb8SMadhusudhan Chikkature int irq; 2082cd3a2a5SAndreas Fenkart int wake_irq; 209a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 210c5c98927SRussell King struct dma_chan *tx_chan; 211c5c98927SRussell King struct dma_chan *rx_chan; 2124a694dc9SAdrian Hunter int response_busy; 21311dd62a7SDenis Karpov int context_loss; 214b62f6228SAdrian Hunter int protect_card; 215b62f6228SAdrian Hunter int reqs_blocked; 216b417577dSAdrian Hunter int req_in_progress; 2176e3076c2SBalaji T K unsigned long clk_rate; 218a2e77152SBalaji T K unsigned int flags; 2192cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2202cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2219782aff8SPer Forlin struct omap_hsmmc_next next_data; 22255143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 223b5cd43f0SAndreas Fenkart 224b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 225b5cd43f0SAndreas Fenkart * 226b5cd43f0SAndreas Fenkart * possible return values: 227b5cd43f0SAndreas Fenkart * 0 - closed 228b5cd43f0SAndreas Fenkart * 1 - open 229b5cd43f0SAndreas Fenkart */ 23080412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 231b5cd43f0SAndreas Fenkart 23280412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 233a45c6cb8SMadhusudhan Chikkature }; 234a45c6cb8SMadhusudhan Chikkature 23559445b10SNishanth Menon struct omap_mmc_of_data { 23659445b10SNishanth Menon u32 reg_offset; 23759445b10SNishanth Menon u8 controller_flags; 23859445b10SNishanth Menon }; 23959445b10SNishanth Menon 240bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 241bf129e1cSBalaji T K 24280412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 243db0fefc5SAdrian Hunter { 2449ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 245db0fefc5SAdrian Hunter 24641afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 247db0fefc5SAdrian Hunter } 248db0fefc5SAdrian Hunter 24980412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 250db0fefc5SAdrian Hunter { 2519ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 252db0fefc5SAdrian Hunter 25341afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 254db0fefc5SAdrian Hunter } 255db0fefc5SAdrian Hunter 256b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 257b702b106SAdrian Hunter 25880412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 259db0fefc5SAdrian Hunter { 260db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 261db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 262db0fefc5SAdrian Hunter int ret = 0; 263db0fefc5SAdrian Hunter 264f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 265f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 266f7f0f035SAndreas Fenkart 267db0fefc5SAdrian Hunter /* 268db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 269db0fefc5SAdrian Hunter * voltage always-on regulator. 270db0fefc5SAdrian Hunter */ 271db0fefc5SAdrian Hunter if (!host->vcc) 272db0fefc5SAdrian Hunter return 0; 273db0fefc5SAdrian Hunter 274326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 27580412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 276db0fefc5SAdrian Hunter 277e99448ffSBalaji T K if (host->pbias) { 278e99448ffSBalaji T K if (host->pbias_enabled == 1) { 279e99448ffSBalaji T K ret = regulator_disable(host->pbias); 280e99448ffSBalaji T K if (!ret) 281e99448ffSBalaji T K host->pbias_enabled = 0; 282e99448ffSBalaji T K } 283e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 284e99448ffSBalaji T K } 285e99448ffSBalaji T K 286db0fefc5SAdrian Hunter /* 287db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 288db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 289db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 290db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 291db0fefc5SAdrian Hunter * 292db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 293db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 294db0fefc5SAdrian Hunter * 295db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 296db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 297db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 298db0fefc5SAdrian Hunter */ 299db0fefc5SAdrian Hunter if (power_on) { 300987fd49bSBalaji T K if (host->vcc) 30199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 302db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 303db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 304db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 305987fd49bSBalaji T K if (ret < 0 && host->vcc) 30699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30799fc5131SLinus Walleij host->vcc, 0); 308db0fefc5SAdrian Hunter } 309db0fefc5SAdrian Hunter } else { 31099fc5131SLinus Walleij /* Shut down the rail */ 3116da20c89SAdrian Hunter if (host->vcc_aux) 312db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 313987fd49bSBalaji T K if (host->vcc) { 31499fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31699fc5131SLinus Walleij host->vcc, 0); 31799fc5131SLinus Walleij } 318db0fefc5SAdrian Hunter } 319db0fefc5SAdrian Hunter 320e99448ffSBalaji T K if (host->pbias) { 321e99448ffSBalaji T K if (vdd <= VDD_165_195) 322e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 323e99448ffSBalaji T K VDD_1V8); 324e99448ffSBalaji T K else 325e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 326e99448ffSBalaji T K VDD_3V0); 327e99448ffSBalaji T K if (ret < 0) 328e99448ffSBalaji T K goto error_set_power; 329e99448ffSBalaji T K 330e99448ffSBalaji T K if (host->pbias_enabled == 0) { 331e99448ffSBalaji T K ret = regulator_enable(host->pbias); 332e99448ffSBalaji T K if (!ret) 333e99448ffSBalaji T K host->pbias_enabled = 1; 334e99448ffSBalaji T K } 335e99448ffSBalaji T K } 336e99448ffSBalaji T K 337326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 33880412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 339db0fefc5SAdrian Hunter 340e99448ffSBalaji T K error_set_power: 341db0fefc5SAdrian Hunter return ret; 342db0fefc5SAdrian Hunter } 343db0fefc5SAdrian Hunter 344db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 345db0fefc5SAdrian Hunter { 346db0fefc5SAdrian Hunter struct regulator *reg; 34764be9782Skishore kadiyala int ocr_value = 0; 3487d607f91SKishon Vijay Abraham I int ret; 349db0fefc5SAdrian Hunter 350f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 351f7f0f035SAndreas Fenkart return 0; 352f7f0f035SAndreas Fenkart 3537d607f91SKishon Vijay Abraham I reg = devm_regulator_get_optional(host->dev, "vmmc"); 354db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 3557d607f91SKishon Vijay Abraham I ret = PTR_ERR(reg); 3567d607f91SKishon Vijay Abraham I if (ret != -ENODEV) 3577d607f91SKishon Vijay Abraham I return ret; 3587d607f91SKishon Vijay Abraham I host->vcc = NULL; 3597d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 360987fd49bSBalaji T K PTR_ERR(reg)); 361db0fefc5SAdrian Hunter } else { 362db0fefc5SAdrian Hunter host->vcc = reg; 36364be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 364326119c9SAndreas Fenkart if (!mmc_pdata(host)->ocr_mask) { 365326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 36664be9782Skishore kadiyala } else { 367326119c9SAndreas Fenkart if (!(mmc_pdata(host)->ocr_mask & ocr_value)) { 3682cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 369326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask); 370326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = 0; 37164be9782Skishore kadiyala return -EINVAL; 37264be9782Skishore kadiyala } 37364be9782Skishore kadiyala } 374987fd49bSBalaji T K } 375db0fefc5SAdrian Hunter 376db0fefc5SAdrian Hunter /* Allow an aux regulator */ 377f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 378db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 379db0fefc5SAdrian Hunter 380e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 381e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 382e99448ffSBalaji T K 383b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 384326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 385b1c1df7aSBalaji T K return 0; 386db0fefc5SAdrian Hunter /* 387987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 388987fd49bSBalaji T K * to increase usecount and then disable it. 389db0fefc5SAdrian Hunter */ 390987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 391e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 392326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 393e840ce13SAdrian Hunter 394f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, vdd); 395f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 396db0fefc5SAdrian Hunter } 397db0fefc5SAdrian Hunter 398db0fefc5SAdrian Hunter return 0; 399db0fefc5SAdrian Hunter } 400db0fefc5SAdrian Hunter 401b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 402b702b106SAdrian Hunter { 403b702b106SAdrian Hunter return 1; 404b702b106SAdrian Hunter } 405b702b106SAdrian Hunter 406b702b106SAdrian Hunter #else 407b702b106SAdrian Hunter 408f7f0f035SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 409f7f0f035SAndreas Fenkart { 410f7f0f035SAndreas Fenkart return 0; 411f7f0f035SAndreas Fenkart } 412f7f0f035SAndreas Fenkart 413b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 414b702b106SAdrian Hunter { 415b702b106SAdrian Hunter return -EINVAL; 416b702b106SAdrian Hunter } 417b702b106SAdrian Hunter 418b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 419b702b106SAdrian Hunter { 420b702b106SAdrian Hunter return 0; 421b702b106SAdrian Hunter } 422b702b106SAdrian Hunter 423b702b106SAdrian Hunter #endif 424b702b106SAdrian Hunter 425cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 42641afa314SNeilBrown 42741afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 42841afa314SNeilBrown struct omap_hsmmc_host *host, 4291e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 430b702b106SAdrian Hunter { 431b702b106SAdrian Hunter int ret; 432b702b106SAdrian Hunter 433b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 434b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 435b702b106SAdrian Hunter if (ret) 436b702b106SAdrian Hunter return ret; 437cde592cbSAndreas Fenkart 438cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 439cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 440b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 441b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 442cde592cbSAndreas Fenkart if (ret) 443cde592cbSAndreas Fenkart return ret; 444cde592cbSAndreas Fenkart 445cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 446326119c9SAndreas Fenkart } 447b702b106SAdrian Hunter 448326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 44941afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 450b702b106SAdrian Hunter if (ret) 45141afa314SNeilBrown return ret; 452326119c9SAndreas Fenkart } 453b702b106SAdrian Hunter 454b702b106SAdrian Hunter return 0; 455b702b106SAdrian Hunter } 456b702b106SAdrian Hunter 457a45c6cb8SMadhusudhan Chikkature /* 458e0c7f99bSAndy Shevchenko * Start clock to the card 459e0c7f99bSAndy Shevchenko */ 460e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 461e0c7f99bSAndy Shevchenko { 462e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 463e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 464e0c7f99bSAndy Shevchenko } 465e0c7f99bSAndy Shevchenko 466e0c7f99bSAndy Shevchenko /* 467a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 468a45c6cb8SMadhusudhan Chikkature */ 46970a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 470a45c6cb8SMadhusudhan Chikkature { 471a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 472a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 473a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4747122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 475a45c6cb8SMadhusudhan Chikkature } 476a45c6cb8SMadhusudhan Chikkature 47793caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 47893caf8e6SAdrian Hunter struct mmc_command *cmd) 479b417577dSAdrian Hunter { 4802cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 4812cd3a2a5SAndreas Fenkart unsigned long flags; 482b417577dSAdrian Hunter 483b417577dSAdrian Hunter if (host->use_dma) 4842cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 485b417577dSAdrian Hunter 48693caf8e6SAdrian Hunter /* Disable timeout for erases */ 48793caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 488a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 48993caf8e6SAdrian Hunter 4902cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 491b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 492b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 4932cd3a2a5SAndreas Fenkart 4942cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 4952cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 4962cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 497b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 4982cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 499b417577dSAdrian Hunter } 500b417577dSAdrian Hunter 501b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 502b417577dSAdrian Hunter { 5032cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5042cd3a2a5SAndreas Fenkart unsigned long flags; 5052cd3a2a5SAndreas Fenkart 5062cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5072cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5082cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5092cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5112cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 512b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5132cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 514b417577dSAdrian Hunter } 515b417577dSAdrian Hunter 516ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 517d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 518ac330f44SAndy Shevchenko { 519ac330f44SAndy Shevchenko u16 dsor = 0; 520ac330f44SAndy Shevchenko 521ac330f44SAndy Shevchenko if (ios->clock) { 522d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 523ed164182SBalaji T K if (dsor > CLKD_MAX) 524ed164182SBalaji T K dsor = CLKD_MAX; 525ac330f44SAndy Shevchenko } 526ac330f44SAndy Shevchenko 527ac330f44SAndy Shevchenko return dsor; 528ac330f44SAndy Shevchenko } 529ac330f44SAndy Shevchenko 5305934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5315934df2fSAndy Shevchenko { 5325934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5335934df2fSAndy Shevchenko unsigned long regval; 5345934df2fSAndy Shevchenko unsigned long timeout; 535cd587096SHebbar, Gururaja unsigned long clkdiv; 5365934df2fSAndy Shevchenko 5378986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5385934df2fSAndy Shevchenko 5395934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5405934df2fSAndy Shevchenko 5415934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5425934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 543cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 544cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5455934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5465934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5475934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5485934df2fSAndy Shevchenko 5495934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5505934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5515934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5525934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5535934df2fSAndy Shevchenko cpu_relax(); 5545934df2fSAndy Shevchenko 555cd587096SHebbar, Gururaja /* 556cd587096SHebbar, Gururaja * Enable High-Speed Support 557cd587096SHebbar, Gururaja * Pre-Requisites 558cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 559cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 560cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 561cd587096SHebbar, Gururaja * in capabilities register 562cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 563cd587096SHebbar, Gururaja */ 564326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 5655438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 566903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 567cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 568cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 569cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 570cd587096SHebbar, Gururaja regval |= HSPE; 571cd587096SHebbar, Gururaja else 572cd587096SHebbar, Gururaja regval &= ~HSPE; 573cd587096SHebbar, Gururaja 574cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 575cd587096SHebbar, Gururaja } 576cd587096SHebbar, Gururaja 5775934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5785934df2fSAndy Shevchenko } 5795934df2fSAndy Shevchenko 5803796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5813796fb8aSAndy Shevchenko { 5823796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5833796fb8aSAndy Shevchenko u32 con; 5843796fb8aSAndy Shevchenko 5853796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 586903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 587903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 58803b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 58903b5d924SBalaji T K else 59003b5d924SBalaji T K con &= ~DDR; 5913796fb8aSAndy Shevchenko switch (ios->bus_width) { 5923796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5933796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5943796fb8aSAndy Shevchenko break; 5953796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5973796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5983796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5993796fb8aSAndy Shevchenko break; 6003796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6013796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6023796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6033796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6043796fb8aSAndy Shevchenko break; 6053796fb8aSAndy Shevchenko } 6063796fb8aSAndy Shevchenko } 6073796fb8aSAndy Shevchenko 6083796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6093796fb8aSAndy Shevchenko { 6103796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6113796fb8aSAndy Shevchenko u32 con; 6123796fb8aSAndy Shevchenko 6133796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6143796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6153796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6163796fb8aSAndy Shevchenko else 6173796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6183796fb8aSAndy Shevchenko } 6193796fb8aSAndy Shevchenko 62011dd62a7SDenis Karpov #ifdef CONFIG_PM 62111dd62a7SDenis Karpov 62211dd62a7SDenis Karpov /* 62311dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 62411dd62a7SDenis Karpov * power state change. 62511dd62a7SDenis Karpov */ 62670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 62711dd62a7SDenis Karpov { 62811dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6293796fb8aSAndy Shevchenko u32 hctl, capa; 63011dd62a7SDenis Karpov unsigned long timeout; 63111dd62a7SDenis Karpov 6320a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6330a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6340a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6350a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6360a82e06eSTony Lindgren return 0; 6370a82e06eSTony Lindgren 6380a82e06eSTony Lindgren host->context_loss++; 6390a82e06eSTony Lindgren 640c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 64111dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 64211dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 64311dd62a7SDenis Karpov hctl = SDVS18; 64411dd62a7SDenis Karpov else 64511dd62a7SDenis Karpov hctl = SDVS30; 64611dd62a7SDenis Karpov capa = VS30 | VS18; 64711dd62a7SDenis Karpov } else { 64811dd62a7SDenis Karpov hctl = SDVS18; 64911dd62a7SDenis Karpov capa = VS18; 65011dd62a7SDenis Karpov } 65111dd62a7SDenis Karpov 6525a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6535a52b08bSBalaji T K hctl |= IWE; 6545a52b08bSBalaji T K 65511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 65611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 65711dd62a7SDenis Karpov 65811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 65911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 66011dd62a7SDenis Karpov 66111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 66311dd62a7SDenis Karpov 66411dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 66511dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 66611dd62a7SDenis Karpov && time_before(jiffies, timeout)) 66711dd62a7SDenis Karpov ; 66811dd62a7SDenis Karpov 6692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 6702cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 6712cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 67211dd62a7SDenis Karpov 67311dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 67411dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 67511dd62a7SDenis Karpov goto out; 67611dd62a7SDenis Karpov 6773796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 67811dd62a7SDenis Karpov 6795934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 68011dd62a7SDenis Karpov 6813796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6823796fb8aSAndy Shevchenko 68311dd62a7SDenis Karpov out: 6840a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6850a82e06eSTony Lindgren host->context_loss); 68611dd62a7SDenis Karpov return 0; 68711dd62a7SDenis Karpov } 68811dd62a7SDenis Karpov 68911dd62a7SDenis Karpov /* 69011dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 69111dd62a7SDenis Karpov */ 69270a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 69311dd62a7SDenis Karpov { 6940a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6950a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6960a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6970a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 69811dd62a7SDenis Karpov } 69911dd62a7SDenis Karpov 70011dd62a7SDenis Karpov #else 70111dd62a7SDenis Karpov 70270a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70311dd62a7SDenis Karpov { 70411dd62a7SDenis Karpov return 0; 70511dd62a7SDenis Karpov } 70611dd62a7SDenis Karpov 70770a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70811dd62a7SDenis Karpov { 70911dd62a7SDenis Karpov } 71011dd62a7SDenis Karpov 71111dd62a7SDenis Karpov #endif 71211dd62a7SDenis Karpov 713a45c6cb8SMadhusudhan Chikkature /* 714a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 715a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 716a45c6cb8SMadhusudhan Chikkature */ 71770a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 718a45c6cb8SMadhusudhan Chikkature { 719a45c6cb8SMadhusudhan Chikkature int reg = 0; 720a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 721a45c6cb8SMadhusudhan Chikkature 722b62f6228SAdrian Hunter if (host->protect_card) 723b62f6228SAdrian Hunter return; 724b62f6228SAdrian Hunter 725a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 726b417577dSAdrian Hunter 727b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 728a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 729a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 730a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 731a45c6cb8SMadhusudhan Chikkature 732a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 733a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 734a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 735a45c6cb8SMadhusudhan Chikkature 736a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 737a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 738c653a6d4SAdrian Hunter 739c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 740c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 741c653a6d4SAdrian Hunter 742a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 743a45c6cb8SMadhusudhan Chikkature } 744a45c6cb8SMadhusudhan Chikkature 745a45c6cb8SMadhusudhan Chikkature static inline 74670a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 747a45c6cb8SMadhusudhan Chikkature { 748a45c6cb8SMadhusudhan Chikkature int r = 1; 749a45c6cb8SMadhusudhan Chikkature 750b5cd43f0SAndreas Fenkart if (host->get_cover_state) 75180412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 752a45c6cb8SMadhusudhan Chikkature return r; 753a45c6cb8SMadhusudhan Chikkature } 754a45c6cb8SMadhusudhan Chikkature 755a45c6cb8SMadhusudhan Chikkature static ssize_t 75670a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 757a45c6cb8SMadhusudhan Chikkature char *buf) 758a45c6cb8SMadhusudhan Chikkature { 759a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 76070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 761a45c6cb8SMadhusudhan Chikkature 76270a3341aSDenis Karpov return sprintf(buf, "%s\n", 76370a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 764a45c6cb8SMadhusudhan Chikkature } 765a45c6cb8SMadhusudhan Chikkature 76670a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 767a45c6cb8SMadhusudhan Chikkature 768a45c6cb8SMadhusudhan Chikkature static ssize_t 76970a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 770a45c6cb8SMadhusudhan Chikkature char *buf) 771a45c6cb8SMadhusudhan Chikkature { 772a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 77370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 774a45c6cb8SMadhusudhan Chikkature 775326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 776a45c6cb8SMadhusudhan Chikkature } 777a45c6cb8SMadhusudhan Chikkature 77870a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 779a45c6cb8SMadhusudhan Chikkature 780a45c6cb8SMadhusudhan Chikkature /* 781a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 782a45c6cb8SMadhusudhan Chikkature */ 783a45c6cb8SMadhusudhan Chikkature static void 78470a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 785a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 786a45c6cb8SMadhusudhan Chikkature { 787a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 788a45c6cb8SMadhusudhan Chikkature 7898986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 790a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 791a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 792a45c6cb8SMadhusudhan Chikkature 79393caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 794a45c6cb8SMadhusudhan Chikkature 7954a694dc9SAdrian Hunter host->response_busy = 0; 796a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 797a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 798a45c6cb8SMadhusudhan Chikkature resptype = 1; 7994a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8004a694dc9SAdrian Hunter resptype = 3; 8014a694dc9SAdrian Hunter host->response_busy = 1; 8024a694dc9SAdrian Hunter } else 803a45c6cb8SMadhusudhan Chikkature resptype = 2; 804a45c6cb8SMadhusudhan Chikkature } 805a45c6cb8SMadhusudhan Chikkature 806a45c6cb8SMadhusudhan Chikkature /* 807a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 808a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 809a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 810a45c6cb8SMadhusudhan Chikkature */ 811a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 812a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 813a45c6cb8SMadhusudhan Chikkature 814a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 815a45c6cb8SMadhusudhan Chikkature 816a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 817a2e77152SBalaji T K host->mrq->sbc) { 818a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 819a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 820a2e77152SBalaji T K } 821a45c6cb8SMadhusudhan Chikkature if (data) { 822a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 823a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 824a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 825a45c6cb8SMadhusudhan Chikkature else 826a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 827a45c6cb8SMadhusudhan Chikkature } 828a45c6cb8SMadhusudhan Chikkature 829a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 830a7e96879SVenkatraman S cmdreg |= DMAE; 831a45c6cb8SMadhusudhan Chikkature 832b417577dSAdrian Hunter host->req_in_progress = 1; 8334dffd7a2SAdrian Hunter 834a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 835a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 836a45c6cb8SMadhusudhan Chikkature } 837a45c6cb8SMadhusudhan Chikkature 8380ccd76d4SJuha Yrjola static int 83970a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8400ccd76d4SJuha Yrjola { 8410ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8420ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8430ccd76d4SJuha Yrjola else 8440ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8450ccd76d4SJuha Yrjola } 8460ccd76d4SJuha Yrjola 847c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 848c5c98927SRussell King struct mmc_data *data) 849c5c98927SRussell King { 850c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 851c5c98927SRussell King } 852c5c98927SRussell King 853b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 854b417577dSAdrian Hunter { 855b417577dSAdrian Hunter int dma_ch; 85631463b14SVenkatraman S unsigned long flags; 857b417577dSAdrian Hunter 85831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 859b417577dSAdrian Hunter host->req_in_progress = 0; 860b417577dSAdrian Hunter dma_ch = host->dma_ch; 86131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 862b417577dSAdrian Hunter 863b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 864b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 865b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 866b417577dSAdrian Hunter return; 867b417577dSAdrian Hunter host->mrq = NULL; 868b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 869f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 870f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 871b417577dSAdrian Hunter } 872b417577dSAdrian Hunter 873a45c6cb8SMadhusudhan Chikkature /* 874a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 875a45c6cb8SMadhusudhan Chikkature */ 876a45c6cb8SMadhusudhan Chikkature static void 87770a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 878a45c6cb8SMadhusudhan Chikkature { 8794a694dc9SAdrian Hunter if (!data) { 8804a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8814a694dc9SAdrian Hunter 88223050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 88323050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 88423050103SAdrian Hunter host->response_busy) { 88523050103SAdrian Hunter host->response_busy = 0; 88623050103SAdrian Hunter return; 88723050103SAdrian Hunter } 88823050103SAdrian Hunter 889b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8904a694dc9SAdrian Hunter return; 8914a694dc9SAdrian Hunter } 8924a694dc9SAdrian Hunter 893a45c6cb8SMadhusudhan Chikkature host->data = NULL; 894a45c6cb8SMadhusudhan Chikkature 895a45c6cb8SMadhusudhan Chikkature if (!data->error) 896a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 897a45c6cb8SMadhusudhan Chikkature else 898a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 899a45c6cb8SMadhusudhan Chikkature 900bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 901fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 902bf129e1cSBalaji T K else 903bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 904a45c6cb8SMadhusudhan Chikkature } 905a45c6cb8SMadhusudhan Chikkature 906a45c6cb8SMadhusudhan Chikkature /* 907a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 908a45c6cb8SMadhusudhan Chikkature */ 909a45c6cb8SMadhusudhan Chikkature static void 91070a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 911a45c6cb8SMadhusudhan Chikkature { 912bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 913a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9142177fa94SBalaji T K host->cmd = NULL; 915bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 916bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 917bf129e1cSBalaji T K host->mrq->data); 918bf129e1cSBalaji T K return; 919bf129e1cSBalaji T K } 920bf129e1cSBalaji T K 9212177fa94SBalaji T K host->cmd = NULL; 9222177fa94SBalaji T K 923a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 924a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 925a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 926a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 927a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 928a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 929a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 930a45c6cb8SMadhusudhan Chikkature } else { 931a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 932a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 933a45c6cb8SMadhusudhan Chikkature } 934a45c6cb8SMadhusudhan Chikkature } 935b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 936d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 937a45c6cb8SMadhusudhan Chikkature } 938a45c6cb8SMadhusudhan Chikkature 939a45c6cb8SMadhusudhan Chikkature /* 940a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 941a45c6cb8SMadhusudhan Chikkature */ 94270a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 943a45c6cb8SMadhusudhan Chikkature { 944b417577dSAdrian Hunter int dma_ch; 94531463b14SVenkatraman S unsigned long flags; 946b417577dSAdrian Hunter 94782788ff5SJarkko Lavinen host->data->error = errno; 948a45c6cb8SMadhusudhan Chikkature 94931463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 950b417577dSAdrian Hunter dma_ch = host->dma_ch; 951b417577dSAdrian Hunter host->dma_ch = -1; 95231463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 953b417577dSAdrian Hunter 954b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 955c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 956c5c98927SRussell King 957c5c98927SRussell King dmaengine_terminate_all(chan); 958c5c98927SRussell King dma_unmap_sg(chan->device->dev, 959c5c98927SRussell King host->data->sg, host->data->sg_len, 96070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 961c5c98927SRussell King 962053bf34fSPer Forlin host->data->host_cookie = 0; 963a45c6cb8SMadhusudhan Chikkature } 964a45c6cb8SMadhusudhan Chikkature host->data = NULL; 965a45c6cb8SMadhusudhan Chikkature } 966a45c6cb8SMadhusudhan Chikkature 967a45c6cb8SMadhusudhan Chikkature /* 968a45c6cb8SMadhusudhan Chikkature * Readable error output 969a45c6cb8SMadhusudhan Chikkature */ 970a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 971699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 972a45c6cb8SMadhusudhan Chikkature { 973a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 97470a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 975699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 976699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 977699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 978699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 979a45c6cb8SMadhusudhan Chikkature }; 980a45c6cb8SMadhusudhan Chikkature char res[256]; 981a45c6cb8SMadhusudhan Chikkature char *buf = res; 982a45c6cb8SMadhusudhan Chikkature int len, i; 983a45c6cb8SMadhusudhan Chikkature 984a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 985a45c6cb8SMadhusudhan Chikkature buf += len; 986a45c6cb8SMadhusudhan Chikkature 98770a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 988a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 98970a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 990a45c6cb8SMadhusudhan Chikkature buf += len; 991a45c6cb8SMadhusudhan Chikkature } 992a45c6cb8SMadhusudhan Chikkature 9938986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 994a45c6cb8SMadhusudhan Chikkature } 995699b958bSAdrian Hunter #else 996699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 997699b958bSAdrian Hunter u32 status) 998699b958bSAdrian Hunter { 999699b958bSAdrian Hunter } 1000a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1001a45c6cb8SMadhusudhan Chikkature 10023ebf74b1SJean Pihet /* 10033ebf74b1SJean Pihet * MMC controller internal state machines reset 10043ebf74b1SJean Pihet * 10053ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10063ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10073ebf74b1SJean Pihet * Can be called from interrupt context 10083ebf74b1SJean Pihet */ 100970a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10103ebf74b1SJean Pihet unsigned long bit) 10113ebf74b1SJean Pihet { 10123ebf74b1SJean Pihet unsigned long i = 0; 10131e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10143ebf74b1SJean Pihet 10153ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10163ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10173ebf74b1SJean Pihet 101807ad64b6SMadhusudhan Chikkature /* 101907ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 102007ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 102107ad64b6SMadhusudhan Chikkature */ 1022326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1023b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 102407ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10251e881786SJianpeng Ma udelay(1); 102607ad64b6SMadhusudhan Chikkature } 102707ad64b6SMadhusudhan Chikkature i = 0; 102807ad64b6SMadhusudhan Chikkature 10293ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10303ebf74b1SJean Pihet (i++ < limit)) 10311e881786SJianpeng Ma udelay(1); 10323ebf74b1SJean Pihet 10333ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10343ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10353ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10363ebf74b1SJean Pihet __func__); 10373ebf74b1SJean Pihet } 1038a45c6cb8SMadhusudhan Chikkature 103925e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 104025e1897bSBalaji T K int err, int end_cmd) 1041ae4bf788SVenkatraman S { 104225e1897bSBalaji T K if (end_cmd) { 104394d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 104425e1897bSBalaji T K if (host->cmd) 1045ae4bf788SVenkatraman S host->cmd->error = err; 104625e1897bSBalaji T K } 1047ae4bf788SVenkatraman S 1048ae4bf788SVenkatraman S if (host->data) { 1049ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1050ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1051dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1052dc7745bdSBalaji T K host->mrq->cmd->error = err; 1053ae4bf788SVenkatraman S } 1054ae4bf788SVenkatraman S 1055b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1056a45c6cb8SMadhusudhan Chikkature { 1057a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1058b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1059a2e77152SBalaji T K int error = 0; 1060a45c6cb8SMadhusudhan Chikkature 1061a45c6cb8SMadhusudhan Chikkature data = host->data; 10628986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1063a45c6cb8SMadhusudhan Chikkature 1064a7e96879SVenkatraman S if (status & ERR_EN) { 1065699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10664a694dc9SAdrian Hunter 1067a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1068a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1069408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1070408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1071408806f7SKishon Vijay Abraham I host->response_busy = 0; 1072408806f7SKishon Vijay Abraham I } 1073a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 107425e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 10755027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 10765027cd1eSVignesh R BADA_EN)) 107725e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 107825e1897bSBalaji T K 1079a2e77152SBalaji T K if (status & ACE_EN) { 1080a2e77152SBalaji T K u32 ac12; 1081a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1082a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1083a2e77152SBalaji T K end_cmd = 1; 1084a2e77152SBalaji T K if (ac12 & ACTO) 1085a2e77152SBalaji T K error = -ETIMEDOUT; 1086a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1087a2e77152SBalaji T K error = -EILSEQ; 1088a2e77152SBalaji T K host->mrq->sbc->error = error; 1089a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1090a2e77152SBalaji T K } 1091a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1092a2e77152SBalaji T K } 1093a45c6cb8SMadhusudhan Chikkature } 1094a45c6cb8SMadhusudhan Chikkature 10957472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1096a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 109770a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1098a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 109970a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1100b417577dSAdrian Hunter } 1101a45c6cb8SMadhusudhan Chikkature 1102b417577dSAdrian Hunter /* 1103b417577dSAdrian Hunter * MMC controller IRQ handler 1104b417577dSAdrian Hunter */ 1105b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1106b417577dSAdrian Hunter { 1107b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1108b417577dSAdrian Hunter int status; 1109b417577dSAdrian Hunter 1110b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11112cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11122cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1113b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11141f6b9fa4SVenkatraman S 11152cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11162cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11172cd3a2a5SAndreas Fenkart 1118b417577dSAdrian Hunter /* Flush posted write */ 1119b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11201f6b9fa4SVenkatraman S } 11214dffd7a2SAdrian Hunter 1122a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1123a45c6cb8SMadhusudhan Chikkature } 1124a45c6cb8SMadhusudhan Chikkature 112570a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1126e13bb300SAdrian Hunter { 1127e13bb300SAdrian Hunter unsigned long i; 1128e13bb300SAdrian Hunter 1129e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1130e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1131e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1132e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1133e13bb300SAdrian Hunter break; 1134e13bb300SAdrian Hunter cpu_relax(); 1135e13bb300SAdrian Hunter } 1136e13bb300SAdrian Hunter } 1137e13bb300SAdrian Hunter 1138a45c6cb8SMadhusudhan Chikkature /* 1139eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1140eb250826SDavid Brownell * 1141eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1142eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1143eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1144a45c6cb8SMadhusudhan Chikkature */ 114570a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1146a45c6cb8SMadhusudhan Chikkature { 1147a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1148a45c6cb8SMadhusudhan Chikkature int ret; 1149a45c6cb8SMadhusudhan Chikkature 1150a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1151fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1152cd03d9a8SRajendra Nayak if (host->dbclk) 115394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1154a45c6cb8SMadhusudhan Chikkature 1155a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1156f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1157a45c6cb8SMadhusudhan Chikkature 1158a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11592bec0893SAdrian Hunter if (!ret) 1160f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1161fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1162cd03d9a8SRajendra Nayak if (host->dbclk) 116394c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11642bec0893SAdrian Hunter 1165a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1166a45c6cb8SMadhusudhan Chikkature goto err; 1167a45c6cb8SMadhusudhan Chikkature 1168a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1169a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1170a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1171eb250826SDavid Brownell 1172a45c6cb8SMadhusudhan Chikkature /* 1173a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1174a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 117570a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1176a45c6cb8SMadhusudhan Chikkature * 1177eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1178eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1179eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1180eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1181eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1182eb250826SDavid Brownell * 1183eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1184eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1185eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1186a45c6cb8SMadhusudhan Chikkature */ 1187eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1188a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1189eb250826SDavid Brownell else 1190eb250826SDavid Brownell reg_val |= SDVS30; 1191a45c6cb8SMadhusudhan Chikkature 1192a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1193e13bb300SAdrian Hunter set_sd_bus_power(host); 1194a45c6cb8SMadhusudhan Chikkature 1195a45c6cb8SMadhusudhan Chikkature return 0; 1196a45c6cb8SMadhusudhan Chikkature err: 1197b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1198a45c6cb8SMadhusudhan Chikkature return ret; 1199a45c6cb8SMadhusudhan Chikkature } 1200a45c6cb8SMadhusudhan Chikkature 1201b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1202b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1203b62f6228SAdrian Hunter { 1204b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1205b62f6228SAdrian Hunter return; 1206b62f6228SAdrian Hunter 1207b62f6228SAdrian Hunter host->reqs_blocked = 0; 120880412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1209b62f6228SAdrian Hunter if (host->protect_card) { 12102cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1211b62f6228SAdrian Hunter "card is now accessible\n", 1212b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1213b62f6228SAdrian Hunter host->protect_card = 0; 1214b62f6228SAdrian Hunter } 1215b62f6228SAdrian Hunter } else { 1216b62f6228SAdrian Hunter if (!host->protect_card) { 12172cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1218b62f6228SAdrian Hunter "card is now inaccessible\n", 1219b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1220b62f6228SAdrian Hunter host->protect_card = 1; 1221b62f6228SAdrian Hunter } 1222b62f6228SAdrian Hunter } 1223b62f6228SAdrian Hunter } 1224b62f6228SAdrian Hunter 1225a45c6cb8SMadhusudhan Chikkature /* 1226cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1227cde592cbSAndreas Fenkart */ 1228cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1229cde592cbSAndreas Fenkart { 1230cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1231cde592cbSAndreas Fenkart 1232cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1233cde592cbSAndreas Fenkart 1234cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1235cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1236cde592cbSAndreas Fenkart return IRQ_HANDLED; 1237cde592cbSAndreas Fenkart } 1238cde592cbSAndreas Fenkart 1239c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12400ccd76d4SJuha Yrjola { 1241c5c98927SRussell King struct omap_hsmmc_host *host = param; 1242c5c98927SRussell King struct dma_chan *chan; 1243770d7432SAdrian Hunter struct mmc_data *data; 1244c5c98927SRussell King int req_in_progress; 1245a45c6cb8SMadhusudhan Chikkature 1246c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1247b417577dSAdrian Hunter if (host->dma_ch < 0) { 1248c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1249a45c6cb8SMadhusudhan Chikkature return; 1250b417577dSAdrian Hunter } 1251a45c6cb8SMadhusudhan Chikkature 1252770d7432SAdrian Hunter data = host->mrq->data; 1253c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12549782aff8SPer Forlin if (!data->host_cookie) 1255c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1256c5c98927SRussell King data->sg, data->sg_len, 1257b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1258b417577dSAdrian Hunter 1259b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1260a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1261c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1262b417577dSAdrian Hunter 1263b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1264b417577dSAdrian Hunter if (!req_in_progress) { 1265b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1266b417577dSAdrian Hunter 1267b417577dSAdrian Hunter host->mrq = NULL; 1268b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1269f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1270f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1271b417577dSAdrian Hunter } 1272a45c6cb8SMadhusudhan Chikkature } 1273a45c6cb8SMadhusudhan Chikkature 12749782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12759782aff8SPer Forlin struct mmc_data *data, 1276c5c98927SRussell King struct omap_hsmmc_next *next, 127726b88520SRussell King struct dma_chan *chan) 12789782aff8SPer Forlin { 12799782aff8SPer Forlin int dma_len; 12809782aff8SPer Forlin 12819782aff8SPer Forlin if (!next && data->host_cookie && 12829782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12832cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12849782aff8SPer Forlin " host->next_data.cookie %d\n", 12859782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12869782aff8SPer Forlin data->host_cookie = 0; 12879782aff8SPer Forlin } 12889782aff8SPer Forlin 12899782aff8SPer Forlin /* Check if next job is already prepared */ 1290b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 129126b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12929782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12939782aff8SPer Forlin 12949782aff8SPer Forlin } else { 12959782aff8SPer Forlin dma_len = host->next_data.dma_len; 12969782aff8SPer Forlin host->next_data.dma_len = 0; 12979782aff8SPer Forlin } 12989782aff8SPer Forlin 12999782aff8SPer Forlin 13009782aff8SPer Forlin if (dma_len == 0) 13019782aff8SPer Forlin return -EINVAL; 13029782aff8SPer Forlin 13039782aff8SPer Forlin if (next) { 13049782aff8SPer Forlin next->dma_len = dma_len; 13059782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13069782aff8SPer Forlin } else 13079782aff8SPer Forlin host->dma_len = dma_len; 13089782aff8SPer Forlin 13099782aff8SPer Forlin return 0; 13109782aff8SPer Forlin } 13119782aff8SPer Forlin 1312a45c6cb8SMadhusudhan Chikkature /* 1313a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1314a45c6cb8SMadhusudhan Chikkature */ 13159d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 131670a3341aSDenis Karpov struct mmc_request *req) 1317a45c6cb8SMadhusudhan Chikkature { 131826b88520SRussell King struct dma_slave_config cfg; 131926b88520SRussell King struct dma_async_tx_descriptor *tx; 132026b88520SRussell King int ret = 0, i; 1321a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1322c5c98927SRussell King struct dma_chan *chan; 1323a45c6cb8SMadhusudhan Chikkature 13240ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1325a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13260ccd76d4SJuha Yrjola struct scatterlist *sgl; 13270ccd76d4SJuha Yrjola 13280ccd76d4SJuha Yrjola sgl = data->sg + i; 13290ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13300ccd76d4SJuha Yrjola return -EINVAL; 13310ccd76d4SJuha Yrjola } 13320ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13330ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13340ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13350ccd76d4SJuha Yrjola */ 13360ccd76d4SJuha Yrjola return -EINVAL; 13370ccd76d4SJuha Yrjola 1338b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1339a45c6cb8SMadhusudhan Chikkature 1340c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1341c5c98927SRussell King 1342c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1343c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1344c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1345c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1346c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1347c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1348c5c98927SRussell King 1349c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13509782aff8SPer Forlin if (ret) 13519782aff8SPer Forlin return ret; 1352a45c6cb8SMadhusudhan Chikkature 135326b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1354c5c98927SRussell King if (ret) 1355c5c98927SRussell King return ret; 1356a45c6cb8SMadhusudhan Chikkature 1357c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1358c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1359c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1360c5c98927SRussell King if (!tx) { 1361c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1362c5c98927SRussell King /* FIXME: cleanup */ 1363c5c98927SRussell King return -1; 1364c5c98927SRussell King } 1365c5c98927SRussell King 1366c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1367c5c98927SRussell King tx->callback_param = host; 1368c5c98927SRussell King 1369c5c98927SRussell King /* Does not fail */ 1370c5c98927SRussell King dmaengine_submit(tx); 1371c5c98927SRussell King 137226b88520SRussell King host->dma_ch = 1; 1373c5c98927SRussell King 1374a45c6cb8SMadhusudhan Chikkature return 0; 1375a45c6cb8SMadhusudhan Chikkature } 1376a45c6cb8SMadhusudhan Chikkature 137770a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1378e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1379e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1380a45c6cb8SMadhusudhan Chikkature { 1381a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1382a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1383a45c6cb8SMadhusudhan Chikkature 1384a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1385a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1386a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1387a45c6cb8SMadhusudhan Chikkature clkd = 1; 1388a45c6cb8SMadhusudhan Chikkature 13896e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1390e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1391e2bf08d6SAdrian Hunter timeout += timeout_clks; 1392a45c6cb8SMadhusudhan Chikkature if (timeout) { 1393a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1394a45c6cb8SMadhusudhan Chikkature dto += 1; 1395a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1396a45c6cb8SMadhusudhan Chikkature } 1397a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1398a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1399a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1400a45c6cb8SMadhusudhan Chikkature dto += 1; 1401a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1402a45c6cb8SMadhusudhan Chikkature dto -= 13; 1403a45c6cb8SMadhusudhan Chikkature else 1404a45c6cb8SMadhusudhan Chikkature dto = 0; 1405a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1406a45c6cb8SMadhusudhan Chikkature dto = 14; 1407a45c6cb8SMadhusudhan Chikkature } 1408a45c6cb8SMadhusudhan Chikkature 1409a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1410a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1411a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1412a45c6cb8SMadhusudhan Chikkature } 1413a45c6cb8SMadhusudhan Chikkature 14149d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14159d025334SBalaji T K { 14169d025334SBalaji T K struct mmc_request *req = host->mrq; 14179d025334SBalaji T K struct dma_chan *chan; 14189d025334SBalaji T K 14199d025334SBalaji T K if (!req->data) 14209d025334SBalaji T K return; 14219d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14229d025334SBalaji T K | (req->data->blocks << 16)); 14239d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14249d025334SBalaji T K req->data->timeout_clks); 14259d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14269d025334SBalaji T K dma_async_issue_pending(chan); 14279d025334SBalaji T K } 14289d025334SBalaji T K 1429a45c6cb8SMadhusudhan Chikkature /* 1430a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1431a45c6cb8SMadhusudhan Chikkature */ 1432a45c6cb8SMadhusudhan Chikkature static int 143370a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1434a45c6cb8SMadhusudhan Chikkature { 1435a45c6cb8SMadhusudhan Chikkature int ret; 1436a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1437a45c6cb8SMadhusudhan Chikkature 1438a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1439a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1440e2bf08d6SAdrian Hunter /* 1441e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1442e2bf08d6SAdrian Hunter * busy signal. 1443e2bf08d6SAdrian Hunter */ 1444e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1445e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1446a45c6cb8SMadhusudhan Chikkature return 0; 1447a45c6cb8SMadhusudhan Chikkature } 1448a45c6cb8SMadhusudhan Chikkature 1449a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 14509d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1451a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1452b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1453a45c6cb8SMadhusudhan Chikkature return ret; 1454a45c6cb8SMadhusudhan Chikkature } 1455a45c6cb8SMadhusudhan Chikkature } 1456a45c6cb8SMadhusudhan Chikkature return 0; 1457a45c6cb8SMadhusudhan Chikkature } 1458a45c6cb8SMadhusudhan Chikkature 14599782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14609782aff8SPer Forlin int err) 14619782aff8SPer Forlin { 14629782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14639782aff8SPer Forlin struct mmc_data *data = mrq->data; 14649782aff8SPer Forlin 146526b88520SRussell King if (host->use_dma && data->host_cookie) { 1466c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1467c5c98927SRussell King 146826b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14699782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14709782aff8SPer Forlin data->host_cookie = 0; 14719782aff8SPer Forlin } 14729782aff8SPer Forlin } 14739782aff8SPer Forlin 14749782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14759782aff8SPer Forlin bool is_first_req) 14769782aff8SPer Forlin { 14779782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14789782aff8SPer Forlin 14799782aff8SPer Forlin if (mrq->data->host_cookie) { 14809782aff8SPer Forlin mrq->data->host_cookie = 0; 14819782aff8SPer Forlin return ; 14829782aff8SPer Forlin } 14839782aff8SPer Forlin 1484c5c98927SRussell King if (host->use_dma) { 1485c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1486c5c98927SRussell King 14879782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 148826b88520SRussell King &host->next_data, c)) 14899782aff8SPer Forlin mrq->data->host_cookie = 0; 14909782aff8SPer Forlin } 1491c5c98927SRussell King } 14929782aff8SPer Forlin 1493a45c6cb8SMadhusudhan Chikkature /* 1494a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1495a45c6cb8SMadhusudhan Chikkature */ 149670a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1497a45c6cb8SMadhusudhan Chikkature { 149870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1499a3f406f8SJarkko Lavinen int err; 1500a45c6cb8SMadhusudhan Chikkature 1501b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1502b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1503f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1504b62f6228SAdrian Hunter if (host->protect_card) { 1505b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1506b62f6228SAdrian Hunter /* 1507b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1508b62f6228SAdrian Hunter * state by resetting the command and data state 1509b62f6228SAdrian Hunter * machines. 1510b62f6228SAdrian Hunter */ 1511b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1512b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1513b62f6228SAdrian Hunter host->reqs_blocked += 1; 1514b62f6228SAdrian Hunter } 1515b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1516b62f6228SAdrian Hunter if (req->data) 1517b62f6228SAdrian Hunter req->data->error = -EBADF; 1518b417577dSAdrian Hunter req->cmd->retries = 0; 1519b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1520f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1521f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1522b62f6228SAdrian Hunter return; 1523b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1524b62f6228SAdrian Hunter host->reqs_blocked = 0; 1525a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1526a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15276e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 152870a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1529a3f406f8SJarkko Lavinen if (err) { 1530a3f406f8SJarkko Lavinen req->cmd->error = err; 1531a3f406f8SJarkko Lavinen if (req->data) 1532a3f406f8SJarkko Lavinen req->data->error = err; 1533a3f406f8SJarkko Lavinen host->mrq = NULL; 1534a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1535f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1536f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1537a3f406f8SJarkko Lavinen return; 1538a3f406f8SJarkko Lavinen } 1539a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1540bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1541bf129e1cSBalaji T K return; 1542bf129e1cSBalaji T K } 1543a3f406f8SJarkko Lavinen 15449d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 154570a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1546a45c6cb8SMadhusudhan Chikkature } 1547a45c6cb8SMadhusudhan Chikkature 1548a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 154970a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1550a45c6cb8SMadhusudhan Chikkature { 155170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1552a3621465SAdrian Hunter int do_send_init_stream = 0; 1553a45c6cb8SMadhusudhan Chikkature 1554fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15555e2ea617SAdrian Hunter 1556a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1557a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1558a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1559f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1560a45c6cb8SMadhusudhan Chikkature break; 1561a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1562f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1563a45c6cb8SMadhusudhan Chikkature break; 1564a3621465SAdrian Hunter case MMC_POWER_ON: 1565a3621465SAdrian Hunter do_send_init_stream = 1; 1566a3621465SAdrian Hunter break; 1567a3621465SAdrian Hunter } 1568a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1569a45c6cb8SMadhusudhan Chikkature } 1570a45c6cb8SMadhusudhan Chikkature 1571dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1572dd498effSDenis Karpov 15733796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1574a45c6cb8SMadhusudhan Chikkature 15754621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1576eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1577eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1578eb250826SDavid Brownell */ 1579a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15802cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1581a45c6cb8SMadhusudhan Chikkature /* 1582a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1583a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1584a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1585a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1586a45c6cb8SMadhusudhan Chikkature */ 158770a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1588a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1589a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1590a45c6cb8SMadhusudhan Chikkature } 1591a45c6cb8SMadhusudhan Chikkature } 1592a45c6cb8SMadhusudhan Chikkature 15935934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1594a45c6cb8SMadhusudhan Chikkature 1595a3621465SAdrian Hunter if (do_send_init_stream) 1596a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1597a45c6cb8SMadhusudhan Chikkature 15983796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15995e2ea617SAdrian Hunter 1600fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1601a45c6cb8SMadhusudhan Chikkature } 1602a45c6cb8SMadhusudhan Chikkature 1603a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1604a45c6cb8SMadhusudhan Chikkature { 160570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1606a45c6cb8SMadhusudhan Chikkature 1607b5cd43f0SAndreas Fenkart if (!host->card_detect) 1608a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 160980412ca8SAndreas Fenkart return host->card_detect(host->dev); 1610a45c6cb8SMadhusudhan Chikkature } 1611a45c6cb8SMadhusudhan Chikkature 16124816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16134816858cSGrazvydas Ignotas { 16144816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16154816858cSGrazvydas Ignotas 1616326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1617326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16184816858cSGrazvydas Ignotas } 16194816858cSGrazvydas Ignotas 16202cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16212cd3a2a5SAndreas Fenkart { 16222cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16235a52b08bSBalaji T K u32 irq_mask, con; 16242cd3a2a5SAndreas Fenkart unsigned long flags; 16252cd3a2a5SAndreas Fenkart 16262cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16272cd3a2a5SAndreas Fenkart 16285a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16292cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16302cd3a2a5SAndreas Fenkart if (enable) { 16312cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16322cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16335a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16342cd3a2a5SAndreas Fenkart } else { 16352cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16362cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16375a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 16382cd3a2a5SAndreas Fenkart } 16395a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 16402cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 16412cd3a2a5SAndreas Fenkart 16422cd3a2a5SAndreas Fenkart /* 16432cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 16442cd3a2a5SAndreas Fenkart * but always disable immediately 16452cd3a2a5SAndreas Fenkart */ 16462cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 16472cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 16482cd3a2a5SAndreas Fenkart 16492cd3a2a5SAndreas Fenkart /* flush posted write */ 16502cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 16512cd3a2a5SAndreas Fenkart 16522cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 16532cd3a2a5SAndreas Fenkart } 16542cd3a2a5SAndreas Fenkart 16552cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 16562cd3a2a5SAndreas Fenkart { 16572cd3a2a5SAndreas Fenkart int ret; 16582cd3a2a5SAndreas Fenkart 16592cd3a2a5SAndreas Fenkart /* 16602cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 16612cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 16622cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 16632cd3a2a5SAndreas Fenkart * with functional clock disabled. 16642cd3a2a5SAndreas Fenkart */ 16652cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 16662cd3a2a5SAndreas Fenkart return -ENODEV; 16672cd3a2a5SAndreas Fenkart 16685b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 16692cd3a2a5SAndreas Fenkart if (ret) { 16702cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 16712cd3a2a5SAndreas Fenkart goto err; 16722cd3a2a5SAndreas Fenkart } 16732cd3a2a5SAndreas Fenkart 16742cd3a2a5SAndreas Fenkart /* 16752cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 16762cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 16772cd3a2a5SAndreas Fenkart */ 16782cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1679455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1680455e5cd6SAndreas Fenkart if (!p) { 16812cd3a2a5SAndreas Fenkart ret = -ENODEV; 1682455e5cd6SAndreas Fenkart goto err_free_irq; 1683455e5cd6SAndreas Fenkart } 1684455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1685455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1686455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1687455e5cd6SAndreas Fenkart ret = -EINVAL; 1688455e5cd6SAndreas Fenkart goto err_free_irq; 1689455e5cd6SAndreas Fenkart } 1690455e5cd6SAndreas Fenkart 1691455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1692455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1693455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1694455e5cd6SAndreas Fenkart ret = -EINVAL; 1695455e5cd6SAndreas Fenkart goto err_free_irq; 1696455e5cd6SAndreas Fenkart } 1697455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 16982cd3a2a5SAndreas Fenkart } 16992cd3a2a5SAndreas Fenkart 17005a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17015a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17022cd3a2a5SAndreas Fenkart return 0; 17032cd3a2a5SAndreas Fenkart 1704455e5cd6SAndreas Fenkart err_free_irq: 17055b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17062cd3a2a5SAndreas Fenkart err: 17072cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17082cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17092cd3a2a5SAndreas Fenkart return ret; 17102cd3a2a5SAndreas Fenkart } 17112cd3a2a5SAndreas Fenkart 171270a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17131b331e69SKim Kyuwon { 17141b331e69SKim Kyuwon u32 hctl, capa, value; 17151b331e69SKim Kyuwon 17161b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17174621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17181b331e69SKim Kyuwon hctl = SDVS30; 17191b331e69SKim Kyuwon capa = VS30 | VS18; 17201b331e69SKim Kyuwon } else { 17211b331e69SKim Kyuwon hctl = SDVS18; 17221b331e69SKim Kyuwon capa = VS18; 17231b331e69SKim Kyuwon } 17241b331e69SKim Kyuwon 17251b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17261b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17271b331e69SKim Kyuwon 17281b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17291b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17301b331e69SKim Kyuwon 17311b331e69SKim Kyuwon /* Set SD bus power bit */ 1732e13bb300SAdrian Hunter set_sd_bus_power(host); 17331b331e69SKim Kyuwon } 17341b331e69SKim Kyuwon 1735afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1736afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1737afd8c29dSKuninori Morimoto { 1738afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1739afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1740afd8c29dSKuninori Morimoto return 1; 1741afd8c29dSKuninori Morimoto 1742afd8c29dSKuninori Morimoto return blk_size; 1743afd8c29dSKuninori Morimoto } 1744afd8c29dSKuninori Morimoto 1745afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 17469782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17479782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 174870a3341aSDenis Karpov .request = omap_hsmmc_request, 174970a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1750dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1751a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 17524816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 17532cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1754dd498effSDenis Karpov }; 1755dd498effSDenis Karpov 1756d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1757d900f712SDenis Karpov 175870a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1759d900f712SDenis Karpov { 1760d900f712SDenis Karpov struct mmc_host *mmc = s->private; 176170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 176211dd62a7SDenis Karpov 1763bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1764bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1765bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1766bb0635f0SAndreas Fenkart 1767bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1768bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1769bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1770bb0635f0SAndreas Fenkart : "disabled"); 1771bb0635f0SAndreas Fenkart } 1772bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 17735e2ea617SAdrian Hunter 1774fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1775bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1776d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1777d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1778bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1779bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1780d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1781d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1782d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1783d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1784d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1785d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1786d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1787d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1788d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1789d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 17905e2ea617SAdrian Hunter 1791fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1792fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1793dd498effSDenis Karpov 1794d900f712SDenis Karpov return 0; 1795d900f712SDenis Karpov } 1796d900f712SDenis Karpov 179770a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1798d900f712SDenis Karpov { 179970a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1800d900f712SDenis Karpov } 1801d900f712SDenis Karpov 1802d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 180370a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1804d900f712SDenis Karpov .read = seq_read, 1805d900f712SDenis Karpov .llseek = seq_lseek, 1806d900f712SDenis Karpov .release = single_release, 1807d900f712SDenis Karpov }; 1808d900f712SDenis Karpov 180970a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1810d900f712SDenis Karpov { 1811d900f712SDenis Karpov if (mmc->debugfs_root) 1812d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1813d900f712SDenis Karpov mmc, &mmc_regs_fops); 1814d900f712SDenis Karpov } 1815d900f712SDenis Karpov 1816d900f712SDenis Karpov #else 1817d900f712SDenis Karpov 181870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1819d900f712SDenis Karpov { 1820d900f712SDenis Karpov } 1821d900f712SDenis Karpov 1822d900f712SDenis Karpov #endif 1823d900f712SDenis Karpov 182446856a68SRajendra Nayak #ifdef CONFIG_OF 182559445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 182659445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 182759445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 182859445b10SNishanth Menon }; 182959445b10SNishanth Menon 183059445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 183159445b10SNishanth Menon .reg_offset = 0x100, 183259445b10SNishanth Menon }; 18332cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18342cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18352cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18362cd3a2a5SAndreas Fenkart }; 183746856a68SRajendra Nayak 183846856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 183946856a68SRajendra Nayak { 184046856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 184146856a68SRajendra Nayak }, 184246856a68SRajendra Nayak { 184359445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 184459445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 184559445b10SNishanth Menon }, 184659445b10SNishanth Menon { 184746856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 184846856a68SRajendra Nayak }, 184946856a68SRajendra Nayak { 185046856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 185159445b10SNishanth Menon .data = &omap4_mmc_of_data, 185246856a68SRajendra Nayak }, 18532cd3a2a5SAndreas Fenkart { 18542cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 18552cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 18562cd3a2a5SAndreas Fenkart }, 185746856a68SRajendra Nayak {}, 1858b6d085f6SChris Ball }; 185946856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 186046856a68SRajendra Nayak 186155143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 186246856a68SRajendra Nayak { 186355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 186446856a68SRajendra Nayak struct device_node *np = dev->of_node; 186546856a68SRajendra Nayak 186646856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 186746856a68SRajendra Nayak if (!pdata) 186819df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 186946856a68SRajendra Nayak 187046856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 187146856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 187246856a68SRajendra Nayak 1873b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1874b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1875fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 187646856a68SRajendra Nayak 187746856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1878326119c9SAndreas Fenkart pdata->nonremovable = true; 1879326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 188046856a68SRajendra Nayak } 188146856a68SRajendra Nayak 188246856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1883326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 188446856a68SRajendra Nayak 1885cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1886326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1887cd587096SHebbar, Gururaja 188846856a68SRajendra Nayak return pdata; 188946856a68SRajendra Nayak } 189046856a68SRajendra Nayak #else 189155143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 189246856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 189346856a68SRajendra Nayak { 189419df45bcSBalaji T K return ERR_PTR(-EINVAL); 189546856a68SRajendra Nayak } 189646856a68SRajendra Nayak #endif 189746856a68SRajendra Nayak 1898c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1899a45c6cb8SMadhusudhan Chikkature { 190055143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1901a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 190270a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1903a45c6cb8SMadhusudhan Chikkature struct resource *res; 1904db0fefc5SAdrian Hunter int ret, irq; 190546856a68SRajendra Nayak const struct of_device_id *match; 190626b88520SRussell King dma_cap_mask_t mask; 190726b88520SRussell King unsigned tx_req, rx_req; 190859445b10SNishanth Menon const struct omap_mmc_of_data *data; 190977fae219SBalaji T K void __iomem *base; 191046856a68SRajendra Nayak 191146856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 191246856a68SRajendra Nayak if (match) { 191346856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1914dc642c28SJan Luebbe 1915dc642c28SJan Luebbe if (IS_ERR(pdata)) 1916dc642c28SJan Luebbe return PTR_ERR(pdata); 1917dc642c28SJan Luebbe 191846856a68SRajendra Nayak if (match->data) { 191959445b10SNishanth Menon data = match->data; 192059445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 192159445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 192246856a68SRajendra Nayak } 192346856a68SRajendra Nayak } 1924a45c6cb8SMadhusudhan Chikkature 1925a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1926a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1927a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1928a45c6cb8SMadhusudhan Chikkature } 1929a45c6cb8SMadhusudhan Chikkature 1930a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1931a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1932a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1933a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1934a45c6cb8SMadhusudhan Chikkature 193577fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 193677fae219SBalaji T K if (IS_ERR(base)) 193777fae219SBalaji T K return PTR_ERR(base); 1938a45c6cb8SMadhusudhan Chikkature 193970a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1940a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1941a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 19421e363e3bSAndreas Fenkart goto err; 1943a45c6cb8SMadhusudhan Chikkature } 1944a45c6cb8SMadhusudhan Chikkature 1945fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 1946fdb9de12SNeilBrown if (ret) 1947fdb9de12SNeilBrown goto err1; 1948fdb9de12SNeilBrown 1949a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1950a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1951a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1952a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1953a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1954a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1955a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1956fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 195777fae219SBalaji T K host->base = base + pdata->reg_offset; 19586da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 19599782aff8SPer Forlin host->next_data.cookie = 1; 1960e99448ffSBalaji T K host->pbias_enabled = 0; 1961a45c6cb8SMadhusudhan Chikkature 196241afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 19631e363e3bSAndreas Fenkart if (ret) 19641e363e3bSAndreas Fenkart goto err_gpio; 19651e363e3bSAndreas Fenkart 1966a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1967a45c6cb8SMadhusudhan Chikkature 19682cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 19692cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 19702cd3a2a5SAndreas Fenkart 197170a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1972dd498effSDenis Karpov 19736b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1974d418ed87SDaniel Mack 1975d418ed87SDaniel Mack if (pdata->max_freq > 0) 1976d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1977fdb9de12SNeilBrown else if (mmc->f_max == 0) 19786b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1979a45c6cb8SMadhusudhan Chikkature 19804dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1981a45c6cb8SMadhusudhan Chikkature 19829618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 1983a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1984a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1985a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1986a45c6cb8SMadhusudhan Chikkature goto err1; 1987a45c6cb8SMadhusudhan Chikkature } 1988a45c6cb8SMadhusudhan Chikkature 19899b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 19909b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1991afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 19929b68256cSPaul Walmsley } 1993dd498effSDenis Karpov 19945b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 1995fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1996fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1997fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1998fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1999a45c6cb8SMadhusudhan Chikkature 200092a3aebfSBalaji T K omap_hsmmc_context_save(host); 200192a3aebfSBalaji T K 20029618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2003a45c6cb8SMadhusudhan Chikkature /* 2004a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2005a45c6cb8SMadhusudhan Chikkature */ 2006cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2007cd03d9a8SRajendra Nayak host->dbclk = NULL; 200894c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2009cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2010cd03d9a8SRajendra Nayak host->dbclk = NULL; 20112bec0893SAdrian Hunter } 2012a45c6cb8SMadhusudhan Chikkature 20130ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20140ccd76d4SJuha Yrjola * as we want. */ 2015a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20160ccd76d4SJuha Yrjola 2017a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2018a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2019a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2020a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2021a45c6cb8SMadhusudhan Chikkature 202213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 202393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2024a45c6cb8SMadhusudhan Chikkature 2025326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20263a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2027a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2028a45c6cb8SMadhusudhan Chikkature 2029326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 203023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 203123d99bb9SAdrian Hunter 2032fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 20336fdc75deSEliad Peller 203470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2035a45c6cb8SMadhusudhan Chikkature 20364a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2037b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2038b7bf773bSBalaji T K if (!res) { 2039b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 20409c17d08cSKevin Hilman ret = -ENXIO; 2041f3e2f1ddSGrazvydas Ignotas goto err_irq; 2042a45c6cb8SMadhusudhan Chikkature } 204326b88520SRussell King tx_req = res->start; 2044b7bf773bSBalaji T K 2045b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2046b7bf773bSBalaji T K if (!res) { 2047b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 20489c17d08cSKevin Hilman ret = -ENXIO; 2049b7bf773bSBalaji T K goto err_irq; 2050b7bf773bSBalaji T K } 205126b88520SRussell King rx_req = res->start; 20524a29b559SSantosh Shilimkar } 2053c5c98927SRussell King 2054c5c98927SRussell King dma_cap_zero(mask); 2055c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 205626b88520SRussell King 2057d272fbf0SMatt Porter host->rx_chan = 2058d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2059d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2060d272fbf0SMatt Porter 2061c5c98927SRussell King if (!host->rx_chan) { 206226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 206304e8c7bcSKevin Hilman ret = -ENXIO; 206426b88520SRussell King goto err_irq; 2065c5c98927SRussell King } 206626b88520SRussell King 2067d272fbf0SMatt Porter host->tx_chan = 2068d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2069d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2070d272fbf0SMatt Porter 2071c5c98927SRussell King if (!host->tx_chan) { 207226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 207304e8c7bcSKevin Hilman ret = -ENXIO; 207426b88520SRussell King goto err_irq; 2075c5c98927SRussell King } 2076a45c6cb8SMadhusudhan Chikkature 2077a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2078e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2079a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2080a45c6cb8SMadhusudhan Chikkature if (ret) { 2081b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2082a45c6cb8SMadhusudhan Chikkature goto err_irq; 2083a45c6cb8SMadhusudhan Chikkature } 2084a45c6cb8SMadhusudhan Chikkature 2085f7f0f035SAndreas Fenkart if (omap_hsmmc_have_reg()) { 2086db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2087db0fefc5SAdrian Hunter if (ret) 2088bb09d151SAndreas Fenkart goto err_irq; 2089db0fefc5SAdrian Hunter } 2090db0fefc5SAdrian Hunter 2091326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2092a45c6cb8SMadhusudhan Chikkature 2093b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2094a45c6cb8SMadhusudhan Chikkature 20952cd3a2a5SAndreas Fenkart /* 20962cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 20972cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 20982cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 20992cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21002cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21012cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21022cd3a2a5SAndreas Fenkart */ 21032cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21042cd3a2a5SAndreas Fenkart if (!ret) 21052cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21062cd3a2a5SAndreas Fenkart 2107b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2108b62f6228SAdrian Hunter 2109a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2110a45c6cb8SMadhusudhan Chikkature 2111326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2112a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2113a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2114a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2115a45c6cb8SMadhusudhan Chikkature } 2116cde592cbSAndreas Fenkart if (host->get_cover_state) { 2117a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2118a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2119a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2120db0fefc5SAdrian Hunter goto err_slot_name; 2121a45c6cb8SMadhusudhan Chikkature } 2122a45c6cb8SMadhusudhan Chikkature 212370a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2124fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2125fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2126d900f712SDenis Karpov 2127a45c6cb8SMadhusudhan Chikkature return 0; 2128a45c6cb8SMadhusudhan Chikkature 2129a45c6cb8SMadhusudhan Chikkature err_slot_name: 2130a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2131a45c6cb8SMadhusudhan Chikkature err_irq: 21325b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2133c5c98927SRussell King if (host->tx_chan) 2134c5c98927SRussell King dma_release_channel(host->tx_chan); 2135c5c98927SRussell King if (host->rx_chan) 2136c5c98927SRussell King dma_release_channel(host->rx_chan); 2137d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 213837f6190dSTony Lindgren pm_runtime_disable(host->dev); 21399618195eSBalaji T K if (host->dbclk) 214094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2141a45c6cb8SMadhusudhan Chikkature err1: 21421e363e3bSAndreas Fenkart err_gpio: 2143a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2144db0fefc5SAdrian Hunter err: 2145a45c6cb8SMadhusudhan Chikkature return ret; 2146a45c6cb8SMadhusudhan Chikkature } 2147a45c6cb8SMadhusudhan Chikkature 21486e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2149a45c6cb8SMadhusudhan Chikkature { 215070a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2151a45c6cb8SMadhusudhan Chikkature 2152fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2153a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2154a45c6cb8SMadhusudhan Chikkature 2155c5c98927SRussell King if (host->tx_chan) 2156c5c98927SRussell King dma_release_channel(host->tx_chan); 2157c5c98927SRussell King if (host->rx_chan) 2158c5c98927SRussell King dma_release_channel(host->rx_chan); 2159c5c98927SRussell King 2160fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2161fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 21625b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 21639618195eSBalaji T K if (host->dbclk) 216494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2165a45c6cb8SMadhusudhan Chikkature 21669d1f0286SBalaji T K mmc_free_host(host->mmc); 2167a45c6cb8SMadhusudhan Chikkature 2168a45c6cb8SMadhusudhan Chikkature return 0; 2169a45c6cb8SMadhusudhan Chikkature } 2170a45c6cb8SMadhusudhan Chikkature 21713d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2172a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2173a45c6cb8SMadhusudhan Chikkature { 2174927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2175927ce944SFelipe Balbi 2176927ce944SFelipe Balbi if (!host) 2177927ce944SFelipe Balbi return 0; 2178a45c6cb8SMadhusudhan Chikkature 2179fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 218031f9d463SEliad Peller 218131f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 21822cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 21832cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 21842cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 218531f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 218631f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 218731f9d463SEliad Peller } 2188927ce944SFelipe Balbi 2189cd03d9a8SRajendra Nayak if (host->dbclk) 219094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 21913932afd5SUlf Hansson 2192fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 21933932afd5SUlf Hansson return 0; 2194a45c6cb8SMadhusudhan Chikkature } 2195a45c6cb8SMadhusudhan Chikkature 2196a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2197a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2198a45c6cb8SMadhusudhan Chikkature { 2199927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2200927ce944SFelipe Balbi 2201927ce944SFelipe Balbi if (!host) 2202927ce944SFelipe Balbi return 0; 2203a45c6cb8SMadhusudhan Chikkature 2204fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 220511dd62a7SDenis Karpov 2206cd03d9a8SRajendra Nayak if (host->dbclk) 220794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22082bec0893SAdrian Hunter 220931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 221070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22111b331e69SKim Kyuwon 2212b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2213fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2214fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22153932afd5SUlf Hansson return 0; 2216a45c6cb8SMadhusudhan Chikkature } 2217a45c6cb8SMadhusudhan Chikkature #endif 2218a45c6cb8SMadhusudhan Chikkature 2219fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2220fa4aa2d4SBalaji T K { 2221fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22222cd3a2a5SAndreas Fenkart unsigned long flags; 2223f945901fSAndreas Fenkart int ret = 0; 2224fa4aa2d4SBalaji T K 2225fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2226fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2227927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2228fa4aa2d4SBalaji T K 22292cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22302cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22312cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22322cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 22332cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22342cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2235f945901fSAndreas Fenkart 2236f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2237f945901fSAndreas Fenkart /* 2238f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2239f945901fSAndreas Fenkart * race condition: possible irq handler running on 2240f945901fSAndreas Fenkart * multi-core, abort 2241f945901fSAndreas Fenkart */ 2242f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 22432cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2244f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2245f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2246f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2247f945901fSAndreas Fenkart ret = -EBUSY; 2248f945901fSAndreas Fenkart goto abort; 2249f945901fSAndreas Fenkart } 22502cd3a2a5SAndreas Fenkart 225197978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 225297978a44SAndreas Fenkart } else { 225397978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 22542cd3a2a5SAndreas Fenkart } 225597978a44SAndreas Fenkart 2256f945901fSAndreas Fenkart abort: 22572cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2258f945901fSAndreas Fenkart return ret; 2259fa4aa2d4SBalaji T K } 2260fa4aa2d4SBalaji T K 2261fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2262fa4aa2d4SBalaji T K { 2263fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22642cd3a2a5SAndreas Fenkart unsigned long flags; 2265fa4aa2d4SBalaji T K 2266fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2267fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2268927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2269fa4aa2d4SBalaji T K 22702cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22712cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22722cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22732cd3a2a5SAndreas Fenkart 227497978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 227597978a44SAndreas Fenkart 227697978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 22772cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 22782cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 22792cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 228097978a44SAndreas Fenkart } else { 228197978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 22822cd3a2a5SAndreas Fenkart } 22832cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2284fa4aa2d4SBalaji T K return 0; 2285fa4aa2d4SBalaji T K } 2286fa4aa2d4SBalaji T K 2287a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 22883d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2289fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2290fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2291a791daa1SKevin Hilman }; 2292a791daa1SKevin Hilman 2293a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2294efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22950433c143SBill Pemberton .remove = omap_hsmmc_remove, 2296a45c6cb8SMadhusudhan Chikkature .driver = { 2297a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2298a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 229946856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2300a45c6cb8SMadhusudhan Chikkature }, 2301a45c6cb8SMadhusudhan Chikkature }; 2302a45c6cb8SMadhusudhan Chikkature 2303b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2304a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2305a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2306a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2307a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2308