1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20d900f712SDenis Karpov #include <linux/debugfs.h> 21d900f712SDenis Karpov #include <linux/seq_file.h> 22a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/workqueue.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3013189e78SJarkko Lavinen #include <linux/mmc/core.h> 31a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 32a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 33a45c6cb8SMadhusudhan Chikkature #include <mach/dma.h> 34a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 35a45c6cb8SMadhusudhan Chikkature #include <mach/board.h> 36a45c6cb8SMadhusudhan Chikkature #include <mach/mmc.h> 37a45c6cb8SMadhusudhan Chikkature #include <mach/cpu.h> 38a45c6cb8SMadhusudhan Chikkature 39a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 40a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 4111dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 42a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 43a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 44a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 45a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 46a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 57a45c6cb8SMadhusudhan Chikkature 58a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 59a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 60a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 61a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 62eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 631b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 64a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 65a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 66a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 67a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 68a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 69a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 70a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 71a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 72a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 73a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 74a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 75a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 76a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 77ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 78ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 79a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 80a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 81a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 82a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 83a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 84a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 85a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 8673153010SJarkko Lavinen #define DW8 (1 << 5) 87a45c6cb8SMadhusudhan Chikkature #define CC 0x1 88a45c6cb8SMadhusudhan Chikkature #define TC 0x02 89a45c6cb8SMadhusudhan Chikkature #define OD 0x1 90a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 91a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 92a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 93a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 94a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 95a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 96a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 97a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 98a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 99a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 100a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10111dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10211dd62a7SDenis Karpov #define RESETDONE (1 << 0) 103a45c6cb8SMadhusudhan Chikkature 104a45c6cb8SMadhusudhan Chikkature /* 105a45c6cb8SMadhusudhan Chikkature * FIXME: Most likely all the data using these _DEVID defines should come 106a45c6cb8SMadhusudhan Chikkature * from the platform_data, or implemented in controller and slot specific 107a45c6cb8SMadhusudhan Chikkature * functions. 108a45c6cb8SMadhusudhan Chikkature */ 109a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC1_DEVID 0 110a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC2_DEVID 1 111f3e2f1ddSGrazvydas Ignotas #define OMAP_MMC3_DEVID 2 112a45c6cb8SMadhusudhan Chikkature 113a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 114a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_MASTER_CLOCK 96000000 115a45c6cb8SMadhusudhan Chikkature #define DRIVER_NAME "mmci-omap-hs" 116a45c6cb8SMadhusudhan Chikkature 117dd498effSDenis Karpov /* Timeouts for entering power saving states on inactivity, msec */ 118dd498effSDenis Karpov #define OMAP_MMC_DISABLED_TIMEOUT 100 11913189e78SJarkko Lavinen #define OMAP_MMC_SLEEP_TIMEOUT 1000 12013189e78SJarkko Lavinen #define OMAP_MMC_OFF_TIMEOUT 8000 121dd498effSDenis Karpov 122a45c6cb8SMadhusudhan Chikkature /* 123a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 124a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 125a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 126a45c6cb8SMadhusudhan Chikkature */ 127a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 128a45c6cb8SMadhusudhan Chikkature 129a45c6cb8SMadhusudhan Chikkature /* 130a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 131a45c6cb8SMadhusudhan Chikkature */ 132a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 133a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 134a45c6cb8SMadhusudhan Chikkature 135a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 136a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 137a45c6cb8SMadhusudhan Chikkature 13870a3341aSDenis Karpov struct omap_hsmmc_host { 139a45c6cb8SMadhusudhan Chikkature struct device *dev; 140a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 141a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 142a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 143a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 144a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 145a45c6cb8SMadhusudhan Chikkature struct clk *iclk; 146a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 147a45c6cb8SMadhusudhan Chikkature struct semaphore sem; 148a45c6cb8SMadhusudhan Chikkature struct work_struct mmc_carddetect_work; 149a45c6cb8SMadhusudhan Chikkature void __iomem *base; 150a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1514dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 1524dffd7a2SAdrian Hunter unsigned long flags; 153a45c6cb8SMadhusudhan Chikkature unsigned int id; 154a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1550ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 156a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 157a3621465SAdrian Hunter unsigned char power_mode; 158a45c6cb8SMadhusudhan Chikkature u32 *buffer; 159a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 160a45c6cb8SMadhusudhan Chikkature int suspended; 161a45c6cb8SMadhusudhan Chikkature int irq; 162a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 163f3e2f1ddSGrazvydas Ignotas int dma_line_tx, dma_line_rx; 164a45c6cb8SMadhusudhan Chikkature int slot_id; 165a45c6cb8SMadhusudhan Chikkature int dbclk_enabled; 1664a694dc9SAdrian Hunter int response_busy; 16711dd62a7SDenis Karpov int context_loss; 168dd498effSDenis Karpov int dpm_state; 169623821f7SAdrian Hunter int vdd; 17011dd62a7SDenis Karpov 171a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 172a45c6cb8SMadhusudhan Chikkature }; 173a45c6cb8SMadhusudhan Chikkature 174a45c6cb8SMadhusudhan Chikkature /* 175a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 176a45c6cb8SMadhusudhan Chikkature */ 17770a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 178a45c6cb8SMadhusudhan Chikkature { 179a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 180a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 181a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 182a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 183a45c6cb8SMadhusudhan Chikkature } 184a45c6cb8SMadhusudhan Chikkature 18511dd62a7SDenis Karpov #ifdef CONFIG_PM 18611dd62a7SDenis Karpov 18711dd62a7SDenis Karpov /* 18811dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 18911dd62a7SDenis Karpov * power state change. 19011dd62a7SDenis Karpov */ 19170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 19211dd62a7SDenis Karpov { 19311dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 19411dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 19511dd62a7SDenis Karpov int context_loss = 0; 19611dd62a7SDenis Karpov u32 hctl, capa, con; 19711dd62a7SDenis Karpov u16 dsor = 0; 19811dd62a7SDenis Karpov unsigned long timeout; 19911dd62a7SDenis Karpov 20011dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 20111dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 20211dd62a7SDenis Karpov if (context_loss < 0) 20311dd62a7SDenis Karpov return 1; 20411dd62a7SDenis Karpov } 20511dd62a7SDenis Karpov 20611dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 20711dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 20811dd62a7SDenis Karpov if (host->context_loss == context_loss) 20911dd62a7SDenis Karpov return 1; 21011dd62a7SDenis Karpov 21111dd62a7SDenis Karpov /* Wait for hardware reset */ 21211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 21311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 21411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 21511dd62a7SDenis Karpov ; 21611dd62a7SDenis Karpov 21711dd62a7SDenis Karpov /* Do software reset */ 21811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 21911dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 22011dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 22111dd62a7SDenis Karpov && time_before(jiffies, timeout)) 22211dd62a7SDenis Karpov ; 22311dd62a7SDenis Karpov 22411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 22511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 22611dd62a7SDenis Karpov 22711dd62a7SDenis Karpov if (host->id == OMAP_MMC1_DEVID) { 22811dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 22911dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 23011dd62a7SDenis Karpov hctl = SDVS18; 23111dd62a7SDenis Karpov else 23211dd62a7SDenis Karpov hctl = SDVS30; 23311dd62a7SDenis Karpov capa = VS30 | VS18; 23411dd62a7SDenis Karpov } else { 23511dd62a7SDenis Karpov hctl = SDVS18; 23611dd62a7SDenis Karpov capa = VS18; 23711dd62a7SDenis Karpov } 23811dd62a7SDenis Karpov 23911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 24011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 24111dd62a7SDenis Karpov 24211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 24311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 24411dd62a7SDenis Karpov 24511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 24611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 24711dd62a7SDenis Karpov 24811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 24911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 25011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 25111dd62a7SDenis Karpov ; 25211dd62a7SDenis Karpov 25311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 25411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 25511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 25611dd62a7SDenis Karpov 25711dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 25811dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 25911dd62a7SDenis Karpov goto out; 26011dd62a7SDenis Karpov 26111dd62a7SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 26211dd62a7SDenis Karpov switch (ios->bus_width) { 26311dd62a7SDenis Karpov case MMC_BUS_WIDTH_8: 26411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 26511dd62a7SDenis Karpov break; 26611dd62a7SDenis Karpov case MMC_BUS_WIDTH_4: 26711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 26811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 26911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 27011dd62a7SDenis Karpov break; 27111dd62a7SDenis Karpov case MMC_BUS_WIDTH_1: 27211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 27311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 27411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 27511dd62a7SDenis Karpov break; 27611dd62a7SDenis Karpov } 27711dd62a7SDenis Karpov 27811dd62a7SDenis Karpov if (ios->clock) { 27911dd62a7SDenis Karpov dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 28011dd62a7SDenis Karpov if (dsor < 1) 28111dd62a7SDenis Karpov dsor = 1; 28211dd62a7SDenis Karpov 28311dd62a7SDenis Karpov if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 28411dd62a7SDenis Karpov dsor++; 28511dd62a7SDenis Karpov 28611dd62a7SDenis Karpov if (dsor > 250) 28711dd62a7SDenis Karpov dsor = 250; 28811dd62a7SDenis Karpov } 28911dd62a7SDenis Karpov 29011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 29111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 29211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 29311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 29411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 29511dd62a7SDenis Karpov 29611dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 29711dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 29811dd62a7SDenis Karpov && time_before(jiffies, timeout)) 29911dd62a7SDenis Karpov ; 30011dd62a7SDenis Karpov 30111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 30211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 30311dd62a7SDenis Karpov 30411dd62a7SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 30511dd62a7SDenis Karpov if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 30611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | OD); 30711dd62a7SDenis Karpov else 30811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 30911dd62a7SDenis Karpov out: 31011dd62a7SDenis Karpov host->context_loss = context_loss; 31111dd62a7SDenis Karpov 31211dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 31311dd62a7SDenis Karpov return 0; 31411dd62a7SDenis Karpov } 31511dd62a7SDenis Karpov 31611dd62a7SDenis Karpov /* 31711dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 31811dd62a7SDenis Karpov */ 31970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 32011dd62a7SDenis Karpov { 32111dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 32211dd62a7SDenis Karpov int context_loss; 32311dd62a7SDenis Karpov 32411dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 32511dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 32611dd62a7SDenis Karpov if (context_loss < 0) 32711dd62a7SDenis Karpov return; 32811dd62a7SDenis Karpov host->context_loss = context_loss; 32911dd62a7SDenis Karpov } 33011dd62a7SDenis Karpov } 33111dd62a7SDenis Karpov 33211dd62a7SDenis Karpov #else 33311dd62a7SDenis Karpov 33470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 33511dd62a7SDenis Karpov { 33611dd62a7SDenis Karpov return 0; 33711dd62a7SDenis Karpov } 33811dd62a7SDenis Karpov 33970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 34011dd62a7SDenis Karpov { 34111dd62a7SDenis Karpov } 34211dd62a7SDenis Karpov 34311dd62a7SDenis Karpov #endif 34411dd62a7SDenis Karpov 345a45c6cb8SMadhusudhan Chikkature /* 346a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 347a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 348a45c6cb8SMadhusudhan Chikkature */ 34970a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 350a45c6cb8SMadhusudhan Chikkature { 351a45c6cb8SMadhusudhan Chikkature int reg = 0; 352a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 353a45c6cb8SMadhusudhan Chikkature 354a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 355a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 356a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 357a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 358a45c6cb8SMadhusudhan Chikkature 359a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 360a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 361a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 362a45c6cb8SMadhusudhan Chikkature 363a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 364a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 365c653a6d4SAdrian Hunter 366c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 367c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 368c653a6d4SAdrian Hunter 369a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 370a45c6cb8SMadhusudhan Chikkature } 371a45c6cb8SMadhusudhan Chikkature 372a45c6cb8SMadhusudhan Chikkature static inline 37370a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 374a45c6cb8SMadhusudhan Chikkature { 375a45c6cb8SMadhusudhan Chikkature int r = 1; 376a45c6cb8SMadhusudhan Chikkature 377191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 378191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 379a45c6cb8SMadhusudhan Chikkature return r; 380a45c6cb8SMadhusudhan Chikkature } 381a45c6cb8SMadhusudhan Chikkature 382a45c6cb8SMadhusudhan Chikkature static ssize_t 38370a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 384a45c6cb8SMadhusudhan Chikkature char *buf) 385a45c6cb8SMadhusudhan Chikkature { 386a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 38770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 388a45c6cb8SMadhusudhan Chikkature 38970a3341aSDenis Karpov return sprintf(buf, "%s\n", 39070a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 391a45c6cb8SMadhusudhan Chikkature } 392a45c6cb8SMadhusudhan Chikkature 39370a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 394a45c6cb8SMadhusudhan Chikkature 395a45c6cb8SMadhusudhan Chikkature static ssize_t 39670a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 397a45c6cb8SMadhusudhan Chikkature char *buf) 398a45c6cb8SMadhusudhan Chikkature { 399a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 40070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 401a45c6cb8SMadhusudhan Chikkature 402191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 403a45c6cb8SMadhusudhan Chikkature } 404a45c6cb8SMadhusudhan Chikkature 40570a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 406a45c6cb8SMadhusudhan Chikkature 407a45c6cb8SMadhusudhan Chikkature /* 408a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 409a45c6cb8SMadhusudhan Chikkature */ 410a45c6cb8SMadhusudhan Chikkature static void 41170a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 412a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 413a45c6cb8SMadhusudhan Chikkature { 414a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 415a45c6cb8SMadhusudhan Chikkature 416a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 417a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 418a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 419a45c6cb8SMadhusudhan Chikkature 420a45c6cb8SMadhusudhan Chikkature /* 421a45c6cb8SMadhusudhan Chikkature * Clear status bits and enable interrupts 422a45c6cb8SMadhusudhan Chikkature */ 423a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 424a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 425ccdfe3a6SAnand Gadiyar 426ccdfe3a6SAnand Gadiyar if (host->use_dma) 427ccdfe3a6SAnand Gadiyar OMAP_HSMMC_WRITE(host->base, IE, 428ccdfe3a6SAnand Gadiyar INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE)); 429ccdfe3a6SAnand Gadiyar else 430a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 431a45c6cb8SMadhusudhan Chikkature 4324a694dc9SAdrian Hunter host->response_busy = 0; 433a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 434a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 435a45c6cb8SMadhusudhan Chikkature resptype = 1; 4364a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 4374a694dc9SAdrian Hunter resptype = 3; 4384a694dc9SAdrian Hunter host->response_busy = 1; 4394a694dc9SAdrian Hunter } else 440a45c6cb8SMadhusudhan Chikkature resptype = 2; 441a45c6cb8SMadhusudhan Chikkature } 442a45c6cb8SMadhusudhan Chikkature 443a45c6cb8SMadhusudhan Chikkature /* 444a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 445a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 446a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 447a45c6cb8SMadhusudhan Chikkature */ 448a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 449a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 450a45c6cb8SMadhusudhan Chikkature 451a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 452a45c6cb8SMadhusudhan Chikkature 453a45c6cb8SMadhusudhan Chikkature if (data) { 454a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 455a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 456a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 457a45c6cb8SMadhusudhan Chikkature else 458a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 459a45c6cb8SMadhusudhan Chikkature } 460a45c6cb8SMadhusudhan Chikkature 461a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 462a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 463a45c6cb8SMadhusudhan Chikkature 4644dffd7a2SAdrian Hunter /* 4654dffd7a2SAdrian Hunter * In an interrupt context (i.e. STOP command), the spinlock is unlocked 4664dffd7a2SAdrian Hunter * by the interrupt handler, otherwise (i.e. for a new request) it is 4674dffd7a2SAdrian Hunter * unlocked here. 4684dffd7a2SAdrian Hunter */ 4694dffd7a2SAdrian Hunter if (!in_interrupt()) 4704dffd7a2SAdrian Hunter spin_unlock_irqrestore(&host->irq_lock, host->flags); 4714dffd7a2SAdrian Hunter 472a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 473a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 474a45c6cb8SMadhusudhan Chikkature } 475a45c6cb8SMadhusudhan Chikkature 4760ccd76d4SJuha Yrjola static int 47770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 4780ccd76d4SJuha Yrjola { 4790ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 4800ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 4810ccd76d4SJuha Yrjola else 4820ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 4830ccd76d4SJuha Yrjola } 4840ccd76d4SJuha Yrjola 485a45c6cb8SMadhusudhan Chikkature /* 486a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 487a45c6cb8SMadhusudhan Chikkature */ 488a45c6cb8SMadhusudhan Chikkature static void 48970a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 490a45c6cb8SMadhusudhan Chikkature { 4914a694dc9SAdrian Hunter if (!data) { 4924a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 4934a694dc9SAdrian Hunter 49423050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 49523050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 49623050103SAdrian Hunter host->response_busy) { 49723050103SAdrian Hunter host->response_busy = 0; 49823050103SAdrian Hunter return; 49923050103SAdrian Hunter } 50023050103SAdrian Hunter 5014a694dc9SAdrian Hunter host->mrq = NULL; 5024a694dc9SAdrian Hunter mmc_request_done(host->mmc, mrq); 5034a694dc9SAdrian Hunter return; 5044a694dc9SAdrian Hunter } 5054a694dc9SAdrian Hunter 506a45c6cb8SMadhusudhan Chikkature host->data = NULL; 507a45c6cb8SMadhusudhan Chikkature 508a45c6cb8SMadhusudhan Chikkature if (host->use_dma && host->dma_ch != -1) 509a45c6cb8SMadhusudhan Chikkature dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 51070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, data)); 511a45c6cb8SMadhusudhan Chikkature 512a45c6cb8SMadhusudhan Chikkature if (!data->error) 513a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 514a45c6cb8SMadhusudhan Chikkature else 515a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 516a45c6cb8SMadhusudhan Chikkature 517a45c6cb8SMadhusudhan Chikkature if (!data->stop) { 518a45c6cb8SMadhusudhan Chikkature host->mrq = NULL; 519a45c6cb8SMadhusudhan Chikkature mmc_request_done(host->mmc, data->mrq); 520a45c6cb8SMadhusudhan Chikkature return; 521a45c6cb8SMadhusudhan Chikkature } 52270a3341aSDenis Karpov omap_hsmmc_start_command(host, data->stop, NULL); 523a45c6cb8SMadhusudhan Chikkature } 524a45c6cb8SMadhusudhan Chikkature 525a45c6cb8SMadhusudhan Chikkature /* 526a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 527a45c6cb8SMadhusudhan Chikkature */ 528a45c6cb8SMadhusudhan Chikkature static void 52970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 530a45c6cb8SMadhusudhan Chikkature { 531a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 532a45c6cb8SMadhusudhan Chikkature 533a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 534a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 535a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 536a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 537a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 538a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 539a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 540a45c6cb8SMadhusudhan Chikkature } else { 541a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 542a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 543a45c6cb8SMadhusudhan Chikkature } 544a45c6cb8SMadhusudhan Chikkature } 5454a694dc9SAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) { 546a45c6cb8SMadhusudhan Chikkature host->mrq = NULL; 547a45c6cb8SMadhusudhan Chikkature mmc_request_done(host->mmc, cmd->mrq); 548a45c6cb8SMadhusudhan Chikkature } 549a45c6cb8SMadhusudhan Chikkature } 550a45c6cb8SMadhusudhan Chikkature 551a45c6cb8SMadhusudhan Chikkature /* 552a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 553a45c6cb8SMadhusudhan Chikkature */ 55470a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 555a45c6cb8SMadhusudhan Chikkature { 55682788ff5SJarkko Lavinen host->data->error = errno; 557a45c6cb8SMadhusudhan Chikkature 558a45c6cb8SMadhusudhan Chikkature if (host->use_dma && host->dma_ch != -1) { 559a45c6cb8SMadhusudhan Chikkature dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 56070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 561a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 562a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 563a45c6cb8SMadhusudhan Chikkature up(&host->sem); 564a45c6cb8SMadhusudhan Chikkature } 565a45c6cb8SMadhusudhan Chikkature host->data = NULL; 566a45c6cb8SMadhusudhan Chikkature } 567a45c6cb8SMadhusudhan Chikkature 568a45c6cb8SMadhusudhan Chikkature /* 569a45c6cb8SMadhusudhan Chikkature * Readable error output 570a45c6cb8SMadhusudhan Chikkature */ 571a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 57270a3341aSDenis Karpov static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 573a45c6cb8SMadhusudhan Chikkature { 574a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 57570a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 576a45c6cb8SMadhusudhan Chikkature "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 577a45c6cb8SMadhusudhan Chikkature "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 578a45c6cb8SMadhusudhan Chikkature "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 579a45c6cb8SMadhusudhan Chikkature "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 580a45c6cb8SMadhusudhan Chikkature }; 581a45c6cb8SMadhusudhan Chikkature char res[256]; 582a45c6cb8SMadhusudhan Chikkature char *buf = res; 583a45c6cb8SMadhusudhan Chikkature int len, i; 584a45c6cb8SMadhusudhan Chikkature 585a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 586a45c6cb8SMadhusudhan Chikkature buf += len; 587a45c6cb8SMadhusudhan Chikkature 58870a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 589a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 59070a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 591a45c6cb8SMadhusudhan Chikkature buf += len; 592a45c6cb8SMadhusudhan Chikkature } 593a45c6cb8SMadhusudhan Chikkature 594a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 595a45c6cb8SMadhusudhan Chikkature } 596a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 597a45c6cb8SMadhusudhan Chikkature 5983ebf74b1SJean Pihet /* 5993ebf74b1SJean Pihet * MMC controller internal state machines reset 6003ebf74b1SJean Pihet * 6013ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 6023ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 6033ebf74b1SJean Pihet * Can be called from interrupt context 6043ebf74b1SJean Pihet */ 60570a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 6063ebf74b1SJean Pihet unsigned long bit) 6073ebf74b1SJean Pihet { 6083ebf74b1SJean Pihet unsigned long i = 0; 6093ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 6103ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 6113ebf74b1SJean Pihet 6123ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 6133ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 6143ebf74b1SJean Pihet 6153ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 6163ebf74b1SJean Pihet (i++ < limit)) 6173ebf74b1SJean Pihet cpu_relax(); 6183ebf74b1SJean Pihet 6193ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 6203ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 6213ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 6223ebf74b1SJean Pihet __func__); 6233ebf74b1SJean Pihet } 624a45c6cb8SMadhusudhan Chikkature 625a45c6cb8SMadhusudhan Chikkature /* 626a45c6cb8SMadhusudhan Chikkature * MMC controller IRQ handler 627a45c6cb8SMadhusudhan Chikkature */ 62870a3341aSDenis Karpov static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 629a45c6cb8SMadhusudhan Chikkature { 63070a3341aSDenis Karpov struct omap_hsmmc_host *host = dev_id; 631a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 632a45c6cb8SMadhusudhan Chikkature int end_cmd = 0, end_trans = 0, status; 633a45c6cb8SMadhusudhan Chikkature 6344dffd7a2SAdrian Hunter spin_lock(&host->irq_lock); 6354dffd7a2SAdrian Hunter 6364a694dc9SAdrian Hunter if (host->mrq == NULL) { 637a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, 638a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, STAT)); 63900adadc1SKevin Hilman /* Flush posted write */ 64000adadc1SKevin Hilman OMAP_HSMMC_READ(host->base, STAT); 6414dffd7a2SAdrian Hunter spin_unlock(&host->irq_lock); 642a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 643a45c6cb8SMadhusudhan Chikkature } 644a45c6cb8SMadhusudhan Chikkature 645a45c6cb8SMadhusudhan Chikkature data = host->data; 646a45c6cb8SMadhusudhan Chikkature status = OMAP_HSMMC_READ(host->base, STAT); 647a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 648a45c6cb8SMadhusudhan Chikkature 649a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 650a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 65170a3341aSDenis Karpov omap_hsmmc_report_irq(host, status); 652a45c6cb8SMadhusudhan Chikkature #endif 653a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 654a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 655a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 656a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 65770a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 658191d1f1dSDenis Karpov SRC); 659a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 660a45c6cb8SMadhusudhan Chikkature } else { 661a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 662a45c6cb8SMadhusudhan Chikkature } 663a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 664a45c6cb8SMadhusudhan Chikkature } 6654a694dc9SAdrian Hunter if (host->data || host->response_busy) { 6664a694dc9SAdrian Hunter if (host->data) 66770a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 66870a3341aSDenis Karpov -ETIMEDOUT); 6694a694dc9SAdrian Hunter host->response_busy = 0; 67070a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 671c232f457SJean Pihet } 672a45c6cb8SMadhusudhan Chikkature } 673a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 674a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 6754a694dc9SAdrian Hunter if (host->data || host->response_busy) { 6764a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 6774a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 6784a694dc9SAdrian Hunter 6794a694dc9SAdrian Hunter if (host->data) 68070a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 681a45c6cb8SMadhusudhan Chikkature else 6824a694dc9SAdrian Hunter host->mrq->cmd->error = err; 6834a694dc9SAdrian Hunter host->response_busy = 0; 68470a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 685a45c6cb8SMadhusudhan Chikkature end_trans = 1; 686a45c6cb8SMadhusudhan Chikkature } 687a45c6cb8SMadhusudhan Chikkature } 688a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 689a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 690a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 691a45c6cb8SMadhusudhan Chikkature if (host->cmd) 692a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 693a45c6cb8SMadhusudhan Chikkature if (host->data) 694a45c6cb8SMadhusudhan Chikkature end_trans = 1; 695a45c6cb8SMadhusudhan Chikkature } 696a45c6cb8SMadhusudhan Chikkature } 697a45c6cb8SMadhusudhan Chikkature 698a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 69900adadc1SKevin Hilman /* Flush posted write */ 70000adadc1SKevin Hilman OMAP_HSMMC_READ(host->base, STAT); 701a45c6cb8SMadhusudhan Chikkature 702a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 70370a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 7040a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 70570a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 706a45c6cb8SMadhusudhan Chikkature 7074dffd7a2SAdrian Hunter spin_unlock(&host->irq_lock); 7084dffd7a2SAdrian Hunter 709a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 710a45c6cb8SMadhusudhan Chikkature } 711a45c6cb8SMadhusudhan Chikkature 71270a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 713e13bb300SAdrian Hunter { 714e13bb300SAdrian Hunter unsigned long i; 715e13bb300SAdrian Hunter 716e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 717e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 718e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 719e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 720e13bb300SAdrian Hunter break; 721e13bb300SAdrian Hunter cpu_relax(); 722e13bb300SAdrian Hunter } 723e13bb300SAdrian Hunter } 724e13bb300SAdrian Hunter 725a45c6cb8SMadhusudhan Chikkature /* 726eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 727eb250826SDavid Brownell * 728eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 729eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 730eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 731a45c6cb8SMadhusudhan Chikkature */ 73270a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 733a45c6cb8SMadhusudhan Chikkature { 734a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 735a45c6cb8SMadhusudhan Chikkature int ret; 736a45c6cb8SMadhusudhan Chikkature 737a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 738a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 739a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 740a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 741a45c6cb8SMadhusudhan Chikkature 742a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 743a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 744a45c6cb8SMadhusudhan Chikkature if (ret != 0) 745a45c6cb8SMadhusudhan Chikkature goto err; 746a45c6cb8SMadhusudhan Chikkature 747a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 748a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 749a45c6cb8SMadhusudhan Chikkature if (ret != 0) 750a45c6cb8SMadhusudhan Chikkature goto err; 751a45c6cb8SMadhusudhan Chikkature 752a45c6cb8SMadhusudhan Chikkature clk_enable(host->fclk); 753a45c6cb8SMadhusudhan Chikkature clk_enable(host->iclk); 754a45c6cb8SMadhusudhan Chikkature clk_enable(host->dbclk); 755a45c6cb8SMadhusudhan Chikkature 756a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 757a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 758a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 759eb250826SDavid Brownell 760a45c6cb8SMadhusudhan Chikkature /* 761a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 762a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 76370a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 764a45c6cb8SMadhusudhan Chikkature * 765eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 766eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 767eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 768eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 769eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 770eb250826SDavid Brownell * 771eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 772eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 773eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 774a45c6cb8SMadhusudhan Chikkature */ 775eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 776a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 777eb250826SDavid Brownell else 778eb250826SDavid Brownell reg_val |= SDVS30; 779a45c6cb8SMadhusudhan Chikkature 780a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 781e13bb300SAdrian Hunter set_sd_bus_power(host); 782a45c6cb8SMadhusudhan Chikkature 783a45c6cb8SMadhusudhan Chikkature return 0; 784a45c6cb8SMadhusudhan Chikkature err: 785a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 786a45c6cb8SMadhusudhan Chikkature return ret; 787a45c6cb8SMadhusudhan Chikkature } 788a45c6cb8SMadhusudhan Chikkature 789a45c6cb8SMadhusudhan Chikkature /* 790a45c6cb8SMadhusudhan Chikkature * Work Item to notify the core about card insertion/removal 791a45c6cb8SMadhusudhan Chikkature */ 79270a3341aSDenis Karpov static void omap_hsmmc_detect(struct work_struct *work) 793a45c6cb8SMadhusudhan Chikkature { 79470a3341aSDenis Karpov struct omap_hsmmc_host *host = 79570a3341aSDenis Karpov container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 796249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 797a6b2240dSAdrian Hunter int carddetect; 798249d0fa9SDavid Brownell 799a6b2240dSAdrian Hunter if (host->suspended) 800a6b2240dSAdrian Hunter return; 801a45c6cb8SMadhusudhan Chikkature 802a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 803a6b2240dSAdrian Hunter 804191d1f1dSDenis Karpov if (slot->card_detect) 805a6b2240dSAdrian Hunter carddetect = slot->card_detect(slot->card_detect_irq); 806a6b2240dSAdrian Hunter else 807a6b2240dSAdrian Hunter carddetect = -ENOSYS; 808a6b2240dSAdrian Hunter 809a6b2240dSAdrian Hunter if (carddetect) { 810a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 811a45c6cb8SMadhusudhan Chikkature } else { 8125e2ea617SAdrian Hunter mmc_host_enable(host->mmc); 81370a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 8145e2ea617SAdrian Hunter mmc_host_lazy_disable(host->mmc); 81570a3341aSDenis Karpov 816a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 817a45c6cb8SMadhusudhan Chikkature } 818a45c6cb8SMadhusudhan Chikkature } 819a45c6cb8SMadhusudhan Chikkature 820a45c6cb8SMadhusudhan Chikkature /* 821a45c6cb8SMadhusudhan Chikkature * ISR for handling card insertion and removal 822a45c6cb8SMadhusudhan Chikkature */ 82370a3341aSDenis Karpov static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 824a45c6cb8SMadhusudhan Chikkature { 82570a3341aSDenis Karpov struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 826a45c6cb8SMadhusudhan Chikkature 827a6b2240dSAdrian Hunter if (host->suspended) 828a6b2240dSAdrian Hunter return IRQ_HANDLED; 829a45c6cb8SMadhusudhan Chikkature schedule_work(&host->mmc_carddetect_work); 830a45c6cb8SMadhusudhan Chikkature 831a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 832a45c6cb8SMadhusudhan Chikkature } 833a45c6cb8SMadhusudhan Chikkature 83470a3341aSDenis Karpov static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 8350ccd76d4SJuha Yrjola struct mmc_data *data) 8360ccd76d4SJuha Yrjola { 8370ccd76d4SJuha Yrjola int sync_dev; 8380ccd76d4SJuha Yrjola 839f3e2f1ddSGrazvydas Ignotas if (data->flags & MMC_DATA_WRITE) 840f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_tx; 8410ccd76d4SJuha Yrjola else 842f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_rx; 8430ccd76d4SJuha Yrjola return sync_dev; 8440ccd76d4SJuha Yrjola } 8450ccd76d4SJuha Yrjola 84670a3341aSDenis Karpov static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 8470ccd76d4SJuha Yrjola struct mmc_data *data, 8480ccd76d4SJuha Yrjola struct scatterlist *sgl) 8490ccd76d4SJuha Yrjola { 8500ccd76d4SJuha Yrjola int blksz, nblk, dma_ch; 8510ccd76d4SJuha Yrjola 8520ccd76d4SJuha Yrjola dma_ch = host->dma_ch; 8530ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) { 8540ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 8550ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 8560ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 8570ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 8580ccd76d4SJuha Yrjola } else { 8590ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 8600ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 8610ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 8620ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 8630ccd76d4SJuha Yrjola } 8640ccd76d4SJuha Yrjola 8650ccd76d4SJuha Yrjola blksz = host->data->blksz; 8660ccd76d4SJuha Yrjola nblk = sg_dma_len(sgl) / blksz; 8670ccd76d4SJuha Yrjola 8680ccd76d4SJuha Yrjola omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 8690ccd76d4SJuha Yrjola blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 87070a3341aSDenis Karpov omap_hsmmc_get_dma_sync_dev(host, data), 8710ccd76d4SJuha Yrjola !(data->flags & MMC_DATA_WRITE)); 8720ccd76d4SJuha Yrjola 8730ccd76d4SJuha Yrjola omap_start_dma(dma_ch); 8740ccd76d4SJuha Yrjola } 8750ccd76d4SJuha Yrjola 876a45c6cb8SMadhusudhan Chikkature /* 877a45c6cb8SMadhusudhan Chikkature * DMA call back function 878a45c6cb8SMadhusudhan Chikkature */ 87970a3341aSDenis Karpov static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) 880a45c6cb8SMadhusudhan Chikkature { 88170a3341aSDenis Karpov struct omap_hsmmc_host *host = data; 882a45c6cb8SMadhusudhan Chikkature 883a45c6cb8SMadhusudhan Chikkature if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) 884a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); 885a45c6cb8SMadhusudhan Chikkature 886a45c6cb8SMadhusudhan Chikkature if (host->dma_ch < 0) 887a45c6cb8SMadhusudhan Chikkature return; 888a45c6cb8SMadhusudhan Chikkature 8890ccd76d4SJuha Yrjola host->dma_sg_idx++; 8900ccd76d4SJuha Yrjola if (host->dma_sg_idx < host->dma_len) { 8910ccd76d4SJuha Yrjola /* Fire up the next transfer. */ 89270a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, host->data, 8930ccd76d4SJuha Yrjola host->data->sg + host->dma_sg_idx); 8940ccd76d4SJuha Yrjola return; 8950ccd76d4SJuha Yrjola } 8960ccd76d4SJuha Yrjola 897a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 898a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 899a45c6cb8SMadhusudhan Chikkature /* 900a45c6cb8SMadhusudhan Chikkature * DMA Callback: run in interrupt context. 90185b84322SAnand Gadiyar * mutex_unlock will throw a kernel warning if used. 902a45c6cb8SMadhusudhan Chikkature */ 903a45c6cb8SMadhusudhan Chikkature up(&host->sem); 904a45c6cb8SMadhusudhan Chikkature } 905a45c6cb8SMadhusudhan Chikkature 906a45c6cb8SMadhusudhan Chikkature /* 907a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 908a45c6cb8SMadhusudhan Chikkature */ 90970a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 91070a3341aSDenis Karpov struct mmc_request *req) 911a45c6cb8SMadhusudhan Chikkature { 9120ccd76d4SJuha Yrjola int dma_ch = 0, ret = 0, err = 1, i; 913a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 914a45c6cb8SMadhusudhan Chikkature 9150ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 916a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 9170ccd76d4SJuha Yrjola struct scatterlist *sgl; 9180ccd76d4SJuha Yrjola 9190ccd76d4SJuha Yrjola sgl = data->sg + i; 9200ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 9210ccd76d4SJuha Yrjola return -EINVAL; 9220ccd76d4SJuha Yrjola } 9230ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 9240ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 9250ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 9260ccd76d4SJuha Yrjola */ 9270ccd76d4SJuha Yrjola return -EINVAL; 9280ccd76d4SJuha Yrjola 929a45c6cb8SMadhusudhan Chikkature /* 930a45c6cb8SMadhusudhan Chikkature * If for some reason the DMA transfer is still active, 931a45c6cb8SMadhusudhan Chikkature * we wait for timeout period and free the dma 932a45c6cb8SMadhusudhan Chikkature */ 933a45c6cb8SMadhusudhan Chikkature if (host->dma_ch != -1) { 934a45c6cb8SMadhusudhan Chikkature set_current_state(TASK_UNINTERRUPTIBLE); 935a45c6cb8SMadhusudhan Chikkature schedule_timeout(100); 936a45c6cb8SMadhusudhan Chikkature if (down_trylock(&host->sem)) { 937a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 938a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 939a45c6cb8SMadhusudhan Chikkature up(&host->sem); 940a45c6cb8SMadhusudhan Chikkature return err; 941a45c6cb8SMadhusudhan Chikkature } 942a45c6cb8SMadhusudhan Chikkature } else { 943a45c6cb8SMadhusudhan Chikkature if (down_trylock(&host->sem)) 944a45c6cb8SMadhusudhan Chikkature return err; 945a45c6cb8SMadhusudhan Chikkature } 946a45c6cb8SMadhusudhan Chikkature 94770a3341aSDenis Karpov ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 94870a3341aSDenis Karpov "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 949a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 9500ccd76d4SJuha Yrjola dev_err(mmc_dev(host->mmc), 951a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 952a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 953a45c6cb8SMadhusudhan Chikkature return ret; 954a45c6cb8SMadhusudhan Chikkature } 955a45c6cb8SMadhusudhan Chikkature 956a45c6cb8SMadhusudhan Chikkature host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 95770a3341aSDenis Karpov data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 958a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 9590ccd76d4SJuha Yrjola host->dma_sg_idx = 0; 960a45c6cb8SMadhusudhan Chikkature 96170a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, data, data->sg); 962a45c6cb8SMadhusudhan Chikkature 963a45c6cb8SMadhusudhan Chikkature return 0; 964a45c6cb8SMadhusudhan Chikkature } 965a45c6cb8SMadhusudhan Chikkature 96670a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 967a45c6cb8SMadhusudhan Chikkature struct mmc_request *req) 968a45c6cb8SMadhusudhan Chikkature { 969a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 970a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 971a45c6cb8SMadhusudhan Chikkature 972a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 973a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 974a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 975a45c6cb8SMadhusudhan Chikkature clkd = 1; 976a45c6cb8SMadhusudhan Chikkature 977a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 978a45c6cb8SMadhusudhan Chikkature timeout = req->data->timeout_ns / cycle_ns; 979a45c6cb8SMadhusudhan Chikkature timeout += req->data->timeout_clks; 980a45c6cb8SMadhusudhan Chikkature if (timeout) { 981a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 982a45c6cb8SMadhusudhan Chikkature dto += 1; 983a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 984a45c6cb8SMadhusudhan Chikkature } 985a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 986a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 987a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 988a45c6cb8SMadhusudhan Chikkature dto += 1; 989a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 990a45c6cb8SMadhusudhan Chikkature dto -= 13; 991a45c6cb8SMadhusudhan Chikkature else 992a45c6cb8SMadhusudhan Chikkature dto = 0; 993a45c6cb8SMadhusudhan Chikkature if (dto > 14) 994a45c6cb8SMadhusudhan Chikkature dto = 14; 995a45c6cb8SMadhusudhan Chikkature } 996a45c6cb8SMadhusudhan Chikkature 997a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 998a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 999a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1000a45c6cb8SMadhusudhan Chikkature } 1001a45c6cb8SMadhusudhan Chikkature 1002a45c6cb8SMadhusudhan Chikkature /* 1003a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1004a45c6cb8SMadhusudhan Chikkature */ 1005a45c6cb8SMadhusudhan Chikkature static int 100670a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1007a45c6cb8SMadhusudhan Chikkature { 1008a45c6cb8SMadhusudhan Chikkature int ret; 1009a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1010a45c6cb8SMadhusudhan Chikkature 1011a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1012a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1013a45c6cb8SMadhusudhan Chikkature return 0; 1014a45c6cb8SMadhusudhan Chikkature } 1015a45c6cb8SMadhusudhan Chikkature 1016a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1017a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1018a45c6cb8SMadhusudhan Chikkature set_data_timeout(host, req); 1019a45c6cb8SMadhusudhan Chikkature 1020a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 102170a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1022a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1023a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1024a45c6cb8SMadhusudhan Chikkature return ret; 1025a45c6cb8SMadhusudhan Chikkature } 1026a45c6cb8SMadhusudhan Chikkature } 1027a45c6cb8SMadhusudhan Chikkature return 0; 1028a45c6cb8SMadhusudhan Chikkature } 1029a45c6cb8SMadhusudhan Chikkature 1030a45c6cb8SMadhusudhan Chikkature /* 1031a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1032a45c6cb8SMadhusudhan Chikkature */ 103370a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1034a45c6cb8SMadhusudhan Chikkature { 103570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1036a3f406f8SJarkko Lavinen int err; 1037a45c6cb8SMadhusudhan Chikkature 10384dffd7a2SAdrian Hunter /* 10394dffd7a2SAdrian Hunter * Prevent races with the interrupt handler because of unexpected 10404dffd7a2SAdrian Hunter * interrupts, but not if we are already in interrupt context i.e. 10414dffd7a2SAdrian Hunter * retries. 10424dffd7a2SAdrian Hunter */ 10434dffd7a2SAdrian Hunter if (!in_interrupt()) 10444dffd7a2SAdrian Hunter spin_lock_irqsave(&host->irq_lock, host->flags); 1045a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1046a45c6cb8SMadhusudhan Chikkature host->mrq = req; 104770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1048a3f406f8SJarkko Lavinen if (err) { 1049a3f406f8SJarkko Lavinen req->cmd->error = err; 1050a3f406f8SJarkko Lavinen if (req->data) 1051a3f406f8SJarkko Lavinen req->data->error = err; 1052a3f406f8SJarkko Lavinen host->mrq = NULL; 10534dffd7a2SAdrian Hunter if (!in_interrupt()) 10544dffd7a2SAdrian Hunter spin_unlock_irqrestore(&host->irq_lock, host->flags); 1055a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1056a3f406f8SJarkko Lavinen return; 1057a3f406f8SJarkko Lavinen } 1058a3f406f8SJarkko Lavinen 105970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1060a45c6cb8SMadhusudhan Chikkature } 1061a45c6cb8SMadhusudhan Chikkature 1062a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 106370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1064a45c6cb8SMadhusudhan Chikkature { 106570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1066a45c6cb8SMadhusudhan Chikkature u16 dsor = 0; 1067a45c6cb8SMadhusudhan Chikkature unsigned long regval; 1068a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 106973153010SJarkko Lavinen u32 con; 1070a3621465SAdrian Hunter int do_send_init_stream = 0; 1071a45c6cb8SMadhusudhan Chikkature 10725e2ea617SAdrian Hunter mmc_host_enable(host->mmc); 10735e2ea617SAdrian Hunter 1074a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1075a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1076a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1077a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1078a3621465SAdrian Hunter 0, 0); 1079623821f7SAdrian Hunter host->vdd = 0; 1080a45c6cb8SMadhusudhan Chikkature break; 1081a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1082a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1083a3621465SAdrian Hunter 1, ios->vdd); 1084623821f7SAdrian Hunter host->vdd = ios->vdd; 1085a45c6cb8SMadhusudhan Chikkature break; 1086a3621465SAdrian Hunter case MMC_POWER_ON: 1087a3621465SAdrian Hunter do_send_init_stream = 1; 1088a3621465SAdrian Hunter break; 1089a3621465SAdrian Hunter } 1090a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1091a45c6cb8SMadhusudhan Chikkature } 1092a45c6cb8SMadhusudhan Chikkature 1093dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1094dd498effSDenis Karpov 109573153010SJarkko Lavinen con = OMAP_HSMMC_READ(host->base, CON); 1096a45c6cb8SMadhusudhan Chikkature switch (mmc->ios.bus_width) { 109773153010SJarkko Lavinen case MMC_BUS_WIDTH_8: 109873153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 109973153010SJarkko Lavinen break; 1100a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_4: 110173153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1102a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1103a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1104a45c6cb8SMadhusudhan Chikkature break; 1105a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_1: 110673153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1107a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1108a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1109a45c6cb8SMadhusudhan Chikkature break; 1110a45c6cb8SMadhusudhan Chikkature } 1111a45c6cb8SMadhusudhan Chikkature 1112a45c6cb8SMadhusudhan Chikkature if (host->id == OMAP_MMC1_DEVID) { 1113eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1114eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1115eb250826SDavid Brownell */ 1116a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1117a45c6cb8SMadhusudhan Chikkature (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1118a45c6cb8SMadhusudhan Chikkature /* 1119a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1120a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1121a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1122a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1123a45c6cb8SMadhusudhan Chikkature */ 112470a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1125a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1126a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1127a45c6cb8SMadhusudhan Chikkature } 1128a45c6cb8SMadhusudhan Chikkature } 1129a45c6cb8SMadhusudhan Chikkature 1130a45c6cb8SMadhusudhan Chikkature if (ios->clock) { 1131a45c6cb8SMadhusudhan Chikkature dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1132a45c6cb8SMadhusudhan Chikkature if (dsor < 1) 1133a45c6cb8SMadhusudhan Chikkature dsor = 1; 1134a45c6cb8SMadhusudhan Chikkature 1135a45c6cb8SMadhusudhan Chikkature if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1136a45c6cb8SMadhusudhan Chikkature dsor++; 1137a45c6cb8SMadhusudhan Chikkature 1138a45c6cb8SMadhusudhan Chikkature if (dsor > 250) 1139a45c6cb8SMadhusudhan Chikkature dsor = 250; 1140a45c6cb8SMadhusudhan Chikkature } 114170a3341aSDenis Karpov omap_hsmmc_stop_clock(host); 1142a45c6cb8SMadhusudhan Chikkature regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1143a45c6cb8SMadhusudhan Chikkature regval = regval & ~(CLKD_MASK); 1144a45c6cb8SMadhusudhan Chikkature regval = regval | (dsor << 6) | (DTO << 16); 1145a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1146a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 1147a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1148a45c6cb8SMadhusudhan Chikkature 1149a45c6cb8SMadhusudhan Chikkature /* Wait till the ICS bit is set */ 1150a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 115111dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1152a45c6cb8SMadhusudhan Chikkature && time_before(jiffies, timeout)) 1153a45c6cb8SMadhusudhan Chikkature msleep(1); 1154a45c6cb8SMadhusudhan Chikkature 1155a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 1156a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1157a45c6cb8SMadhusudhan Chikkature 1158a3621465SAdrian Hunter if (do_send_init_stream) 1159a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1160a45c6cb8SMadhusudhan Chikkature 1161abb28e73SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 1162a45c6cb8SMadhusudhan Chikkature if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1163abb28e73SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1164abb28e73SDenis Karpov else 1165abb28e73SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 11665e2ea617SAdrian Hunter 1167dd498effSDenis Karpov if (host->power_mode == MMC_POWER_OFF) 1168dd498effSDenis Karpov mmc_host_disable(host->mmc); 1169dd498effSDenis Karpov else 11705e2ea617SAdrian Hunter mmc_host_lazy_disable(host->mmc); 1171a45c6cb8SMadhusudhan Chikkature } 1172a45c6cb8SMadhusudhan Chikkature 1173a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1174a45c6cb8SMadhusudhan Chikkature { 117570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1176a45c6cb8SMadhusudhan Chikkature 1177191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1178a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1179191d1f1dSDenis Karpov return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq); 1180a45c6cb8SMadhusudhan Chikkature } 1181a45c6cb8SMadhusudhan Chikkature 1182a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1183a45c6cb8SMadhusudhan Chikkature { 118470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1185a45c6cb8SMadhusudhan Chikkature 1186191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1187a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1188191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1189a45c6cb8SMadhusudhan Chikkature } 1190a45c6cb8SMadhusudhan Chikkature 119170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 11921b331e69SKim Kyuwon { 11931b331e69SKim Kyuwon u32 hctl, capa, value; 11941b331e69SKim Kyuwon 11951b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 11961b331e69SKim Kyuwon if (host->id == OMAP_MMC1_DEVID) { 11971b331e69SKim Kyuwon hctl = SDVS30; 11981b331e69SKim Kyuwon capa = VS30 | VS18; 11991b331e69SKim Kyuwon } else { 12001b331e69SKim Kyuwon hctl = SDVS18; 12011b331e69SKim Kyuwon capa = VS18; 12021b331e69SKim Kyuwon } 12031b331e69SKim Kyuwon 12041b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 12051b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 12061b331e69SKim Kyuwon 12071b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 12081b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 12091b331e69SKim Kyuwon 12101b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 12111b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 12121b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 12131b331e69SKim Kyuwon 12141b331e69SKim Kyuwon /* Set SD bus power bit */ 1215e13bb300SAdrian Hunter set_sd_bus_power(host); 12161b331e69SKim Kyuwon } 12171b331e69SKim Kyuwon 1218dd498effSDenis Karpov /* 1219dd498effSDenis Karpov * Dynamic power saving handling, FSM: 122013189e78SJarkko Lavinen * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 122113189e78SJarkko Lavinen * ^___________| | | 122213189e78SJarkko Lavinen * |______________________|______________________| 1223dd498effSDenis Karpov * 1224dd498effSDenis Karpov * ENABLED: mmc host is fully functional 1225dd498effSDenis Karpov * DISABLED: fclk is off 122613189e78SJarkko Lavinen * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1227623821f7SAdrian Hunter * REGSLEEP: fclk is off, voltage regulator is asleep 122813189e78SJarkko Lavinen * OFF: fclk is off, voltage regulator is off 1229dd498effSDenis Karpov * 1230dd498effSDenis Karpov * Transition handlers return the timeout for the next state transition 1231dd498effSDenis Karpov * or negative error. 1232dd498effSDenis Karpov */ 1233dd498effSDenis Karpov 123413189e78SJarkko Lavinen enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1235dd498effSDenis Karpov 1236dd498effSDenis Karpov /* Handler for [ENABLED -> DISABLED] transition */ 123770a3341aSDenis Karpov static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1238dd498effSDenis Karpov { 123970a3341aSDenis Karpov omap_hsmmc_context_save(host); 1240dd498effSDenis Karpov clk_disable(host->fclk); 1241dd498effSDenis Karpov host->dpm_state = DISABLED; 1242dd498effSDenis Karpov 1243dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1244dd498effSDenis Karpov 1245dd498effSDenis Karpov if (host->power_mode == MMC_POWER_OFF) 1246dd498effSDenis Karpov return 0; 1247dd498effSDenis Karpov 124813189e78SJarkko Lavinen return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT); 1249dd498effSDenis Karpov } 1250dd498effSDenis Karpov 125113189e78SJarkko Lavinen /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 125270a3341aSDenis Karpov static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1253dd498effSDenis Karpov { 125413189e78SJarkko Lavinen int err, new_state; 1255dd498effSDenis Karpov 1256dd498effSDenis Karpov if (!mmc_try_claim_host(host->mmc)) 1257dd498effSDenis Karpov return 0; 1258dd498effSDenis Karpov 1259dd498effSDenis Karpov clk_enable(host->fclk); 126070a3341aSDenis Karpov omap_hsmmc_context_restore(host); 126113189e78SJarkko Lavinen if (mmc_card_can_sleep(host->mmc)) { 126213189e78SJarkko Lavinen err = mmc_card_sleep(host->mmc); 126313189e78SJarkko Lavinen if (err < 0) { 126413189e78SJarkko Lavinen clk_disable(host->fclk); 126513189e78SJarkko Lavinen mmc_release_host(host->mmc); 126613189e78SJarkko Lavinen return err; 126713189e78SJarkko Lavinen } 126813189e78SJarkko Lavinen new_state = CARDSLEEP; 126970a3341aSDenis Karpov } else { 127013189e78SJarkko Lavinen new_state = REGSLEEP; 127170a3341aSDenis Karpov } 127213189e78SJarkko Lavinen if (mmc_slot(host).set_sleep) 127313189e78SJarkko Lavinen mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 127413189e78SJarkko Lavinen new_state == CARDSLEEP); 127513189e78SJarkko Lavinen /* FIXME: turn off bus power and perhaps interrupts too */ 127613189e78SJarkko Lavinen clk_disable(host->fclk); 127713189e78SJarkko Lavinen host->dpm_state = new_state; 127813189e78SJarkko Lavinen 127913189e78SJarkko Lavinen mmc_release_host(host->mmc); 128013189e78SJarkko Lavinen 128113189e78SJarkko Lavinen dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 128213189e78SJarkko Lavinen host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1283dd498effSDenis Karpov 1284dd498effSDenis Karpov if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1285dd498effSDenis Karpov mmc_slot(host).card_detect || 1286dd498effSDenis Karpov (mmc_slot(host).get_cover_state && 128713189e78SJarkko Lavinen mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 128813189e78SJarkko Lavinen return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT); 128913189e78SJarkko Lavinen 129013189e78SJarkko Lavinen return 0; 1291623821f7SAdrian Hunter } 1292dd498effSDenis Karpov 129313189e78SJarkko Lavinen /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 129470a3341aSDenis Karpov static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 129513189e78SJarkko Lavinen { 129613189e78SJarkko Lavinen if (!mmc_try_claim_host(host->mmc)) 129713189e78SJarkko Lavinen return 0; 1298dd498effSDenis Karpov 129913189e78SJarkko Lavinen if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 130013189e78SJarkko Lavinen mmc_slot(host).card_detect || 130113189e78SJarkko Lavinen (mmc_slot(host).get_cover_state && 130213189e78SJarkko Lavinen mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 130313189e78SJarkko Lavinen mmc_release_host(host->mmc); 130413189e78SJarkko Lavinen return 0; 130513189e78SJarkko Lavinen } 1306dd498effSDenis Karpov 130713189e78SJarkko Lavinen mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 130813189e78SJarkko Lavinen host->vdd = 0; 130913189e78SJarkko Lavinen host->power_mode = MMC_POWER_OFF; 131013189e78SJarkko Lavinen 131113189e78SJarkko Lavinen dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 131213189e78SJarkko Lavinen host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 131313189e78SJarkko Lavinen 131413189e78SJarkko Lavinen host->dpm_state = OFF; 1315dd498effSDenis Karpov 1316dd498effSDenis Karpov mmc_release_host(host->mmc); 1317dd498effSDenis Karpov 1318dd498effSDenis Karpov return 0; 1319dd498effSDenis Karpov } 1320dd498effSDenis Karpov 1321dd498effSDenis Karpov /* Handler for [DISABLED -> ENABLED] transition */ 132270a3341aSDenis Karpov static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1323dd498effSDenis Karpov { 1324dd498effSDenis Karpov int err; 1325dd498effSDenis Karpov 1326dd498effSDenis Karpov err = clk_enable(host->fclk); 1327dd498effSDenis Karpov if (err < 0) 1328dd498effSDenis Karpov return err; 1329dd498effSDenis Karpov 133070a3341aSDenis Karpov omap_hsmmc_context_restore(host); 1331dd498effSDenis Karpov host->dpm_state = ENABLED; 1332dd498effSDenis Karpov 1333dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1334dd498effSDenis Karpov 1335dd498effSDenis Karpov return 0; 1336dd498effSDenis Karpov } 1337dd498effSDenis Karpov 133813189e78SJarkko Lavinen /* Handler for [SLEEP -> ENABLED] transition */ 133970a3341aSDenis Karpov static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 134013189e78SJarkko Lavinen { 134113189e78SJarkko Lavinen if (!mmc_try_claim_host(host->mmc)) 134213189e78SJarkko Lavinen return 0; 134313189e78SJarkko Lavinen 134413189e78SJarkko Lavinen clk_enable(host->fclk); 134570a3341aSDenis Karpov omap_hsmmc_context_restore(host); 134613189e78SJarkko Lavinen if (mmc_slot(host).set_sleep) 134713189e78SJarkko Lavinen mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 134813189e78SJarkko Lavinen host->vdd, host->dpm_state == CARDSLEEP); 134913189e78SJarkko Lavinen if (mmc_card_can_sleep(host->mmc)) 135013189e78SJarkko Lavinen mmc_card_awake(host->mmc); 135113189e78SJarkko Lavinen 135213189e78SJarkko Lavinen dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 135313189e78SJarkko Lavinen host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 135413189e78SJarkko Lavinen 135513189e78SJarkko Lavinen host->dpm_state = ENABLED; 135613189e78SJarkko Lavinen 135713189e78SJarkko Lavinen mmc_release_host(host->mmc); 135813189e78SJarkko Lavinen 135913189e78SJarkko Lavinen return 0; 136013189e78SJarkko Lavinen } 136113189e78SJarkko Lavinen 1362dd498effSDenis Karpov /* Handler for [OFF -> ENABLED] transition */ 136370a3341aSDenis Karpov static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1364dd498effSDenis Karpov { 1365dd498effSDenis Karpov clk_enable(host->fclk); 1366dd498effSDenis Karpov 136770a3341aSDenis Karpov omap_hsmmc_context_restore(host); 136870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1369dd498effSDenis Karpov mmc_power_restore_host(host->mmc); 1370dd498effSDenis Karpov 1371dd498effSDenis Karpov host->dpm_state = ENABLED; 1372dd498effSDenis Karpov 1373dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1374dd498effSDenis Karpov 1375dd498effSDenis Karpov return 0; 1376dd498effSDenis Karpov } 1377dd498effSDenis Karpov 1378dd498effSDenis Karpov /* 1379dd498effSDenis Karpov * Bring MMC host to ENABLED from any other PM state. 1380dd498effSDenis Karpov */ 138170a3341aSDenis Karpov static int omap_hsmmc_enable(struct mmc_host *mmc) 1382dd498effSDenis Karpov { 138370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1384dd498effSDenis Karpov 1385dd498effSDenis Karpov switch (host->dpm_state) { 1386dd498effSDenis Karpov case DISABLED: 138770a3341aSDenis Karpov return omap_hsmmc_disabled_to_enabled(host); 138813189e78SJarkko Lavinen case CARDSLEEP: 1389623821f7SAdrian Hunter case REGSLEEP: 139070a3341aSDenis Karpov return omap_hsmmc_sleep_to_enabled(host); 1391dd498effSDenis Karpov case OFF: 139270a3341aSDenis Karpov return omap_hsmmc_off_to_enabled(host); 1393dd498effSDenis Karpov default: 1394dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1395dd498effSDenis Karpov return -EINVAL; 1396dd498effSDenis Karpov } 1397dd498effSDenis Karpov } 1398dd498effSDenis Karpov 1399dd498effSDenis Karpov /* 1400dd498effSDenis Karpov * Bring MMC host in PM state (one level deeper). 1401dd498effSDenis Karpov */ 140270a3341aSDenis Karpov static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1403dd498effSDenis Karpov { 140470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1405dd498effSDenis Karpov 1406dd498effSDenis Karpov switch (host->dpm_state) { 1407dd498effSDenis Karpov case ENABLED: { 1408dd498effSDenis Karpov int delay; 1409dd498effSDenis Karpov 141070a3341aSDenis Karpov delay = omap_hsmmc_enabled_to_disabled(host); 1411dd498effSDenis Karpov if (lazy || delay < 0) 1412dd498effSDenis Karpov return delay; 1413dd498effSDenis Karpov return 0; 1414dd498effSDenis Karpov } 1415dd498effSDenis Karpov case DISABLED: 141670a3341aSDenis Karpov return omap_hsmmc_disabled_to_sleep(host); 141713189e78SJarkko Lavinen case CARDSLEEP: 141813189e78SJarkko Lavinen case REGSLEEP: 141970a3341aSDenis Karpov return omap_hsmmc_sleep_to_off(host); 1420dd498effSDenis Karpov default: 1421dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1422dd498effSDenis Karpov return -EINVAL; 1423dd498effSDenis Karpov } 1424dd498effSDenis Karpov } 1425dd498effSDenis Karpov 142670a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1427dd498effSDenis Karpov { 142870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1429dd498effSDenis Karpov int err; 1430dd498effSDenis Karpov 1431dd498effSDenis Karpov err = clk_enable(host->fclk); 1432dd498effSDenis Karpov if (err) 1433dd498effSDenis Karpov return err; 1434dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 143570a3341aSDenis Karpov omap_hsmmc_context_restore(host); 1436dd498effSDenis Karpov return 0; 1437dd498effSDenis Karpov } 1438dd498effSDenis Karpov 143970a3341aSDenis Karpov static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1440dd498effSDenis Karpov { 144170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1442dd498effSDenis Karpov 144370a3341aSDenis Karpov omap_hsmmc_context_save(host); 1444dd498effSDenis Karpov clk_disable(host->fclk); 1445dd498effSDenis Karpov dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1446dd498effSDenis Karpov return 0; 1447dd498effSDenis Karpov } 1448dd498effSDenis Karpov 144970a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 145070a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 145170a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 145270a3341aSDenis Karpov .request = omap_hsmmc_request, 145370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1454dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1455dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 1456dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1457dd498effSDenis Karpov }; 1458dd498effSDenis Karpov 145970a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ps_ops = { 146070a3341aSDenis Karpov .enable = omap_hsmmc_enable, 146170a3341aSDenis Karpov .disable = omap_hsmmc_disable, 146270a3341aSDenis Karpov .request = omap_hsmmc_request, 146370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1464a45c6cb8SMadhusudhan Chikkature .get_cd = omap_hsmmc_get_cd, 1465a45c6cb8SMadhusudhan Chikkature .get_ro = omap_hsmmc_get_ro, 1466a45c6cb8SMadhusudhan Chikkature /* NYET -- enable_sdio_irq */ 1467a45c6cb8SMadhusudhan Chikkature }; 1468a45c6cb8SMadhusudhan Chikkature 1469d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1470d900f712SDenis Karpov 147170a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1472d900f712SDenis Karpov { 1473d900f712SDenis Karpov struct mmc_host *mmc = s->private; 147470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 147511dd62a7SDenis Karpov int context_loss = 0; 147611dd62a7SDenis Karpov 147770a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 147870a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1479d900f712SDenis Karpov 14805e2ea617SAdrian Hunter seq_printf(s, "mmc%d:\n" 14815e2ea617SAdrian Hunter " enabled:\t%d\n" 1482dd498effSDenis Karpov " dpm_state:\t%d\n" 14835e2ea617SAdrian Hunter " nesting_cnt:\t%d\n" 148411dd62a7SDenis Karpov " ctx_loss:\t%d:%d\n" 14855e2ea617SAdrian Hunter "\nregs:\n", 1486dd498effSDenis Karpov mmc->index, mmc->enabled ? 1 : 0, 1487dd498effSDenis Karpov host->dpm_state, mmc->nesting_cnt, 148811dd62a7SDenis Karpov host->context_loss, context_loss); 14895e2ea617SAdrian Hunter 149013189e78SJarkko Lavinen if (host->suspended || host->dpm_state == OFF) { 1491dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1492dd498effSDenis Karpov return 0; 1493dd498effSDenis Karpov } 1494dd498effSDenis Karpov 14955e2ea617SAdrian Hunter if (clk_enable(host->fclk) != 0) { 14965e2ea617SAdrian Hunter seq_printf(s, "can't read the regs\n"); 1497dd498effSDenis Karpov return 0; 14985e2ea617SAdrian Hunter } 1499d900f712SDenis Karpov 1500d900f712SDenis Karpov seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1501d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1502d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1503d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1504d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1505d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1506d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1507d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1508d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1509d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1510d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1511d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1512d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1513d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 15145e2ea617SAdrian Hunter 15155e2ea617SAdrian Hunter clk_disable(host->fclk); 1516dd498effSDenis Karpov 1517d900f712SDenis Karpov return 0; 1518d900f712SDenis Karpov } 1519d900f712SDenis Karpov 152070a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1521d900f712SDenis Karpov { 152270a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1523d900f712SDenis Karpov } 1524d900f712SDenis Karpov 1525d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 152670a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1527d900f712SDenis Karpov .read = seq_read, 1528d900f712SDenis Karpov .llseek = seq_lseek, 1529d900f712SDenis Karpov .release = single_release, 1530d900f712SDenis Karpov }; 1531d900f712SDenis Karpov 153270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1533d900f712SDenis Karpov { 1534d900f712SDenis Karpov if (mmc->debugfs_root) 1535d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1536d900f712SDenis Karpov mmc, &mmc_regs_fops); 1537d900f712SDenis Karpov } 1538d900f712SDenis Karpov 1539d900f712SDenis Karpov #else 1540d900f712SDenis Karpov 154170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1542d900f712SDenis Karpov { 1543d900f712SDenis Karpov } 1544d900f712SDenis Karpov 1545d900f712SDenis Karpov #endif 1546d900f712SDenis Karpov 154770a3341aSDenis Karpov static int __init omap_hsmmc_probe(struct platform_device *pdev) 1548a45c6cb8SMadhusudhan Chikkature { 1549a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1550a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 155170a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1552a45c6cb8SMadhusudhan Chikkature struct resource *res; 1553a45c6cb8SMadhusudhan Chikkature int ret = 0, irq; 1554a45c6cb8SMadhusudhan Chikkature 1555a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1556a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1557a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1558a45c6cb8SMadhusudhan Chikkature } 1559a45c6cb8SMadhusudhan Chikkature 1560a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1561a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1562a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1563a45c6cb8SMadhusudhan Chikkature } 1564a45c6cb8SMadhusudhan Chikkature 1565a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1566a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1567a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1568a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1569a45c6cb8SMadhusudhan Chikkature 1570a45c6cb8SMadhusudhan Chikkature res = request_mem_region(res->start, res->end - res->start + 1, 1571a45c6cb8SMadhusudhan Chikkature pdev->name); 1572a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1573a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1574a45c6cb8SMadhusudhan Chikkature 157570a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1576a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1577a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1578a45c6cb8SMadhusudhan Chikkature goto err; 1579a45c6cb8SMadhusudhan Chikkature } 1580a45c6cb8SMadhusudhan Chikkature 1581a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1582a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1583a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1584a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1585a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1586a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 1587a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1588a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1589a45c6cb8SMadhusudhan Chikkature host->id = pdev->id; 1590a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1591a45c6cb8SMadhusudhan Chikkature host->mapbase = res->start; 1592a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 1593a3621465SAdrian Hunter host->power_mode = -1; 1594a45c6cb8SMadhusudhan Chikkature 1595a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 159670a3341aSDenis Karpov INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 1597a45c6cb8SMadhusudhan Chikkature 1598191d1f1dSDenis Karpov if (mmc_slot(host).power_saving) 159970a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ps_ops; 1600dd498effSDenis Karpov else 160170a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1602dd498effSDenis Karpov 1603a45c6cb8SMadhusudhan Chikkature mmc->f_min = 400000; 1604a45c6cb8SMadhusudhan Chikkature mmc->f_max = 52000000; 1605a45c6cb8SMadhusudhan Chikkature 1606a45c6cb8SMadhusudhan Chikkature sema_init(&host->sem, 1); 16074dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1608a45c6cb8SMadhusudhan Chikkature 16096f7607ccSRussell King host->iclk = clk_get(&pdev->dev, "ick"); 1610a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->iclk)) { 1611a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->iclk); 1612a45c6cb8SMadhusudhan Chikkature host->iclk = NULL; 1613a45c6cb8SMadhusudhan Chikkature goto err1; 1614a45c6cb8SMadhusudhan Chikkature } 16156f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1616a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1617a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1618a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1619a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1620a45c6cb8SMadhusudhan Chikkature goto err1; 1621a45c6cb8SMadhusudhan Chikkature } 1622a45c6cb8SMadhusudhan Chikkature 162370a3341aSDenis Karpov omap_hsmmc_context_save(host); 162411dd62a7SDenis Karpov 16255e2ea617SAdrian Hunter mmc->caps |= MMC_CAP_DISABLE; 1626dd498effSDenis Karpov mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 1627dd498effSDenis Karpov /* we start off in DISABLED state */ 1628dd498effSDenis Karpov host->dpm_state = DISABLED; 1629dd498effSDenis Karpov 16305e2ea617SAdrian Hunter if (mmc_host_enable(host->mmc) != 0) { 1631a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1632a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1633a45c6cb8SMadhusudhan Chikkature goto err1; 1634a45c6cb8SMadhusudhan Chikkature } 1635a45c6cb8SMadhusudhan Chikkature 1636a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->iclk) != 0) { 16375e2ea617SAdrian Hunter mmc_host_disable(host->mmc); 1638a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1639a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1640a45c6cb8SMadhusudhan Chikkature goto err1; 1641a45c6cb8SMadhusudhan Chikkature } 1642a45c6cb8SMadhusudhan Chikkature 1643a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1644a45c6cb8SMadhusudhan Chikkature /* 1645a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1646a45c6cb8SMadhusudhan Chikkature */ 1647a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->dbclk)) 1648a45c6cb8SMadhusudhan Chikkature dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); 1649a45c6cb8SMadhusudhan Chikkature else 1650a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1651a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 1652a45c6cb8SMadhusudhan Chikkature " clk failed\n"); 1653a45c6cb8SMadhusudhan Chikkature else 1654a45c6cb8SMadhusudhan Chikkature host->dbclk_enabled = 1; 1655a45c6cb8SMadhusudhan Chikkature 16560ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 16570ccd76d4SJuha Yrjola * as we want. */ 16580ccd76d4SJuha Yrjola mmc->max_phys_segs = 1024; 16590ccd76d4SJuha Yrjola mmc->max_hw_segs = 1024; 16600ccd76d4SJuha Yrjola 1661a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1662a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1663a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1664a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1665a45c6cb8SMadhusudhan Chikkature 166613189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 166713189e78SJarkko Lavinen MMC_CAP_WAIT_WHILE_BUSY; 1668a45c6cb8SMadhusudhan Chikkature 1669191d1f1dSDenis Karpov if (mmc_slot(host).wires >= 8) 167073153010SJarkko Lavinen mmc->caps |= MMC_CAP_8_BIT_DATA; 1671191d1f1dSDenis Karpov else if (mmc_slot(host).wires >= 4) 1672a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1673a45c6cb8SMadhusudhan Chikkature 1674191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 167523d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 167623d99bb9SAdrian Hunter 167770a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1678a45c6cb8SMadhusudhan Chikkature 1679f3e2f1ddSGrazvydas Ignotas /* Select DMA lines */ 1680f3e2f1ddSGrazvydas Ignotas switch (host->id) { 1681f3e2f1ddSGrazvydas Ignotas case OMAP_MMC1_DEVID: 1682f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 1683f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 1684f3e2f1ddSGrazvydas Ignotas break; 1685f3e2f1ddSGrazvydas Ignotas case OMAP_MMC2_DEVID: 1686f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 1687f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 1688f3e2f1ddSGrazvydas Ignotas break; 1689f3e2f1ddSGrazvydas Ignotas case OMAP_MMC3_DEVID: 1690f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 1691f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 1692f3e2f1ddSGrazvydas Ignotas break; 1693f3e2f1ddSGrazvydas Ignotas default: 1694f3e2f1ddSGrazvydas Ignotas dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 1695f3e2f1ddSGrazvydas Ignotas goto err_irq; 1696a45c6cb8SMadhusudhan Chikkature } 1697a45c6cb8SMadhusudhan Chikkature 1698a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 169970a3341aSDenis Karpov ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 1700a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1701a45c6cb8SMadhusudhan Chikkature if (ret) { 1702a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1703a45c6cb8SMadhusudhan Chikkature goto err_irq; 1704a45c6cb8SMadhusudhan Chikkature } 1705a45c6cb8SMadhusudhan Chikkature 1706b583f26dSDavid Brownell /* initialize power supplies, gpios, etc */ 1707a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1708a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 170970a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 171070a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1711a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1712a45c6cb8SMadhusudhan Chikkature } 1713a45c6cb8SMadhusudhan Chikkature } 1714b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1715a45c6cb8SMadhusudhan Chikkature 1716a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1717e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 1718a45c6cb8SMadhusudhan Chikkature ret = request_irq(mmc_slot(host).card_detect_irq, 171970a3341aSDenis Karpov omap_hsmmc_cd_handler, 1720a45c6cb8SMadhusudhan Chikkature IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 1721a45c6cb8SMadhusudhan Chikkature | IRQF_DISABLED, 1722a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1723a45c6cb8SMadhusudhan Chikkature if (ret) { 1724a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1725a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1726a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1727a45c6cb8SMadhusudhan Chikkature } 1728a45c6cb8SMadhusudhan Chikkature } 1729a45c6cb8SMadhusudhan Chikkature 1730a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 1731a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 1732a45c6cb8SMadhusudhan Chikkature 17335e2ea617SAdrian Hunter mmc_host_lazy_disable(host->mmc); 17345e2ea617SAdrian Hunter 1735a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1736a45c6cb8SMadhusudhan Chikkature 1737191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1738a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1739a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1740a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1741a45c6cb8SMadhusudhan Chikkature } 1742191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1743a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 1744a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 1745a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1746a45c6cb8SMadhusudhan Chikkature goto err_cover_switch; 1747a45c6cb8SMadhusudhan Chikkature } 1748a45c6cb8SMadhusudhan Chikkature 174970a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 1750d900f712SDenis Karpov 1751a45c6cb8SMadhusudhan Chikkature return 0; 1752a45c6cb8SMadhusudhan Chikkature 1753a45c6cb8SMadhusudhan Chikkature err_cover_switch: 1754a45c6cb8SMadhusudhan Chikkature device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1755a45c6cb8SMadhusudhan Chikkature err_slot_name: 1756a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 1757a45c6cb8SMadhusudhan Chikkature err_irq_cd: 1758a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1759a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 1760a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1761a45c6cb8SMadhusudhan Chikkature err_irq: 17625e2ea617SAdrian Hunter mmc_host_disable(host->mmc); 1763a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1764a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1765a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1766a45c6cb8SMadhusudhan Chikkature if (host->dbclk_enabled) { 1767a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1768a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1769a45c6cb8SMadhusudhan Chikkature } 1770a45c6cb8SMadhusudhan Chikkature 1771a45c6cb8SMadhusudhan Chikkature err1: 1772a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1773a45c6cb8SMadhusudhan Chikkature err: 1774a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); 1775a45c6cb8SMadhusudhan Chikkature release_mem_region(res->start, res->end - res->start + 1); 1776a45c6cb8SMadhusudhan Chikkature if (host) 1777a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 1778a45c6cb8SMadhusudhan Chikkature return ret; 1779a45c6cb8SMadhusudhan Chikkature } 1780a45c6cb8SMadhusudhan Chikkature 178170a3341aSDenis Karpov static int omap_hsmmc_remove(struct platform_device *pdev) 1782a45c6cb8SMadhusudhan Chikkature { 178370a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 1784a45c6cb8SMadhusudhan Chikkature struct resource *res; 1785a45c6cb8SMadhusudhan Chikkature 1786a45c6cb8SMadhusudhan Chikkature if (host) { 17875e2ea617SAdrian Hunter mmc_host_enable(host->mmc); 1788a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 1789a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 1790a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 1791a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1792a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 1793a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1794a45c6cb8SMadhusudhan Chikkature flush_scheduled_work(); 1795a45c6cb8SMadhusudhan Chikkature 17965e2ea617SAdrian Hunter mmc_host_disable(host->mmc); 1797a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1798a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1799a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1800a45c6cb8SMadhusudhan Chikkature if (host->dbclk_enabled) { 1801a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1802a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1803a45c6cb8SMadhusudhan Chikkature } 1804a45c6cb8SMadhusudhan Chikkature 1805a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 1806a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1807a45c6cb8SMadhusudhan Chikkature } 1808a45c6cb8SMadhusudhan Chikkature 1809a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1810a45c6cb8SMadhusudhan Chikkature if (res) 1811a45c6cb8SMadhusudhan Chikkature release_mem_region(res->start, res->end - res->start + 1); 1812a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 1813a45c6cb8SMadhusudhan Chikkature 1814a45c6cb8SMadhusudhan Chikkature return 0; 1815a45c6cb8SMadhusudhan Chikkature } 1816a45c6cb8SMadhusudhan Chikkature 1817a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 181870a3341aSDenis Karpov static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) 1819a45c6cb8SMadhusudhan Chikkature { 1820a45c6cb8SMadhusudhan Chikkature int ret = 0; 182170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 1822a45c6cb8SMadhusudhan Chikkature 1823a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 1824a45c6cb8SMadhusudhan Chikkature return 0; 1825a45c6cb8SMadhusudhan Chikkature 1826a45c6cb8SMadhusudhan Chikkature if (host) { 1827a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 1828a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 1829a45c6cb8SMadhusudhan Chikkature ret = host->pdata->suspend(&pdev->dev, 1830a45c6cb8SMadhusudhan Chikkature host->slot_id); 1831a6b2240dSAdrian Hunter if (ret) { 1832a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1833a45c6cb8SMadhusudhan Chikkature "Unable to handle MMC board" 1834a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 1835a6b2240dSAdrian Hunter host->suspended = 0; 1836a6b2240dSAdrian Hunter return ret; 1837a45c6cb8SMadhusudhan Chikkature } 1838a6b2240dSAdrian Hunter } 1839a6b2240dSAdrian Hunter cancel_work_sync(&host->mmc_carddetect_work); 1840a6b2240dSAdrian Hunter mmc_host_enable(host->mmc); 1841a6b2240dSAdrian Hunter ret = mmc_suspend_host(host->mmc, state); 1842a6b2240dSAdrian Hunter if (ret == 0) { 1843a6b2240dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 1844a6b2240dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 1845a6b2240dSAdrian Hunter 1846a45c6cb8SMadhusudhan Chikkature 1847a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 18480683af48SJarkko Lavinen OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 18495e2ea617SAdrian Hunter mmc_host_disable(host->mmc); 1850a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1851a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1852a6b2240dSAdrian Hunter } else { 1853a6b2240dSAdrian Hunter host->suspended = 0; 1854a6b2240dSAdrian Hunter if (host->pdata->resume) { 1855a6b2240dSAdrian Hunter ret = host->pdata->resume(&pdev->dev, 1856a6b2240dSAdrian Hunter host->slot_id); 1857a6b2240dSAdrian Hunter if (ret) 1858a6b2240dSAdrian Hunter dev_dbg(mmc_dev(host->mmc), 1859a6b2240dSAdrian Hunter "Unmask interrupt failed\n"); 1860a6b2240dSAdrian Hunter } 18615e2ea617SAdrian Hunter mmc_host_disable(host->mmc); 1862a6b2240dSAdrian Hunter } 1863a45c6cb8SMadhusudhan Chikkature 1864a45c6cb8SMadhusudhan Chikkature } 1865a45c6cb8SMadhusudhan Chikkature return ret; 1866a45c6cb8SMadhusudhan Chikkature } 1867a45c6cb8SMadhusudhan Chikkature 1868a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 186970a3341aSDenis Karpov static int omap_hsmmc_resume(struct platform_device *pdev) 1870a45c6cb8SMadhusudhan Chikkature { 1871a45c6cb8SMadhusudhan Chikkature int ret = 0; 187270a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 1873a45c6cb8SMadhusudhan Chikkature 1874a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 1875a45c6cb8SMadhusudhan Chikkature return 0; 1876a45c6cb8SMadhusudhan Chikkature 1877a45c6cb8SMadhusudhan Chikkature if (host) { 1878a45c6cb8SMadhusudhan Chikkature ret = clk_enable(host->iclk); 187911dd62a7SDenis Karpov if (ret) 1880a45c6cb8SMadhusudhan Chikkature goto clk_en_err; 1881a45c6cb8SMadhusudhan Chikkature 1882a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1883a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1884a45c6cb8SMadhusudhan Chikkature "Enabling debounce clk failed\n"); 1885a45c6cb8SMadhusudhan Chikkature 188611dd62a7SDenis Karpov if (mmc_host_enable(host->mmc) != 0) { 188711dd62a7SDenis Karpov clk_disable(host->iclk); 188811dd62a7SDenis Karpov goto clk_en_err; 188911dd62a7SDenis Karpov } 189011dd62a7SDenis Karpov 189170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 18921b331e69SKim Kyuwon 1893a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 1894a45c6cb8SMadhusudhan Chikkature ret = host->pdata->resume(&pdev->dev, host->slot_id); 1895a45c6cb8SMadhusudhan Chikkature if (ret) 1896a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1897a45c6cb8SMadhusudhan Chikkature "Unmask interrupt failed\n"); 1898a45c6cb8SMadhusudhan Chikkature } 1899a45c6cb8SMadhusudhan Chikkature 1900a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 1901a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 1902a45c6cb8SMadhusudhan Chikkature if (ret == 0) 1903a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 190470a3341aSDenis Karpov 19055e2ea617SAdrian Hunter mmc_host_lazy_disable(host->mmc); 1906a45c6cb8SMadhusudhan Chikkature } 1907a45c6cb8SMadhusudhan Chikkature 1908a45c6cb8SMadhusudhan Chikkature return ret; 1909a45c6cb8SMadhusudhan Chikkature 1910a45c6cb8SMadhusudhan Chikkature clk_en_err: 1911a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1912a45c6cb8SMadhusudhan Chikkature "Failed to enable MMC clocks during resume\n"); 1913a45c6cb8SMadhusudhan Chikkature return ret; 1914a45c6cb8SMadhusudhan Chikkature } 1915a45c6cb8SMadhusudhan Chikkature 1916a45c6cb8SMadhusudhan Chikkature #else 191770a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 191870a3341aSDenis Karpov #define omap_hsmmc_resume NULL 1919a45c6cb8SMadhusudhan Chikkature #endif 1920a45c6cb8SMadhusudhan Chikkature 192170a3341aSDenis Karpov static struct platform_driver omap_hsmmc_driver = { 192270a3341aSDenis Karpov .remove = omap_hsmmc_remove, 192370a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 192470a3341aSDenis Karpov .resume = omap_hsmmc_resume, 1925a45c6cb8SMadhusudhan Chikkature .driver = { 1926a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 1927a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 1928a45c6cb8SMadhusudhan Chikkature }, 1929a45c6cb8SMadhusudhan Chikkature }; 1930a45c6cb8SMadhusudhan Chikkature 193170a3341aSDenis Karpov static int __init omap_hsmmc_init(void) 1932a45c6cb8SMadhusudhan Chikkature { 1933a45c6cb8SMadhusudhan Chikkature /* Register the MMC driver */ 193470a3341aSDenis Karpov return platform_driver_register(&omap_hsmmc_driver); 1935a45c6cb8SMadhusudhan Chikkature } 1936a45c6cb8SMadhusudhan Chikkature 193770a3341aSDenis Karpov static void __exit omap_hsmmc_cleanup(void) 1938a45c6cb8SMadhusudhan Chikkature { 1939a45c6cb8SMadhusudhan Chikkature /* Unregister MMC driver */ 194070a3341aSDenis Karpov platform_driver_unregister(&omap_hsmmc_driver); 1941a45c6cb8SMadhusudhan Chikkature } 1942a45c6cb8SMadhusudhan Chikkature 194370a3341aSDenis Karpov module_init(omap_hsmmc_init); 194470a3341aSDenis Karpov module_exit(omap_hsmmc_cleanup); 1945a45c6cb8SMadhusudhan Chikkature 1946a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 1947a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 1948a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 1949a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 1950