1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3841afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 455b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 47a45c6cb8SMadhusudhan Chikkature 48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 66a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 68a45c6cb8SMadhusudhan Chikkature 69a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 70a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 71cd587096SHebbar, Gururaja #define HSS (1 << 21) 72a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 73a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 74eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 751b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 77a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 79a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 80a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 81a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 82a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 83a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 84ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 90a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 92a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 93a7e96879SVenkatraman S #define DMAE 0x1 94a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 97cd587096SHebbar, Gururaja #define HSPE (1 << 2) 985a52b08bSBalaji T K #define IWE (1 << 24) 9903b5d924SBalaji T K #define DDR (1 << 19) 1005a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1015a52b08bSBalaji T K #define CTPL (1 << 11) 10273153010SJarkko Lavinen #define DW8 (1 << 5) 103a45c6cb8SMadhusudhan Chikkature #define OD 0x1 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 110a45c6cb8SMadhusudhan Chikkature 111f945901fSAndreas Fenkart /* PSTATE */ 112f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 113f945901fSAndreas Fenkart 114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 115a7e96879SVenkatraman S #define CC_EN (1 << 0) 116a7e96879SVenkatraman S #define TC_EN (1 << 1) 117a7e96879SVenkatraman S #define BWR_EN (1 << 4) 118a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1192cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 120a7e96879SVenkatraman S #define ERR_EN (1 << 15) 121a7e96879SVenkatraman S #define CTO_EN (1 << 16) 122a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 123a7e96879SVenkatraman S #define CEB_EN (1 << 18) 124a7e96879SVenkatraman S #define CIE_EN (1 << 19) 125a7e96879SVenkatraman S #define DTO_EN (1 << 20) 126a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 127a7e96879SVenkatraman S #define DEB_EN (1 << 22) 128a2e77152SBalaji T K #define ACE_EN (1 << 24) 129a7e96879SVenkatraman S #define CERR_EN (1 << 28) 130a7e96879SVenkatraman S #define BADA_EN (1 << 29) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 135a7e96879SVenkatraman S 136a2e77152SBalaji T K #define CNI (1 << 7) 137a2e77152SBalaji T K #define ACIE (1 << 4) 138a2e77152SBalaji T K #define ACEB (1 << 3) 139a2e77152SBalaji T K #define ACCE (1 << 2) 140a2e77152SBalaji T K #define ACTO (1 << 1) 141a2e77152SBalaji T K #define ACNE (1 << 0) 142a2e77152SBalaji T K 143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1451e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1480005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 149a45c6cb8SMadhusudhan Chikkature 150e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 151e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 152e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 153e99448ffSBalaji T K 154a45c6cb8SMadhusudhan Chikkature /* 155a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 156a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 157a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 158a45c6cb8SMadhusudhan Chikkature */ 159326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 160a45c6cb8SMadhusudhan Chikkature 161a45c6cb8SMadhusudhan Chikkature /* 162a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 163a45c6cb8SMadhusudhan Chikkature */ 164a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 165a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 166a45c6cb8SMadhusudhan Chikkature 167a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 168a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 169a45c6cb8SMadhusudhan Chikkature 1709782aff8SPer Forlin struct omap_hsmmc_next { 1719782aff8SPer Forlin unsigned int dma_len; 1729782aff8SPer Forlin s32 cookie; 1739782aff8SPer Forlin }; 1749782aff8SPer Forlin 17570a3341aSDenis Karpov struct omap_hsmmc_host { 176a45c6cb8SMadhusudhan Chikkature struct device *dev; 177a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 178a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 179a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 180a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 181a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 182a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 183e99448ffSBalaji T K struct regulator *pbias; 184bb2726b5STony Lindgren bool pbias_enabled; 185a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1863f77f702SKishon Vijay Abraham I int vqmmc_enabled; 187a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1884dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 189a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1900ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 191a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 192a3621465SAdrian Hunter unsigned char power_mode; 193a45c6cb8SMadhusudhan Chikkature int suspended; 1940a82e06eSTony Lindgren u32 con; 1950a82e06eSTony Lindgren u32 hctl; 1960a82e06eSTony Lindgren u32 sysctl; 1970a82e06eSTony Lindgren u32 capa; 198a45c6cb8SMadhusudhan Chikkature int irq; 1992cd3a2a5SAndreas Fenkart int wake_irq; 200a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 201c5c98927SRussell King struct dma_chan *tx_chan; 202c5c98927SRussell King struct dma_chan *rx_chan; 2034a694dc9SAdrian Hunter int response_busy; 20411dd62a7SDenis Karpov int context_loss; 205b62f6228SAdrian Hunter int protect_card; 206b62f6228SAdrian Hunter int reqs_blocked; 207b417577dSAdrian Hunter int req_in_progress; 2086e3076c2SBalaji T K unsigned long clk_rate; 209a2e77152SBalaji T K unsigned int flags; 2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2129782aff8SPer Forlin struct omap_hsmmc_next next_data; 21355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 214b5cd43f0SAndreas Fenkart 215b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 216b5cd43f0SAndreas Fenkart * 217b5cd43f0SAndreas Fenkart * possible return values: 218b5cd43f0SAndreas Fenkart * 0 - closed 219b5cd43f0SAndreas Fenkart * 1 - open 220b5cd43f0SAndreas Fenkart */ 22180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 222b5cd43f0SAndreas Fenkart 22380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 224a45c6cb8SMadhusudhan Chikkature }; 225a45c6cb8SMadhusudhan Chikkature 22659445b10SNishanth Menon struct omap_mmc_of_data { 22759445b10SNishanth Menon u32 reg_offset; 22859445b10SNishanth Menon u8 controller_flags; 22959445b10SNishanth Menon }; 23059445b10SNishanth Menon 231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232bf129e1cSBalaji T K 23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236db0fefc5SAdrian Hunter 23741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 241db0fefc5SAdrian Hunter { 2429ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243db0fefc5SAdrian Hunter 24441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 2471d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 2482a17f844SKishon Vijay Abraham I { 2492a17f844SKishon Vijay Abraham I int ret; 2503f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2511d17f30bSKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 2522a17f844SKishon Vijay Abraham I 25386d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2541d17f30bSKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 2552a17f844SKishon Vijay Abraham I if (ret) 2562a17f844SKishon Vijay Abraham I return ret; 2572a17f844SKishon Vijay Abraham I } 2582a17f844SKishon Vijay Abraham I 2592a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 26086d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 2612a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2622a17f844SKishon Vijay Abraham I if (ret) { 2632a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2642a17f844SKishon Vijay Abraham I goto err_vqmmc; 2652a17f844SKishon Vijay Abraham I } 2663f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2672a17f844SKishon Vijay Abraham I } 2682a17f844SKishon Vijay Abraham I 2692a17f844SKishon Vijay Abraham I return 0; 2702a17f844SKishon Vijay Abraham I 2712a17f844SKishon Vijay Abraham I err_vqmmc: 27286d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) 2732a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2742a17f844SKishon Vijay Abraham I 2752a17f844SKishon Vijay Abraham I return ret; 2762a17f844SKishon Vijay Abraham I } 2772a17f844SKishon Vijay Abraham I 2782a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2792a17f844SKishon Vijay Abraham I { 2802a17f844SKishon Vijay Abraham I int ret; 2812a17f844SKishon Vijay Abraham I int status; 2823f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2832a17f844SKishon Vijay Abraham I 28486d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 2852a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2862a17f844SKishon Vijay Abraham I if (ret) { 2872a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2882a17f844SKishon Vijay Abraham I return ret; 2892a17f844SKishon Vijay Abraham I } 2903f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2912a17f844SKishon Vijay Abraham I } 2922a17f844SKishon Vijay Abraham I 29386d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2942a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2952a17f844SKishon Vijay Abraham I if (ret) 2962a17f844SKishon Vijay Abraham I goto err_set_ocr; 2972a17f844SKishon Vijay Abraham I } 2982a17f844SKishon Vijay Abraham I 2992a17f844SKishon Vijay Abraham I return 0; 3002a17f844SKishon Vijay Abraham I 3012a17f844SKishon Vijay Abraham I err_set_ocr: 30286d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc)) { 3032a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3042a17f844SKishon Vijay Abraham I if (status) 3052a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3062a17f844SKishon Vijay Abraham I } 3072a17f844SKishon Vijay Abraham I 3082a17f844SKishon Vijay Abraham I return ret; 3092a17f844SKishon Vijay Abraham I } 3102a17f844SKishon Vijay Abraham I 311ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 312ec85c95eSKishon Vijay Abraham I int vdd) 313ec85c95eSKishon Vijay Abraham I { 314ec85c95eSKishon Vijay Abraham I int ret; 315ec85c95eSKishon Vijay Abraham I 31686d79da0SKishon Vijay Abraham I if (IS_ERR(host->pbias)) 317ec85c95eSKishon Vijay Abraham I return 0; 318ec85c95eSKishon Vijay Abraham I 319ec85c95eSKishon Vijay Abraham I if (power_on) { 320ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 321ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 322ec85c95eSKishon Vijay Abraham I VDD_1V8); 323ec85c95eSKishon Vijay Abraham I else 324ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 325ec85c95eSKishon Vijay Abraham I VDD_3V0); 326ec85c95eSKishon Vijay Abraham I if (ret < 0) { 327ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 328ec85c95eSKishon Vijay Abraham I return ret; 329ec85c95eSKishon Vijay Abraham I } 330ec85c95eSKishon Vijay Abraham I 331bb2726b5STony Lindgren if (host->pbias_enabled == 0) { 332ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 333ec85c95eSKishon Vijay Abraham I if (ret) { 334ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 335ec85c95eSKishon Vijay Abraham I return ret; 336ec85c95eSKishon Vijay Abraham I } 337bb2726b5STony Lindgren host->pbias_enabled = 1; 338ec85c95eSKishon Vijay Abraham I } 339ec85c95eSKishon Vijay Abraham I } else { 340bb2726b5STony Lindgren if (host->pbias_enabled == 1) { 341ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 342ec85c95eSKishon Vijay Abraham I if (ret) { 343ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 344ec85c95eSKishon Vijay Abraham I return ret; 345ec85c95eSKishon Vijay Abraham I } 346bb2726b5STony Lindgren host->pbias_enabled = 0; 347ec85c95eSKishon Vijay Abraham I } 348ec85c95eSKishon Vijay Abraham I } 349ec85c95eSKishon Vijay Abraham I 350ec85c95eSKishon Vijay Abraham I return 0; 351ec85c95eSKishon Vijay Abraham I } 352ec85c95eSKishon Vijay Abraham I 3531ca4d359SAndreas Fenkart static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, 3541ca4d359SAndreas Fenkart int vdd) 355db0fefc5SAdrian Hunter { 356aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 357db0fefc5SAdrian Hunter int ret = 0; 358db0fefc5SAdrian Hunter 359db0fefc5SAdrian Hunter /* 360db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 361db0fefc5SAdrian Hunter * voltage always-on regulator. 362db0fefc5SAdrian Hunter */ 36386d79da0SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) 364db0fefc5SAdrian Hunter return 0; 365db0fefc5SAdrian Hunter 366ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 367ec85c95eSKishon Vijay Abraham I if (ret) 368229f3292SKishon Vijay Abraham I return ret; 369e99448ffSBalaji T K 370db0fefc5SAdrian Hunter /* 371db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 372db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 373db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 374db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 375db0fefc5SAdrian Hunter * 376db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 377db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 378db0fefc5SAdrian Hunter * 379db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 380db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 381db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 382db0fefc5SAdrian Hunter */ 383db0fefc5SAdrian Hunter if (power_on) { 3841d17f30bSKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc); 385229f3292SKishon Vijay Abraham I if (ret) 386229f3292SKishon Vijay Abraham I return ret; 38797fe7e5aSKishon Vijay Abraham I 38897fe7e5aSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 38997fe7e5aSKishon Vijay Abraham I if (ret) 39097fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 391db0fefc5SAdrian Hunter } else { 3922a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 393229f3292SKishon Vijay Abraham I if (ret) 394229f3292SKishon Vijay Abraham I return ret; 39599fc5131SLinus Walleij } 396db0fefc5SAdrian Hunter 397229f3292SKishon Vijay Abraham I return 0; 398229f3292SKishon Vijay Abraham I 399229f3292SKishon Vijay Abraham I err_set_voltage: 4002a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 401229f3292SKishon Vijay Abraham I 402db0fefc5SAdrian Hunter return ret; 403db0fefc5SAdrian Hunter } 404db0fefc5SAdrian Hunter 405c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 406c8518efaSKishon Vijay Abraham I { 407c8518efaSKishon Vijay Abraham I int ret; 408c8518efaSKishon Vijay Abraham I 40986d79da0SKishon Vijay Abraham I if (IS_ERR(reg)) 410c8518efaSKishon Vijay Abraham I return 0; 411c8518efaSKishon Vijay Abraham I 412c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 413c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 414c8518efaSKishon Vijay Abraham I if (ret) 415c8518efaSKishon Vijay Abraham I return ret; 416c8518efaSKishon Vijay Abraham I 417c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 418c8518efaSKishon Vijay Abraham I if (ret) 419c8518efaSKishon Vijay Abraham I return ret; 420c8518efaSKishon Vijay Abraham I } 421c8518efaSKishon Vijay Abraham I 422c8518efaSKishon Vijay Abraham I return 0; 423c8518efaSKishon Vijay Abraham I } 424c8518efaSKishon Vijay Abraham I 425c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 426c8518efaSKishon Vijay Abraham I { 427c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 428c8518efaSKishon Vijay Abraham I int ret; 429c8518efaSKishon Vijay Abraham I 430c8518efaSKishon Vijay Abraham I /* 431c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 432c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 433c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 434c8518efaSKishon Vijay Abraham I */ 435c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 436c8518efaSKishon Vijay Abraham I if (ret) { 437c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 438c8518efaSKishon Vijay Abraham I return ret; 439c8518efaSKishon Vijay Abraham I } 440c8518efaSKishon Vijay Abraham I 441c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 442c8518efaSKishon Vijay Abraham I if (ret) { 443c8518efaSKishon Vijay Abraham I dev_err(host->dev, 444c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 445c8518efaSKishon Vijay Abraham I return ret; 446c8518efaSKishon Vijay Abraham I } 447c8518efaSKishon Vijay Abraham I 448c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 449c8518efaSKishon Vijay Abraham I if (ret) { 450c8518efaSKishon Vijay Abraham I dev_err(host->dev, 451c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 452c8518efaSKishon Vijay Abraham I return ret; 453c8518efaSKishon Vijay Abraham I } 454c8518efaSKishon Vijay Abraham I 455c8518efaSKishon Vijay Abraham I return 0; 456c8518efaSKishon Vijay Abraham I } 457c8518efaSKishon Vijay Abraham I 458db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 459db0fefc5SAdrian Hunter { 4607d607f91SKishon Vijay Abraham I int ret; 461aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 462db0fefc5SAdrian Hunter 463f7f0f035SAndreas Fenkart 46413ab2a66SKishon Vijay Abraham I ret = mmc_regulator_get_supply(mmc); 46513ab2a66SKishon Vijay Abraham I if (ret == -EPROBE_DEFER) 4667d607f91SKishon Vijay Abraham I return ret; 467db0fefc5SAdrian Hunter 468db0fefc5SAdrian Hunter /* Allow an aux regulator */ 46913ab2a66SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 47013ab2a66SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 47113ab2a66SKishon Vijay Abraham I "vmmc_aux"); 472aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 473aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 474123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4756a9b2ff0SKishon Vijay Abraham I return ret; 4766a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 477aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 4786a9b2ff0SKishon Vijay Abraham I } 47913ab2a66SKishon Vijay Abraham I } 480db0fefc5SAdrian Hunter 481c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 482c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 483c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 4849143757bSKishon Vijay Abraham I if ((ret != -ENODEV) && host->dev->of_node) { 4859143757bSKishon Vijay Abraham I dev_err(host->dev, 4869143757bSKishon Vijay Abraham I "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 4876a9b2ff0SKishon Vijay Abraham I return ret; 4889143757bSKishon Vijay Abraham I } 4896a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 490c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 4916a9b2ff0SKishon Vijay Abraham I } 492e99448ffSBalaji T K 493b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 494326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 495b1c1df7aSBalaji T K return 0; 496e840ce13SAdrian Hunter 497c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 498c8518efaSKishon Vijay Abraham I if (ret) 499c8518efaSKishon Vijay Abraham I return ret; 500db0fefc5SAdrian Hunter 501db0fefc5SAdrian Hunter return 0; 502db0fefc5SAdrian Hunter } 503db0fefc5SAdrian Hunter 504cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 50541afa314SNeilBrown 50641afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 50741afa314SNeilBrown struct omap_hsmmc_host *host, 5081e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 509b702b106SAdrian Hunter { 510b702b106SAdrian Hunter int ret; 511b702b106SAdrian Hunter 512b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 513b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 514b702b106SAdrian Hunter if (ret) 515b702b106SAdrian Hunter return ret; 516cde592cbSAndreas Fenkart 517cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 518cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 519b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 520b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 521cde592cbSAndreas Fenkart if (ret) 522cde592cbSAndreas Fenkart return ret; 523cde592cbSAndreas Fenkart 524cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 525326119c9SAndreas Fenkart } 526b702b106SAdrian Hunter 527326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 52841afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 529b702b106SAdrian Hunter if (ret) 53041afa314SNeilBrown return ret; 531326119c9SAndreas Fenkart } 532b702b106SAdrian Hunter 533b702b106SAdrian Hunter return 0; 534b702b106SAdrian Hunter } 535b702b106SAdrian Hunter 536a45c6cb8SMadhusudhan Chikkature /* 537e0c7f99bSAndy Shevchenko * Start clock to the card 538e0c7f99bSAndy Shevchenko */ 539e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 540e0c7f99bSAndy Shevchenko { 541e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 542e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 543e0c7f99bSAndy Shevchenko } 544e0c7f99bSAndy Shevchenko 545e0c7f99bSAndy Shevchenko /* 546a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 547a45c6cb8SMadhusudhan Chikkature */ 54870a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 549a45c6cb8SMadhusudhan Chikkature { 550a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 551a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 552a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5537122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 554a45c6cb8SMadhusudhan Chikkature } 555a45c6cb8SMadhusudhan Chikkature 55693caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 55793caf8e6SAdrian Hunter struct mmc_command *cmd) 558b417577dSAdrian Hunter { 5592cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5602cd3a2a5SAndreas Fenkart unsigned long flags; 561b417577dSAdrian Hunter 562b417577dSAdrian Hunter if (host->use_dma) 5632cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 564b417577dSAdrian Hunter 56593caf8e6SAdrian Hunter /* Disable timeout for erases */ 56693caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 567a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 56893caf8e6SAdrian Hunter 5692cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 570b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 571b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5722cd3a2a5SAndreas Fenkart 5732cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5742cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5752cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 576b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5772cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 578b417577dSAdrian Hunter } 579b417577dSAdrian Hunter 580b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 581b417577dSAdrian Hunter { 5822cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5832cd3a2a5SAndreas Fenkart unsigned long flags; 5842cd3a2a5SAndreas Fenkart 5852cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5862cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5872cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5882cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5892cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5902cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 591b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5922cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 593b417577dSAdrian Hunter } 594b417577dSAdrian Hunter 595ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 596d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 597ac330f44SAndy Shevchenko { 598ac330f44SAndy Shevchenko u16 dsor = 0; 599ac330f44SAndy Shevchenko 600ac330f44SAndy Shevchenko if (ios->clock) { 601d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 602ed164182SBalaji T K if (dsor > CLKD_MAX) 603ed164182SBalaji T K dsor = CLKD_MAX; 604ac330f44SAndy Shevchenko } 605ac330f44SAndy Shevchenko 606ac330f44SAndy Shevchenko return dsor; 607ac330f44SAndy Shevchenko } 608ac330f44SAndy Shevchenko 6095934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6105934df2fSAndy Shevchenko { 6115934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6125934df2fSAndy Shevchenko unsigned long regval; 6135934df2fSAndy Shevchenko unsigned long timeout; 614cd587096SHebbar, Gururaja unsigned long clkdiv; 6155934df2fSAndy Shevchenko 6168986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6175934df2fSAndy Shevchenko 6185934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6195934df2fSAndy Shevchenko 6205934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6215934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 622cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 623cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6245934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6255934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6265934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6275934df2fSAndy Shevchenko 6285934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6295934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6305934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6315934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6325934df2fSAndy Shevchenko cpu_relax(); 6335934df2fSAndy Shevchenko 634cd587096SHebbar, Gururaja /* 635cd587096SHebbar, Gururaja * Enable High-Speed Support 636cd587096SHebbar, Gururaja * Pre-Requisites 637cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 638cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 639cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 640cd587096SHebbar, Gururaja * in capabilities register 641cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 642cd587096SHebbar, Gururaja */ 643326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6445438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 645903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 646cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 647cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 648cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 649cd587096SHebbar, Gururaja regval |= HSPE; 650cd587096SHebbar, Gururaja else 651cd587096SHebbar, Gururaja regval &= ~HSPE; 652cd587096SHebbar, Gururaja 653cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 654cd587096SHebbar, Gururaja } 655cd587096SHebbar, Gururaja 6565934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6575934df2fSAndy Shevchenko } 6585934df2fSAndy Shevchenko 6593796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6603796fb8aSAndy Shevchenko { 6613796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6623796fb8aSAndy Shevchenko u32 con; 6633796fb8aSAndy Shevchenko 6643796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 665903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 666903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 66703b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 66803b5d924SBalaji T K else 66903b5d924SBalaji T K con &= ~DDR; 6703796fb8aSAndy Shevchenko switch (ios->bus_width) { 6713796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6723796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6733796fb8aSAndy Shevchenko break; 6743796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6753796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6763796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6773796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6783796fb8aSAndy Shevchenko break; 6793796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6803796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6813796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6823796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6833796fb8aSAndy Shevchenko break; 6843796fb8aSAndy Shevchenko } 6853796fb8aSAndy Shevchenko } 6863796fb8aSAndy Shevchenko 6873796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6883796fb8aSAndy Shevchenko { 6893796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6903796fb8aSAndy Shevchenko u32 con; 6913796fb8aSAndy Shevchenko 6923796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6933796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6943796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6953796fb8aSAndy Shevchenko else 6963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6973796fb8aSAndy Shevchenko } 6983796fb8aSAndy Shevchenko 69911dd62a7SDenis Karpov #ifdef CONFIG_PM 70011dd62a7SDenis Karpov 70111dd62a7SDenis Karpov /* 70211dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 70311dd62a7SDenis Karpov * power state change. 70411dd62a7SDenis Karpov */ 70570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70611dd62a7SDenis Karpov { 70711dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7083796fb8aSAndy Shevchenko u32 hctl, capa; 70911dd62a7SDenis Karpov unsigned long timeout; 71011dd62a7SDenis Karpov 7110a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7120a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7130a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7140a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7150a82e06eSTony Lindgren return 0; 7160a82e06eSTony Lindgren 7170a82e06eSTony Lindgren host->context_loss++; 7180a82e06eSTony Lindgren 719c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 72011dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 72111dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 72211dd62a7SDenis Karpov hctl = SDVS18; 72311dd62a7SDenis Karpov else 72411dd62a7SDenis Karpov hctl = SDVS30; 72511dd62a7SDenis Karpov capa = VS30 | VS18; 72611dd62a7SDenis Karpov } else { 72711dd62a7SDenis Karpov hctl = SDVS18; 72811dd62a7SDenis Karpov capa = VS18; 72911dd62a7SDenis Karpov } 73011dd62a7SDenis Karpov 7315a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7325a52b08bSBalaji T K hctl |= IWE; 7335a52b08bSBalaji T K 73411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 73511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 73611dd62a7SDenis Karpov 73711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 73811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 73911dd62a7SDenis Karpov 74011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 74111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 74211dd62a7SDenis Karpov 74311dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 74411dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 74511dd62a7SDenis Karpov && time_before(jiffies, timeout)) 74611dd62a7SDenis Karpov ; 74711dd62a7SDenis Karpov 7482cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7492cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7502cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 75111dd62a7SDenis Karpov 75211dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 75311dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 75411dd62a7SDenis Karpov goto out; 75511dd62a7SDenis Karpov 7563796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 75711dd62a7SDenis Karpov 7585934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 75911dd62a7SDenis Karpov 7603796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7613796fb8aSAndy Shevchenko 76211dd62a7SDenis Karpov out: 7630a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7640a82e06eSTony Lindgren host->context_loss); 76511dd62a7SDenis Karpov return 0; 76611dd62a7SDenis Karpov } 76711dd62a7SDenis Karpov 76811dd62a7SDenis Karpov /* 76911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 77011dd62a7SDenis Karpov */ 77170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 77211dd62a7SDenis Karpov { 7730a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7740a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7750a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7760a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 77711dd62a7SDenis Karpov } 77811dd62a7SDenis Karpov 77911dd62a7SDenis Karpov #else 78011dd62a7SDenis Karpov 78170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 78211dd62a7SDenis Karpov { 78311dd62a7SDenis Karpov return 0; 78411dd62a7SDenis Karpov } 78511dd62a7SDenis Karpov 78670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 78711dd62a7SDenis Karpov { 78811dd62a7SDenis Karpov } 78911dd62a7SDenis Karpov 79011dd62a7SDenis Karpov #endif 79111dd62a7SDenis Karpov 792a45c6cb8SMadhusudhan Chikkature /* 793a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 794a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 795a45c6cb8SMadhusudhan Chikkature */ 79670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 797a45c6cb8SMadhusudhan Chikkature { 798a45c6cb8SMadhusudhan Chikkature int reg = 0; 799a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 800a45c6cb8SMadhusudhan Chikkature 801b62f6228SAdrian Hunter if (host->protect_card) 802b62f6228SAdrian Hunter return; 803b62f6228SAdrian Hunter 804a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 805b417577dSAdrian Hunter 806b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 807a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 808a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 809a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 810a45c6cb8SMadhusudhan Chikkature 811a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 812a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 813a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 814a45c6cb8SMadhusudhan Chikkature 815a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 816a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 817c653a6d4SAdrian Hunter 818c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 819c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 820c653a6d4SAdrian Hunter 821a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 822a45c6cb8SMadhusudhan Chikkature } 823a45c6cb8SMadhusudhan Chikkature 824a45c6cb8SMadhusudhan Chikkature static inline 82570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 826a45c6cb8SMadhusudhan Chikkature { 827a45c6cb8SMadhusudhan Chikkature int r = 1; 828a45c6cb8SMadhusudhan Chikkature 829b5cd43f0SAndreas Fenkart if (host->get_cover_state) 83080412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 831a45c6cb8SMadhusudhan Chikkature return r; 832a45c6cb8SMadhusudhan Chikkature } 833a45c6cb8SMadhusudhan Chikkature 834a45c6cb8SMadhusudhan Chikkature static ssize_t 83570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 836a45c6cb8SMadhusudhan Chikkature char *buf) 837a45c6cb8SMadhusudhan Chikkature { 838a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 83970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 840a45c6cb8SMadhusudhan Chikkature 84170a3341aSDenis Karpov return sprintf(buf, "%s\n", 84270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 843a45c6cb8SMadhusudhan Chikkature } 844a45c6cb8SMadhusudhan Chikkature 84570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 846a45c6cb8SMadhusudhan Chikkature 847a45c6cb8SMadhusudhan Chikkature static ssize_t 84870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 849a45c6cb8SMadhusudhan Chikkature char *buf) 850a45c6cb8SMadhusudhan Chikkature { 851a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 85270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 853a45c6cb8SMadhusudhan Chikkature 854326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 855a45c6cb8SMadhusudhan Chikkature } 856a45c6cb8SMadhusudhan Chikkature 85770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 858a45c6cb8SMadhusudhan Chikkature 859a45c6cb8SMadhusudhan Chikkature /* 860a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 861a45c6cb8SMadhusudhan Chikkature */ 862a45c6cb8SMadhusudhan Chikkature static void 86370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 864a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 865a45c6cb8SMadhusudhan Chikkature { 866a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 867a45c6cb8SMadhusudhan Chikkature 8688986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 869a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 870a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 871a45c6cb8SMadhusudhan Chikkature 87293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 873a45c6cb8SMadhusudhan Chikkature 8744a694dc9SAdrian Hunter host->response_busy = 0; 875a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 876a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 877a45c6cb8SMadhusudhan Chikkature resptype = 1; 8784a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8794a694dc9SAdrian Hunter resptype = 3; 8804a694dc9SAdrian Hunter host->response_busy = 1; 8814a694dc9SAdrian Hunter } else 882a45c6cb8SMadhusudhan Chikkature resptype = 2; 883a45c6cb8SMadhusudhan Chikkature } 884a45c6cb8SMadhusudhan Chikkature 885a45c6cb8SMadhusudhan Chikkature /* 886a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 887a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 888a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 889a45c6cb8SMadhusudhan Chikkature */ 890a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 891a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 892a45c6cb8SMadhusudhan Chikkature 893a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 894a45c6cb8SMadhusudhan Chikkature 895a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 896a2e77152SBalaji T K host->mrq->sbc) { 897a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 898a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 899a2e77152SBalaji T K } 900a45c6cb8SMadhusudhan Chikkature if (data) { 901a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 902a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 903a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 904a45c6cb8SMadhusudhan Chikkature else 905a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 906a45c6cb8SMadhusudhan Chikkature } 907a45c6cb8SMadhusudhan Chikkature 908a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 909a7e96879SVenkatraman S cmdreg |= DMAE; 910a45c6cb8SMadhusudhan Chikkature 911b417577dSAdrian Hunter host->req_in_progress = 1; 9124dffd7a2SAdrian Hunter 913a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 914a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 915a45c6cb8SMadhusudhan Chikkature } 916a45c6cb8SMadhusudhan Chikkature 917c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 918c5c98927SRussell King struct mmc_data *data) 919c5c98927SRussell King { 920c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 921c5c98927SRussell King } 922c5c98927SRussell King 923b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 924b417577dSAdrian Hunter { 925b417577dSAdrian Hunter int dma_ch; 92631463b14SVenkatraman S unsigned long flags; 927b417577dSAdrian Hunter 92831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 929b417577dSAdrian Hunter host->req_in_progress = 0; 930b417577dSAdrian Hunter dma_ch = host->dma_ch; 93131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 932b417577dSAdrian Hunter 933b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 934b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 935b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 936b417577dSAdrian Hunter return; 937b417577dSAdrian Hunter host->mrq = NULL; 938b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 939b417577dSAdrian Hunter } 940b417577dSAdrian Hunter 941a45c6cb8SMadhusudhan Chikkature /* 942a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 943a45c6cb8SMadhusudhan Chikkature */ 944a45c6cb8SMadhusudhan Chikkature static void 94570a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 946a45c6cb8SMadhusudhan Chikkature { 9474a694dc9SAdrian Hunter if (!data) { 9484a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9494a694dc9SAdrian Hunter 95023050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 95123050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 95223050103SAdrian Hunter host->response_busy) { 95323050103SAdrian Hunter host->response_busy = 0; 95423050103SAdrian Hunter return; 95523050103SAdrian Hunter } 95623050103SAdrian Hunter 957b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9584a694dc9SAdrian Hunter return; 9594a694dc9SAdrian Hunter } 9604a694dc9SAdrian Hunter 961a45c6cb8SMadhusudhan Chikkature host->data = NULL; 962a45c6cb8SMadhusudhan Chikkature 963a45c6cb8SMadhusudhan Chikkature if (!data->error) 964a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 965a45c6cb8SMadhusudhan Chikkature else 966a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 967a45c6cb8SMadhusudhan Chikkature 968bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 969fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 970bf129e1cSBalaji T K else 971bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 972a45c6cb8SMadhusudhan Chikkature } 973a45c6cb8SMadhusudhan Chikkature 974a45c6cb8SMadhusudhan Chikkature /* 975a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 976a45c6cb8SMadhusudhan Chikkature */ 977a45c6cb8SMadhusudhan Chikkature static void 97870a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 979a45c6cb8SMadhusudhan Chikkature { 980bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 981a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9822177fa94SBalaji T K host->cmd = NULL; 983bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 984bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 985bf129e1cSBalaji T K host->mrq->data); 986bf129e1cSBalaji T K return; 987bf129e1cSBalaji T K } 988bf129e1cSBalaji T K 9892177fa94SBalaji T K host->cmd = NULL; 9902177fa94SBalaji T K 991a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 992a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 993a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 994a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 995a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 996a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 997a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 998a45c6cb8SMadhusudhan Chikkature } else { 999a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1000a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1001a45c6cb8SMadhusudhan Chikkature } 1002a45c6cb8SMadhusudhan Chikkature } 1003b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1004d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1005a45c6cb8SMadhusudhan Chikkature } 1006a45c6cb8SMadhusudhan Chikkature 1007a45c6cb8SMadhusudhan Chikkature /* 1008a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1009a45c6cb8SMadhusudhan Chikkature */ 101070a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1011a45c6cb8SMadhusudhan Chikkature { 1012b417577dSAdrian Hunter int dma_ch; 101331463b14SVenkatraman S unsigned long flags; 1014b417577dSAdrian Hunter 101582788ff5SJarkko Lavinen host->data->error = errno; 1016a45c6cb8SMadhusudhan Chikkature 101731463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1018b417577dSAdrian Hunter dma_ch = host->dma_ch; 1019b417577dSAdrian Hunter host->dma_ch = -1; 102031463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1021b417577dSAdrian Hunter 1022b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1023c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1024c5c98927SRussell King 1025c5c98927SRussell King dmaengine_terminate_all(chan); 1026c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1027c5c98927SRussell King host->data->sg, host->data->sg_len, 1028feeef096SHeiner Kallweit mmc_get_dma_dir(host->data)); 1029c5c98927SRussell King 1030053bf34fSPer Forlin host->data->host_cookie = 0; 1031a45c6cb8SMadhusudhan Chikkature } 1032a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1033a45c6cb8SMadhusudhan Chikkature } 1034a45c6cb8SMadhusudhan Chikkature 1035a45c6cb8SMadhusudhan Chikkature /* 1036a45c6cb8SMadhusudhan Chikkature * Readable error output 1037a45c6cb8SMadhusudhan Chikkature */ 1038a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1039699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1040a45c6cb8SMadhusudhan Chikkature { 1041a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 104270a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1043699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1044699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1045699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1046699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1047a45c6cb8SMadhusudhan Chikkature }; 1048a45c6cb8SMadhusudhan Chikkature char res[256]; 1049a45c6cb8SMadhusudhan Chikkature char *buf = res; 1050a45c6cb8SMadhusudhan Chikkature int len, i; 1051a45c6cb8SMadhusudhan Chikkature 1052a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1053a45c6cb8SMadhusudhan Chikkature buf += len; 1054a45c6cb8SMadhusudhan Chikkature 105570a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1056a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 105770a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1058a45c6cb8SMadhusudhan Chikkature buf += len; 1059a45c6cb8SMadhusudhan Chikkature } 1060a45c6cb8SMadhusudhan Chikkature 10618986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1062a45c6cb8SMadhusudhan Chikkature } 1063699b958bSAdrian Hunter #else 1064699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1065699b958bSAdrian Hunter u32 status) 1066699b958bSAdrian Hunter { 1067699b958bSAdrian Hunter } 1068a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1069a45c6cb8SMadhusudhan Chikkature 10703ebf74b1SJean Pihet /* 10713ebf74b1SJean Pihet * MMC controller internal state machines reset 10723ebf74b1SJean Pihet * 10733ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10743ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10753ebf74b1SJean Pihet * Can be called from interrupt context 10763ebf74b1SJean Pihet */ 107770a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10783ebf74b1SJean Pihet unsigned long bit) 10793ebf74b1SJean Pihet { 10803ebf74b1SJean Pihet unsigned long i = 0; 10811e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10823ebf74b1SJean Pihet 10833ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10843ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10853ebf74b1SJean Pihet 108607ad64b6SMadhusudhan Chikkature /* 108707ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 108807ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 108907ad64b6SMadhusudhan Chikkature */ 1090326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1091b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 109207ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10931e881786SJianpeng Ma udelay(1); 109407ad64b6SMadhusudhan Chikkature } 109507ad64b6SMadhusudhan Chikkature i = 0; 109607ad64b6SMadhusudhan Chikkature 10973ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10983ebf74b1SJean Pihet (i++ < limit)) 10991e881786SJianpeng Ma udelay(1); 11003ebf74b1SJean Pihet 11013ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11023ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11033ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11043ebf74b1SJean Pihet __func__); 11053ebf74b1SJean Pihet } 1106a45c6cb8SMadhusudhan Chikkature 110725e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 110825e1897bSBalaji T K int err, int end_cmd) 1109ae4bf788SVenkatraman S { 111025e1897bSBalaji T K if (end_cmd) { 111194d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 111225e1897bSBalaji T K if (host->cmd) 1113ae4bf788SVenkatraman S host->cmd->error = err; 111425e1897bSBalaji T K } 1115ae4bf788SVenkatraman S 1116ae4bf788SVenkatraman S if (host->data) { 1117ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1118ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1119dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1120dc7745bdSBalaji T K host->mrq->cmd->error = err; 1121ae4bf788SVenkatraman S } 1122ae4bf788SVenkatraman S 1123b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1124a45c6cb8SMadhusudhan Chikkature { 1125a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1126b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1127a2e77152SBalaji T K int error = 0; 1128a45c6cb8SMadhusudhan Chikkature 1129a45c6cb8SMadhusudhan Chikkature data = host->data; 11308986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1131a45c6cb8SMadhusudhan Chikkature 1132a7e96879SVenkatraman S if (status & ERR_EN) { 1133699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11344a694dc9SAdrian Hunter 113524380dd4SRavikumar Kattekola if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1136a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1137408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1138408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1139408806f7SKishon Vijay Abraham I host->response_busy = 0; 1140408806f7SKishon Vijay Abraham I } 1141a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 114225e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11435027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11445027cd1eSVignesh R BADA_EN)) 114525e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 114625e1897bSBalaji T K 1147a2e77152SBalaji T K if (status & ACE_EN) { 1148a2e77152SBalaji T K u32 ac12; 1149a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1150a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1151a2e77152SBalaji T K end_cmd = 1; 1152a2e77152SBalaji T K if (ac12 & ACTO) 1153a2e77152SBalaji T K error = -ETIMEDOUT; 1154a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1155a2e77152SBalaji T K error = -EILSEQ; 1156a2e77152SBalaji T K host->mrq->sbc->error = error; 1157a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1158a2e77152SBalaji T K } 1159a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1160a2e77152SBalaji T K } 1161a45c6cb8SMadhusudhan Chikkature } 1162a45c6cb8SMadhusudhan Chikkature 11637472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1164a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 116570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1166a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 116770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1168b417577dSAdrian Hunter } 1169a45c6cb8SMadhusudhan Chikkature 1170b417577dSAdrian Hunter /* 1171b417577dSAdrian Hunter * MMC controller IRQ handler 1172b417577dSAdrian Hunter */ 1173b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1174b417577dSAdrian Hunter { 1175b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1176b417577dSAdrian Hunter int status; 1177b417577dSAdrian Hunter 1178b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11792cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11802cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1181b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11821f6b9fa4SVenkatraman S 11832cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11842cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11852cd3a2a5SAndreas Fenkart 1186b417577dSAdrian Hunter /* Flush posted write */ 1187b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11881f6b9fa4SVenkatraman S } 11894dffd7a2SAdrian Hunter 1190a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1191a45c6cb8SMadhusudhan Chikkature } 1192a45c6cb8SMadhusudhan Chikkature 119370a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1194e13bb300SAdrian Hunter { 1195e13bb300SAdrian Hunter unsigned long i; 1196e13bb300SAdrian Hunter 1197e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1198e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1199e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1200e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1201e13bb300SAdrian Hunter break; 1202e13bb300SAdrian Hunter cpu_relax(); 1203e13bb300SAdrian Hunter } 1204e13bb300SAdrian Hunter } 1205e13bb300SAdrian Hunter 1206a45c6cb8SMadhusudhan Chikkature /* 1207eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1208eb250826SDavid Brownell * 1209eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1210eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1211eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1212a45c6cb8SMadhusudhan Chikkature */ 121370a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1214a45c6cb8SMadhusudhan Chikkature { 1215a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1216a45c6cb8SMadhusudhan Chikkature int ret; 1217a45c6cb8SMadhusudhan Chikkature 1218a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1219cd03d9a8SRajendra Nayak if (host->dbclk) 122094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1221a45c6cb8SMadhusudhan Chikkature 1222a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 12231ca4d359SAndreas Fenkart ret = omap_hsmmc_set_power(host, 0, 0); 1224a45c6cb8SMadhusudhan Chikkature 1225a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12262bec0893SAdrian Hunter if (!ret) 12271ca4d359SAndreas Fenkart ret = omap_hsmmc_set_power(host, 1, vdd); 1228cd03d9a8SRajendra Nayak if (host->dbclk) 122994c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12302bec0893SAdrian Hunter 1231a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1232a45c6cb8SMadhusudhan Chikkature goto err; 1233a45c6cb8SMadhusudhan Chikkature 1234a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1235a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1236a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1237eb250826SDavid Brownell 1238a45c6cb8SMadhusudhan Chikkature /* 1239a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1240a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 124170a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1242a45c6cb8SMadhusudhan Chikkature * 1243eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1244eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1245eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1246eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1247eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1248eb250826SDavid Brownell * 1249eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1250eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1251eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1252a45c6cb8SMadhusudhan Chikkature */ 1253eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1254a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1255eb250826SDavid Brownell else 1256eb250826SDavid Brownell reg_val |= SDVS30; 1257a45c6cb8SMadhusudhan Chikkature 1258a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1259e13bb300SAdrian Hunter set_sd_bus_power(host); 1260a45c6cb8SMadhusudhan Chikkature 1261a45c6cb8SMadhusudhan Chikkature return 0; 1262a45c6cb8SMadhusudhan Chikkature err: 1263b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1264a45c6cb8SMadhusudhan Chikkature return ret; 1265a45c6cb8SMadhusudhan Chikkature } 1266a45c6cb8SMadhusudhan Chikkature 1267b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1268b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1269b62f6228SAdrian Hunter { 1270b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1271b62f6228SAdrian Hunter return; 1272b62f6228SAdrian Hunter 1273b62f6228SAdrian Hunter host->reqs_blocked = 0; 127480412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1275b62f6228SAdrian Hunter if (host->protect_card) { 12762cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1277b62f6228SAdrian Hunter "card is now accessible\n", 1278b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1279b62f6228SAdrian Hunter host->protect_card = 0; 1280b62f6228SAdrian Hunter } 1281b62f6228SAdrian Hunter } else { 1282b62f6228SAdrian Hunter if (!host->protect_card) { 12832cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1284b62f6228SAdrian Hunter "card is now inaccessible\n", 1285b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1286b62f6228SAdrian Hunter host->protect_card = 1; 1287b62f6228SAdrian Hunter } 1288b62f6228SAdrian Hunter } 1289b62f6228SAdrian Hunter } 1290b62f6228SAdrian Hunter 1291a45c6cb8SMadhusudhan Chikkature /* 1292cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1293cde592cbSAndreas Fenkart */ 1294cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1295cde592cbSAndreas Fenkart { 1296cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1297cde592cbSAndreas Fenkart 1298cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1299cde592cbSAndreas Fenkart 1300cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1301cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1302cde592cbSAndreas Fenkart return IRQ_HANDLED; 1303cde592cbSAndreas Fenkart } 1304cde592cbSAndreas Fenkart 1305c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13060ccd76d4SJuha Yrjola { 1307c5c98927SRussell King struct omap_hsmmc_host *host = param; 1308c5c98927SRussell King struct dma_chan *chan; 1309770d7432SAdrian Hunter struct mmc_data *data; 1310c5c98927SRussell King int req_in_progress; 1311a45c6cb8SMadhusudhan Chikkature 1312c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1313b417577dSAdrian Hunter if (host->dma_ch < 0) { 1314c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1315a45c6cb8SMadhusudhan Chikkature return; 1316b417577dSAdrian Hunter } 1317a45c6cb8SMadhusudhan Chikkature 1318770d7432SAdrian Hunter data = host->mrq->data; 1319c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13209782aff8SPer Forlin if (!data->host_cookie) 1321c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1322c5c98927SRussell King data->sg, data->sg_len, 1323feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 1324b417577dSAdrian Hunter 1325b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1326a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1327c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1328b417577dSAdrian Hunter 1329b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1330b417577dSAdrian Hunter if (!req_in_progress) { 1331b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1332b417577dSAdrian Hunter 1333b417577dSAdrian Hunter host->mrq = NULL; 1334b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1335b417577dSAdrian Hunter } 1336a45c6cb8SMadhusudhan Chikkature } 1337a45c6cb8SMadhusudhan Chikkature 13389782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13399782aff8SPer Forlin struct mmc_data *data, 1340c5c98927SRussell King struct omap_hsmmc_next *next, 134126b88520SRussell King struct dma_chan *chan) 13429782aff8SPer Forlin { 13439782aff8SPer Forlin int dma_len; 13449782aff8SPer Forlin 13459782aff8SPer Forlin if (!next && data->host_cookie && 13469782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13472cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13489782aff8SPer Forlin " host->next_data.cookie %d\n", 13499782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13509782aff8SPer Forlin data->host_cookie = 0; 13519782aff8SPer Forlin } 13529782aff8SPer Forlin 13539782aff8SPer Forlin /* Check if next job is already prepared */ 1354b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 135526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1356feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 13579782aff8SPer Forlin 13589782aff8SPer Forlin } else { 13599782aff8SPer Forlin dma_len = host->next_data.dma_len; 13609782aff8SPer Forlin host->next_data.dma_len = 0; 13619782aff8SPer Forlin } 13629782aff8SPer Forlin 13639782aff8SPer Forlin 13649782aff8SPer Forlin if (dma_len == 0) 13659782aff8SPer Forlin return -EINVAL; 13669782aff8SPer Forlin 13679782aff8SPer Forlin if (next) { 13689782aff8SPer Forlin next->dma_len = dma_len; 13699782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13709782aff8SPer Forlin } else 13719782aff8SPer Forlin host->dma_len = dma_len; 13729782aff8SPer Forlin 13739782aff8SPer Forlin return 0; 13749782aff8SPer Forlin } 13759782aff8SPer Forlin 1376a45c6cb8SMadhusudhan Chikkature /* 1377a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1378a45c6cb8SMadhusudhan Chikkature */ 13799d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 138070a3341aSDenis Karpov struct mmc_request *req) 1381a45c6cb8SMadhusudhan Chikkature { 138226b88520SRussell King struct dma_async_tx_descriptor *tx; 138326b88520SRussell King int ret = 0, i; 1384a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1385c5c98927SRussell King struct dma_chan *chan; 1386e5789608SPeter Ujfalusi struct dma_slave_config cfg = { 1387e5789608SPeter Ujfalusi .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1388e5789608SPeter Ujfalusi .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1389e5789608SPeter Ujfalusi .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1390e5789608SPeter Ujfalusi .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1391e5789608SPeter Ujfalusi .src_maxburst = data->blksz / 4, 1392e5789608SPeter Ujfalusi .dst_maxburst = data->blksz / 4, 1393e5789608SPeter Ujfalusi }; 1394a45c6cb8SMadhusudhan Chikkature 13950ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1396a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13970ccd76d4SJuha Yrjola struct scatterlist *sgl; 13980ccd76d4SJuha Yrjola 13990ccd76d4SJuha Yrjola sgl = data->sg + i; 14000ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14010ccd76d4SJuha Yrjola return -EINVAL; 14020ccd76d4SJuha Yrjola } 14030ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14040ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14050ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14060ccd76d4SJuha Yrjola */ 14070ccd76d4SJuha Yrjola return -EINVAL; 14080ccd76d4SJuha Yrjola 1409b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1410a45c6cb8SMadhusudhan Chikkature 1411c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1412c5c98927SRussell King 1413c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14149782aff8SPer Forlin if (ret) 14159782aff8SPer Forlin return ret; 1416a45c6cb8SMadhusudhan Chikkature 141726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1418c5c98927SRussell King if (ret) 1419c5c98927SRussell King return ret; 1420a45c6cb8SMadhusudhan Chikkature 1421c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1422c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1423c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1424c5c98927SRussell King if (!tx) { 1425c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1426c5c98927SRussell King /* FIXME: cleanup */ 1427c5c98927SRussell King return -1; 1428c5c98927SRussell King } 1429c5c98927SRussell King 1430c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1431c5c98927SRussell King tx->callback_param = host; 1432c5c98927SRussell King 1433c5c98927SRussell King /* Does not fail */ 1434c5c98927SRussell King dmaengine_submit(tx); 1435c5c98927SRussell King 143626b88520SRussell King host->dma_ch = 1; 1437c5c98927SRussell King 1438a45c6cb8SMadhusudhan Chikkature return 0; 1439a45c6cb8SMadhusudhan Chikkature } 1440a45c6cb8SMadhusudhan Chikkature 144170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1442a53210f5SRavikumar Kattekola unsigned long long timeout_ns, 1443e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1444a45c6cb8SMadhusudhan Chikkature { 1445a53210f5SRavikumar Kattekola unsigned long long timeout = timeout_ns; 1446a53210f5SRavikumar Kattekola unsigned int cycle_ns; 1447a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1448a45c6cb8SMadhusudhan Chikkature 1449a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1450a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1451a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1452a45c6cb8SMadhusudhan Chikkature clkd = 1; 1453a45c6cb8SMadhusudhan Chikkature 14546e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1455a53210f5SRavikumar Kattekola do_div(timeout, cycle_ns); 1456e2bf08d6SAdrian Hunter timeout += timeout_clks; 1457a45c6cb8SMadhusudhan Chikkature if (timeout) { 1458a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1459a45c6cb8SMadhusudhan Chikkature dto += 1; 1460a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1461a45c6cb8SMadhusudhan Chikkature } 1462a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1463a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1464a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1465a45c6cb8SMadhusudhan Chikkature dto += 1; 1466a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1467a45c6cb8SMadhusudhan Chikkature dto -= 13; 1468a45c6cb8SMadhusudhan Chikkature else 1469a45c6cb8SMadhusudhan Chikkature dto = 0; 1470a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1471a45c6cb8SMadhusudhan Chikkature dto = 14; 1472a45c6cb8SMadhusudhan Chikkature } 1473a45c6cb8SMadhusudhan Chikkature 1474a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1475a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1476a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1477a45c6cb8SMadhusudhan Chikkature } 1478a45c6cb8SMadhusudhan Chikkature 14799d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14809d025334SBalaji T K { 14819d025334SBalaji T K struct mmc_request *req = host->mrq; 14829d025334SBalaji T K struct dma_chan *chan; 14839d025334SBalaji T K 14849d025334SBalaji T K if (!req->data) 14859d025334SBalaji T K return; 14869d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14879d025334SBalaji T K | (req->data->blocks << 16)); 14889d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14899d025334SBalaji T K req->data->timeout_clks); 14909d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14919d025334SBalaji T K dma_async_issue_pending(chan); 14929d025334SBalaji T K } 14939d025334SBalaji T K 1494a45c6cb8SMadhusudhan Chikkature /* 1495a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1496a45c6cb8SMadhusudhan Chikkature */ 1497a45c6cb8SMadhusudhan Chikkature static int 149870a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1499a45c6cb8SMadhusudhan Chikkature { 1500a45c6cb8SMadhusudhan Chikkature int ret; 1501a53210f5SRavikumar Kattekola unsigned long long timeout; 15028cc9a3e7SKishon Vijay Abraham I 1503a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1504a45c6cb8SMadhusudhan Chikkature 1505a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1506a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 15078cc9a3e7SKishon Vijay Abraham I if (req->cmd->flags & MMC_RSP_BUSY) { 15088cc9a3e7SKishon Vijay Abraham I timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 15098cc9a3e7SKishon Vijay Abraham I 1510e2bf08d6SAdrian Hunter /* 1511e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 15128cc9a3e7SKishon Vijay Abraham I * busy signal and no indication of busy_timeout. 1513e2bf08d6SAdrian Hunter */ 15148cc9a3e7SKishon Vijay Abraham I if (!timeout) 15158cc9a3e7SKishon Vijay Abraham I timeout = 100000000U; 15168cc9a3e7SKishon Vijay Abraham I 15178cc9a3e7SKishon Vijay Abraham I set_data_timeout(host, timeout, 0); 15188cc9a3e7SKishon Vijay Abraham I } 1519a45c6cb8SMadhusudhan Chikkature return 0; 1520a45c6cb8SMadhusudhan Chikkature } 1521a45c6cb8SMadhusudhan Chikkature 1522a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15239d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1524a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1525b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1526a45c6cb8SMadhusudhan Chikkature return ret; 1527a45c6cb8SMadhusudhan Chikkature } 1528a45c6cb8SMadhusudhan Chikkature } 1529a45c6cb8SMadhusudhan Chikkature return 0; 1530a45c6cb8SMadhusudhan Chikkature } 1531a45c6cb8SMadhusudhan Chikkature 15329782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15339782aff8SPer Forlin int err) 15349782aff8SPer Forlin { 15359782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15369782aff8SPer Forlin struct mmc_data *data = mrq->data; 15379782aff8SPer Forlin 153826b88520SRussell King if (host->use_dma && data->host_cookie) { 1539c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1540c5c98927SRussell King 154126b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1542feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 15439782aff8SPer Forlin data->host_cookie = 0; 15449782aff8SPer Forlin } 15459782aff8SPer Forlin } 15469782aff8SPer Forlin 1547d3c6aac3SLinus Walleij static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 15489782aff8SPer Forlin { 15499782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15509782aff8SPer Forlin 15519782aff8SPer Forlin if (mrq->data->host_cookie) { 15529782aff8SPer Forlin mrq->data->host_cookie = 0; 15539782aff8SPer Forlin return ; 15549782aff8SPer Forlin } 15559782aff8SPer Forlin 1556c5c98927SRussell King if (host->use_dma) { 1557c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1558c5c98927SRussell King 15599782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 156026b88520SRussell King &host->next_data, c)) 15619782aff8SPer Forlin mrq->data->host_cookie = 0; 15629782aff8SPer Forlin } 1563c5c98927SRussell King } 15649782aff8SPer Forlin 1565a45c6cb8SMadhusudhan Chikkature /* 1566a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1567a45c6cb8SMadhusudhan Chikkature */ 156870a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1569a45c6cb8SMadhusudhan Chikkature { 157070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1571a3f406f8SJarkko Lavinen int err; 1572a45c6cb8SMadhusudhan Chikkature 1573b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1574b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1575b62f6228SAdrian Hunter if (host->protect_card) { 1576b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1577b62f6228SAdrian Hunter /* 1578b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1579b62f6228SAdrian Hunter * state by resetting the command and data state 1580b62f6228SAdrian Hunter * machines. 1581b62f6228SAdrian Hunter */ 1582b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1583b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1584b62f6228SAdrian Hunter host->reqs_blocked += 1; 1585b62f6228SAdrian Hunter } 1586b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1587b62f6228SAdrian Hunter if (req->data) 1588b62f6228SAdrian Hunter req->data->error = -EBADF; 1589b417577dSAdrian Hunter req->cmd->retries = 0; 1590b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1591b62f6228SAdrian Hunter return; 1592b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1593b62f6228SAdrian Hunter host->reqs_blocked = 0; 1594a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1595a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15966e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 159770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1598a3f406f8SJarkko Lavinen if (err) { 1599a3f406f8SJarkko Lavinen req->cmd->error = err; 1600a3f406f8SJarkko Lavinen if (req->data) 1601a3f406f8SJarkko Lavinen req->data->error = err; 1602a3f406f8SJarkko Lavinen host->mrq = NULL; 1603a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1604a3f406f8SJarkko Lavinen return; 1605a3f406f8SJarkko Lavinen } 1606a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1607bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1608bf129e1cSBalaji T K return; 1609bf129e1cSBalaji T K } 1610a3f406f8SJarkko Lavinen 16119d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 161270a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1613a45c6cb8SMadhusudhan Chikkature } 1614a45c6cb8SMadhusudhan Chikkature 1615a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 161670a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1617a45c6cb8SMadhusudhan Chikkature { 161870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1619a3621465SAdrian Hunter int do_send_init_stream = 0; 1620a45c6cb8SMadhusudhan Chikkature 1621a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1622a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1623a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 16241ca4d359SAndreas Fenkart omap_hsmmc_set_power(host, 0, 0); 1625a45c6cb8SMadhusudhan Chikkature break; 1626a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 16271ca4d359SAndreas Fenkart omap_hsmmc_set_power(host, 1, ios->vdd); 1628a45c6cb8SMadhusudhan Chikkature break; 1629a3621465SAdrian Hunter case MMC_POWER_ON: 1630a3621465SAdrian Hunter do_send_init_stream = 1; 1631a3621465SAdrian Hunter break; 1632a3621465SAdrian Hunter } 1633a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1634a45c6cb8SMadhusudhan Chikkature } 1635a45c6cb8SMadhusudhan Chikkature 1636dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1637dd498effSDenis Karpov 16383796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1639a45c6cb8SMadhusudhan Chikkature 16404621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1641eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1642eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1643eb250826SDavid Brownell */ 1644a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16452cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1646a45c6cb8SMadhusudhan Chikkature /* 1647a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1648a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1649a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1650a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1651a45c6cb8SMadhusudhan Chikkature */ 165270a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1653a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1654a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1655a45c6cb8SMadhusudhan Chikkature } 1656a45c6cb8SMadhusudhan Chikkature } 1657a45c6cb8SMadhusudhan Chikkature 16585934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1659a45c6cb8SMadhusudhan Chikkature 1660a3621465SAdrian Hunter if (do_send_init_stream) 1661a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1662a45c6cb8SMadhusudhan Chikkature 16633796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 1664a45c6cb8SMadhusudhan Chikkature } 1665a45c6cb8SMadhusudhan Chikkature 1666a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1667a45c6cb8SMadhusudhan Chikkature { 166870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1669a45c6cb8SMadhusudhan Chikkature 1670b5cd43f0SAndreas Fenkart if (!host->card_detect) 1671a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 167280412ca8SAndreas Fenkart return host->card_detect(host->dev); 1673a45c6cb8SMadhusudhan Chikkature } 1674a45c6cb8SMadhusudhan Chikkature 16754816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16764816858cSGrazvydas Ignotas { 16774816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16784816858cSGrazvydas Ignotas 1679326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1680326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16814816858cSGrazvydas Ignotas } 16824816858cSGrazvydas Ignotas 16832cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16842cd3a2a5SAndreas Fenkart { 16852cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16865a52b08bSBalaji T K u32 irq_mask, con; 16872cd3a2a5SAndreas Fenkart unsigned long flags; 16882cd3a2a5SAndreas Fenkart 16892cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16902cd3a2a5SAndreas Fenkart 16915a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16922cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16932cd3a2a5SAndreas Fenkart if (enable) { 16942cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16952cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16965a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16972cd3a2a5SAndreas Fenkart } else { 16982cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16992cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17005a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17012cd3a2a5SAndreas Fenkart } 17025a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17042cd3a2a5SAndreas Fenkart 17052cd3a2a5SAndreas Fenkart /* 17062cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17072cd3a2a5SAndreas Fenkart * but always disable immediately 17082cd3a2a5SAndreas Fenkart */ 17092cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17112cd3a2a5SAndreas Fenkart 17122cd3a2a5SAndreas Fenkart /* flush posted write */ 17132cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17142cd3a2a5SAndreas Fenkart 17152cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17162cd3a2a5SAndreas Fenkart } 17172cd3a2a5SAndreas Fenkart 17182cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17192cd3a2a5SAndreas Fenkart { 17202cd3a2a5SAndreas Fenkart int ret; 17212cd3a2a5SAndreas Fenkart 17222cd3a2a5SAndreas Fenkart /* 17232cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17242cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17252cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17262cd3a2a5SAndreas Fenkart * with functional clock disabled. 17272cd3a2a5SAndreas Fenkart */ 17282cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17292cd3a2a5SAndreas Fenkart return -ENODEV; 17302cd3a2a5SAndreas Fenkart 17315b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17322cd3a2a5SAndreas Fenkart if (ret) { 17332cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17342cd3a2a5SAndreas Fenkart goto err; 17352cd3a2a5SAndreas Fenkart } 17362cd3a2a5SAndreas Fenkart 17372cd3a2a5SAndreas Fenkart /* 17382cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17392cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17402cd3a2a5SAndreas Fenkart */ 17412cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1742455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1743ec5ab893SDan Carpenter if (IS_ERR(p)) { 1744ec5ab893SDan Carpenter ret = PTR_ERR(p); 1745455e5cd6SAndreas Fenkart goto err_free_irq; 1746455e5cd6SAndreas Fenkart } 1747455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1748455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1749455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1750455e5cd6SAndreas Fenkart ret = -EINVAL; 1751455e5cd6SAndreas Fenkart goto err_free_irq; 1752455e5cd6SAndreas Fenkart } 1753455e5cd6SAndreas Fenkart 1754455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1755455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1756455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1757455e5cd6SAndreas Fenkart ret = -EINVAL; 1758455e5cd6SAndreas Fenkart goto err_free_irq; 1759455e5cd6SAndreas Fenkart } 1760455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17612cd3a2a5SAndreas Fenkart } 17622cd3a2a5SAndreas Fenkart 17635a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17645a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17652cd3a2a5SAndreas Fenkart return 0; 17662cd3a2a5SAndreas Fenkart 1767455e5cd6SAndreas Fenkart err_free_irq: 17685b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17692cd3a2a5SAndreas Fenkart err: 17702cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17712cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17722cd3a2a5SAndreas Fenkart return ret; 17732cd3a2a5SAndreas Fenkart } 17742cd3a2a5SAndreas Fenkart 177570a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17761b331e69SKim Kyuwon { 17771b331e69SKim Kyuwon u32 hctl, capa, value; 17781b331e69SKim Kyuwon 17791b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17804621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17811b331e69SKim Kyuwon hctl = SDVS30; 17821b331e69SKim Kyuwon capa = VS30 | VS18; 17831b331e69SKim Kyuwon } else { 17841b331e69SKim Kyuwon hctl = SDVS18; 17851b331e69SKim Kyuwon capa = VS18; 17861b331e69SKim Kyuwon } 17871b331e69SKim Kyuwon 17881b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17891b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17901b331e69SKim Kyuwon 17911b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17921b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17931b331e69SKim Kyuwon 17941b331e69SKim Kyuwon /* Set SD bus power bit */ 1795e13bb300SAdrian Hunter set_sd_bus_power(host); 17961b331e69SKim Kyuwon } 17971b331e69SKim Kyuwon 1798afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1799afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1800afd8c29dSKuninori Morimoto { 1801afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1802afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1803afd8c29dSKuninori Morimoto return 1; 1804afd8c29dSKuninori Morimoto 1805afd8c29dSKuninori Morimoto return blk_size; 1806afd8c29dSKuninori Morimoto } 1807afd8c29dSKuninori Morimoto 1808afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18099782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18109782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 181170a3341aSDenis Karpov .request = omap_hsmmc_request, 181270a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1813dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1814a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18154816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18162cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1817dd498effSDenis Karpov }; 1818dd498effSDenis Karpov 1819d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1820d900f712SDenis Karpov 182170a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1822d900f712SDenis Karpov { 1823d900f712SDenis Karpov struct mmc_host *mmc = s->private; 182470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 182511dd62a7SDenis Karpov 1826bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1827bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1828bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1829bb0635f0SAndreas Fenkart 1830bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1831bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1832bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1833bb0635f0SAndreas Fenkart : "disabled"); 1834bb0635f0SAndreas Fenkart } 1835bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18365e2ea617SAdrian Hunter 1837fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1838bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1839d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1840d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1841bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1842bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1843d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1844d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1845d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1846d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1847d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1848d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1849d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1850d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1851d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1852d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18535e2ea617SAdrian Hunter 1854fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1855fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1856dd498effSDenis Karpov 1857d900f712SDenis Karpov return 0; 1858d900f712SDenis Karpov } 1859d900f712SDenis Karpov 186070a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1861d900f712SDenis Karpov { 186270a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1863d900f712SDenis Karpov } 1864d900f712SDenis Karpov 1865d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 186670a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1867d900f712SDenis Karpov .read = seq_read, 1868d900f712SDenis Karpov .llseek = seq_lseek, 1869d900f712SDenis Karpov .release = single_release, 1870d900f712SDenis Karpov }; 1871d900f712SDenis Karpov 187270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1873d900f712SDenis Karpov { 1874d900f712SDenis Karpov if (mmc->debugfs_root) 1875d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1876d900f712SDenis Karpov mmc, &mmc_regs_fops); 1877d900f712SDenis Karpov } 1878d900f712SDenis Karpov 1879d900f712SDenis Karpov #else 1880d900f712SDenis Karpov 188170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1882d900f712SDenis Karpov { 1883d900f712SDenis Karpov } 1884d900f712SDenis Karpov 1885d900f712SDenis Karpov #endif 1886d900f712SDenis Karpov 188746856a68SRajendra Nayak #ifdef CONFIG_OF 188859445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 188959445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 189059445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 189159445b10SNishanth Menon }; 189259445b10SNishanth Menon 189359445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 189459445b10SNishanth Menon .reg_offset = 0x100, 189559445b10SNishanth Menon }; 18962cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18972cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18982cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18992cd3a2a5SAndreas Fenkart }; 190046856a68SRajendra Nayak 190146856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 190246856a68SRajendra Nayak { 190346856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 190446856a68SRajendra Nayak }, 190546856a68SRajendra Nayak { 190659445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 190759445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 190859445b10SNishanth Menon }, 190959445b10SNishanth Menon { 191046856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 191146856a68SRajendra Nayak }, 191246856a68SRajendra Nayak { 191346856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 191459445b10SNishanth Menon .data = &omap4_mmc_of_data, 191546856a68SRajendra Nayak }, 19162cd3a2a5SAndreas Fenkart { 19172cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19182cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19192cd3a2a5SAndreas Fenkart }, 192046856a68SRajendra Nayak {}, 1921b6d085f6SChris Ball }; 192246856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 192346856a68SRajendra Nayak 192455143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 192546856a68SRajendra Nayak { 1926db863d89STony Lindgren struct omap_hsmmc_platform_data *pdata, *legacy; 192746856a68SRajendra Nayak struct device_node *np = dev->of_node; 192846856a68SRajendra Nayak 192946856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 193046856a68SRajendra Nayak if (!pdata) 193119df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 193246856a68SRajendra Nayak 1933db863d89STony Lindgren legacy = dev_get_platdata(dev); 1934db863d89STony Lindgren if (legacy && legacy->name) 1935db863d89STony Lindgren pdata->name = legacy->name; 1936db863d89STony Lindgren 193746856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 193846856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 193946856a68SRajendra Nayak 1940b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1941b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1942fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 194346856a68SRajendra Nayak 194446856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1945326119c9SAndreas Fenkart pdata->nonremovable = true; 1946326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 194746856a68SRajendra Nayak } 194846856a68SRajendra Nayak 194946856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1950326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 195146856a68SRajendra Nayak 1952cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1953326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1954cd587096SHebbar, Gururaja 195546856a68SRajendra Nayak return pdata; 195646856a68SRajendra Nayak } 195746856a68SRajendra Nayak #else 195855143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 195946856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 196046856a68SRajendra Nayak { 196119df45bcSBalaji T K return ERR_PTR(-EINVAL); 196246856a68SRajendra Nayak } 196346856a68SRajendra Nayak #endif 196446856a68SRajendra Nayak 1965c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1966a45c6cb8SMadhusudhan Chikkature { 196755143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1968a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 196970a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1970a45c6cb8SMadhusudhan Chikkature struct resource *res; 1971db0fefc5SAdrian Hunter int ret, irq; 197246856a68SRajendra Nayak const struct of_device_id *match; 197359445b10SNishanth Menon const struct omap_mmc_of_data *data; 197477fae219SBalaji T K void __iomem *base; 197546856a68SRajendra Nayak 197646856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 197746856a68SRajendra Nayak if (match) { 197846856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1979dc642c28SJan Luebbe 1980dc642c28SJan Luebbe if (IS_ERR(pdata)) 1981dc642c28SJan Luebbe return PTR_ERR(pdata); 1982dc642c28SJan Luebbe 198346856a68SRajendra Nayak if (match->data) { 198459445b10SNishanth Menon data = match->data; 198559445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 198659445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 198746856a68SRajendra Nayak } 198846856a68SRajendra Nayak } 1989a45c6cb8SMadhusudhan Chikkature 1990a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1991a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1992a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1993a45c6cb8SMadhusudhan Chikkature } 1994a45c6cb8SMadhusudhan Chikkature 1995a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1996a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1997a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1998a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1999a45c6cb8SMadhusudhan Chikkature 200077fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 200177fae219SBalaji T K if (IS_ERR(base)) 200277fae219SBalaji T K return PTR_ERR(base); 2003a45c6cb8SMadhusudhan Chikkature 200470a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2005a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2006a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20071e363e3bSAndreas Fenkart goto err; 2008a45c6cb8SMadhusudhan Chikkature } 2009a45c6cb8SMadhusudhan Chikkature 2010fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2011fdb9de12SNeilBrown if (ret) 2012fdb9de12SNeilBrown goto err1; 2013fdb9de12SNeilBrown 2014a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2015a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2016a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2017a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2018a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2019a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2020a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2021fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 202277fae219SBalaji T K host->base = base + pdata->reg_offset; 20236da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20249782aff8SPer Forlin host->next_data.cookie = 1; 2025bb2726b5STony Lindgren host->pbias_enabled = 0; 20263f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2027a45c6cb8SMadhusudhan Chikkature 202841afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20291e363e3bSAndreas Fenkart if (ret) 20301e363e3bSAndreas Fenkart goto err_gpio; 20311e363e3bSAndreas Fenkart 2032a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2033a45c6cb8SMadhusudhan Chikkature 20342cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20352cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20362cd3a2a5SAndreas Fenkart 203770a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2038dd498effSDenis Karpov 20396b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2040d418ed87SDaniel Mack 2041d418ed87SDaniel Mack if (pdata->max_freq > 0) 2042d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2043fdb9de12SNeilBrown else if (mmc->f_max == 0) 20446b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2045a45c6cb8SMadhusudhan Chikkature 20464dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2047a45c6cb8SMadhusudhan Chikkature 20489618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2049a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2050a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2051a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2052a45c6cb8SMadhusudhan Chikkature goto err1; 2053a45c6cb8SMadhusudhan Chikkature } 2054a45c6cb8SMadhusudhan Chikkature 20559b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20569b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2057afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20589b68256cSPaul Walmsley } 2059dd498effSDenis Karpov 20605b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2061fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2062fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2063fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2064fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2065a45c6cb8SMadhusudhan Chikkature 206692a3aebfSBalaji T K omap_hsmmc_context_save(host); 206792a3aebfSBalaji T K 20689618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2069a45c6cb8SMadhusudhan Chikkature /* 2070a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2071a45c6cb8SMadhusudhan Chikkature */ 2072cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2073cd03d9a8SRajendra Nayak host->dbclk = NULL; 207494c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2075cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2076cd03d9a8SRajendra Nayak host->dbclk = NULL; 20772bec0893SAdrian Hunter } 2078a45c6cb8SMadhusudhan Chikkature 20790ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20800ccd76d4SJuha Yrjola * as we want. */ 2081a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20820ccd76d4SJuha Yrjola 2083a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2084a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2085a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2086a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2087a45c6cb8SMadhusudhan Chikkature 208813189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2089ac2b2115SKishon Vijay Abraham I MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; 2090a45c6cb8SMadhusudhan Chikkature 2091326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20923a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2093a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2094a45c6cb8SMadhusudhan Chikkature 2095326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 209623d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 209723d99bb9SAdrian Hunter 2098fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 20996fdc75deSEliad Peller 210070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2101a45c6cb8SMadhusudhan Chikkature 210281eef6caSPeter Ujfalusi host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 210381eef6caSPeter Ujfalusi if (IS_ERR(host->rx_chan)) { 210481eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 210581eef6caSPeter Ujfalusi ret = PTR_ERR(host->rx_chan); 210626b88520SRussell King goto err_irq; 2107c5c98927SRussell King } 210826b88520SRussell King 210981eef6caSPeter Ujfalusi host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 211081eef6caSPeter Ujfalusi if (IS_ERR(host->tx_chan)) { 211181eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 211281eef6caSPeter Ujfalusi ret = PTR_ERR(host->tx_chan); 211326b88520SRussell King goto err_irq; 2114c5c98927SRussell King } 2115a45c6cb8SMadhusudhan Chikkature 2116a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2117e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2118a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2119a45c6cb8SMadhusudhan Chikkature if (ret) { 2120b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2121a45c6cb8SMadhusudhan Chikkature goto err_irq; 2122a45c6cb8SMadhusudhan Chikkature } 2123a45c6cb8SMadhusudhan Chikkature 2124db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2125db0fefc5SAdrian Hunter if (ret) 2126bb09d151SAndreas Fenkart goto err_irq; 2127db0fefc5SAdrian Hunter 212813ab2a66SKishon Vijay Abraham I if (!mmc->ocr_avail) 2129326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2130a45c6cb8SMadhusudhan Chikkature 2131b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2132a45c6cb8SMadhusudhan Chikkature 21332cd3a2a5SAndreas Fenkart /* 21342cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21352cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21362cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21372cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21382cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21392cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21402cd3a2a5SAndreas Fenkart */ 21412cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21422cd3a2a5SAndreas Fenkart if (!ret) 21432cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21442cd3a2a5SAndreas Fenkart 2145b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2146b62f6228SAdrian Hunter 2147a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2148a45c6cb8SMadhusudhan Chikkature 2149326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2150a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2151a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2152a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2153a45c6cb8SMadhusudhan Chikkature } 2154cde592cbSAndreas Fenkart if (host->get_cover_state) { 2155a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2156a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2157a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2158db0fefc5SAdrian Hunter goto err_slot_name; 2159a45c6cb8SMadhusudhan Chikkature } 2160a45c6cb8SMadhusudhan Chikkature 216170a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2162fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2163fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2164d900f712SDenis Karpov 2165a45c6cb8SMadhusudhan Chikkature return 0; 2166a45c6cb8SMadhusudhan Chikkature 2167a45c6cb8SMadhusudhan Chikkature err_slot_name: 2168a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2169a45c6cb8SMadhusudhan Chikkature err_irq: 21705b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 217181eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->tx_chan)) 2172c5c98927SRussell King dma_release_channel(host->tx_chan); 217381eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->rx_chan)) 2174c5c98927SRussell King dma_release_channel(host->rx_chan); 2175814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2176d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 217737f6190dSTony Lindgren pm_runtime_disable(host->dev); 21789618195eSBalaji T K if (host->dbclk) 217994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2180a45c6cb8SMadhusudhan Chikkature err1: 21811e363e3bSAndreas Fenkart err_gpio: 2182a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2183db0fefc5SAdrian Hunter err: 2184a45c6cb8SMadhusudhan Chikkature return ret; 2185a45c6cb8SMadhusudhan Chikkature } 2186a45c6cb8SMadhusudhan Chikkature 21876e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2188a45c6cb8SMadhusudhan Chikkature { 218970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2190a45c6cb8SMadhusudhan Chikkature 2191fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2192a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2193a45c6cb8SMadhusudhan Chikkature 2194c5c98927SRussell King dma_release_channel(host->tx_chan); 2195c5c98927SRussell King dma_release_channel(host->rx_chan); 2196c5c98927SRussell King 2197814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2198fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2199fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22005b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22019618195eSBalaji T K if (host->dbclk) 220294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2203a45c6cb8SMadhusudhan Chikkature 22049d1f0286SBalaji T K mmc_free_host(host->mmc); 2205a45c6cb8SMadhusudhan Chikkature 2206a45c6cb8SMadhusudhan Chikkature return 0; 2207a45c6cb8SMadhusudhan Chikkature } 2208a45c6cb8SMadhusudhan Chikkature 22093d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2210a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2211a45c6cb8SMadhusudhan Chikkature { 2212927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2213927ce944SFelipe Balbi 2214927ce944SFelipe Balbi if (!host) 2215927ce944SFelipe Balbi return 0; 2216a45c6cb8SMadhusudhan Chikkature 2217fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 221831f9d463SEliad Peller 221931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22202cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22212cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22222cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 222331f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 222431f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 222531f9d463SEliad Peller } 2226927ce944SFelipe Balbi 2227cd03d9a8SRajendra Nayak if (host->dbclk) 222894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22293932afd5SUlf Hansson 2230fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22313932afd5SUlf Hansson return 0; 2232a45c6cb8SMadhusudhan Chikkature } 2233a45c6cb8SMadhusudhan Chikkature 2234a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2235a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2236a45c6cb8SMadhusudhan Chikkature { 2237927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2238927ce944SFelipe Balbi 2239927ce944SFelipe Balbi if (!host) 2240927ce944SFelipe Balbi return 0; 2241a45c6cb8SMadhusudhan Chikkature 2242fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 224311dd62a7SDenis Karpov 2244cd03d9a8SRajendra Nayak if (host->dbclk) 224594c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22462bec0893SAdrian Hunter 224731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 224870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22491b331e69SKim Kyuwon 2250b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2251fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2252fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22533932afd5SUlf Hansson return 0; 2254a45c6cb8SMadhusudhan Chikkature } 2255a45c6cb8SMadhusudhan Chikkature #endif 2256a45c6cb8SMadhusudhan Chikkature 2257fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2258fa4aa2d4SBalaji T K { 2259fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22602cd3a2a5SAndreas Fenkart unsigned long flags; 2261f945901fSAndreas Fenkart int ret = 0; 2262fa4aa2d4SBalaji T K 2263fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2264fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2265927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2266fa4aa2d4SBalaji T K 22672cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22682cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22692cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22702cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 22712cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22722cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2273f945901fSAndreas Fenkart 2274f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2275f945901fSAndreas Fenkart /* 2276f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2277f945901fSAndreas Fenkart * race condition: possible irq handler running on 2278f945901fSAndreas Fenkart * multi-core, abort 2279f945901fSAndreas Fenkart */ 2280f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 22812cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2282f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2283f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2284f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2285f945901fSAndreas Fenkart ret = -EBUSY; 2286f945901fSAndreas Fenkart goto abort; 2287f945901fSAndreas Fenkart } 22882cd3a2a5SAndreas Fenkart 228997978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 229097978a44SAndreas Fenkart } else { 229197978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 22922cd3a2a5SAndreas Fenkart } 229397978a44SAndreas Fenkart 2294f945901fSAndreas Fenkart abort: 22952cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2296f945901fSAndreas Fenkart return ret; 2297fa4aa2d4SBalaji T K } 2298fa4aa2d4SBalaji T K 2299fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2300fa4aa2d4SBalaji T K { 2301fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23022cd3a2a5SAndreas Fenkart unsigned long flags; 2303fa4aa2d4SBalaji T K 2304fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2305fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2306927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2307fa4aa2d4SBalaji T K 23082cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23092cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23102cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23112cd3a2a5SAndreas Fenkart 231297978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 231397978a44SAndreas Fenkart 231497978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23152cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23162cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23172cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 231897978a44SAndreas Fenkart } else { 231997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23202cd3a2a5SAndreas Fenkart } 23212cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2322fa4aa2d4SBalaji T K return 0; 2323fa4aa2d4SBalaji T K } 2324fa4aa2d4SBalaji T K 23256bba4064SArvind Yadav static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23263d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2327fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2328fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2329a791daa1SKevin Hilman }; 2330a791daa1SKevin Hilman 2331a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2332efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23330433c143SBill Pemberton .remove = omap_hsmmc_remove, 2334a45c6cb8SMadhusudhan Chikkature .driver = { 2335a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2336a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 233746856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2338a45c6cb8SMadhusudhan Chikkature }, 2339a45c6cb8SMadhusudhan Chikkature }; 2340a45c6cb8SMadhusudhan Chikkature 2341b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2342a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2343a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2344a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2345a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2346