1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20d900f712SDenis Karpov #include <linux/debugfs.h> 21d900f712SDenis Karpov #include <linux/seq_file.h> 22a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/workqueue.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3013189e78SJarkko Lavinen #include <linux/mmc/core.h> 3193caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 32a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 33a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 34db0fefc5SAdrian Hunter #include <linux/gpio.h> 35db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 36fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 37ce491cf8STony Lindgren #include <plat/dma.h> 38a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 39ce491cf8STony Lindgren #include <plat/board.h> 40ce491cf8STony Lindgren #include <plat/mmc.h> 41ce491cf8STony Lindgren #include <plat/cpu.h> 42a45c6cb8SMadhusudhan Chikkature 43a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 44a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 4511dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 46a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 61a45c6cb8SMadhusudhan Chikkature 62a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 63a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 64a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 65a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 66eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 671b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 68a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 69a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 70a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 71a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 72a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 73a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 74a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 75a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 76a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 77a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 78a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 79a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 80a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 81ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 82ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8393caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 84a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 85a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 86a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 87a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 88a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 89a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 90a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9173153010SJarkko Lavinen #define DW8 (1 << 5) 92a45c6cb8SMadhusudhan Chikkature #define CC 0x1 93a45c6cb8SMadhusudhan Chikkature #define TC 0x02 94a45c6cb8SMadhusudhan Chikkature #define OD 0x1 95a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 96a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 97a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 98a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 99a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 100a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 101a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 102a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 103a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 104a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 105a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10611dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10711dd62a7SDenis Karpov #define RESETDONE (1 << 0) 108a45c6cb8SMadhusudhan Chikkature 109a45c6cb8SMadhusudhan Chikkature /* 110a45c6cb8SMadhusudhan Chikkature * FIXME: Most likely all the data using these _DEVID defines should come 111a45c6cb8SMadhusudhan Chikkature * from the platform_data, or implemented in controller and slot specific 112a45c6cb8SMadhusudhan Chikkature * functions. 113a45c6cb8SMadhusudhan Chikkature */ 114a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC1_DEVID 0 115a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC2_DEVID 1 116f3e2f1ddSGrazvydas Ignotas #define OMAP_MMC3_DEVID 2 11782cf818dSkishore kadiyala #define OMAP_MMC4_DEVID 3 11882cf818dSkishore kadiyala #define OMAP_MMC5_DEVID 4 119a45c6cb8SMadhusudhan Chikkature 120fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 121a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 122a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_MASTER_CLOCK 96000000 1230005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 124a45c6cb8SMadhusudhan Chikkature 125a45c6cb8SMadhusudhan Chikkature /* 126a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 127a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 128a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 129a45c6cb8SMadhusudhan Chikkature */ 130a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 131a45c6cb8SMadhusudhan Chikkature 132a45c6cb8SMadhusudhan Chikkature /* 133a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 134a45c6cb8SMadhusudhan Chikkature */ 135a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 136a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 137a45c6cb8SMadhusudhan Chikkature 138a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 139a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 140a45c6cb8SMadhusudhan Chikkature 1419782aff8SPer Forlin struct omap_hsmmc_next { 1429782aff8SPer Forlin unsigned int dma_len; 1439782aff8SPer Forlin s32 cookie; 1449782aff8SPer Forlin }; 1459782aff8SPer Forlin 14670a3341aSDenis Karpov struct omap_hsmmc_host { 147a45c6cb8SMadhusudhan Chikkature struct device *dev; 148a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 149a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 150a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 151a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 152a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 153a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 154db0fefc5SAdrian Hunter /* 155db0fefc5SAdrian Hunter * vcc == configured supply 156db0fefc5SAdrian Hunter * vcc_aux == optional 157db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 158db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 159db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 160db0fefc5SAdrian Hunter */ 161db0fefc5SAdrian Hunter struct regulator *vcc; 162db0fefc5SAdrian Hunter struct regulator *vcc_aux; 163a45c6cb8SMadhusudhan Chikkature struct work_struct mmc_carddetect_work; 164a45c6cb8SMadhusudhan Chikkature void __iomem *base; 165a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1664dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 167a45c6cb8SMadhusudhan Chikkature unsigned int id; 168a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1690ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 170a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 171a3621465SAdrian Hunter unsigned char power_mode; 172a45c6cb8SMadhusudhan Chikkature u32 *buffer; 173a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 174a45c6cb8SMadhusudhan Chikkature int suspended; 175a45c6cb8SMadhusudhan Chikkature int irq; 176a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 177f3e2f1ddSGrazvydas Ignotas int dma_line_tx, dma_line_rx; 178a45c6cb8SMadhusudhan Chikkature int slot_id; 1792bec0893SAdrian Hunter int got_dbclk; 1804a694dc9SAdrian Hunter int response_busy; 18111dd62a7SDenis Karpov int context_loss; 182dd498effSDenis Karpov int dpm_state; 183623821f7SAdrian Hunter int vdd; 184b62f6228SAdrian Hunter int protect_card; 185b62f6228SAdrian Hunter int reqs_blocked; 186db0fefc5SAdrian Hunter int use_reg; 187b417577dSAdrian Hunter int req_in_progress; 1889782aff8SPer Forlin struct omap_hsmmc_next next_data; 18911dd62a7SDenis Karpov 190a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 191a45c6cb8SMadhusudhan Chikkature }; 192a45c6cb8SMadhusudhan Chikkature 193db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 194db0fefc5SAdrian Hunter { 195db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 196db0fefc5SAdrian Hunter 197db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 198db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 199db0fefc5SAdrian Hunter } 200db0fefc5SAdrian Hunter 201db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 202db0fefc5SAdrian Hunter { 203db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 204db0fefc5SAdrian Hunter 205db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 206db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 207db0fefc5SAdrian Hunter } 208db0fefc5SAdrian Hunter 209db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 210db0fefc5SAdrian Hunter { 211db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 212db0fefc5SAdrian Hunter 213db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 214db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 215db0fefc5SAdrian Hunter } 216db0fefc5SAdrian Hunter 217db0fefc5SAdrian Hunter #ifdef CONFIG_PM 218db0fefc5SAdrian Hunter 219db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 220db0fefc5SAdrian Hunter { 221db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 222db0fefc5SAdrian Hunter 223db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 224db0fefc5SAdrian Hunter return 0; 225db0fefc5SAdrian Hunter } 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 228db0fefc5SAdrian Hunter { 229db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 230db0fefc5SAdrian Hunter 231db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 232db0fefc5SAdrian Hunter return 0; 233db0fefc5SAdrian Hunter } 234db0fefc5SAdrian Hunter 235db0fefc5SAdrian Hunter #else 236db0fefc5SAdrian Hunter 237db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 238db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 239db0fefc5SAdrian Hunter 240db0fefc5SAdrian Hunter #endif 241db0fefc5SAdrian Hunter 242b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 243b702b106SAdrian Hunter 244db0fefc5SAdrian Hunter static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 245db0fefc5SAdrian Hunter int vdd) 246db0fefc5SAdrian Hunter { 247db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 248db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 249db0fefc5SAdrian Hunter int ret; 250db0fefc5SAdrian Hunter 251db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 252db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 253db0fefc5SAdrian Hunter 254db0fefc5SAdrian Hunter if (power_on) 25599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 256db0fefc5SAdrian Hunter else 25799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 258db0fefc5SAdrian Hunter 259db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 260db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 261db0fefc5SAdrian Hunter 262db0fefc5SAdrian Hunter return ret; 263db0fefc5SAdrian Hunter } 264db0fefc5SAdrian Hunter 2657715db5aSKishore Kadiyala static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, 266db0fefc5SAdrian Hunter int vdd) 267db0fefc5SAdrian Hunter { 268db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 269db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 270db0fefc5SAdrian Hunter int ret = 0; 271db0fefc5SAdrian Hunter 272db0fefc5SAdrian Hunter /* 273db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 274db0fefc5SAdrian Hunter * voltage always-on regulator. 275db0fefc5SAdrian Hunter */ 276db0fefc5SAdrian Hunter if (!host->vcc) 277db0fefc5SAdrian Hunter return 0; 278db0fefc5SAdrian Hunter 279db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 280db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 281db0fefc5SAdrian Hunter 282db0fefc5SAdrian Hunter /* 283db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 284db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 285db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 286db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 287db0fefc5SAdrian Hunter * 288db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 289db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 290db0fefc5SAdrian Hunter * 291db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 292db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 293db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 294db0fefc5SAdrian Hunter */ 295db0fefc5SAdrian Hunter if (power_on) { 29699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 297db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 298db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 299db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 300db0fefc5SAdrian Hunter if (ret < 0) 30199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30299fc5131SLinus Walleij host->vcc, 0); 303db0fefc5SAdrian Hunter } 304db0fefc5SAdrian Hunter } else { 30599fc5131SLinus Walleij /* Shut down the rail */ 3066da20c89SAdrian Hunter if (host->vcc_aux) 307db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 30899fc5131SLinus Walleij if (!ret) { 30999fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31199fc5131SLinus Walleij host->vcc, 0); 31299fc5131SLinus Walleij } 313db0fefc5SAdrian Hunter } 314db0fefc5SAdrian Hunter 315db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 316db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 317db0fefc5SAdrian Hunter 318db0fefc5SAdrian Hunter return ret; 319db0fefc5SAdrian Hunter } 320db0fefc5SAdrian Hunter 3217715db5aSKishore Kadiyala static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, 3227715db5aSKishore Kadiyala int vdd) 3237715db5aSKishore Kadiyala { 3247715db5aSKishore Kadiyala return 0; 3257715db5aSKishore Kadiyala } 3267715db5aSKishore Kadiyala 327db0fefc5SAdrian Hunter static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 328db0fefc5SAdrian Hunter int vdd, int cardsleep) 329db0fefc5SAdrian Hunter { 330db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 331db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 332db0fefc5SAdrian Hunter int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 333db0fefc5SAdrian Hunter 334db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc, mode); 335db0fefc5SAdrian Hunter } 336db0fefc5SAdrian Hunter 3377715db5aSKishore Kadiyala static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, 338db0fefc5SAdrian Hunter int vdd, int cardsleep) 339db0fefc5SAdrian Hunter { 340db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 341db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 342db0fefc5SAdrian Hunter int err, mode; 343db0fefc5SAdrian Hunter 344db0fefc5SAdrian Hunter /* 345db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 346db0fefc5SAdrian Hunter * voltage always-on regulator. 347db0fefc5SAdrian Hunter */ 348db0fefc5SAdrian Hunter if (!host->vcc) 349db0fefc5SAdrian Hunter return 0; 350db0fefc5SAdrian Hunter 351db0fefc5SAdrian Hunter mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 352db0fefc5SAdrian Hunter 353db0fefc5SAdrian Hunter if (!host->vcc_aux) 354db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc, mode); 355db0fefc5SAdrian Hunter 356db0fefc5SAdrian Hunter if (cardsleep) { 357db0fefc5SAdrian Hunter /* VCC can be turned off if card is asleep */ 358db0fefc5SAdrian Hunter if (sleep) 35999fc5131SLinus Walleij err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 360db0fefc5SAdrian Hunter else 36199fc5131SLinus Walleij err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 362db0fefc5SAdrian Hunter } else 363db0fefc5SAdrian Hunter err = regulator_set_mode(host->vcc, mode); 364db0fefc5SAdrian Hunter if (err) 365db0fefc5SAdrian Hunter return err; 366e0eb2424SAdrian Hunter 367e0eb2424SAdrian Hunter if (!mmc_slot(host).vcc_aux_disable_is_sleep) 368db0fefc5SAdrian Hunter return regulator_set_mode(host->vcc_aux, mode); 369e0eb2424SAdrian Hunter 370e0eb2424SAdrian Hunter if (sleep) 371e0eb2424SAdrian Hunter return regulator_disable(host->vcc_aux); 372e0eb2424SAdrian Hunter else 373e0eb2424SAdrian Hunter return regulator_enable(host->vcc_aux); 374db0fefc5SAdrian Hunter } 375db0fefc5SAdrian Hunter 3767715db5aSKishore Kadiyala static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, 3777715db5aSKishore Kadiyala int vdd, int cardsleep) 3787715db5aSKishore Kadiyala { 3797715db5aSKishore Kadiyala return 0; 3807715db5aSKishore Kadiyala } 3817715db5aSKishore Kadiyala 382db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 383db0fefc5SAdrian Hunter { 384db0fefc5SAdrian Hunter struct regulator *reg; 385db0fefc5SAdrian Hunter int ret = 0; 38664be9782Skishore kadiyala int ocr_value = 0; 387db0fefc5SAdrian Hunter 388db0fefc5SAdrian Hunter switch (host->id) { 389db0fefc5SAdrian Hunter case OMAP_MMC1_DEVID: 390db0fefc5SAdrian Hunter /* On-chip level shifting via PBIAS0/PBIAS1 */ 391db0fefc5SAdrian Hunter mmc_slot(host).set_power = omap_hsmmc_1_set_power; 392db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 393db0fefc5SAdrian Hunter break; 394db0fefc5SAdrian Hunter case OMAP_MMC2_DEVID: 395db0fefc5SAdrian Hunter case OMAP_MMC3_DEVID: 3967715db5aSKishore Kadiyala case OMAP_MMC5_DEVID: 397db0fefc5SAdrian Hunter /* Off-chip level shifting, or none */ 3987715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_235_set_power; 3997715db5aSKishore Kadiyala mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; 400db0fefc5SAdrian Hunter break; 4017715db5aSKishore Kadiyala case OMAP_MMC4_DEVID: 4027715db5aSKishore Kadiyala mmc_slot(host).set_power = omap_hsmmc_4_set_power; 4037715db5aSKishore Kadiyala mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; 404db0fefc5SAdrian Hunter default: 405db0fefc5SAdrian Hunter pr_err("MMC%d configuration not supported!\n", host->id); 406db0fefc5SAdrian Hunter return -EINVAL; 407db0fefc5SAdrian Hunter } 408db0fefc5SAdrian Hunter 409db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 410db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 411db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 412db0fefc5SAdrian Hunter /* 413db0fefc5SAdrian Hunter * HACK: until fixed.c regulator is usable, 414db0fefc5SAdrian Hunter * we don't require a main regulator 415db0fefc5SAdrian Hunter * for MMC2 or MMC3 416db0fefc5SAdrian Hunter */ 417db0fefc5SAdrian Hunter if (host->id == OMAP_MMC1_DEVID) { 418db0fefc5SAdrian Hunter ret = PTR_ERR(reg); 419db0fefc5SAdrian Hunter goto err; 420db0fefc5SAdrian Hunter } 421db0fefc5SAdrian Hunter } else { 422db0fefc5SAdrian Hunter host->vcc = reg; 42364be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 42464be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 42564be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 42664be9782Skishore kadiyala } else { 42764be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 42864be9782Skishore kadiyala pr_err("MMC%d ocrmask %x is not supported\n", 42964be9782Skishore kadiyala host->id, mmc_slot(host).ocr_mask); 43064be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 43164be9782Skishore kadiyala return -EINVAL; 43264be9782Skishore kadiyala } 43364be9782Skishore kadiyala } 434db0fefc5SAdrian Hunter 435db0fefc5SAdrian Hunter /* Allow an aux regulator */ 436db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 437db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 438db0fefc5SAdrian Hunter 439b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 440b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 441b1c1df7aSBalaji T K return 0; 442db0fefc5SAdrian Hunter /* 443db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 444db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 445db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 446db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 447db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 448db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 449db0fefc5SAdrian Hunter */ 450db0fefc5SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0) { 451db0fefc5SAdrian Hunter regulator_enable(host->vcc); 452db0fefc5SAdrian Hunter regulator_disable(host->vcc); 453db0fefc5SAdrian Hunter } 454db0fefc5SAdrian Hunter if (host->vcc_aux) { 455db0fefc5SAdrian Hunter if (regulator_is_enabled(reg) > 0) { 456db0fefc5SAdrian Hunter regulator_enable(reg); 457db0fefc5SAdrian Hunter regulator_disable(reg); 458db0fefc5SAdrian Hunter } 459db0fefc5SAdrian Hunter } 460db0fefc5SAdrian Hunter } 461db0fefc5SAdrian Hunter 462db0fefc5SAdrian Hunter return 0; 463db0fefc5SAdrian Hunter 464db0fefc5SAdrian Hunter err: 465db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 466db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = NULL; 467db0fefc5SAdrian Hunter return ret; 468db0fefc5SAdrian Hunter } 469db0fefc5SAdrian Hunter 470db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 471db0fefc5SAdrian Hunter { 472db0fefc5SAdrian Hunter regulator_put(host->vcc); 473db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 474db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 475db0fefc5SAdrian Hunter mmc_slot(host).set_sleep = NULL; 476db0fefc5SAdrian Hunter } 477db0fefc5SAdrian Hunter 478b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 479b702b106SAdrian Hunter { 480b702b106SAdrian Hunter return 1; 481b702b106SAdrian Hunter } 482b702b106SAdrian Hunter 483b702b106SAdrian Hunter #else 484b702b106SAdrian Hunter 485b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 486b702b106SAdrian Hunter { 487b702b106SAdrian Hunter return -EINVAL; 488b702b106SAdrian Hunter } 489b702b106SAdrian Hunter 490b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 491b702b106SAdrian Hunter { 492b702b106SAdrian Hunter } 493b702b106SAdrian Hunter 494b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 495b702b106SAdrian Hunter { 496b702b106SAdrian Hunter return 0; 497b702b106SAdrian Hunter } 498b702b106SAdrian Hunter 499b702b106SAdrian Hunter #endif 500b702b106SAdrian Hunter 501b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 502b702b106SAdrian Hunter { 503b702b106SAdrian Hunter int ret; 504b702b106SAdrian Hunter 505b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 506b702b106SAdrian Hunter if (pdata->slots[0].cover) 507b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 508b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 509b702b106SAdrian Hunter else 510b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 511b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 512b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 513b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 514b702b106SAdrian Hunter if (ret) 515b702b106SAdrian Hunter return ret; 516b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 517b702b106SAdrian Hunter if (ret) 518b702b106SAdrian Hunter goto err_free_sp; 519b702b106SAdrian Hunter } else 520b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 521b702b106SAdrian Hunter 522b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 523b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 524b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 525b702b106SAdrian Hunter if (ret) 526b702b106SAdrian Hunter goto err_free_cd; 527b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 528b702b106SAdrian Hunter if (ret) 529b702b106SAdrian Hunter goto err_free_wp; 530b702b106SAdrian Hunter } else 531b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 532b702b106SAdrian Hunter 533b702b106SAdrian Hunter return 0; 534b702b106SAdrian Hunter 535b702b106SAdrian Hunter err_free_wp: 536b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 537b702b106SAdrian Hunter err_free_cd: 538b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 539b702b106SAdrian Hunter err_free_sp: 540b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 541b702b106SAdrian Hunter return ret; 542b702b106SAdrian Hunter } 543b702b106SAdrian Hunter 544b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 545b702b106SAdrian Hunter { 546b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 547b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 548b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 549b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 550b702b106SAdrian Hunter } 551b702b106SAdrian Hunter 552a45c6cb8SMadhusudhan Chikkature /* 553a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 554a45c6cb8SMadhusudhan Chikkature */ 55570a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 556a45c6cb8SMadhusudhan Chikkature { 557a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 558a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 559a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 560a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 561a45c6cb8SMadhusudhan Chikkature } 562a45c6cb8SMadhusudhan Chikkature 56393caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 56493caf8e6SAdrian Hunter struct mmc_command *cmd) 565b417577dSAdrian Hunter { 566b417577dSAdrian Hunter unsigned int irq_mask; 567b417577dSAdrian Hunter 568b417577dSAdrian Hunter if (host->use_dma) 569b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 570b417577dSAdrian Hunter else 571b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 572b417577dSAdrian Hunter 57393caf8e6SAdrian Hunter /* Disable timeout for erases */ 57493caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 57593caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 57693caf8e6SAdrian Hunter 577b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 578b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 579b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 580b417577dSAdrian Hunter } 581b417577dSAdrian Hunter 582b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 583b417577dSAdrian Hunter { 584b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 585b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 586b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 587b417577dSAdrian Hunter } 588b417577dSAdrian Hunter 58911dd62a7SDenis Karpov #ifdef CONFIG_PM 59011dd62a7SDenis Karpov 59111dd62a7SDenis Karpov /* 59211dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 59311dd62a7SDenis Karpov * power state change. 59411dd62a7SDenis Karpov */ 59570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 59611dd62a7SDenis Karpov { 59711dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 59811dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 59911dd62a7SDenis Karpov int context_loss = 0; 60011dd62a7SDenis Karpov u32 hctl, capa, con; 60111dd62a7SDenis Karpov u16 dsor = 0; 60211dd62a7SDenis Karpov unsigned long timeout; 60311dd62a7SDenis Karpov 60411dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 60511dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 60611dd62a7SDenis Karpov if (context_loss < 0) 60711dd62a7SDenis Karpov return 1; 60811dd62a7SDenis Karpov } 60911dd62a7SDenis Karpov 61011dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 61111dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 61211dd62a7SDenis Karpov if (host->context_loss == context_loss) 61311dd62a7SDenis Karpov return 1; 61411dd62a7SDenis Karpov 61511dd62a7SDenis Karpov /* Wait for hardware reset */ 61611dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 61711dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 61811dd62a7SDenis Karpov && time_before(jiffies, timeout)) 61911dd62a7SDenis Karpov ; 62011dd62a7SDenis Karpov 62111dd62a7SDenis Karpov /* Do software reset */ 62211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 62311dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 62411dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 62511dd62a7SDenis Karpov && time_before(jiffies, timeout)) 62611dd62a7SDenis Karpov ; 62711dd62a7SDenis Karpov 62811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 62911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 63011dd62a7SDenis Karpov 63111dd62a7SDenis Karpov if (host->id == OMAP_MMC1_DEVID) { 63211dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 63311dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 63411dd62a7SDenis Karpov hctl = SDVS18; 63511dd62a7SDenis Karpov else 63611dd62a7SDenis Karpov hctl = SDVS30; 63711dd62a7SDenis Karpov capa = VS30 | VS18; 63811dd62a7SDenis Karpov } else { 63911dd62a7SDenis Karpov hctl = SDVS18; 64011dd62a7SDenis Karpov capa = VS18; 64111dd62a7SDenis Karpov } 64211dd62a7SDenis Karpov 64311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 64411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 64511dd62a7SDenis Karpov 64611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 64711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 64811dd62a7SDenis Karpov 64911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 65011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 65111dd62a7SDenis Karpov 65211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 65311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 65411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 65511dd62a7SDenis Karpov ; 65611dd62a7SDenis Karpov 657b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 65811dd62a7SDenis Karpov 65911dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 66011dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 66111dd62a7SDenis Karpov goto out; 66211dd62a7SDenis Karpov 66311dd62a7SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 66411dd62a7SDenis Karpov switch (ios->bus_width) { 66511dd62a7SDenis Karpov case MMC_BUS_WIDTH_8: 66611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 66711dd62a7SDenis Karpov break; 66811dd62a7SDenis Karpov case MMC_BUS_WIDTH_4: 66911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 67011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 67211dd62a7SDenis Karpov break; 67311dd62a7SDenis Karpov case MMC_BUS_WIDTH_1: 67411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 67511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 67711dd62a7SDenis Karpov break; 67811dd62a7SDenis Karpov } 67911dd62a7SDenis Karpov 68011dd62a7SDenis Karpov if (ios->clock) { 68111dd62a7SDenis Karpov dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 68211dd62a7SDenis Karpov if (dsor < 1) 68311dd62a7SDenis Karpov dsor = 1; 68411dd62a7SDenis Karpov 68511dd62a7SDenis Karpov if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 68611dd62a7SDenis Karpov dsor++; 68711dd62a7SDenis Karpov 68811dd62a7SDenis Karpov if (dsor > 250) 68911dd62a7SDenis Karpov dsor = 250; 69011dd62a7SDenis Karpov } 69111dd62a7SDenis Karpov 69211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 69311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 69411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 69511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 69611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 69711dd62a7SDenis Karpov 69811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 69911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 70011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 70111dd62a7SDenis Karpov ; 70211dd62a7SDenis Karpov 70311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, SYSCTL, 70411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 70511dd62a7SDenis Karpov 70611dd62a7SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 70711dd62a7SDenis Karpov if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 70811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | OD); 70911dd62a7SDenis Karpov else 71011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 71111dd62a7SDenis Karpov out: 71211dd62a7SDenis Karpov host->context_loss = context_loss; 71311dd62a7SDenis Karpov 71411dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 71511dd62a7SDenis Karpov return 0; 71611dd62a7SDenis Karpov } 71711dd62a7SDenis Karpov 71811dd62a7SDenis Karpov /* 71911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 72011dd62a7SDenis Karpov */ 72170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 72211dd62a7SDenis Karpov { 72311dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 72411dd62a7SDenis Karpov int context_loss; 72511dd62a7SDenis Karpov 72611dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 72711dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 72811dd62a7SDenis Karpov if (context_loss < 0) 72911dd62a7SDenis Karpov return; 73011dd62a7SDenis Karpov host->context_loss = context_loss; 73111dd62a7SDenis Karpov } 73211dd62a7SDenis Karpov } 73311dd62a7SDenis Karpov 73411dd62a7SDenis Karpov #else 73511dd62a7SDenis Karpov 73670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 73711dd62a7SDenis Karpov { 73811dd62a7SDenis Karpov return 0; 73911dd62a7SDenis Karpov } 74011dd62a7SDenis Karpov 74170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 74211dd62a7SDenis Karpov { 74311dd62a7SDenis Karpov } 74411dd62a7SDenis Karpov 74511dd62a7SDenis Karpov #endif 74611dd62a7SDenis Karpov 747a45c6cb8SMadhusudhan Chikkature /* 748a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 749a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 750a45c6cb8SMadhusudhan Chikkature */ 75170a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 752a45c6cb8SMadhusudhan Chikkature { 753a45c6cb8SMadhusudhan Chikkature int reg = 0; 754a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 755a45c6cb8SMadhusudhan Chikkature 756b62f6228SAdrian Hunter if (host->protect_card) 757b62f6228SAdrian Hunter return; 758b62f6228SAdrian Hunter 759a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 760b417577dSAdrian Hunter 761b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 762a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 763a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 764a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 765a45c6cb8SMadhusudhan Chikkature 766a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 767a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 768a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 769a45c6cb8SMadhusudhan Chikkature 770a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 771a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 772c653a6d4SAdrian Hunter 773c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 774c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 775c653a6d4SAdrian Hunter 776a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 777a45c6cb8SMadhusudhan Chikkature } 778a45c6cb8SMadhusudhan Chikkature 779a45c6cb8SMadhusudhan Chikkature static inline 78070a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 781a45c6cb8SMadhusudhan Chikkature { 782a45c6cb8SMadhusudhan Chikkature int r = 1; 783a45c6cb8SMadhusudhan Chikkature 784191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 785191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 786a45c6cb8SMadhusudhan Chikkature return r; 787a45c6cb8SMadhusudhan Chikkature } 788a45c6cb8SMadhusudhan Chikkature 789a45c6cb8SMadhusudhan Chikkature static ssize_t 79070a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 791a45c6cb8SMadhusudhan Chikkature char *buf) 792a45c6cb8SMadhusudhan Chikkature { 793a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 79470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 795a45c6cb8SMadhusudhan Chikkature 79670a3341aSDenis Karpov return sprintf(buf, "%s\n", 79770a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 798a45c6cb8SMadhusudhan Chikkature } 799a45c6cb8SMadhusudhan Chikkature 80070a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 801a45c6cb8SMadhusudhan Chikkature 802a45c6cb8SMadhusudhan Chikkature static ssize_t 80370a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 804a45c6cb8SMadhusudhan Chikkature char *buf) 805a45c6cb8SMadhusudhan Chikkature { 806a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 80770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 808a45c6cb8SMadhusudhan Chikkature 809191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 810a45c6cb8SMadhusudhan Chikkature } 811a45c6cb8SMadhusudhan Chikkature 81270a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 813a45c6cb8SMadhusudhan Chikkature 814a45c6cb8SMadhusudhan Chikkature /* 815a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 816a45c6cb8SMadhusudhan Chikkature */ 817a45c6cb8SMadhusudhan Chikkature static void 81870a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 819a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 820a45c6cb8SMadhusudhan Chikkature { 821a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 822a45c6cb8SMadhusudhan Chikkature 823a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 824a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 825a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 826a45c6cb8SMadhusudhan Chikkature 82793caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 828a45c6cb8SMadhusudhan Chikkature 8294a694dc9SAdrian Hunter host->response_busy = 0; 830a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 831a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 832a45c6cb8SMadhusudhan Chikkature resptype = 1; 8334a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8344a694dc9SAdrian Hunter resptype = 3; 8354a694dc9SAdrian Hunter host->response_busy = 1; 8364a694dc9SAdrian Hunter } else 837a45c6cb8SMadhusudhan Chikkature resptype = 2; 838a45c6cb8SMadhusudhan Chikkature } 839a45c6cb8SMadhusudhan Chikkature 840a45c6cb8SMadhusudhan Chikkature /* 841a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 842a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 843a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 844a45c6cb8SMadhusudhan Chikkature */ 845a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 846a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 847a45c6cb8SMadhusudhan Chikkature 848a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 849a45c6cb8SMadhusudhan Chikkature 850a45c6cb8SMadhusudhan Chikkature if (data) { 851a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 852a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 853a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 854a45c6cb8SMadhusudhan Chikkature else 855a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 856a45c6cb8SMadhusudhan Chikkature } 857a45c6cb8SMadhusudhan Chikkature 858a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 859a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 860a45c6cb8SMadhusudhan Chikkature 861b417577dSAdrian Hunter host->req_in_progress = 1; 8624dffd7a2SAdrian Hunter 863a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 864a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 865a45c6cb8SMadhusudhan Chikkature } 866a45c6cb8SMadhusudhan Chikkature 8670ccd76d4SJuha Yrjola static int 86870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8690ccd76d4SJuha Yrjola { 8700ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8710ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8720ccd76d4SJuha Yrjola else 8730ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8740ccd76d4SJuha Yrjola } 8750ccd76d4SJuha Yrjola 876b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 877b417577dSAdrian Hunter { 878b417577dSAdrian Hunter int dma_ch; 879b417577dSAdrian Hunter 880b417577dSAdrian Hunter spin_lock(&host->irq_lock); 881b417577dSAdrian Hunter host->req_in_progress = 0; 882b417577dSAdrian Hunter dma_ch = host->dma_ch; 883b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 884b417577dSAdrian Hunter 885b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 886b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 887b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 888b417577dSAdrian Hunter return; 889b417577dSAdrian Hunter host->mrq = NULL; 890b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 891b417577dSAdrian Hunter } 892b417577dSAdrian Hunter 893a45c6cb8SMadhusudhan Chikkature /* 894a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 895a45c6cb8SMadhusudhan Chikkature */ 896a45c6cb8SMadhusudhan Chikkature static void 89770a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 898a45c6cb8SMadhusudhan Chikkature { 8994a694dc9SAdrian Hunter if (!data) { 9004a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9014a694dc9SAdrian Hunter 90223050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 90323050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 90423050103SAdrian Hunter host->response_busy) { 90523050103SAdrian Hunter host->response_busy = 0; 90623050103SAdrian Hunter return; 90723050103SAdrian Hunter } 90823050103SAdrian Hunter 909b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9104a694dc9SAdrian Hunter return; 9114a694dc9SAdrian Hunter } 9124a694dc9SAdrian Hunter 913a45c6cb8SMadhusudhan Chikkature host->data = NULL; 914a45c6cb8SMadhusudhan Chikkature 915a45c6cb8SMadhusudhan Chikkature if (!data->error) 916a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 917a45c6cb8SMadhusudhan Chikkature else 918a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 919a45c6cb8SMadhusudhan Chikkature 920a45c6cb8SMadhusudhan Chikkature if (!data->stop) { 921b417577dSAdrian Hunter omap_hsmmc_request_done(host, data->mrq); 922a45c6cb8SMadhusudhan Chikkature return; 923a45c6cb8SMadhusudhan Chikkature } 92470a3341aSDenis Karpov omap_hsmmc_start_command(host, data->stop, NULL); 925a45c6cb8SMadhusudhan Chikkature } 926a45c6cb8SMadhusudhan Chikkature 927a45c6cb8SMadhusudhan Chikkature /* 928a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 929a45c6cb8SMadhusudhan Chikkature */ 930a45c6cb8SMadhusudhan Chikkature static void 93170a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 932a45c6cb8SMadhusudhan Chikkature { 933a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 934a45c6cb8SMadhusudhan Chikkature 935a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 936a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 937a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 938a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 939a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 940a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 941a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 942a45c6cb8SMadhusudhan Chikkature } else { 943a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 944a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 945a45c6cb8SMadhusudhan Chikkature } 946a45c6cb8SMadhusudhan Chikkature } 947b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 948b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 949a45c6cb8SMadhusudhan Chikkature } 950a45c6cb8SMadhusudhan Chikkature 951a45c6cb8SMadhusudhan Chikkature /* 952a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 953a45c6cb8SMadhusudhan Chikkature */ 95470a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 955a45c6cb8SMadhusudhan Chikkature { 956b417577dSAdrian Hunter int dma_ch; 957b417577dSAdrian Hunter 95882788ff5SJarkko Lavinen host->data->error = errno; 959a45c6cb8SMadhusudhan Chikkature 960b417577dSAdrian Hunter spin_lock(&host->irq_lock); 961b417577dSAdrian Hunter dma_ch = host->dma_ch; 962b417577dSAdrian Hunter host->dma_ch = -1; 963b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 964b417577dSAdrian Hunter 965b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 966a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, 967a9120c33SPer Forlin host->data->sg_len, 96870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 969b417577dSAdrian Hunter omap_free_dma(dma_ch); 970a45c6cb8SMadhusudhan Chikkature } 971a45c6cb8SMadhusudhan Chikkature host->data = NULL; 972a45c6cb8SMadhusudhan Chikkature } 973a45c6cb8SMadhusudhan Chikkature 974a45c6cb8SMadhusudhan Chikkature /* 975a45c6cb8SMadhusudhan Chikkature * Readable error output 976a45c6cb8SMadhusudhan Chikkature */ 977a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 978699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 979a45c6cb8SMadhusudhan Chikkature { 980a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 98170a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 982699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 983699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 984699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 985699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 986a45c6cb8SMadhusudhan Chikkature }; 987a45c6cb8SMadhusudhan Chikkature char res[256]; 988a45c6cb8SMadhusudhan Chikkature char *buf = res; 989a45c6cb8SMadhusudhan Chikkature int len, i; 990a45c6cb8SMadhusudhan Chikkature 991a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 992a45c6cb8SMadhusudhan Chikkature buf += len; 993a45c6cb8SMadhusudhan Chikkature 99470a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 995a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 99670a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 997a45c6cb8SMadhusudhan Chikkature buf += len; 998a45c6cb8SMadhusudhan Chikkature } 999a45c6cb8SMadhusudhan Chikkature 1000a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 1001a45c6cb8SMadhusudhan Chikkature } 1002699b958bSAdrian Hunter #else 1003699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1004699b958bSAdrian Hunter u32 status) 1005699b958bSAdrian Hunter { 1006699b958bSAdrian Hunter } 1007a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1008a45c6cb8SMadhusudhan Chikkature 10093ebf74b1SJean Pihet /* 10103ebf74b1SJean Pihet * MMC controller internal state machines reset 10113ebf74b1SJean Pihet * 10123ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10133ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10143ebf74b1SJean Pihet * Can be called from interrupt context 10153ebf74b1SJean Pihet */ 101670a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10173ebf74b1SJean Pihet unsigned long bit) 10183ebf74b1SJean Pihet { 10193ebf74b1SJean Pihet unsigned long i = 0; 10203ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 10213ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 10223ebf74b1SJean Pihet 10233ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10243ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10253ebf74b1SJean Pihet 102607ad64b6SMadhusudhan Chikkature /* 102707ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 102807ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 102907ad64b6SMadhusudhan Chikkature */ 103007ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1031b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 103207ad64b6SMadhusudhan Chikkature && (i++ < limit)) 103307ad64b6SMadhusudhan Chikkature cpu_relax(); 103407ad64b6SMadhusudhan Chikkature } 103507ad64b6SMadhusudhan Chikkature i = 0; 103607ad64b6SMadhusudhan Chikkature 10373ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10383ebf74b1SJean Pihet (i++ < limit)) 10393ebf74b1SJean Pihet cpu_relax(); 10403ebf74b1SJean Pihet 10413ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10423ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10433ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10443ebf74b1SJean Pihet __func__); 10453ebf74b1SJean Pihet } 1046a45c6cb8SMadhusudhan Chikkature 1047b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1048a45c6cb8SMadhusudhan Chikkature { 1049a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1050b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1051a45c6cb8SMadhusudhan Chikkature 1052b417577dSAdrian Hunter if (!host->req_in_progress) { 1053b417577dSAdrian Hunter do { 1054b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, status); 105500adadc1SKevin Hilman /* Flush posted write */ 1056b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1057b417577dSAdrian Hunter } while (status & INT_EN_MASK); 1058b417577dSAdrian Hunter return; 1059a45c6cb8SMadhusudhan Chikkature } 1060a45c6cb8SMadhusudhan Chikkature 1061a45c6cb8SMadhusudhan Chikkature data = host->data; 1062a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1063a45c6cb8SMadhusudhan Chikkature 1064a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 1065699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 1066a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 1067a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 1068a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 1069a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 107070a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 1071191d1f1dSDenis Karpov SRC); 1072a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 1073a45c6cb8SMadhusudhan Chikkature } else { 1074a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 1075a45c6cb8SMadhusudhan Chikkature } 1076a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1077a45c6cb8SMadhusudhan Chikkature } 10784a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10794a694dc9SAdrian Hunter if (host->data) 108070a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 108170a3341aSDenis Karpov -ETIMEDOUT); 10824a694dc9SAdrian Hunter host->response_busy = 0; 108370a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1084c232f457SJean Pihet } 1085a45c6cb8SMadhusudhan Chikkature } 1086a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 1087a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 10884a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10894a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 10904a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 10914a694dc9SAdrian Hunter 10924a694dc9SAdrian Hunter if (host->data) 109370a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 1094a45c6cb8SMadhusudhan Chikkature else 10954a694dc9SAdrian Hunter host->mrq->cmd->error = err; 10964a694dc9SAdrian Hunter host->response_busy = 0; 109770a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1098a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1099a45c6cb8SMadhusudhan Chikkature } 1100a45c6cb8SMadhusudhan Chikkature } 1101a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 1102a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1103a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 1104a45c6cb8SMadhusudhan Chikkature if (host->cmd) 1105a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1106a45c6cb8SMadhusudhan Chikkature if (host->data) 1107a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1108a45c6cb8SMadhusudhan Chikkature } 1109a45c6cb8SMadhusudhan Chikkature } 1110a45c6cb8SMadhusudhan Chikkature 1111a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 1112a45c6cb8SMadhusudhan Chikkature 1113a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 111470a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 11150a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 111670a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1117b417577dSAdrian Hunter } 1118a45c6cb8SMadhusudhan Chikkature 1119b417577dSAdrian Hunter /* 1120b417577dSAdrian Hunter * MMC controller IRQ handler 1121b417577dSAdrian Hunter */ 1122b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1123b417577dSAdrian Hunter { 1124b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1125b417577dSAdrian Hunter int status; 1126b417577dSAdrian Hunter 1127b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1128b417577dSAdrian Hunter do { 1129b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 1130b417577dSAdrian Hunter /* Flush posted write */ 1131b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 1132b417577dSAdrian Hunter } while (status & INT_EN_MASK); 11334dffd7a2SAdrian Hunter 1134a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1135a45c6cb8SMadhusudhan Chikkature } 1136a45c6cb8SMadhusudhan Chikkature 113770a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1138e13bb300SAdrian Hunter { 1139e13bb300SAdrian Hunter unsigned long i; 1140e13bb300SAdrian Hunter 1141e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1142e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1143e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1144e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1145e13bb300SAdrian Hunter break; 1146e13bb300SAdrian Hunter cpu_relax(); 1147e13bb300SAdrian Hunter } 1148e13bb300SAdrian Hunter } 1149e13bb300SAdrian Hunter 1150a45c6cb8SMadhusudhan Chikkature /* 1151eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1152eb250826SDavid Brownell * 1153eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1154eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1155eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1156a45c6cb8SMadhusudhan Chikkature */ 115770a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1158a45c6cb8SMadhusudhan Chikkature { 1159a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1160a45c6cb8SMadhusudhan Chikkature int ret; 1161a45c6cb8SMadhusudhan Chikkature 1162a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1163fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 11642bec0893SAdrian Hunter if (host->got_dbclk) 1165a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1166a45c6cb8SMadhusudhan Chikkature 1167a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1168a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1169a45c6cb8SMadhusudhan Chikkature 1170a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11712bec0893SAdrian Hunter if (!ret) 11722bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11732bec0893SAdrian Hunter vdd); 1174fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 11752bec0893SAdrian Hunter if (host->got_dbclk) 11762bec0893SAdrian Hunter clk_enable(host->dbclk); 11772bec0893SAdrian Hunter 1178a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1179a45c6cb8SMadhusudhan Chikkature goto err; 1180a45c6cb8SMadhusudhan Chikkature 1181a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1182a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1183a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1184eb250826SDavid Brownell 1185a45c6cb8SMadhusudhan Chikkature /* 1186a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1187a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 118870a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1189a45c6cb8SMadhusudhan Chikkature * 1190eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1191eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1192eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1193eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1194eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1195eb250826SDavid Brownell * 1196eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1197eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1198eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1199a45c6cb8SMadhusudhan Chikkature */ 1200eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1201a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1202eb250826SDavid Brownell else 1203eb250826SDavid Brownell reg_val |= SDVS30; 1204a45c6cb8SMadhusudhan Chikkature 1205a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1206e13bb300SAdrian Hunter set_sd_bus_power(host); 1207a45c6cb8SMadhusudhan Chikkature 1208a45c6cb8SMadhusudhan Chikkature return 0; 1209a45c6cb8SMadhusudhan Chikkature err: 1210a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1211a45c6cb8SMadhusudhan Chikkature return ret; 1212a45c6cb8SMadhusudhan Chikkature } 1213a45c6cb8SMadhusudhan Chikkature 1214b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1215b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1216b62f6228SAdrian Hunter { 1217b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1218b62f6228SAdrian Hunter return; 1219b62f6228SAdrian Hunter 1220b62f6228SAdrian Hunter host->reqs_blocked = 0; 1221b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1222b62f6228SAdrian Hunter if (host->protect_card) { 1223b62f6228SAdrian Hunter printk(KERN_INFO "%s: cover is closed, " 1224b62f6228SAdrian Hunter "card is now accessible\n", 1225b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1226b62f6228SAdrian Hunter host->protect_card = 0; 1227b62f6228SAdrian Hunter } 1228b62f6228SAdrian Hunter } else { 1229b62f6228SAdrian Hunter if (!host->protect_card) { 1230b62f6228SAdrian Hunter printk(KERN_INFO "%s: cover is open, " 1231b62f6228SAdrian Hunter "card is now inaccessible\n", 1232b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1233b62f6228SAdrian Hunter host->protect_card = 1; 1234b62f6228SAdrian Hunter } 1235b62f6228SAdrian Hunter } 1236b62f6228SAdrian Hunter } 1237b62f6228SAdrian Hunter 1238a45c6cb8SMadhusudhan Chikkature /* 1239a45c6cb8SMadhusudhan Chikkature * Work Item to notify the core about card insertion/removal 1240a45c6cb8SMadhusudhan Chikkature */ 124170a3341aSDenis Karpov static void omap_hsmmc_detect(struct work_struct *work) 1242a45c6cb8SMadhusudhan Chikkature { 124370a3341aSDenis Karpov struct omap_hsmmc_host *host = 124470a3341aSDenis Karpov container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1245249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1246a6b2240dSAdrian Hunter int carddetect; 1247249d0fa9SDavid Brownell 1248a6b2240dSAdrian Hunter if (host->suspended) 1249a6b2240dSAdrian Hunter return; 1250a45c6cb8SMadhusudhan Chikkature 1251a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1252a6b2240dSAdrian Hunter 1253191d1f1dSDenis Karpov if (slot->card_detect) 1254db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1255b62f6228SAdrian Hunter else { 1256b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1257a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1258b62f6228SAdrian Hunter } 1259a6b2240dSAdrian Hunter 1260cdeebaddSMadhusudhan Chikkature if (carddetect) 1261a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1262cdeebaddSMadhusudhan Chikkature else 1263a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1264a45c6cb8SMadhusudhan Chikkature } 1265a45c6cb8SMadhusudhan Chikkature 1266a45c6cb8SMadhusudhan Chikkature /* 1267a45c6cb8SMadhusudhan Chikkature * ISR for handling card insertion and removal 1268a45c6cb8SMadhusudhan Chikkature */ 126970a3341aSDenis Karpov static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1270a45c6cb8SMadhusudhan Chikkature { 127170a3341aSDenis Karpov struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1272a45c6cb8SMadhusudhan Chikkature 1273a6b2240dSAdrian Hunter if (host->suspended) 1274a6b2240dSAdrian Hunter return IRQ_HANDLED; 1275a45c6cb8SMadhusudhan Chikkature schedule_work(&host->mmc_carddetect_work); 1276a45c6cb8SMadhusudhan Chikkature 1277a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1278a45c6cb8SMadhusudhan Chikkature } 1279a45c6cb8SMadhusudhan Chikkature 128070a3341aSDenis Karpov static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 12810ccd76d4SJuha Yrjola struct mmc_data *data) 12820ccd76d4SJuha Yrjola { 12830ccd76d4SJuha Yrjola int sync_dev; 12840ccd76d4SJuha Yrjola 1285f3e2f1ddSGrazvydas Ignotas if (data->flags & MMC_DATA_WRITE) 1286f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_tx; 12870ccd76d4SJuha Yrjola else 1288f3e2f1ddSGrazvydas Ignotas sync_dev = host->dma_line_rx; 12890ccd76d4SJuha Yrjola return sync_dev; 12900ccd76d4SJuha Yrjola } 12910ccd76d4SJuha Yrjola 129270a3341aSDenis Karpov static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 12930ccd76d4SJuha Yrjola struct mmc_data *data, 12940ccd76d4SJuha Yrjola struct scatterlist *sgl) 12950ccd76d4SJuha Yrjola { 12960ccd76d4SJuha Yrjola int blksz, nblk, dma_ch; 12970ccd76d4SJuha Yrjola 12980ccd76d4SJuha Yrjola dma_ch = host->dma_ch; 12990ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) { 13000ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 13010ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 13020ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 13030ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 13040ccd76d4SJuha Yrjola } else { 13050ccd76d4SJuha Yrjola omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 13060ccd76d4SJuha Yrjola (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 13070ccd76d4SJuha Yrjola omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 13080ccd76d4SJuha Yrjola sg_dma_address(sgl), 0, 0); 13090ccd76d4SJuha Yrjola } 13100ccd76d4SJuha Yrjola 13110ccd76d4SJuha Yrjola blksz = host->data->blksz; 13120ccd76d4SJuha Yrjola nblk = sg_dma_len(sgl) / blksz; 13130ccd76d4SJuha Yrjola 13140ccd76d4SJuha Yrjola omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 13150ccd76d4SJuha Yrjola blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 131670a3341aSDenis Karpov omap_hsmmc_get_dma_sync_dev(host, data), 13170ccd76d4SJuha Yrjola !(data->flags & MMC_DATA_WRITE)); 13180ccd76d4SJuha Yrjola 13190ccd76d4SJuha Yrjola omap_start_dma(dma_ch); 13200ccd76d4SJuha Yrjola } 13210ccd76d4SJuha Yrjola 1322a45c6cb8SMadhusudhan Chikkature /* 1323a45c6cb8SMadhusudhan Chikkature * DMA call back function 1324a45c6cb8SMadhusudhan Chikkature */ 1325b417577dSAdrian Hunter static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1326a45c6cb8SMadhusudhan Chikkature { 1327b417577dSAdrian Hunter struct omap_hsmmc_host *host = cb_data; 1328b417577dSAdrian Hunter struct mmc_data *data = host->mrq->data; 1329b417577dSAdrian Hunter int dma_ch, req_in_progress; 1330a45c6cb8SMadhusudhan Chikkature 1331f3584e5eSVenkatraman S if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1332f3584e5eSVenkatraman S dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1333f3584e5eSVenkatraman S ch_status); 1334f3584e5eSVenkatraman S return; 1335f3584e5eSVenkatraman S } 1336a45c6cb8SMadhusudhan Chikkature 1337b417577dSAdrian Hunter spin_lock(&host->irq_lock); 1338b417577dSAdrian Hunter if (host->dma_ch < 0) { 1339b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1340a45c6cb8SMadhusudhan Chikkature return; 1341b417577dSAdrian Hunter } 1342a45c6cb8SMadhusudhan Chikkature 13430ccd76d4SJuha Yrjola host->dma_sg_idx++; 13440ccd76d4SJuha Yrjola if (host->dma_sg_idx < host->dma_len) { 13450ccd76d4SJuha Yrjola /* Fire up the next transfer. */ 1346b417577dSAdrian Hunter omap_hsmmc_config_dma_params(host, data, 1347b417577dSAdrian Hunter data->sg + host->dma_sg_idx); 1348b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 13490ccd76d4SJuha Yrjola return; 13500ccd76d4SJuha Yrjola } 13510ccd76d4SJuha Yrjola 13529782aff8SPer Forlin if (!data->host_cookie) 1353a9120c33SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1354b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1355b417577dSAdrian Hunter 1356b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1357b417577dSAdrian Hunter dma_ch = host->dma_ch; 1358a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1359b417577dSAdrian Hunter spin_unlock(&host->irq_lock); 1360b417577dSAdrian Hunter 1361b417577dSAdrian Hunter omap_free_dma(dma_ch); 1362b417577dSAdrian Hunter 1363b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1364b417577dSAdrian Hunter if (!req_in_progress) { 1365b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1366b417577dSAdrian Hunter 1367b417577dSAdrian Hunter host->mrq = NULL; 1368b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1369b417577dSAdrian Hunter } 1370a45c6cb8SMadhusudhan Chikkature } 1371a45c6cb8SMadhusudhan Chikkature 13729782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13739782aff8SPer Forlin struct mmc_data *data, 13749782aff8SPer Forlin struct omap_hsmmc_next *next) 13759782aff8SPer Forlin { 13769782aff8SPer Forlin int dma_len; 13779782aff8SPer Forlin 13789782aff8SPer Forlin if (!next && data->host_cookie && 13799782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13809782aff8SPer Forlin printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d" 13819782aff8SPer Forlin " host->next_data.cookie %d\n", 13829782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13839782aff8SPer Forlin data->host_cookie = 0; 13849782aff8SPer Forlin } 13859782aff8SPer Forlin 13869782aff8SPer Forlin /* Check if next job is already prepared */ 13879782aff8SPer Forlin if (next || 13889782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 13899782aff8SPer Forlin dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 13909782aff8SPer Forlin data->sg_len, 13919782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13929782aff8SPer Forlin 13939782aff8SPer Forlin } else { 13949782aff8SPer Forlin dma_len = host->next_data.dma_len; 13959782aff8SPer Forlin host->next_data.dma_len = 0; 13969782aff8SPer Forlin } 13979782aff8SPer Forlin 13989782aff8SPer Forlin 13999782aff8SPer Forlin if (dma_len == 0) 14009782aff8SPer Forlin return -EINVAL; 14019782aff8SPer Forlin 14029782aff8SPer Forlin if (next) { 14039782aff8SPer Forlin next->dma_len = dma_len; 14049782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 14059782aff8SPer Forlin } else 14069782aff8SPer Forlin host->dma_len = dma_len; 14079782aff8SPer Forlin 14089782aff8SPer Forlin return 0; 14099782aff8SPer Forlin } 14109782aff8SPer Forlin 1411a45c6cb8SMadhusudhan Chikkature /* 1412a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1413a45c6cb8SMadhusudhan Chikkature */ 141470a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 141570a3341aSDenis Karpov struct mmc_request *req) 1416a45c6cb8SMadhusudhan Chikkature { 1417b417577dSAdrian Hunter int dma_ch = 0, ret = 0, i; 1418a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1419a45c6cb8SMadhusudhan Chikkature 14200ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1421a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14220ccd76d4SJuha Yrjola struct scatterlist *sgl; 14230ccd76d4SJuha Yrjola 14240ccd76d4SJuha Yrjola sgl = data->sg + i; 14250ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14260ccd76d4SJuha Yrjola return -EINVAL; 14270ccd76d4SJuha Yrjola } 14280ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14290ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14300ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14310ccd76d4SJuha Yrjola */ 14320ccd76d4SJuha Yrjola return -EINVAL; 14330ccd76d4SJuha Yrjola 1434b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1435a45c6cb8SMadhusudhan Chikkature 143670a3341aSDenis Karpov ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 143770a3341aSDenis Karpov "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1438a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 14390ccd76d4SJuha Yrjola dev_err(mmc_dev(host->mmc), 1440a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 1441a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 1442a45c6cb8SMadhusudhan Chikkature return ret; 1443a45c6cb8SMadhusudhan Chikkature } 14449782aff8SPer Forlin ret = omap_hsmmc_pre_dma_transfer(host, data, NULL); 14459782aff8SPer Forlin if (ret) 14469782aff8SPer Forlin return ret; 1447a45c6cb8SMadhusudhan Chikkature 1448a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 14490ccd76d4SJuha Yrjola host->dma_sg_idx = 0; 1450a45c6cb8SMadhusudhan Chikkature 145170a3341aSDenis Karpov omap_hsmmc_config_dma_params(host, data, data->sg); 1452a45c6cb8SMadhusudhan Chikkature 1453a45c6cb8SMadhusudhan Chikkature return 0; 1454a45c6cb8SMadhusudhan Chikkature } 1455a45c6cb8SMadhusudhan Chikkature 145670a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1457e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1458e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1459a45c6cb8SMadhusudhan Chikkature { 1460a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1461a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1462a45c6cb8SMadhusudhan Chikkature 1463a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1464a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1465a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1466a45c6cb8SMadhusudhan Chikkature clkd = 1; 1467a45c6cb8SMadhusudhan Chikkature 1468a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1469e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1470e2bf08d6SAdrian Hunter timeout += timeout_clks; 1471a45c6cb8SMadhusudhan Chikkature if (timeout) { 1472a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1473a45c6cb8SMadhusudhan Chikkature dto += 1; 1474a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1475a45c6cb8SMadhusudhan Chikkature } 1476a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1477a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1478a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1479a45c6cb8SMadhusudhan Chikkature dto += 1; 1480a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1481a45c6cb8SMadhusudhan Chikkature dto -= 13; 1482a45c6cb8SMadhusudhan Chikkature else 1483a45c6cb8SMadhusudhan Chikkature dto = 0; 1484a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1485a45c6cb8SMadhusudhan Chikkature dto = 14; 1486a45c6cb8SMadhusudhan Chikkature } 1487a45c6cb8SMadhusudhan Chikkature 1488a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1489a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1490a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1491a45c6cb8SMadhusudhan Chikkature } 1492a45c6cb8SMadhusudhan Chikkature 1493a45c6cb8SMadhusudhan Chikkature /* 1494a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1495a45c6cb8SMadhusudhan Chikkature */ 1496a45c6cb8SMadhusudhan Chikkature static int 149770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1498a45c6cb8SMadhusudhan Chikkature { 1499a45c6cb8SMadhusudhan Chikkature int ret; 1500a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1501a45c6cb8SMadhusudhan Chikkature 1502a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1503a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1504e2bf08d6SAdrian Hunter /* 1505e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1506e2bf08d6SAdrian Hunter * busy signal. 1507e2bf08d6SAdrian Hunter */ 1508e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1509e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1510a45c6cb8SMadhusudhan Chikkature return 0; 1511a45c6cb8SMadhusudhan Chikkature } 1512a45c6cb8SMadhusudhan Chikkature 1513a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1514a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1515e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1516a45c6cb8SMadhusudhan Chikkature 1517a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 151870a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1519a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1520a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1521a45c6cb8SMadhusudhan Chikkature return ret; 1522a45c6cb8SMadhusudhan Chikkature } 1523a45c6cb8SMadhusudhan Chikkature } 1524a45c6cb8SMadhusudhan Chikkature return 0; 1525a45c6cb8SMadhusudhan Chikkature } 1526a45c6cb8SMadhusudhan Chikkature 15279782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15289782aff8SPer Forlin int err) 15299782aff8SPer Forlin { 15309782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15319782aff8SPer Forlin struct mmc_data *data = mrq->data; 15329782aff8SPer Forlin 15339782aff8SPer Forlin if (host->use_dma) { 15349782aff8SPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 15359782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15369782aff8SPer Forlin data->host_cookie = 0; 15379782aff8SPer Forlin } 15389782aff8SPer Forlin } 15399782aff8SPer Forlin 15409782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15419782aff8SPer Forlin bool is_first_req) 15429782aff8SPer Forlin { 15439782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15449782aff8SPer Forlin 15459782aff8SPer Forlin if (mrq->data->host_cookie) { 15469782aff8SPer Forlin mrq->data->host_cookie = 0; 15479782aff8SPer Forlin return ; 15489782aff8SPer Forlin } 15499782aff8SPer Forlin 15509782aff8SPer Forlin if (host->use_dma) 15519782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 15529782aff8SPer Forlin &host->next_data)) 15539782aff8SPer Forlin mrq->data->host_cookie = 0; 15549782aff8SPer Forlin } 15559782aff8SPer Forlin 1556a45c6cb8SMadhusudhan Chikkature /* 1557a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1558a45c6cb8SMadhusudhan Chikkature */ 155970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1560a45c6cb8SMadhusudhan Chikkature { 156170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1562a3f406f8SJarkko Lavinen int err; 1563a45c6cb8SMadhusudhan Chikkature 1564b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1565b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1566b62f6228SAdrian Hunter if (host->protect_card) { 1567b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1568b62f6228SAdrian Hunter /* 1569b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1570b62f6228SAdrian Hunter * state by resetting the command and data state 1571b62f6228SAdrian Hunter * machines. 1572b62f6228SAdrian Hunter */ 1573b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1574b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1575b62f6228SAdrian Hunter host->reqs_blocked += 1; 1576b62f6228SAdrian Hunter } 1577b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1578b62f6228SAdrian Hunter if (req->data) 1579b62f6228SAdrian Hunter req->data->error = -EBADF; 1580b417577dSAdrian Hunter req->cmd->retries = 0; 1581b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1582b62f6228SAdrian Hunter return; 1583b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1584b62f6228SAdrian Hunter host->reqs_blocked = 0; 1585a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1586a45c6cb8SMadhusudhan Chikkature host->mrq = req; 158770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1588a3f406f8SJarkko Lavinen if (err) { 1589a3f406f8SJarkko Lavinen req->cmd->error = err; 1590a3f406f8SJarkko Lavinen if (req->data) 1591a3f406f8SJarkko Lavinen req->data->error = err; 1592a3f406f8SJarkko Lavinen host->mrq = NULL; 1593a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1594a3f406f8SJarkko Lavinen return; 1595a3f406f8SJarkko Lavinen } 1596a3f406f8SJarkko Lavinen 159770a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1598a45c6cb8SMadhusudhan Chikkature } 1599a45c6cb8SMadhusudhan Chikkature 1600a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 160170a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1602a45c6cb8SMadhusudhan Chikkature { 160370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1604a45c6cb8SMadhusudhan Chikkature u16 dsor = 0; 1605a45c6cb8SMadhusudhan Chikkature unsigned long regval; 1606a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 160773153010SJarkko Lavinen u32 con; 1608a3621465SAdrian Hunter int do_send_init_stream = 0; 1609a45c6cb8SMadhusudhan Chikkature 1610fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16115e2ea617SAdrian Hunter 1612a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1613a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1614a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1615a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1616a3621465SAdrian Hunter 0, 0); 1617623821f7SAdrian Hunter host->vdd = 0; 1618a45c6cb8SMadhusudhan Chikkature break; 1619a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1620a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1621a3621465SAdrian Hunter 1, ios->vdd); 1622623821f7SAdrian Hunter host->vdd = ios->vdd; 1623a45c6cb8SMadhusudhan Chikkature break; 1624a3621465SAdrian Hunter case MMC_POWER_ON: 1625a3621465SAdrian Hunter do_send_init_stream = 1; 1626a3621465SAdrian Hunter break; 1627a3621465SAdrian Hunter } 1628a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1629a45c6cb8SMadhusudhan Chikkature } 1630a45c6cb8SMadhusudhan Chikkature 1631dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1632dd498effSDenis Karpov 163373153010SJarkko Lavinen con = OMAP_HSMMC_READ(host->base, CON); 1634a45c6cb8SMadhusudhan Chikkature switch (mmc->ios.bus_width) { 163573153010SJarkko Lavinen case MMC_BUS_WIDTH_8: 163673153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 163773153010SJarkko Lavinen break; 1638a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_4: 163973153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1640a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1641a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1642a45c6cb8SMadhusudhan Chikkature break; 1643a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_1: 164473153010SJarkko Lavinen OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1645a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1646a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1647a45c6cb8SMadhusudhan Chikkature break; 1648a45c6cb8SMadhusudhan Chikkature } 1649a45c6cb8SMadhusudhan Chikkature 16504621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1651eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1652eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1653eb250826SDavid Brownell */ 1654a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1655a45c6cb8SMadhusudhan Chikkature (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1656a45c6cb8SMadhusudhan Chikkature /* 1657a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1658a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1659a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1660a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1661a45c6cb8SMadhusudhan Chikkature */ 166270a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1663a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1664a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1665a45c6cb8SMadhusudhan Chikkature } 1666a45c6cb8SMadhusudhan Chikkature } 1667a45c6cb8SMadhusudhan Chikkature 1668a45c6cb8SMadhusudhan Chikkature if (ios->clock) { 1669a45c6cb8SMadhusudhan Chikkature dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1670a45c6cb8SMadhusudhan Chikkature if (dsor < 1) 1671a45c6cb8SMadhusudhan Chikkature dsor = 1; 1672a45c6cb8SMadhusudhan Chikkature 1673a45c6cb8SMadhusudhan Chikkature if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1674a45c6cb8SMadhusudhan Chikkature dsor++; 1675a45c6cb8SMadhusudhan Chikkature 1676a45c6cb8SMadhusudhan Chikkature if (dsor > 250) 1677a45c6cb8SMadhusudhan Chikkature dsor = 250; 1678a45c6cb8SMadhusudhan Chikkature } 167970a3341aSDenis Karpov omap_hsmmc_stop_clock(host); 1680a45c6cb8SMadhusudhan Chikkature regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1681a45c6cb8SMadhusudhan Chikkature regval = regval & ~(CLKD_MASK); 1682a45c6cb8SMadhusudhan Chikkature regval = regval | (dsor << 6) | (DTO << 16); 1683a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1684a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 1685a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1686a45c6cb8SMadhusudhan Chikkature 1687a45c6cb8SMadhusudhan Chikkature /* Wait till the ICS bit is set */ 1688a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 168911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1690a45c6cb8SMadhusudhan Chikkature && time_before(jiffies, timeout)) 1691a45c6cb8SMadhusudhan Chikkature msleep(1); 1692a45c6cb8SMadhusudhan Chikkature 1693a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 1694a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1695a45c6cb8SMadhusudhan Chikkature 1696a3621465SAdrian Hunter if (do_send_init_stream) 1697a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1698a45c6cb8SMadhusudhan Chikkature 1699abb28e73SDenis Karpov con = OMAP_HSMMC_READ(host->base, CON); 1700a45c6cb8SMadhusudhan Chikkature if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1701abb28e73SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1702abb28e73SDenis Karpov else 1703abb28e73SDenis Karpov OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 17045e2ea617SAdrian Hunter 1705fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1706a45c6cb8SMadhusudhan Chikkature } 1707a45c6cb8SMadhusudhan Chikkature 1708a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1709a45c6cb8SMadhusudhan Chikkature { 171070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1711a45c6cb8SMadhusudhan Chikkature 1712191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1713a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1714db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1715a45c6cb8SMadhusudhan Chikkature } 1716a45c6cb8SMadhusudhan Chikkature 1717a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1718a45c6cb8SMadhusudhan Chikkature { 171970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1720a45c6cb8SMadhusudhan Chikkature 1721191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1722a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1723191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1724a45c6cb8SMadhusudhan Chikkature } 1725a45c6cb8SMadhusudhan Chikkature 17264816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17274816858cSGrazvydas Ignotas { 17284816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17294816858cSGrazvydas Ignotas 17304816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 17314816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 17324816858cSGrazvydas Ignotas } 17334816858cSGrazvydas Ignotas 173470a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17351b331e69SKim Kyuwon { 17361b331e69SKim Kyuwon u32 hctl, capa, value; 17371b331e69SKim Kyuwon 17381b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17394621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17401b331e69SKim Kyuwon hctl = SDVS30; 17411b331e69SKim Kyuwon capa = VS30 | VS18; 17421b331e69SKim Kyuwon } else { 17431b331e69SKim Kyuwon hctl = SDVS18; 17441b331e69SKim Kyuwon capa = VS18; 17451b331e69SKim Kyuwon } 17461b331e69SKim Kyuwon 17471b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17481b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17491b331e69SKim Kyuwon 17501b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17511b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17521b331e69SKim Kyuwon 17531b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 17541b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 17551b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 17561b331e69SKim Kyuwon 17571b331e69SKim Kyuwon /* Set SD bus power bit */ 1758e13bb300SAdrian Hunter set_sd_bus_power(host); 17591b331e69SKim Kyuwon } 17601b331e69SKim Kyuwon 176170a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1762dd498effSDenis Karpov { 176370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1764dd498effSDenis Karpov 1765fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1766fa4aa2d4SBalaji T K 1767dd498effSDenis Karpov return 0; 1768dd498effSDenis Karpov } 1769dd498effSDenis Karpov 177070a3341aSDenis Karpov static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1771dd498effSDenis Karpov { 177270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1773dd498effSDenis Karpov 1774fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1775fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1776fa4aa2d4SBalaji T K 1777dd498effSDenis Karpov return 0; 1778dd498effSDenis Karpov } 1779dd498effSDenis Karpov 178070a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 178170a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 178270a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 17839782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17849782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 178570a3341aSDenis Karpov .request = omap_hsmmc_request, 178670a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1787dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1788dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 17894816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1790dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1791dd498effSDenis Karpov }; 1792dd498effSDenis Karpov 1793d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1794d900f712SDenis Karpov 179570a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1796d900f712SDenis Karpov { 1797d900f712SDenis Karpov struct mmc_host *mmc = s->private; 179870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 179911dd62a7SDenis Karpov int context_loss = 0; 180011dd62a7SDenis Karpov 180170a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 180270a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1803d900f712SDenis Karpov 18045e2ea617SAdrian Hunter seq_printf(s, "mmc%d:\n" 18055e2ea617SAdrian Hunter " enabled:\t%d\n" 1806dd498effSDenis Karpov " dpm_state:\t%d\n" 18075e2ea617SAdrian Hunter " nesting_cnt:\t%d\n" 180811dd62a7SDenis Karpov " ctx_loss:\t%d:%d\n" 18095e2ea617SAdrian Hunter "\nregs:\n", 1810dd498effSDenis Karpov mmc->index, mmc->enabled ? 1 : 0, 1811dd498effSDenis Karpov host->dpm_state, mmc->nesting_cnt, 181211dd62a7SDenis Karpov host->context_loss, context_loss); 18135e2ea617SAdrian Hunter 18147a8c2cefSBalaji T K if (host->suspended) { 1815dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1816dd498effSDenis Karpov return 0; 1817dd498effSDenis Karpov } 1818dd498effSDenis Karpov 1819fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1820d900f712SDenis Karpov 1821d900f712SDenis Karpov seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1822d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1823d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1824d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1825d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1826d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1827d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1828d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1829d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1830d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1831d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1832d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1833d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1834d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18355e2ea617SAdrian Hunter 1836fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1837fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1838dd498effSDenis Karpov 1839d900f712SDenis Karpov return 0; 1840d900f712SDenis Karpov } 1841d900f712SDenis Karpov 184270a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1843d900f712SDenis Karpov { 184470a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1845d900f712SDenis Karpov } 1846d900f712SDenis Karpov 1847d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 184870a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1849d900f712SDenis Karpov .read = seq_read, 1850d900f712SDenis Karpov .llseek = seq_lseek, 1851d900f712SDenis Karpov .release = single_release, 1852d900f712SDenis Karpov }; 1853d900f712SDenis Karpov 185470a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1855d900f712SDenis Karpov { 1856d900f712SDenis Karpov if (mmc->debugfs_root) 1857d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1858d900f712SDenis Karpov mmc, &mmc_regs_fops); 1859d900f712SDenis Karpov } 1860d900f712SDenis Karpov 1861d900f712SDenis Karpov #else 1862d900f712SDenis Karpov 186370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1864d900f712SDenis Karpov { 1865d900f712SDenis Karpov } 1866d900f712SDenis Karpov 1867d900f712SDenis Karpov #endif 1868d900f712SDenis Karpov 186970a3341aSDenis Karpov static int __init omap_hsmmc_probe(struct platform_device *pdev) 1870a45c6cb8SMadhusudhan Chikkature { 1871a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1872a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 187370a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1874a45c6cb8SMadhusudhan Chikkature struct resource *res; 1875db0fefc5SAdrian Hunter int ret, irq; 1876a45c6cb8SMadhusudhan Chikkature 1877a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1878a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1879a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1880a45c6cb8SMadhusudhan Chikkature } 1881a45c6cb8SMadhusudhan Chikkature 1882a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1883a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1884a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1885a45c6cb8SMadhusudhan Chikkature } 1886a45c6cb8SMadhusudhan Chikkature 1887a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1888a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1889a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1890a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1891a45c6cb8SMadhusudhan Chikkature 189291a0b089Skishore kadiyala res->start += pdata->reg_offset; 189391a0b089Skishore kadiyala res->end += pdata->reg_offset; 1894984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1895a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1896a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1897a45c6cb8SMadhusudhan Chikkature 1898db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1899db0fefc5SAdrian Hunter if (ret) 1900db0fefc5SAdrian Hunter goto err; 1901db0fefc5SAdrian Hunter 190270a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1903a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1904a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1905db0fefc5SAdrian Hunter goto err_alloc; 1906a45c6cb8SMadhusudhan Chikkature } 1907a45c6cb8SMadhusudhan Chikkature 1908a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1909a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1910a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1911a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1912a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1913a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 1914a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1915a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1916a45c6cb8SMadhusudhan Chikkature host->id = pdev->id; 1917a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1918a45c6cb8SMadhusudhan Chikkature host->mapbase = res->start; 1919a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 19206da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 19219782aff8SPer Forlin host->next_data.cookie = 1; 1922a45c6cb8SMadhusudhan Chikkature 1923a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 192470a3341aSDenis Karpov INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 1925a45c6cb8SMadhusudhan Chikkature 192670a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1927dd498effSDenis Karpov 1928e0eb2424SAdrian Hunter /* 1929e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1930e0eb2424SAdrian Hunter * no off state. 1931e0eb2424SAdrian Hunter */ 1932e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1933e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1934e0eb2424SAdrian Hunter 1935a45c6cb8SMadhusudhan Chikkature mmc->f_min = 400000; 1936a45c6cb8SMadhusudhan Chikkature mmc->f_max = 52000000; 1937a45c6cb8SMadhusudhan Chikkature 19384dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1939a45c6cb8SMadhusudhan Chikkature 19406f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1941a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1942a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1943a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1944a45c6cb8SMadhusudhan Chikkature goto err1; 1945a45c6cb8SMadhusudhan Chikkature } 1946a45c6cb8SMadhusudhan Chikkature 194770a3341aSDenis Karpov omap_hsmmc_context_save(host); 194811dd62a7SDenis Karpov 19495e2ea617SAdrian Hunter mmc->caps |= MMC_CAP_DISABLE; 1950dd498effSDenis Karpov 1951fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1952fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1953fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1954fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1955a45c6cb8SMadhusudhan Chikkature 19562bec0893SAdrian Hunter if (cpu_is_omap2430()) { 1957a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1958a45c6cb8SMadhusudhan Chikkature /* 1959a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1960a45c6cb8SMadhusudhan Chikkature */ 1961a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->dbclk)) 19622bec0893SAdrian Hunter dev_warn(mmc_dev(host->mmc), 19632bec0893SAdrian Hunter "Failed to get debounce clock\n"); 1964a45c6cb8SMadhusudhan Chikkature else 19652bec0893SAdrian Hunter host->got_dbclk = 1; 19662bec0893SAdrian Hunter 19672bec0893SAdrian Hunter if (host->got_dbclk) 1968a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1969a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 1970a45c6cb8SMadhusudhan Chikkature " clk failed\n"); 19712bec0893SAdrian Hunter } 1972a45c6cb8SMadhusudhan Chikkature 19730ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 19740ccd76d4SJuha Yrjola * as we want. */ 1975a36274e0SMartin K. Petersen mmc->max_segs = 1024; 19760ccd76d4SJuha Yrjola 1977a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1978a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1979a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1980a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1981a45c6cb8SMadhusudhan Chikkature 198213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 198393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1984a45c6cb8SMadhusudhan Chikkature 19853a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 19863a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1987a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1988a45c6cb8SMadhusudhan Chikkature 1989191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 199023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 199123d99bb9SAdrian Hunter 199270a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1993a45c6cb8SMadhusudhan Chikkature 1994f3e2f1ddSGrazvydas Ignotas /* Select DMA lines */ 1995f3e2f1ddSGrazvydas Ignotas switch (host->id) { 1996f3e2f1ddSGrazvydas Ignotas case OMAP_MMC1_DEVID: 1997f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 1998f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 1999f3e2f1ddSGrazvydas Ignotas break; 2000f3e2f1ddSGrazvydas Ignotas case OMAP_MMC2_DEVID: 2001f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2002f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2003f3e2f1ddSGrazvydas Ignotas break; 2004f3e2f1ddSGrazvydas Ignotas case OMAP_MMC3_DEVID: 2005f3e2f1ddSGrazvydas Ignotas host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2006f3e2f1ddSGrazvydas Ignotas host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2007f3e2f1ddSGrazvydas Ignotas break; 200882cf818dSkishore kadiyala case OMAP_MMC4_DEVID: 200982cf818dSkishore kadiyala host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 201082cf818dSkishore kadiyala host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 201182cf818dSkishore kadiyala break; 201282cf818dSkishore kadiyala case OMAP_MMC5_DEVID: 201382cf818dSkishore kadiyala host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 201482cf818dSkishore kadiyala host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 201582cf818dSkishore kadiyala break; 2016f3e2f1ddSGrazvydas Ignotas default: 2017f3e2f1ddSGrazvydas Ignotas dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2018f3e2f1ddSGrazvydas Ignotas goto err_irq; 2019a45c6cb8SMadhusudhan Chikkature } 2020a45c6cb8SMadhusudhan Chikkature 2021a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 202270a3341aSDenis Karpov ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2023a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2024a45c6cb8SMadhusudhan Chikkature if (ret) { 2025a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2026a45c6cb8SMadhusudhan Chikkature goto err_irq; 2027a45c6cb8SMadhusudhan Chikkature } 2028a45c6cb8SMadhusudhan Chikkature 2029a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 2030a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 203170a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 203270a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 2033a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 2034a45c6cb8SMadhusudhan Chikkature } 2035a45c6cb8SMadhusudhan Chikkature } 2036db0fefc5SAdrian Hunter 2037b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2038db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2039db0fefc5SAdrian Hunter if (ret) 2040db0fefc5SAdrian Hunter goto err_reg; 2041db0fefc5SAdrian Hunter host->use_reg = 1; 2042db0fefc5SAdrian Hunter } 2043db0fefc5SAdrian Hunter 2044b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 2045a45c6cb8SMadhusudhan Chikkature 2046a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2047e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 2048a45c6cb8SMadhusudhan Chikkature ret = request_irq(mmc_slot(host).card_detect_irq, 204970a3341aSDenis Karpov omap_hsmmc_cd_handler, 2050a45c6cb8SMadhusudhan Chikkature IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2051a45c6cb8SMadhusudhan Chikkature | IRQF_DISABLED, 2052a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2053a45c6cb8SMadhusudhan Chikkature if (ret) { 2054a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2055a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2056a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2057a45c6cb8SMadhusudhan Chikkature } 205872f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 205972f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2060a45c6cb8SMadhusudhan Chikkature } 2061a45c6cb8SMadhusudhan Chikkature 2062b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2063a45c6cb8SMadhusudhan Chikkature 2064b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2065b62f6228SAdrian Hunter 2066a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2067a45c6cb8SMadhusudhan Chikkature 2068191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2069a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2070a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2071a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2072a45c6cb8SMadhusudhan Chikkature } 2073191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2074a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2075a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2076a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2077db0fefc5SAdrian Hunter goto err_slot_name; 2078a45c6cb8SMadhusudhan Chikkature } 2079a45c6cb8SMadhusudhan Chikkature 208070a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2081fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2082fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2083d900f712SDenis Karpov 2084a45c6cb8SMadhusudhan Chikkature return 0; 2085a45c6cb8SMadhusudhan Chikkature 2086a45c6cb8SMadhusudhan Chikkature err_slot_name: 2087a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2088a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2089db0fefc5SAdrian Hunter err_irq_cd: 2090db0fefc5SAdrian Hunter if (host->use_reg) 2091db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2092db0fefc5SAdrian Hunter err_reg: 2093db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2094db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2095a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2096a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2097a45c6cb8SMadhusudhan Chikkature err_irq: 2098fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2099fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2100a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 21012bec0893SAdrian Hunter if (host->got_dbclk) { 2102a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2103a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2104a45c6cb8SMadhusudhan Chikkature } 2105a45c6cb8SMadhusudhan Chikkature err1: 2106a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2107db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 2108a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2109db0fefc5SAdrian Hunter err_alloc: 2110db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2111db0fefc5SAdrian Hunter err: 2112984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2113a45c6cb8SMadhusudhan Chikkature return ret; 2114a45c6cb8SMadhusudhan Chikkature } 2115a45c6cb8SMadhusudhan Chikkature 211670a3341aSDenis Karpov static int omap_hsmmc_remove(struct platform_device *pdev) 2117a45c6cb8SMadhusudhan Chikkature { 211870a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2119a45c6cb8SMadhusudhan Chikkature struct resource *res; 2120a45c6cb8SMadhusudhan Chikkature 2121a45c6cb8SMadhusudhan Chikkature if (host) { 2122fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2123a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2124db0fefc5SAdrian Hunter if (host->use_reg) 2125db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2126a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2127a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2128a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2129a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2130a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 21310d9ee5b2STejun Heo flush_work_sync(&host->mmc_carddetect_work); 2132a45c6cb8SMadhusudhan Chikkature 2133fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2134fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2135a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 21362bec0893SAdrian Hunter if (host->got_dbclk) { 2137a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2138a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2139a45c6cb8SMadhusudhan Chikkature } 2140a45c6cb8SMadhusudhan Chikkature 2141a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2142a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2143db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2144a45c6cb8SMadhusudhan Chikkature } 2145a45c6cb8SMadhusudhan Chikkature 2146a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2147a45c6cb8SMadhusudhan Chikkature if (res) 2148984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2149a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2150a45c6cb8SMadhusudhan Chikkature 2151a45c6cb8SMadhusudhan Chikkature return 0; 2152a45c6cb8SMadhusudhan Chikkature } 2153a45c6cb8SMadhusudhan Chikkature 2154a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2155a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2156a45c6cb8SMadhusudhan Chikkature { 2157a45c6cb8SMadhusudhan Chikkature int ret = 0; 2158a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 215970a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2160a45c6cb8SMadhusudhan Chikkature 2161a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2162a45c6cb8SMadhusudhan Chikkature return 0; 2163a45c6cb8SMadhusudhan Chikkature 2164a45c6cb8SMadhusudhan Chikkature if (host) { 2165fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2166a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2167a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2168a45c6cb8SMadhusudhan Chikkature ret = host->pdata->suspend(&pdev->dev, 2169a45c6cb8SMadhusudhan Chikkature host->slot_id); 2170a6b2240dSAdrian Hunter if (ret) { 2171a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2172a45c6cb8SMadhusudhan Chikkature "Unable to handle MMC board" 2173a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2174a6b2240dSAdrian Hunter host->suspended = 0; 2175a6b2240dSAdrian Hunter return ret; 2176a45c6cb8SMadhusudhan Chikkature } 2177a6b2240dSAdrian Hunter } 2178a6b2240dSAdrian Hunter cancel_work_sync(&host->mmc_carddetect_work); 21791a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2180fa4aa2d4SBalaji T K 2181a6b2240dSAdrian Hunter if (ret == 0) { 2182b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2183a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 21840683af48SJarkko Lavinen OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 21852bec0893SAdrian Hunter if (host->got_dbclk) 2186a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 2187a6b2240dSAdrian Hunter } else { 2188a6b2240dSAdrian Hunter host->suspended = 0; 2189a6b2240dSAdrian Hunter if (host->pdata->resume) { 2190a6b2240dSAdrian Hunter ret = host->pdata->resume(&pdev->dev, 2191a6b2240dSAdrian Hunter host->slot_id); 2192a6b2240dSAdrian Hunter if (ret) 2193a6b2240dSAdrian Hunter dev_dbg(mmc_dev(host->mmc), 2194a6b2240dSAdrian Hunter "Unmask interrupt failed\n"); 2195a6b2240dSAdrian Hunter } 2196a6b2240dSAdrian Hunter } 2197fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2198a45c6cb8SMadhusudhan Chikkature } 2199a45c6cb8SMadhusudhan Chikkature return ret; 2200a45c6cb8SMadhusudhan Chikkature } 2201a45c6cb8SMadhusudhan Chikkature 2202a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2203a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2204a45c6cb8SMadhusudhan Chikkature { 2205a45c6cb8SMadhusudhan Chikkature int ret = 0; 2206a791daa1SKevin Hilman struct platform_device *pdev = to_platform_device(dev); 220770a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2208a45c6cb8SMadhusudhan Chikkature 2209a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2210a45c6cb8SMadhusudhan Chikkature return 0; 2211a45c6cb8SMadhusudhan Chikkature 2212a45c6cb8SMadhusudhan Chikkature if (host) { 2213fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 221411dd62a7SDenis Karpov 22152bec0893SAdrian Hunter if (host->got_dbclk) 22162bec0893SAdrian Hunter clk_enable(host->dbclk); 22172bec0893SAdrian Hunter 221870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22191b331e69SKim Kyuwon 2220a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2221a45c6cb8SMadhusudhan Chikkature ret = host->pdata->resume(&pdev->dev, host->slot_id); 2222a45c6cb8SMadhusudhan Chikkature if (ret) 2223a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 2224a45c6cb8SMadhusudhan Chikkature "Unmask interrupt failed\n"); 2225a45c6cb8SMadhusudhan Chikkature } 2226a45c6cb8SMadhusudhan Chikkature 2227b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2228b62f6228SAdrian Hunter 2229a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2230a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2231a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2232a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2233fa4aa2d4SBalaji T K 2234fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2235fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2236a45c6cb8SMadhusudhan Chikkature } 2237a45c6cb8SMadhusudhan Chikkature 2238a45c6cb8SMadhusudhan Chikkature return ret; 2239a45c6cb8SMadhusudhan Chikkature 2240a45c6cb8SMadhusudhan Chikkature } 2241a45c6cb8SMadhusudhan Chikkature 2242a45c6cb8SMadhusudhan Chikkature #else 224370a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 224470a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2245a45c6cb8SMadhusudhan Chikkature #endif 2246a45c6cb8SMadhusudhan Chikkature 2247fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2248fa4aa2d4SBalaji T K { 2249fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2250fa4aa2d4SBalaji T K 2251fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2252fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2253fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "disabled\n"); 2254fa4aa2d4SBalaji T K 2255fa4aa2d4SBalaji T K return 0; 2256fa4aa2d4SBalaji T K } 2257fa4aa2d4SBalaji T K 2258fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2259fa4aa2d4SBalaji T K { 2260fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2261fa4aa2d4SBalaji T K 2262fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2263fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2264fa4aa2d4SBalaji T K dev_dbg(mmc_dev(host->mmc), "enabled\n"); 2265fa4aa2d4SBalaji T K 2266fa4aa2d4SBalaji T K return 0; 2267fa4aa2d4SBalaji T K } 2268fa4aa2d4SBalaji T K 2269a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 227070a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 227170a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2272fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2273fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2274a791daa1SKevin Hilman }; 2275a791daa1SKevin Hilman 2276a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2277a791daa1SKevin Hilman .remove = omap_hsmmc_remove, 2278a45c6cb8SMadhusudhan Chikkature .driver = { 2279a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2280a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2281a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 2282a45c6cb8SMadhusudhan Chikkature }, 2283a45c6cb8SMadhusudhan Chikkature }; 2284a45c6cb8SMadhusudhan Chikkature 228570a3341aSDenis Karpov static int __init omap_hsmmc_init(void) 2286a45c6cb8SMadhusudhan Chikkature { 2287a45c6cb8SMadhusudhan Chikkature /* Register the MMC driver */ 22888753298aSRoger Quadros return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2289a45c6cb8SMadhusudhan Chikkature } 2290a45c6cb8SMadhusudhan Chikkature 229170a3341aSDenis Karpov static void __exit omap_hsmmc_cleanup(void) 2292a45c6cb8SMadhusudhan Chikkature { 2293a45c6cb8SMadhusudhan Chikkature /* Unregister MMC driver */ 229470a3341aSDenis Karpov platform_driver_unregister(&omap_hsmmc_driver); 2295a45c6cb8SMadhusudhan Chikkature } 2296a45c6cb8SMadhusudhan Chikkature 229770a3341aSDenis Karpov module_init(omap_hsmmc_init); 229870a3341aSDenis Karpov module_exit(omap_hsmmc_cleanup); 2299a45c6cb8SMadhusudhan Chikkature 2300a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2301a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2302a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2303a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2304