1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3841afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 455b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 47a45c6cb8SMadhusudhan Chikkature 48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 66a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 68a45c6cb8SMadhusudhan Chikkature 69a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 70a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 71cd587096SHebbar, Gururaja #define HSS (1 << 21) 72a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 73a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 74eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 751b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 77a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 79a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 80a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 81a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 82a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 83a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 84ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 90a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 92a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 93a7e96879SVenkatraman S #define DMAE 0x1 94a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 97cd587096SHebbar, Gururaja #define HSPE (1 << 2) 985a52b08bSBalaji T K #define IWE (1 << 24) 9903b5d924SBalaji T K #define DDR (1 << 19) 1005a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1015a52b08bSBalaji T K #define CTPL (1 << 11) 10273153010SJarkko Lavinen #define DW8 (1 << 5) 103a45c6cb8SMadhusudhan Chikkature #define OD 0x1 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 110a45c6cb8SMadhusudhan Chikkature 111f945901fSAndreas Fenkart /* PSTATE */ 112f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 113f945901fSAndreas Fenkart 114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 115a7e96879SVenkatraman S #define CC_EN (1 << 0) 116a7e96879SVenkatraman S #define TC_EN (1 << 1) 117a7e96879SVenkatraman S #define BWR_EN (1 << 4) 118a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1192cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 120a7e96879SVenkatraman S #define ERR_EN (1 << 15) 121a7e96879SVenkatraman S #define CTO_EN (1 << 16) 122a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 123a7e96879SVenkatraman S #define CEB_EN (1 << 18) 124a7e96879SVenkatraman S #define CIE_EN (1 << 19) 125a7e96879SVenkatraman S #define DTO_EN (1 << 20) 126a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 127a7e96879SVenkatraman S #define DEB_EN (1 << 22) 128a2e77152SBalaji T K #define ACE_EN (1 << 24) 129a7e96879SVenkatraman S #define CERR_EN (1 << 28) 130a7e96879SVenkatraman S #define BADA_EN (1 << 29) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 135a7e96879SVenkatraman S 136a2e77152SBalaji T K #define CNI (1 << 7) 137a2e77152SBalaji T K #define ACIE (1 << 4) 138a2e77152SBalaji T K #define ACEB (1 << 3) 139a2e77152SBalaji T K #define ACCE (1 << 2) 140a2e77152SBalaji T K #define ACTO (1 << 1) 141a2e77152SBalaji T K #define ACNE (1 << 0) 142a2e77152SBalaji T K 143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1451e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1480005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 149a45c6cb8SMadhusudhan Chikkature 150a45c6cb8SMadhusudhan Chikkature /* 151a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 152a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 153a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 154a45c6cb8SMadhusudhan Chikkature */ 155326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 156a45c6cb8SMadhusudhan Chikkature 157a45c6cb8SMadhusudhan Chikkature /* 158a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 159a45c6cb8SMadhusudhan Chikkature */ 160a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 161a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 162a45c6cb8SMadhusudhan Chikkature 163a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 164a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 165a45c6cb8SMadhusudhan Chikkature 1669782aff8SPer Forlin struct omap_hsmmc_next { 1679782aff8SPer Forlin unsigned int dma_len; 1689782aff8SPer Forlin s32 cookie; 1699782aff8SPer Forlin }; 1709782aff8SPer Forlin 17170a3341aSDenis Karpov struct omap_hsmmc_host { 172a45c6cb8SMadhusudhan Chikkature struct device *dev; 173a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 174a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 175a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 176a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 177a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 178a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 179e99448ffSBalaji T K struct regulator *pbias; 180bb2726b5STony Lindgren bool pbias_enabled; 181a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1823f77f702SKishon Vijay Abraham I int vqmmc_enabled; 183a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1844dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 185a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1860ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 187a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 188a3621465SAdrian Hunter unsigned char power_mode; 189a45c6cb8SMadhusudhan Chikkature int suspended; 1900a82e06eSTony Lindgren u32 con; 1910a82e06eSTony Lindgren u32 hctl; 1920a82e06eSTony Lindgren u32 sysctl; 1930a82e06eSTony Lindgren u32 capa; 194a45c6cb8SMadhusudhan Chikkature int irq; 1952cd3a2a5SAndreas Fenkart int wake_irq; 196a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 197c5c98927SRussell King struct dma_chan *tx_chan; 198c5c98927SRussell King struct dma_chan *rx_chan; 1994a694dc9SAdrian Hunter int response_busy; 20011dd62a7SDenis Karpov int context_loss; 201b62f6228SAdrian Hunter int protect_card; 202b62f6228SAdrian Hunter int reqs_blocked; 203b417577dSAdrian Hunter int req_in_progress; 2046e3076c2SBalaji T K unsigned long clk_rate; 205a2e77152SBalaji T K unsigned int flags; 2062cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2072cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2089782aff8SPer Forlin struct omap_hsmmc_next next_data; 20955143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 210b5cd43f0SAndreas Fenkart 211b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 212b5cd43f0SAndreas Fenkart * 213b5cd43f0SAndreas Fenkart * possible return values: 214b5cd43f0SAndreas Fenkart * 0 - closed 215b5cd43f0SAndreas Fenkart * 1 - open 216b5cd43f0SAndreas Fenkart */ 21780412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 218b5cd43f0SAndreas Fenkart 21980412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 220a45c6cb8SMadhusudhan Chikkature }; 221a45c6cb8SMadhusudhan Chikkature 22259445b10SNishanth Menon struct omap_mmc_of_data { 22359445b10SNishanth Menon u32 reg_offset; 22459445b10SNishanth Menon u8 controller_flags; 22559445b10SNishanth Menon }; 22659445b10SNishanth Menon 227bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 228bf129e1cSBalaji T K 22980412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 230db0fefc5SAdrian Hunter { 2319ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 232db0fefc5SAdrian Hunter 23341afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 234db0fefc5SAdrian Hunter } 235db0fefc5SAdrian Hunter 23680412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 237db0fefc5SAdrian Hunter { 2389ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 239db0fefc5SAdrian Hunter 24041afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 241db0fefc5SAdrian Hunter } 242db0fefc5SAdrian Hunter 2431d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 2442a17f844SKishon Vijay Abraham I { 2452a17f844SKishon Vijay Abraham I int ret; 2463f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2471d17f30bSKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 2482a17f844SKishon Vijay Abraham I 24986d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2501d17f30bSKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 2512a17f844SKishon Vijay Abraham I if (ret) 2522a17f844SKishon Vijay Abraham I return ret; 2532a17f844SKishon Vijay Abraham I } 2542a17f844SKishon Vijay Abraham I 2552a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 25686d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 2572a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2582a17f844SKishon Vijay Abraham I if (ret) { 2592a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2602a17f844SKishon Vijay Abraham I goto err_vqmmc; 2612a17f844SKishon Vijay Abraham I } 2623f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2632a17f844SKishon Vijay Abraham I } 2642a17f844SKishon Vijay Abraham I 2652a17f844SKishon Vijay Abraham I return 0; 2662a17f844SKishon Vijay Abraham I 2672a17f844SKishon Vijay Abraham I err_vqmmc: 26886d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) 2692a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2702a17f844SKishon Vijay Abraham I 2712a17f844SKishon Vijay Abraham I return ret; 2722a17f844SKishon Vijay Abraham I } 2732a17f844SKishon Vijay Abraham I 2742a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2752a17f844SKishon Vijay Abraham I { 2762a17f844SKishon Vijay Abraham I int ret; 2772a17f844SKishon Vijay Abraham I int status; 2783f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2792a17f844SKishon Vijay Abraham I 28086d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 2812a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2822a17f844SKishon Vijay Abraham I if (ret) { 2832a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2842a17f844SKishon Vijay Abraham I return ret; 2852a17f844SKishon Vijay Abraham I } 2863f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2872a17f844SKishon Vijay Abraham I } 2882a17f844SKishon Vijay Abraham I 28986d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2902a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2912a17f844SKishon Vijay Abraham I if (ret) 2922a17f844SKishon Vijay Abraham I goto err_set_ocr; 2932a17f844SKishon Vijay Abraham I } 2942a17f844SKishon Vijay Abraham I 2952a17f844SKishon Vijay Abraham I return 0; 2962a17f844SKishon Vijay Abraham I 2972a17f844SKishon Vijay Abraham I err_set_ocr: 29886d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc)) { 2992a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3002a17f844SKishon Vijay Abraham I if (status) 3012a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3022a17f844SKishon Vijay Abraham I } 3032a17f844SKishon Vijay Abraham I 3042a17f844SKishon Vijay Abraham I return ret; 3052a17f844SKishon Vijay Abraham I } 3062a17f844SKishon Vijay Abraham I 30766162becSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on) 308ec85c95eSKishon Vijay Abraham I { 309ec85c95eSKishon Vijay Abraham I int ret; 310ec85c95eSKishon Vijay Abraham I 31186d79da0SKishon Vijay Abraham I if (IS_ERR(host->pbias)) 312ec85c95eSKishon Vijay Abraham I return 0; 313ec85c95eSKishon Vijay Abraham I 314ec85c95eSKishon Vijay Abraham I if (power_on) { 315bb2726b5STony Lindgren if (host->pbias_enabled == 0) { 316ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 317ec85c95eSKishon Vijay Abraham I if (ret) { 318ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 319ec85c95eSKishon Vijay Abraham I return ret; 320ec85c95eSKishon Vijay Abraham I } 321bb2726b5STony Lindgren host->pbias_enabled = 1; 322ec85c95eSKishon Vijay Abraham I } 323ec85c95eSKishon Vijay Abraham I } else { 324bb2726b5STony Lindgren if (host->pbias_enabled == 1) { 325ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 326ec85c95eSKishon Vijay Abraham I if (ret) { 327ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 328ec85c95eSKishon Vijay Abraham I return ret; 329ec85c95eSKishon Vijay Abraham I } 330bb2726b5STony Lindgren host->pbias_enabled = 0; 331ec85c95eSKishon Vijay Abraham I } 332ec85c95eSKishon Vijay Abraham I } 333ec85c95eSKishon Vijay Abraham I 334ec85c95eSKishon Vijay Abraham I return 0; 335ec85c95eSKishon Vijay Abraham I } 336ec85c95eSKishon Vijay Abraham I 33766162becSKishon Vijay Abraham I static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on) 338db0fefc5SAdrian Hunter { 339aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 340db0fefc5SAdrian Hunter int ret = 0; 341db0fefc5SAdrian Hunter 342db0fefc5SAdrian Hunter /* 343db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 344db0fefc5SAdrian Hunter * voltage always-on regulator. 345db0fefc5SAdrian Hunter */ 34686d79da0SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) 347db0fefc5SAdrian Hunter return 0; 348db0fefc5SAdrian Hunter 34966162becSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false); 350ec85c95eSKishon Vijay Abraham I if (ret) 351229f3292SKishon Vijay Abraham I return ret; 352e99448ffSBalaji T K 353db0fefc5SAdrian Hunter /* 354db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 355db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 356db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 357db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 358db0fefc5SAdrian Hunter * 359db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 360db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 361db0fefc5SAdrian Hunter * 362db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 363db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 364db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 365db0fefc5SAdrian Hunter */ 366db0fefc5SAdrian Hunter if (power_on) { 3671d17f30bSKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc); 368229f3292SKishon Vijay Abraham I if (ret) 369229f3292SKishon Vijay Abraham I return ret; 37097fe7e5aSKishon Vijay Abraham I 37166162becSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true); 37297fe7e5aSKishon Vijay Abraham I if (ret) 37397fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 374db0fefc5SAdrian Hunter } else { 3752a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 376229f3292SKishon Vijay Abraham I if (ret) 377229f3292SKishon Vijay Abraham I return ret; 37899fc5131SLinus Walleij } 379db0fefc5SAdrian Hunter 380229f3292SKishon Vijay Abraham I return 0; 381229f3292SKishon Vijay Abraham I 382229f3292SKishon Vijay Abraham I err_set_voltage: 3832a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 384229f3292SKishon Vijay Abraham I 385db0fefc5SAdrian Hunter return ret; 386db0fefc5SAdrian Hunter } 387db0fefc5SAdrian Hunter 388c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 389c8518efaSKishon Vijay Abraham I { 390c8518efaSKishon Vijay Abraham I int ret; 391c8518efaSKishon Vijay Abraham I 39286d79da0SKishon Vijay Abraham I if (IS_ERR(reg)) 393c8518efaSKishon Vijay Abraham I return 0; 394c8518efaSKishon Vijay Abraham I 395c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 396c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 397c8518efaSKishon Vijay Abraham I if (ret) 398c8518efaSKishon Vijay Abraham I return ret; 399c8518efaSKishon Vijay Abraham I 400c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 401c8518efaSKishon Vijay Abraham I if (ret) 402c8518efaSKishon Vijay Abraham I return ret; 403c8518efaSKishon Vijay Abraham I } 404c8518efaSKishon Vijay Abraham I 405c8518efaSKishon Vijay Abraham I return 0; 406c8518efaSKishon Vijay Abraham I } 407c8518efaSKishon Vijay Abraham I 408c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 409c8518efaSKishon Vijay Abraham I { 410c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 411c8518efaSKishon Vijay Abraham I int ret; 412c8518efaSKishon Vijay Abraham I 413c8518efaSKishon Vijay Abraham I /* 414c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 415c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 416c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 417c8518efaSKishon Vijay Abraham I */ 418c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 419c8518efaSKishon Vijay Abraham I if (ret) { 420c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 421c8518efaSKishon Vijay Abraham I return ret; 422c8518efaSKishon Vijay Abraham I } 423c8518efaSKishon Vijay Abraham I 424c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 425c8518efaSKishon Vijay Abraham I if (ret) { 426c8518efaSKishon Vijay Abraham I dev_err(host->dev, 427c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 428c8518efaSKishon Vijay Abraham I return ret; 429c8518efaSKishon Vijay Abraham I } 430c8518efaSKishon Vijay Abraham I 431c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 432c8518efaSKishon Vijay Abraham I if (ret) { 433c8518efaSKishon Vijay Abraham I dev_err(host->dev, 434c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 435c8518efaSKishon Vijay Abraham I return ret; 436c8518efaSKishon Vijay Abraham I } 437c8518efaSKishon Vijay Abraham I 438c8518efaSKishon Vijay Abraham I return 0; 439c8518efaSKishon Vijay Abraham I } 440c8518efaSKishon Vijay Abraham I 441db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 442db0fefc5SAdrian Hunter { 4437d607f91SKishon Vijay Abraham I int ret; 444aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 445db0fefc5SAdrian Hunter 446f7f0f035SAndreas Fenkart 44713ab2a66SKishon Vijay Abraham I ret = mmc_regulator_get_supply(mmc); 44813ab2a66SKishon Vijay Abraham I if (ret == -EPROBE_DEFER) 4497d607f91SKishon Vijay Abraham I return ret; 450db0fefc5SAdrian Hunter 451db0fefc5SAdrian Hunter /* Allow an aux regulator */ 45213ab2a66SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 45313ab2a66SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 45413ab2a66SKishon Vijay Abraham I "vmmc_aux"); 455aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 456aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 457123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4586a9b2ff0SKishon Vijay Abraham I return ret; 4596a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 460aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 4616a9b2ff0SKishon Vijay Abraham I } 46213ab2a66SKishon Vijay Abraham I } 463db0fefc5SAdrian Hunter 464c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 465c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 466c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 4679143757bSKishon Vijay Abraham I if ((ret != -ENODEV) && host->dev->of_node) { 4689143757bSKishon Vijay Abraham I dev_err(host->dev, 4699143757bSKishon Vijay Abraham I "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 4706a9b2ff0SKishon Vijay Abraham I return ret; 4719143757bSKishon Vijay Abraham I } 4726a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 473c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 4746a9b2ff0SKishon Vijay Abraham I } 475e99448ffSBalaji T K 476b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 477326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 478b1c1df7aSBalaji T K return 0; 479e840ce13SAdrian Hunter 480c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 481c8518efaSKishon Vijay Abraham I if (ret) 482c8518efaSKishon Vijay Abraham I return ret; 483db0fefc5SAdrian Hunter 484db0fefc5SAdrian Hunter return 0; 485db0fefc5SAdrian Hunter } 486db0fefc5SAdrian Hunter 487cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 48841afa314SNeilBrown 48941afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 49041afa314SNeilBrown struct omap_hsmmc_host *host, 4911e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 492b702b106SAdrian Hunter { 493b702b106SAdrian Hunter int ret; 494b702b106SAdrian Hunter 495b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 496b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 497b702b106SAdrian Hunter if (ret) 498b702b106SAdrian Hunter return ret; 499cde592cbSAndreas Fenkart 500cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 501cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 502b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 503b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 504cde592cbSAndreas Fenkart if (ret) 505cde592cbSAndreas Fenkart return ret; 506cde592cbSAndreas Fenkart 507cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 508326119c9SAndreas Fenkart } 509b702b106SAdrian Hunter 510326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 51141afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 512b702b106SAdrian Hunter if (ret) 51341afa314SNeilBrown return ret; 514326119c9SAndreas Fenkart } 515b702b106SAdrian Hunter 516b702b106SAdrian Hunter return 0; 517b702b106SAdrian Hunter } 518b702b106SAdrian Hunter 519a45c6cb8SMadhusudhan Chikkature /* 520e0c7f99bSAndy Shevchenko * Start clock to the card 521e0c7f99bSAndy Shevchenko */ 522e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 523e0c7f99bSAndy Shevchenko { 524e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 525e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 526e0c7f99bSAndy Shevchenko } 527e0c7f99bSAndy Shevchenko 528e0c7f99bSAndy Shevchenko /* 529a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 530a45c6cb8SMadhusudhan Chikkature */ 53170a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 532a45c6cb8SMadhusudhan Chikkature { 533a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 534a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 535a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5367122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 537a45c6cb8SMadhusudhan Chikkature } 538a45c6cb8SMadhusudhan Chikkature 53993caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 54093caf8e6SAdrian Hunter struct mmc_command *cmd) 541b417577dSAdrian Hunter { 5422cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5432cd3a2a5SAndreas Fenkart unsigned long flags; 544b417577dSAdrian Hunter 545b417577dSAdrian Hunter if (host->use_dma) 5462cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 547b417577dSAdrian Hunter 54893caf8e6SAdrian Hunter /* Disable timeout for erases */ 54993caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 550a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 55193caf8e6SAdrian Hunter 5522cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 553b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 554b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5552cd3a2a5SAndreas Fenkart 5562cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5572cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5582cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 559b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5602cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 561b417577dSAdrian Hunter } 562b417577dSAdrian Hunter 563b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 564b417577dSAdrian Hunter { 5652cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5662cd3a2a5SAndreas Fenkart unsigned long flags; 5672cd3a2a5SAndreas Fenkart 5682cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5692cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5702cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5712cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5722cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5732cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 574b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5752cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 576b417577dSAdrian Hunter } 577b417577dSAdrian Hunter 578ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 579d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 580ac330f44SAndy Shevchenko { 581ac330f44SAndy Shevchenko u16 dsor = 0; 582ac330f44SAndy Shevchenko 583ac330f44SAndy Shevchenko if (ios->clock) { 584d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 585ed164182SBalaji T K if (dsor > CLKD_MAX) 586ed164182SBalaji T K dsor = CLKD_MAX; 587ac330f44SAndy Shevchenko } 588ac330f44SAndy Shevchenko 589ac330f44SAndy Shevchenko return dsor; 590ac330f44SAndy Shevchenko } 591ac330f44SAndy Shevchenko 5925934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5935934df2fSAndy Shevchenko { 5945934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5955934df2fSAndy Shevchenko unsigned long regval; 5965934df2fSAndy Shevchenko unsigned long timeout; 597cd587096SHebbar, Gururaja unsigned long clkdiv; 5985934df2fSAndy Shevchenko 5998986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6005934df2fSAndy Shevchenko 6015934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6025934df2fSAndy Shevchenko 6035934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6045934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 605cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 606cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6075934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6085934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6095934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6105934df2fSAndy Shevchenko 6115934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6125934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6135934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6145934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6155934df2fSAndy Shevchenko cpu_relax(); 6165934df2fSAndy Shevchenko 617cd587096SHebbar, Gururaja /* 618cd587096SHebbar, Gururaja * Enable High-Speed Support 619cd587096SHebbar, Gururaja * Pre-Requisites 620cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 621cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 622cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 623cd587096SHebbar, Gururaja * in capabilities register 624cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 625cd587096SHebbar, Gururaja */ 626326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6275438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 628903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 629cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 630cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 631cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 632cd587096SHebbar, Gururaja regval |= HSPE; 633cd587096SHebbar, Gururaja else 634cd587096SHebbar, Gururaja regval &= ~HSPE; 635cd587096SHebbar, Gururaja 636cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 637cd587096SHebbar, Gururaja } 638cd587096SHebbar, Gururaja 6395934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6405934df2fSAndy Shevchenko } 6415934df2fSAndy Shevchenko 6423796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6433796fb8aSAndy Shevchenko { 6443796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6453796fb8aSAndy Shevchenko u32 con; 6463796fb8aSAndy Shevchenko 6473796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 648903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 649903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 65003b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 65103b5d924SBalaji T K else 65203b5d924SBalaji T K con &= ~DDR; 6533796fb8aSAndy Shevchenko switch (ios->bus_width) { 6543796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6553796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6563796fb8aSAndy Shevchenko break; 6573796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6583796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6593796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6603796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6613796fb8aSAndy Shevchenko break; 6623796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6633796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6643796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6653796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6663796fb8aSAndy Shevchenko break; 6673796fb8aSAndy Shevchenko } 6683796fb8aSAndy Shevchenko } 6693796fb8aSAndy Shevchenko 6703796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6713796fb8aSAndy Shevchenko { 6723796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6733796fb8aSAndy Shevchenko u32 con; 6743796fb8aSAndy Shevchenko 6753796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6763796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6773796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6783796fb8aSAndy Shevchenko else 6793796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6803796fb8aSAndy Shevchenko } 6813796fb8aSAndy Shevchenko 68211dd62a7SDenis Karpov #ifdef CONFIG_PM 68311dd62a7SDenis Karpov 68411dd62a7SDenis Karpov /* 68511dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 68611dd62a7SDenis Karpov * power state change. 68711dd62a7SDenis Karpov */ 68870a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 68911dd62a7SDenis Karpov { 69011dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6913796fb8aSAndy Shevchenko u32 hctl, capa; 69211dd62a7SDenis Karpov unsigned long timeout; 69311dd62a7SDenis Karpov 6940a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6950a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6960a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6970a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6980a82e06eSTony Lindgren return 0; 6990a82e06eSTony Lindgren 7000a82e06eSTony Lindgren host->context_loss++; 7010a82e06eSTony Lindgren 702c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 70311dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 70411dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 70511dd62a7SDenis Karpov hctl = SDVS18; 70611dd62a7SDenis Karpov else 70711dd62a7SDenis Karpov hctl = SDVS30; 70811dd62a7SDenis Karpov capa = VS30 | VS18; 70911dd62a7SDenis Karpov } else { 71011dd62a7SDenis Karpov hctl = SDVS18; 71111dd62a7SDenis Karpov capa = VS18; 71211dd62a7SDenis Karpov } 71311dd62a7SDenis Karpov 7145a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7155a52b08bSBalaji T K hctl |= IWE; 7165a52b08bSBalaji T K 71711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 71811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 71911dd62a7SDenis Karpov 72011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 72111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 72211dd62a7SDenis Karpov 72311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 72411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 72511dd62a7SDenis Karpov 72611dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 72711dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 72811dd62a7SDenis Karpov && time_before(jiffies, timeout)) 72911dd62a7SDenis Karpov ; 73011dd62a7SDenis Karpov 7312cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7322cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7332cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 73411dd62a7SDenis Karpov 73511dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 73611dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 73711dd62a7SDenis Karpov goto out; 73811dd62a7SDenis Karpov 7393796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 74011dd62a7SDenis Karpov 7415934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 74211dd62a7SDenis Karpov 7433796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7443796fb8aSAndy Shevchenko 74511dd62a7SDenis Karpov out: 7460a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7470a82e06eSTony Lindgren host->context_loss); 74811dd62a7SDenis Karpov return 0; 74911dd62a7SDenis Karpov } 75011dd62a7SDenis Karpov 75111dd62a7SDenis Karpov /* 75211dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 75311dd62a7SDenis Karpov */ 75470a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 75511dd62a7SDenis Karpov { 7560a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7570a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7580a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7590a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 76011dd62a7SDenis Karpov } 76111dd62a7SDenis Karpov 76211dd62a7SDenis Karpov #else 76311dd62a7SDenis Karpov 76470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 76511dd62a7SDenis Karpov { 76611dd62a7SDenis Karpov return 0; 76711dd62a7SDenis Karpov } 76811dd62a7SDenis Karpov 76970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 77011dd62a7SDenis Karpov { 77111dd62a7SDenis Karpov } 77211dd62a7SDenis Karpov 77311dd62a7SDenis Karpov #endif 77411dd62a7SDenis Karpov 775a45c6cb8SMadhusudhan Chikkature /* 776a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 777a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 778a45c6cb8SMadhusudhan Chikkature */ 77970a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 780a45c6cb8SMadhusudhan Chikkature { 781a45c6cb8SMadhusudhan Chikkature int reg = 0; 782a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 783a45c6cb8SMadhusudhan Chikkature 784b62f6228SAdrian Hunter if (host->protect_card) 785b62f6228SAdrian Hunter return; 786b62f6228SAdrian Hunter 787a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 788b417577dSAdrian Hunter 789b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 790a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 791a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 792a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 793a45c6cb8SMadhusudhan Chikkature 794a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 795a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 796a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 797a45c6cb8SMadhusudhan Chikkature 798a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 799a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 800c653a6d4SAdrian Hunter 801c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 802c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 803c653a6d4SAdrian Hunter 804a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 805a45c6cb8SMadhusudhan Chikkature } 806a45c6cb8SMadhusudhan Chikkature 807a45c6cb8SMadhusudhan Chikkature static inline 80870a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 809a45c6cb8SMadhusudhan Chikkature { 810a45c6cb8SMadhusudhan Chikkature int r = 1; 811a45c6cb8SMadhusudhan Chikkature 812b5cd43f0SAndreas Fenkart if (host->get_cover_state) 81380412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 814a45c6cb8SMadhusudhan Chikkature return r; 815a45c6cb8SMadhusudhan Chikkature } 816a45c6cb8SMadhusudhan Chikkature 817a45c6cb8SMadhusudhan Chikkature static ssize_t 81870a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 819a45c6cb8SMadhusudhan Chikkature char *buf) 820a45c6cb8SMadhusudhan Chikkature { 821a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 82270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 823a45c6cb8SMadhusudhan Chikkature 82470a3341aSDenis Karpov return sprintf(buf, "%s\n", 82570a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 826a45c6cb8SMadhusudhan Chikkature } 827a45c6cb8SMadhusudhan Chikkature 82870a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature static ssize_t 83170a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 832a45c6cb8SMadhusudhan Chikkature char *buf) 833a45c6cb8SMadhusudhan Chikkature { 834a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 83570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 836a45c6cb8SMadhusudhan Chikkature 837326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 838a45c6cb8SMadhusudhan Chikkature } 839a45c6cb8SMadhusudhan Chikkature 84070a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 841a45c6cb8SMadhusudhan Chikkature 842a45c6cb8SMadhusudhan Chikkature /* 843a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 844a45c6cb8SMadhusudhan Chikkature */ 845a45c6cb8SMadhusudhan Chikkature static void 84670a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 847a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 848a45c6cb8SMadhusudhan Chikkature { 849a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 850a45c6cb8SMadhusudhan Chikkature 8518986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 852a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 853a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 854a45c6cb8SMadhusudhan Chikkature 85593caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 856a45c6cb8SMadhusudhan Chikkature 8574a694dc9SAdrian Hunter host->response_busy = 0; 858a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 859a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 860a45c6cb8SMadhusudhan Chikkature resptype = 1; 8614a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8624a694dc9SAdrian Hunter resptype = 3; 8634a694dc9SAdrian Hunter host->response_busy = 1; 8644a694dc9SAdrian Hunter } else 865a45c6cb8SMadhusudhan Chikkature resptype = 2; 866a45c6cb8SMadhusudhan Chikkature } 867a45c6cb8SMadhusudhan Chikkature 868a45c6cb8SMadhusudhan Chikkature /* 869a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 870a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 871a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 872a45c6cb8SMadhusudhan Chikkature */ 873a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 874a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 875a45c6cb8SMadhusudhan Chikkature 876a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 877a45c6cb8SMadhusudhan Chikkature 878a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 879a2e77152SBalaji T K host->mrq->sbc) { 880a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 881a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 882a2e77152SBalaji T K } 883a45c6cb8SMadhusudhan Chikkature if (data) { 884a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 885a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 886a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 887a45c6cb8SMadhusudhan Chikkature else 888a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 889a45c6cb8SMadhusudhan Chikkature } 890a45c6cb8SMadhusudhan Chikkature 891a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 892a7e96879SVenkatraman S cmdreg |= DMAE; 893a45c6cb8SMadhusudhan Chikkature 894b417577dSAdrian Hunter host->req_in_progress = 1; 8954dffd7a2SAdrian Hunter 896a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 897a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 898a45c6cb8SMadhusudhan Chikkature } 899a45c6cb8SMadhusudhan Chikkature 900c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 901c5c98927SRussell King struct mmc_data *data) 902c5c98927SRussell King { 903c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 904c5c98927SRussell King } 905c5c98927SRussell King 906b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 907b417577dSAdrian Hunter { 908b417577dSAdrian Hunter int dma_ch; 90931463b14SVenkatraman S unsigned long flags; 910b417577dSAdrian Hunter 91131463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 912b417577dSAdrian Hunter host->req_in_progress = 0; 913b417577dSAdrian Hunter dma_ch = host->dma_ch; 91431463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 915b417577dSAdrian Hunter 916b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 917b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 918b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 919b417577dSAdrian Hunter return; 920b417577dSAdrian Hunter host->mrq = NULL; 921b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 922b417577dSAdrian Hunter } 923b417577dSAdrian Hunter 924a45c6cb8SMadhusudhan Chikkature /* 925a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 926a45c6cb8SMadhusudhan Chikkature */ 927a45c6cb8SMadhusudhan Chikkature static void 92870a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 929a45c6cb8SMadhusudhan Chikkature { 9304a694dc9SAdrian Hunter if (!data) { 9314a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9324a694dc9SAdrian Hunter 93323050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 93423050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 93523050103SAdrian Hunter host->response_busy) { 93623050103SAdrian Hunter host->response_busy = 0; 93723050103SAdrian Hunter return; 93823050103SAdrian Hunter } 93923050103SAdrian Hunter 940b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9414a694dc9SAdrian Hunter return; 9424a694dc9SAdrian Hunter } 9434a694dc9SAdrian Hunter 944a45c6cb8SMadhusudhan Chikkature host->data = NULL; 945a45c6cb8SMadhusudhan Chikkature 946a45c6cb8SMadhusudhan Chikkature if (!data->error) 947a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 948a45c6cb8SMadhusudhan Chikkature else 949a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 950a45c6cb8SMadhusudhan Chikkature 951bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 952fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 953bf129e1cSBalaji T K else 954bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 955a45c6cb8SMadhusudhan Chikkature } 956a45c6cb8SMadhusudhan Chikkature 957a45c6cb8SMadhusudhan Chikkature /* 958a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 959a45c6cb8SMadhusudhan Chikkature */ 960a45c6cb8SMadhusudhan Chikkature static void 96170a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 962a45c6cb8SMadhusudhan Chikkature { 963bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 964a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9652177fa94SBalaji T K host->cmd = NULL; 966bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 967bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 968bf129e1cSBalaji T K host->mrq->data); 969bf129e1cSBalaji T K return; 970bf129e1cSBalaji T K } 971bf129e1cSBalaji T K 9722177fa94SBalaji T K host->cmd = NULL; 9732177fa94SBalaji T K 974a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 975a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 976a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 977a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 978a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 979a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 980a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 981a45c6cb8SMadhusudhan Chikkature } else { 982a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 983a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 984a45c6cb8SMadhusudhan Chikkature } 985a45c6cb8SMadhusudhan Chikkature } 986b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 987d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 988a45c6cb8SMadhusudhan Chikkature } 989a45c6cb8SMadhusudhan Chikkature 990a45c6cb8SMadhusudhan Chikkature /* 991a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 992a45c6cb8SMadhusudhan Chikkature */ 99370a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 994a45c6cb8SMadhusudhan Chikkature { 995b417577dSAdrian Hunter int dma_ch; 99631463b14SVenkatraman S unsigned long flags; 997b417577dSAdrian Hunter 99882788ff5SJarkko Lavinen host->data->error = errno; 999a45c6cb8SMadhusudhan Chikkature 100031463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1001b417577dSAdrian Hunter dma_ch = host->dma_ch; 1002b417577dSAdrian Hunter host->dma_ch = -1; 100331463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1004b417577dSAdrian Hunter 1005b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1006c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1007c5c98927SRussell King 1008c5c98927SRussell King dmaengine_terminate_all(chan); 1009c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1010c5c98927SRussell King host->data->sg, host->data->sg_len, 1011feeef096SHeiner Kallweit mmc_get_dma_dir(host->data)); 1012c5c98927SRussell King 1013053bf34fSPer Forlin host->data->host_cookie = 0; 1014a45c6cb8SMadhusudhan Chikkature } 1015a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1016a45c6cb8SMadhusudhan Chikkature } 1017a45c6cb8SMadhusudhan Chikkature 1018a45c6cb8SMadhusudhan Chikkature /* 1019a45c6cb8SMadhusudhan Chikkature * Readable error output 1020a45c6cb8SMadhusudhan Chikkature */ 1021a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1022699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1023a45c6cb8SMadhusudhan Chikkature { 1024a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 102570a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1026699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1027699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1028699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1029699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1030a45c6cb8SMadhusudhan Chikkature }; 1031a45c6cb8SMadhusudhan Chikkature char res[256]; 1032a45c6cb8SMadhusudhan Chikkature char *buf = res; 1033a45c6cb8SMadhusudhan Chikkature int len, i; 1034a45c6cb8SMadhusudhan Chikkature 1035a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1036a45c6cb8SMadhusudhan Chikkature buf += len; 1037a45c6cb8SMadhusudhan Chikkature 103870a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1039a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 104070a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1041a45c6cb8SMadhusudhan Chikkature buf += len; 1042a45c6cb8SMadhusudhan Chikkature } 1043a45c6cb8SMadhusudhan Chikkature 10448986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1045a45c6cb8SMadhusudhan Chikkature } 1046699b958bSAdrian Hunter #else 1047699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1048699b958bSAdrian Hunter u32 status) 1049699b958bSAdrian Hunter { 1050699b958bSAdrian Hunter } 1051a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1052a45c6cb8SMadhusudhan Chikkature 10533ebf74b1SJean Pihet /* 10543ebf74b1SJean Pihet * MMC controller internal state machines reset 10553ebf74b1SJean Pihet * 10563ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10573ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10583ebf74b1SJean Pihet * Can be called from interrupt context 10593ebf74b1SJean Pihet */ 106070a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10613ebf74b1SJean Pihet unsigned long bit) 10623ebf74b1SJean Pihet { 10633ebf74b1SJean Pihet unsigned long i = 0; 10641e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10653ebf74b1SJean Pihet 10663ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10673ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10683ebf74b1SJean Pihet 106907ad64b6SMadhusudhan Chikkature /* 107007ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 107107ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 107207ad64b6SMadhusudhan Chikkature */ 1073326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1074b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 107507ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10761e881786SJianpeng Ma udelay(1); 107707ad64b6SMadhusudhan Chikkature } 107807ad64b6SMadhusudhan Chikkature i = 0; 107907ad64b6SMadhusudhan Chikkature 10803ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10813ebf74b1SJean Pihet (i++ < limit)) 10821e881786SJianpeng Ma udelay(1); 10833ebf74b1SJean Pihet 10843ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10853ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10863ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10873ebf74b1SJean Pihet __func__); 10883ebf74b1SJean Pihet } 1089a45c6cb8SMadhusudhan Chikkature 109025e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 109125e1897bSBalaji T K int err, int end_cmd) 1092ae4bf788SVenkatraman S { 109325e1897bSBalaji T K if (end_cmd) { 109494d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 109525e1897bSBalaji T K if (host->cmd) 1096ae4bf788SVenkatraman S host->cmd->error = err; 109725e1897bSBalaji T K } 1098ae4bf788SVenkatraman S 1099ae4bf788SVenkatraman S if (host->data) { 1100ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1101ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1102dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1103dc7745bdSBalaji T K host->mrq->cmd->error = err; 1104ae4bf788SVenkatraman S } 1105ae4bf788SVenkatraman S 1106b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1107a45c6cb8SMadhusudhan Chikkature { 1108a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1109b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1110a2e77152SBalaji T K int error = 0; 1111a45c6cb8SMadhusudhan Chikkature 1112a45c6cb8SMadhusudhan Chikkature data = host->data; 11138986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1114a45c6cb8SMadhusudhan Chikkature 1115a7e96879SVenkatraman S if (status & ERR_EN) { 1116699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11174a694dc9SAdrian Hunter 111824380dd4SRavikumar Kattekola if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1119a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1120408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1121408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1122408806f7SKishon Vijay Abraham I host->response_busy = 0; 1123408806f7SKishon Vijay Abraham I } 1124a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 112525e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11265027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11275027cd1eSVignesh R BADA_EN)) 112825e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 112925e1897bSBalaji T K 1130a2e77152SBalaji T K if (status & ACE_EN) { 1131a2e77152SBalaji T K u32 ac12; 1132a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1133a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1134a2e77152SBalaji T K end_cmd = 1; 1135a2e77152SBalaji T K if (ac12 & ACTO) 1136a2e77152SBalaji T K error = -ETIMEDOUT; 1137a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1138a2e77152SBalaji T K error = -EILSEQ; 1139a2e77152SBalaji T K host->mrq->sbc->error = error; 1140a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1141a2e77152SBalaji T K } 1142a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1143a2e77152SBalaji T K } 1144a45c6cb8SMadhusudhan Chikkature } 1145a45c6cb8SMadhusudhan Chikkature 11467472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1147a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 114870a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1149a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 115070a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1151b417577dSAdrian Hunter } 1152a45c6cb8SMadhusudhan Chikkature 1153b417577dSAdrian Hunter /* 1154b417577dSAdrian Hunter * MMC controller IRQ handler 1155b417577dSAdrian Hunter */ 1156b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1157b417577dSAdrian Hunter { 1158b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1159b417577dSAdrian Hunter int status; 1160b417577dSAdrian Hunter 1161b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11622cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11632cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1164b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11651f6b9fa4SVenkatraman S 11662cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11672cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11682cd3a2a5SAndreas Fenkart 1169b417577dSAdrian Hunter /* Flush posted write */ 1170b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11711f6b9fa4SVenkatraman S } 11724dffd7a2SAdrian Hunter 1173a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1174a45c6cb8SMadhusudhan Chikkature } 1175a45c6cb8SMadhusudhan Chikkature 117670a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1177e13bb300SAdrian Hunter { 1178e13bb300SAdrian Hunter unsigned long i; 1179e13bb300SAdrian Hunter 1180e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1181e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1182e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1183e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1184e13bb300SAdrian Hunter break; 1185e13bb300SAdrian Hunter cpu_relax(); 1186e13bb300SAdrian Hunter } 1187e13bb300SAdrian Hunter } 1188e13bb300SAdrian Hunter 1189a45c6cb8SMadhusudhan Chikkature /* 1190eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1191eb250826SDavid Brownell * 1192eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1193eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1194eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1195a45c6cb8SMadhusudhan Chikkature */ 119670a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1197a45c6cb8SMadhusudhan Chikkature { 1198a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1199a45c6cb8SMadhusudhan Chikkature int ret; 1200a45c6cb8SMadhusudhan Chikkature 1201a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1202cd03d9a8SRajendra Nayak if (host->dbclk) 120394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1204a45c6cb8SMadhusudhan Chikkature 1205a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 120666162becSKishon Vijay Abraham I ret = omap_hsmmc_set_power(host, 0); 1207a45c6cb8SMadhusudhan Chikkature 1208a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12092bec0893SAdrian Hunter if (!ret) 121066162becSKishon Vijay Abraham I ret = omap_hsmmc_set_power(host, 1); 1211cd03d9a8SRajendra Nayak if (host->dbclk) 121294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12132bec0893SAdrian Hunter 1214a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1215a45c6cb8SMadhusudhan Chikkature goto err; 1216a45c6cb8SMadhusudhan Chikkature 1217a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1218a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1219a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1220eb250826SDavid Brownell 1221a45c6cb8SMadhusudhan Chikkature /* 1222a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1223a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 122470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1225a45c6cb8SMadhusudhan Chikkature * 1226eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1227eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1228eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1229eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1230eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1231eb250826SDavid Brownell * 1232eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1233eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1234eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1235a45c6cb8SMadhusudhan Chikkature */ 1236eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1237a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1238eb250826SDavid Brownell else 1239eb250826SDavid Brownell reg_val |= SDVS30; 1240a45c6cb8SMadhusudhan Chikkature 1241a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1242e13bb300SAdrian Hunter set_sd_bus_power(host); 1243a45c6cb8SMadhusudhan Chikkature 1244a45c6cb8SMadhusudhan Chikkature return 0; 1245a45c6cb8SMadhusudhan Chikkature err: 1246b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1247a45c6cb8SMadhusudhan Chikkature return ret; 1248a45c6cb8SMadhusudhan Chikkature } 1249a45c6cb8SMadhusudhan Chikkature 1250b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1251b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1252b62f6228SAdrian Hunter { 1253b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1254b62f6228SAdrian Hunter return; 1255b62f6228SAdrian Hunter 1256b62f6228SAdrian Hunter host->reqs_blocked = 0; 125780412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1258b62f6228SAdrian Hunter if (host->protect_card) { 12592cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1260b62f6228SAdrian Hunter "card is now accessible\n", 1261b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1262b62f6228SAdrian Hunter host->protect_card = 0; 1263b62f6228SAdrian Hunter } 1264b62f6228SAdrian Hunter } else { 1265b62f6228SAdrian Hunter if (!host->protect_card) { 12662cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1267b62f6228SAdrian Hunter "card is now inaccessible\n", 1268b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1269b62f6228SAdrian Hunter host->protect_card = 1; 1270b62f6228SAdrian Hunter } 1271b62f6228SAdrian Hunter } 1272b62f6228SAdrian Hunter } 1273b62f6228SAdrian Hunter 1274a45c6cb8SMadhusudhan Chikkature /* 1275cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1276cde592cbSAndreas Fenkart */ 1277cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1278cde592cbSAndreas Fenkart { 1279cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1280cde592cbSAndreas Fenkart 1281cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1282cde592cbSAndreas Fenkart 1283cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1284cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1285cde592cbSAndreas Fenkart return IRQ_HANDLED; 1286cde592cbSAndreas Fenkart } 1287cde592cbSAndreas Fenkart 1288c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12890ccd76d4SJuha Yrjola { 1290c5c98927SRussell King struct omap_hsmmc_host *host = param; 1291c5c98927SRussell King struct dma_chan *chan; 1292770d7432SAdrian Hunter struct mmc_data *data; 1293c5c98927SRussell King int req_in_progress; 1294a45c6cb8SMadhusudhan Chikkature 1295c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1296b417577dSAdrian Hunter if (host->dma_ch < 0) { 1297c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1298a45c6cb8SMadhusudhan Chikkature return; 1299b417577dSAdrian Hunter } 1300a45c6cb8SMadhusudhan Chikkature 1301770d7432SAdrian Hunter data = host->mrq->data; 1302c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13039782aff8SPer Forlin if (!data->host_cookie) 1304c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1305c5c98927SRussell King data->sg, data->sg_len, 1306feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 1307b417577dSAdrian Hunter 1308b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1309a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1310c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1311b417577dSAdrian Hunter 1312b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1313b417577dSAdrian Hunter if (!req_in_progress) { 1314b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1315b417577dSAdrian Hunter 1316b417577dSAdrian Hunter host->mrq = NULL; 1317b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1318b417577dSAdrian Hunter } 1319a45c6cb8SMadhusudhan Chikkature } 1320a45c6cb8SMadhusudhan Chikkature 13219782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13229782aff8SPer Forlin struct mmc_data *data, 1323c5c98927SRussell King struct omap_hsmmc_next *next, 132426b88520SRussell King struct dma_chan *chan) 13259782aff8SPer Forlin { 13269782aff8SPer Forlin int dma_len; 13279782aff8SPer Forlin 13289782aff8SPer Forlin if (!next && data->host_cookie && 13299782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13302cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13319782aff8SPer Forlin " host->next_data.cookie %d\n", 13329782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13339782aff8SPer Forlin data->host_cookie = 0; 13349782aff8SPer Forlin } 13359782aff8SPer Forlin 13369782aff8SPer Forlin /* Check if next job is already prepared */ 1337b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 133826b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1339feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 13409782aff8SPer Forlin 13419782aff8SPer Forlin } else { 13429782aff8SPer Forlin dma_len = host->next_data.dma_len; 13439782aff8SPer Forlin host->next_data.dma_len = 0; 13449782aff8SPer Forlin } 13459782aff8SPer Forlin 13469782aff8SPer Forlin 13479782aff8SPer Forlin if (dma_len == 0) 13489782aff8SPer Forlin return -EINVAL; 13499782aff8SPer Forlin 13509782aff8SPer Forlin if (next) { 13519782aff8SPer Forlin next->dma_len = dma_len; 13529782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13539782aff8SPer Forlin } else 13549782aff8SPer Forlin host->dma_len = dma_len; 13559782aff8SPer Forlin 13569782aff8SPer Forlin return 0; 13579782aff8SPer Forlin } 13589782aff8SPer Forlin 1359a45c6cb8SMadhusudhan Chikkature /* 1360a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1361a45c6cb8SMadhusudhan Chikkature */ 13629d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 136370a3341aSDenis Karpov struct mmc_request *req) 1364a45c6cb8SMadhusudhan Chikkature { 136526b88520SRussell King struct dma_async_tx_descriptor *tx; 136626b88520SRussell King int ret = 0, i; 1367a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1368c5c98927SRussell King struct dma_chan *chan; 1369e5789608SPeter Ujfalusi struct dma_slave_config cfg = { 1370e5789608SPeter Ujfalusi .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1371e5789608SPeter Ujfalusi .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1372e5789608SPeter Ujfalusi .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1373e5789608SPeter Ujfalusi .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1374e5789608SPeter Ujfalusi .src_maxburst = data->blksz / 4, 1375e5789608SPeter Ujfalusi .dst_maxburst = data->blksz / 4, 1376e5789608SPeter Ujfalusi }; 1377a45c6cb8SMadhusudhan Chikkature 13780ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1379a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13800ccd76d4SJuha Yrjola struct scatterlist *sgl; 13810ccd76d4SJuha Yrjola 13820ccd76d4SJuha Yrjola sgl = data->sg + i; 13830ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13840ccd76d4SJuha Yrjola return -EINVAL; 13850ccd76d4SJuha Yrjola } 13860ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13870ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13880ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13890ccd76d4SJuha Yrjola */ 13900ccd76d4SJuha Yrjola return -EINVAL; 13910ccd76d4SJuha Yrjola 1392b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1393a45c6cb8SMadhusudhan Chikkature 1394c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1395c5c98927SRussell King 1396c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13979782aff8SPer Forlin if (ret) 13989782aff8SPer Forlin return ret; 1399a45c6cb8SMadhusudhan Chikkature 140026b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1401c5c98927SRussell King if (ret) 1402c5c98927SRussell King return ret; 1403a45c6cb8SMadhusudhan Chikkature 1404c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1405c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1406c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1407c5c98927SRussell King if (!tx) { 1408c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1409c5c98927SRussell King /* FIXME: cleanup */ 1410c5c98927SRussell King return -1; 1411c5c98927SRussell King } 1412c5c98927SRussell King 1413c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1414c5c98927SRussell King tx->callback_param = host; 1415c5c98927SRussell King 1416c5c98927SRussell King /* Does not fail */ 1417c5c98927SRussell King dmaengine_submit(tx); 1418c5c98927SRussell King 141926b88520SRussell King host->dma_ch = 1; 1420c5c98927SRussell King 1421a45c6cb8SMadhusudhan Chikkature return 0; 1422a45c6cb8SMadhusudhan Chikkature } 1423a45c6cb8SMadhusudhan Chikkature 142470a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1425a53210f5SRavikumar Kattekola unsigned long long timeout_ns, 1426e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1427a45c6cb8SMadhusudhan Chikkature { 1428a53210f5SRavikumar Kattekola unsigned long long timeout = timeout_ns; 1429a53210f5SRavikumar Kattekola unsigned int cycle_ns; 1430a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1431a45c6cb8SMadhusudhan Chikkature 1432a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1433a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1434a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1435a45c6cb8SMadhusudhan Chikkature clkd = 1; 1436a45c6cb8SMadhusudhan Chikkature 14376e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1438a53210f5SRavikumar Kattekola do_div(timeout, cycle_ns); 1439e2bf08d6SAdrian Hunter timeout += timeout_clks; 1440a45c6cb8SMadhusudhan Chikkature if (timeout) { 1441a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1442a45c6cb8SMadhusudhan Chikkature dto += 1; 1443a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1444a45c6cb8SMadhusudhan Chikkature } 1445a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1446a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1447a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1448a45c6cb8SMadhusudhan Chikkature dto += 1; 1449a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1450a45c6cb8SMadhusudhan Chikkature dto -= 13; 1451a45c6cb8SMadhusudhan Chikkature else 1452a45c6cb8SMadhusudhan Chikkature dto = 0; 1453a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1454a45c6cb8SMadhusudhan Chikkature dto = 14; 1455a45c6cb8SMadhusudhan Chikkature } 1456a45c6cb8SMadhusudhan Chikkature 1457a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1458a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1459a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1460a45c6cb8SMadhusudhan Chikkature } 1461a45c6cb8SMadhusudhan Chikkature 14629d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14639d025334SBalaji T K { 14649d025334SBalaji T K struct mmc_request *req = host->mrq; 14659d025334SBalaji T K struct dma_chan *chan; 14669d025334SBalaji T K 14679d025334SBalaji T K if (!req->data) 14689d025334SBalaji T K return; 14699d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14709d025334SBalaji T K | (req->data->blocks << 16)); 14719d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14729d025334SBalaji T K req->data->timeout_clks); 14739d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14749d025334SBalaji T K dma_async_issue_pending(chan); 14759d025334SBalaji T K } 14769d025334SBalaji T K 1477a45c6cb8SMadhusudhan Chikkature /* 1478a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1479a45c6cb8SMadhusudhan Chikkature */ 1480a45c6cb8SMadhusudhan Chikkature static int 148170a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1482a45c6cb8SMadhusudhan Chikkature { 1483a45c6cb8SMadhusudhan Chikkature int ret; 1484a53210f5SRavikumar Kattekola unsigned long long timeout; 14858cc9a3e7SKishon Vijay Abraham I 1486a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1487a45c6cb8SMadhusudhan Chikkature 1488a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1489a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 14908cc9a3e7SKishon Vijay Abraham I if (req->cmd->flags & MMC_RSP_BUSY) { 14918cc9a3e7SKishon Vijay Abraham I timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 14928cc9a3e7SKishon Vijay Abraham I 1493e2bf08d6SAdrian Hunter /* 1494e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 14958cc9a3e7SKishon Vijay Abraham I * busy signal and no indication of busy_timeout. 1496e2bf08d6SAdrian Hunter */ 14978cc9a3e7SKishon Vijay Abraham I if (!timeout) 14988cc9a3e7SKishon Vijay Abraham I timeout = 100000000U; 14998cc9a3e7SKishon Vijay Abraham I 15008cc9a3e7SKishon Vijay Abraham I set_data_timeout(host, timeout, 0); 15018cc9a3e7SKishon Vijay Abraham I } 1502a45c6cb8SMadhusudhan Chikkature return 0; 1503a45c6cb8SMadhusudhan Chikkature } 1504a45c6cb8SMadhusudhan Chikkature 1505a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15069d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1507a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1508b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1509a45c6cb8SMadhusudhan Chikkature return ret; 1510a45c6cb8SMadhusudhan Chikkature } 1511a45c6cb8SMadhusudhan Chikkature } 1512a45c6cb8SMadhusudhan Chikkature return 0; 1513a45c6cb8SMadhusudhan Chikkature } 1514a45c6cb8SMadhusudhan Chikkature 15159782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15169782aff8SPer Forlin int err) 15179782aff8SPer Forlin { 15189782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15199782aff8SPer Forlin struct mmc_data *data = mrq->data; 15209782aff8SPer Forlin 152126b88520SRussell King if (host->use_dma && data->host_cookie) { 1522c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1523c5c98927SRussell King 152426b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1525feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 15269782aff8SPer Forlin data->host_cookie = 0; 15279782aff8SPer Forlin } 15289782aff8SPer Forlin } 15299782aff8SPer Forlin 1530d3c6aac3SLinus Walleij static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 15319782aff8SPer Forlin { 15329782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15339782aff8SPer Forlin 15349782aff8SPer Forlin if (mrq->data->host_cookie) { 15359782aff8SPer Forlin mrq->data->host_cookie = 0; 15369782aff8SPer Forlin return ; 15379782aff8SPer Forlin } 15389782aff8SPer Forlin 1539c5c98927SRussell King if (host->use_dma) { 1540c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1541c5c98927SRussell King 15429782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 154326b88520SRussell King &host->next_data, c)) 15449782aff8SPer Forlin mrq->data->host_cookie = 0; 15459782aff8SPer Forlin } 1546c5c98927SRussell King } 15479782aff8SPer Forlin 1548a45c6cb8SMadhusudhan Chikkature /* 1549a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1550a45c6cb8SMadhusudhan Chikkature */ 155170a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1552a45c6cb8SMadhusudhan Chikkature { 155370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1554a3f406f8SJarkko Lavinen int err; 1555a45c6cb8SMadhusudhan Chikkature 1556b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1557b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1558b62f6228SAdrian Hunter if (host->protect_card) { 1559b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1560b62f6228SAdrian Hunter /* 1561b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1562b62f6228SAdrian Hunter * state by resetting the command and data state 1563b62f6228SAdrian Hunter * machines. 1564b62f6228SAdrian Hunter */ 1565b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1566b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1567b62f6228SAdrian Hunter host->reqs_blocked += 1; 1568b62f6228SAdrian Hunter } 1569b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1570b62f6228SAdrian Hunter if (req->data) 1571b62f6228SAdrian Hunter req->data->error = -EBADF; 1572b417577dSAdrian Hunter req->cmd->retries = 0; 1573b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1574b62f6228SAdrian Hunter return; 1575b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1576b62f6228SAdrian Hunter host->reqs_blocked = 0; 1577a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1578a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15796e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 158070a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1581a3f406f8SJarkko Lavinen if (err) { 1582a3f406f8SJarkko Lavinen req->cmd->error = err; 1583a3f406f8SJarkko Lavinen if (req->data) 1584a3f406f8SJarkko Lavinen req->data->error = err; 1585a3f406f8SJarkko Lavinen host->mrq = NULL; 1586a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1587a3f406f8SJarkko Lavinen return; 1588a3f406f8SJarkko Lavinen } 1589a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1590bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1591bf129e1cSBalaji T K return; 1592bf129e1cSBalaji T K } 1593a3f406f8SJarkko Lavinen 15949d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 159570a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1596a45c6cb8SMadhusudhan Chikkature } 1597a45c6cb8SMadhusudhan Chikkature 1598a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 159970a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1600a45c6cb8SMadhusudhan Chikkature { 160170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1602a3621465SAdrian Hunter int do_send_init_stream = 0; 1603a45c6cb8SMadhusudhan Chikkature 1604a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1605a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1606a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 160766162becSKishon Vijay Abraham I omap_hsmmc_set_power(host, 0); 1608a45c6cb8SMadhusudhan Chikkature break; 1609a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 161066162becSKishon Vijay Abraham I omap_hsmmc_set_power(host, 1); 1611a45c6cb8SMadhusudhan Chikkature break; 1612a3621465SAdrian Hunter case MMC_POWER_ON: 1613a3621465SAdrian Hunter do_send_init_stream = 1; 1614a3621465SAdrian Hunter break; 1615a3621465SAdrian Hunter } 1616a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1617a45c6cb8SMadhusudhan Chikkature } 1618a45c6cb8SMadhusudhan Chikkature 1619dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1620dd498effSDenis Karpov 16213796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1622a45c6cb8SMadhusudhan Chikkature 16234621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1624eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1625eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1626eb250826SDavid Brownell */ 1627a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16282cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1629a45c6cb8SMadhusudhan Chikkature /* 1630a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1631a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1632a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1633a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1634a45c6cb8SMadhusudhan Chikkature */ 163570a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1636a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1637a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1638a45c6cb8SMadhusudhan Chikkature } 1639a45c6cb8SMadhusudhan Chikkature } 1640a45c6cb8SMadhusudhan Chikkature 16415934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1642a45c6cb8SMadhusudhan Chikkature 1643a3621465SAdrian Hunter if (do_send_init_stream) 1644a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1645a45c6cb8SMadhusudhan Chikkature 16463796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 1647a45c6cb8SMadhusudhan Chikkature } 1648a45c6cb8SMadhusudhan Chikkature 1649a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1650a45c6cb8SMadhusudhan Chikkature { 165170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1652a45c6cb8SMadhusudhan Chikkature 1653b5cd43f0SAndreas Fenkart if (!host->card_detect) 1654a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 165580412ca8SAndreas Fenkart return host->card_detect(host->dev); 1656a45c6cb8SMadhusudhan Chikkature } 1657a45c6cb8SMadhusudhan Chikkature 16584816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16594816858cSGrazvydas Ignotas { 16604816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16614816858cSGrazvydas Ignotas 1662326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1663326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16644816858cSGrazvydas Ignotas } 16654816858cSGrazvydas Ignotas 16662cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16672cd3a2a5SAndreas Fenkart { 16682cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16695a52b08bSBalaji T K u32 irq_mask, con; 16702cd3a2a5SAndreas Fenkart unsigned long flags; 16712cd3a2a5SAndreas Fenkart 16722cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16732cd3a2a5SAndreas Fenkart 16745a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16752cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16762cd3a2a5SAndreas Fenkart if (enable) { 16772cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16782cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16795a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16802cd3a2a5SAndreas Fenkart } else { 16812cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16822cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16835a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 16842cd3a2a5SAndreas Fenkart } 16855a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 16862cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 16872cd3a2a5SAndreas Fenkart 16882cd3a2a5SAndreas Fenkart /* 16892cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 16902cd3a2a5SAndreas Fenkart * but always disable immediately 16912cd3a2a5SAndreas Fenkart */ 16922cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 16932cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 16942cd3a2a5SAndreas Fenkart 16952cd3a2a5SAndreas Fenkart /* flush posted write */ 16962cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 16972cd3a2a5SAndreas Fenkart 16982cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 16992cd3a2a5SAndreas Fenkart } 17002cd3a2a5SAndreas Fenkart 17012cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17022cd3a2a5SAndreas Fenkart { 17032cd3a2a5SAndreas Fenkart int ret; 17042cd3a2a5SAndreas Fenkart 17052cd3a2a5SAndreas Fenkart /* 17062cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17072cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17082cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17092cd3a2a5SAndreas Fenkart * with functional clock disabled. 17102cd3a2a5SAndreas Fenkart */ 17112cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17122cd3a2a5SAndreas Fenkart return -ENODEV; 17132cd3a2a5SAndreas Fenkart 17145b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17152cd3a2a5SAndreas Fenkart if (ret) { 17162cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17172cd3a2a5SAndreas Fenkart goto err; 17182cd3a2a5SAndreas Fenkart } 17192cd3a2a5SAndreas Fenkart 17202cd3a2a5SAndreas Fenkart /* 17212cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17222cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17232cd3a2a5SAndreas Fenkart */ 17242cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1725455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1726ec5ab893SDan Carpenter if (IS_ERR(p)) { 1727ec5ab893SDan Carpenter ret = PTR_ERR(p); 1728455e5cd6SAndreas Fenkart goto err_free_irq; 1729455e5cd6SAndreas Fenkart } 1730455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1731455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1732455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1733455e5cd6SAndreas Fenkart ret = -EINVAL; 1734455e5cd6SAndreas Fenkart goto err_free_irq; 1735455e5cd6SAndreas Fenkart } 1736455e5cd6SAndreas Fenkart 1737455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1738455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1739455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1740455e5cd6SAndreas Fenkart ret = -EINVAL; 1741455e5cd6SAndreas Fenkart goto err_free_irq; 1742455e5cd6SAndreas Fenkart } 1743455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17442cd3a2a5SAndreas Fenkart } 17452cd3a2a5SAndreas Fenkart 17465a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17475a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17482cd3a2a5SAndreas Fenkart return 0; 17492cd3a2a5SAndreas Fenkart 1750455e5cd6SAndreas Fenkart err_free_irq: 17515b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17522cd3a2a5SAndreas Fenkart err: 17532cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17542cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17552cd3a2a5SAndreas Fenkart return ret; 17562cd3a2a5SAndreas Fenkart } 17572cd3a2a5SAndreas Fenkart 175870a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17591b331e69SKim Kyuwon { 17601b331e69SKim Kyuwon u32 hctl, capa, value; 17611b331e69SKim Kyuwon 17621b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17634621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17641b331e69SKim Kyuwon hctl = SDVS30; 17651b331e69SKim Kyuwon capa = VS30 | VS18; 17661b331e69SKim Kyuwon } else { 17671b331e69SKim Kyuwon hctl = SDVS18; 17681b331e69SKim Kyuwon capa = VS18; 17691b331e69SKim Kyuwon } 17701b331e69SKim Kyuwon 17711b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17721b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17731b331e69SKim Kyuwon 17741b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17751b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17761b331e69SKim Kyuwon 17771b331e69SKim Kyuwon /* Set SD bus power bit */ 1778e13bb300SAdrian Hunter set_sd_bus_power(host); 17791b331e69SKim Kyuwon } 17801b331e69SKim Kyuwon 1781afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1782afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1783afd8c29dSKuninori Morimoto { 1784afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1785afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1786afd8c29dSKuninori Morimoto return 1; 1787afd8c29dSKuninori Morimoto 1788afd8c29dSKuninori Morimoto return blk_size; 1789afd8c29dSKuninori Morimoto } 1790afd8c29dSKuninori Morimoto 1791afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 17929782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17939782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 179470a3341aSDenis Karpov .request = omap_hsmmc_request, 179570a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1796dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1797a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 17984816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 17992cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1800dd498effSDenis Karpov }; 1801dd498effSDenis Karpov 1802d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1803d900f712SDenis Karpov 180470a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1805d900f712SDenis Karpov { 1806d900f712SDenis Karpov struct mmc_host *mmc = s->private; 180770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 180811dd62a7SDenis Karpov 1809bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1810bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1811bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1812bb0635f0SAndreas Fenkart 1813bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1814bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1815bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1816bb0635f0SAndreas Fenkart : "disabled"); 1817bb0635f0SAndreas Fenkart } 1818bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18195e2ea617SAdrian Hunter 1820fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1821bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1822d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1823d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1824bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1825bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1826d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1827d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1828d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1829d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1830d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1831d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1832d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1833d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1834d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1835d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18365e2ea617SAdrian Hunter 1837fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1838fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1839dd498effSDenis Karpov 1840d900f712SDenis Karpov return 0; 1841d900f712SDenis Karpov } 1842d900f712SDenis Karpov 184370a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1844d900f712SDenis Karpov { 184570a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1846d900f712SDenis Karpov } 1847d900f712SDenis Karpov 1848d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 184970a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1850d900f712SDenis Karpov .read = seq_read, 1851d900f712SDenis Karpov .llseek = seq_lseek, 1852d900f712SDenis Karpov .release = single_release, 1853d900f712SDenis Karpov }; 1854d900f712SDenis Karpov 185570a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1856d900f712SDenis Karpov { 1857d900f712SDenis Karpov if (mmc->debugfs_root) 1858d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1859d900f712SDenis Karpov mmc, &mmc_regs_fops); 1860d900f712SDenis Karpov } 1861d900f712SDenis Karpov 1862d900f712SDenis Karpov #else 1863d900f712SDenis Karpov 186470a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1865d900f712SDenis Karpov { 1866d900f712SDenis Karpov } 1867d900f712SDenis Karpov 1868d900f712SDenis Karpov #endif 1869d900f712SDenis Karpov 187046856a68SRajendra Nayak #ifdef CONFIG_OF 187159445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 187259445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 187359445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 187459445b10SNishanth Menon }; 187559445b10SNishanth Menon 187659445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 187759445b10SNishanth Menon .reg_offset = 0x100, 187859445b10SNishanth Menon }; 18792cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18802cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18812cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18822cd3a2a5SAndreas Fenkart }; 188346856a68SRajendra Nayak 188446856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 188546856a68SRajendra Nayak { 188646856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 188746856a68SRajendra Nayak }, 188846856a68SRajendra Nayak { 188959445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 189059445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 189159445b10SNishanth Menon }, 189259445b10SNishanth Menon { 189346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 189446856a68SRajendra Nayak }, 189546856a68SRajendra Nayak { 189646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 189759445b10SNishanth Menon .data = &omap4_mmc_of_data, 189846856a68SRajendra Nayak }, 18992cd3a2a5SAndreas Fenkart { 19002cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19012cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19022cd3a2a5SAndreas Fenkart }, 190346856a68SRajendra Nayak {}, 1904b6d085f6SChris Ball }; 190546856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 190646856a68SRajendra Nayak 190755143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 190846856a68SRajendra Nayak { 1909db863d89STony Lindgren struct omap_hsmmc_platform_data *pdata, *legacy; 191046856a68SRajendra Nayak struct device_node *np = dev->of_node; 191146856a68SRajendra Nayak 191246856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 191346856a68SRajendra Nayak if (!pdata) 191419df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 191546856a68SRajendra Nayak 1916db863d89STony Lindgren legacy = dev_get_platdata(dev); 1917db863d89STony Lindgren if (legacy && legacy->name) 1918db863d89STony Lindgren pdata->name = legacy->name; 1919db863d89STony Lindgren 192046856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 192146856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 192246856a68SRajendra Nayak 1923b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1924b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1925fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 192646856a68SRajendra Nayak 192746856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1928326119c9SAndreas Fenkart pdata->nonremovable = true; 1929326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 193046856a68SRajendra Nayak } 193146856a68SRajendra Nayak 193246856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1933326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 193446856a68SRajendra Nayak 1935cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1936326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1937cd587096SHebbar, Gururaja 193846856a68SRajendra Nayak return pdata; 193946856a68SRajendra Nayak } 194046856a68SRajendra Nayak #else 194155143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 194246856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 194346856a68SRajendra Nayak { 194419df45bcSBalaji T K return ERR_PTR(-EINVAL); 194546856a68SRajendra Nayak } 194646856a68SRajendra Nayak #endif 194746856a68SRajendra Nayak 1948c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1949a45c6cb8SMadhusudhan Chikkature { 195055143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1951a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 195270a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1953a45c6cb8SMadhusudhan Chikkature struct resource *res; 1954db0fefc5SAdrian Hunter int ret, irq; 195546856a68SRajendra Nayak const struct of_device_id *match; 195659445b10SNishanth Menon const struct omap_mmc_of_data *data; 195777fae219SBalaji T K void __iomem *base; 195846856a68SRajendra Nayak 195946856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 196046856a68SRajendra Nayak if (match) { 196146856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1962dc642c28SJan Luebbe 1963dc642c28SJan Luebbe if (IS_ERR(pdata)) 1964dc642c28SJan Luebbe return PTR_ERR(pdata); 1965dc642c28SJan Luebbe 196646856a68SRajendra Nayak if (match->data) { 196759445b10SNishanth Menon data = match->data; 196859445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 196959445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 197046856a68SRajendra Nayak } 197146856a68SRajendra Nayak } 1972a45c6cb8SMadhusudhan Chikkature 1973a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1974a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1975a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1976a45c6cb8SMadhusudhan Chikkature } 1977a45c6cb8SMadhusudhan Chikkature 1978a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1979a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1980a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1981a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1982a45c6cb8SMadhusudhan Chikkature 198377fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 198477fae219SBalaji T K if (IS_ERR(base)) 198577fae219SBalaji T K return PTR_ERR(base); 1986a45c6cb8SMadhusudhan Chikkature 198770a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1988a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1989a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 19901e363e3bSAndreas Fenkart goto err; 1991a45c6cb8SMadhusudhan Chikkature } 1992a45c6cb8SMadhusudhan Chikkature 1993fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 1994fdb9de12SNeilBrown if (ret) 1995fdb9de12SNeilBrown goto err1; 1996fdb9de12SNeilBrown 1997a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1998a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1999a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2000a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2001a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2002a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2003a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2004fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 200577fae219SBalaji T K host->base = base + pdata->reg_offset; 20066da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20079782aff8SPer Forlin host->next_data.cookie = 1; 2008bb2726b5STony Lindgren host->pbias_enabled = 0; 20093f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2010a45c6cb8SMadhusudhan Chikkature 201141afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20121e363e3bSAndreas Fenkart if (ret) 20131e363e3bSAndreas Fenkart goto err_gpio; 20141e363e3bSAndreas Fenkart 2015a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2016a45c6cb8SMadhusudhan Chikkature 20172cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20182cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20192cd3a2a5SAndreas Fenkart 202070a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2021dd498effSDenis Karpov 20226b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2023d418ed87SDaniel Mack 2024d418ed87SDaniel Mack if (pdata->max_freq > 0) 2025d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2026fdb9de12SNeilBrown else if (mmc->f_max == 0) 20276b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2028a45c6cb8SMadhusudhan Chikkature 20294dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2030a45c6cb8SMadhusudhan Chikkature 20319618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2032a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2033a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2034a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2035a45c6cb8SMadhusudhan Chikkature goto err1; 2036a45c6cb8SMadhusudhan Chikkature } 2037a45c6cb8SMadhusudhan Chikkature 20389b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20399b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2040afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20419b68256cSPaul Walmsley } 2042dd498effSDenis Karpov 20435b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2044fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2045fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2046fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2047fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2048a45c6cb8SMadhusudhan Chikkature 204992a3aebfSBalaji T K omap_hsmmc_context_save(host); 205092a3aebfSBalaji T K 20519618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2052a45c6cb8SMadhusudhan Chikkature /* 2053a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2054a45c6cb8SMadhusudhan Chikkature */ 2055cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2056cd03d9a8SRajendra Nayak host->dbclk = NULL; 205794c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2058cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2059cd03d9a8SRajendra Nayak host->dbclk = NULL; 20602bec0893SAdrian Hunter } 2061a45c6cb8SMadhusudhan Chikkature 206294424004SWill Newton /* Set this to a value that allows allocating an entire descriptor 206394424004SWill Newton * list within a page (zero order allocation). */ 206494424004SWill Newton mmc->max_segs = 64; 20650ccd76d4SJuha Yrjola 2066a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2067a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2068a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2069a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2070a45c6cb8SMadhusudhan Chikkature 207113189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2072ac2b2115SKishon Vijay Abraham I MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; 2073a45c6cb8SMadhusudhan Chikkature 2074326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20753a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2076a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2077a45c6cb8SMadhusudhan Chikkature 2078326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 207923d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 208023d99bb9SAdrian Hunter 2081fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 20826fdc75deSEliad Peller 208370a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2084a45c6cb8SMadhusudhan Chikkature 208581eef6caSPeter Ujfalusi host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 208681eef6caSPeter Ujfalusi if (IS_ERR(host->rx_chan)) { 208781eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 208881eef6caSPeter Ujfalusi ret = PTR_ERR(host->rx_chan); 208926b88520SRussell King goto err_irq; 2090c5c98927SRussell King } 209126b88520SRussell King 209281eef6caSPeter Ujfalusi host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 209381eef6caSPeter Ujfalusi if (IS_ERR(host->tx_chan)) { 209481eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 209581eef6caSPeter Ujfalusi ret = PTR_ERR(host->tx_chan); 209626b88520SRussell King goto err_irq; 2097c5c98927SRussell King } 2098a45c6cb8SMadhusudhan Chikkature 2099a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2100e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2101a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2102a45c6cb8SMadhusudhan Chikkature if (ret) { 2103b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2104a45c6cb8SMadhusudhan Chikkature goto err_irq; 2105a45c6cb8SMadhusudhan Chikkature } 2106a45c6cb8SMadhusudhan Chikkature 2107db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2108db0fefc5SAdrian Hunter if (ret) 2109bb09d151SAndreas Fenkart goto err_irq; 2110db0fefc5SAdrian Hunter 211113ab2a66SKishon Vijay Abraham I if (!mmc->ocr_avail) 2112326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2113a45c6cb8SMadhusudhan Chikkature 2114b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2115a45c6cb8SMadhusudhan Chikkature 21162cd3a2a5SAndreas Fenkart /* 21172cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21182cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21192cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21202cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21212cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21222cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21232cd3a2a5SAndreas Fenkart */ 21242cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21252cd3a2a5SAndreas Fenkart if (!ret) 21262cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21272cd3a2a5SAndreas Fenkart 2128b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2129b62f6228SAdrian Hunter 2130a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2131a45c6cb8SMadhusudhan Chikkature 2132326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2133a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2134a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2135a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2136a45c6cb8SMadhusudhan Chikkature } 2137cde592cbSAndreas Fenkart if (host->get_cover_state) { 2138a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2139a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2140a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2141db0fefc5SAdrian Hunter goto err_slot_name; 2142a45c6cb8SMadhusudhan Chikkature } 2143a45c6cb8SMadhusudhan Chikkature 214470a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2145fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2146fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2147d900f712SDenis Karpov 2148a45c6cb8SMadhusudhan Chikkature return 0; 2149a45c6cb8SMadhusudhan Chikkature 2150a45c6cb8SMadhusudhan Chikkature err_slot_name: 2151a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2152a45c6cb8SMadhusudhan Chikkature err_irq: 21535b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 215481eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->tx_chan)) 2155c5c98927SRussell King dma_release_channel(host->tx_chan); 215681eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->rx_chan)) 2157c5c98927SRussell King dma_release_channel(host->rx_chan); 2158814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2159d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 216037f6190dSTony Lindgren pm_runtime_disable(host->dev); 21619618195eSBalaji T K if (host->dbclk) 216294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2163a45c6cb8SMadhusudhan Chikkature err1: 21641e363e3bSAndreas Fenkart err_gpio: 2165a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2166db0fefc5SAdrian Hunter err: 2167a45c6cb8SMadhusudhan Chikkature return ret; 2168a45c6cb8SMadhusudhan Chikkature } 2169a45c6cb8SMadhusudhan Chikkature 21706e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2171a45c6cb8SMadhusudhan Chikkature { 217270a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2173a45c6cb8SMadhusudhan Chikkature 2174fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2175a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2176a45c6cb8SMadhusudhan Chikkature 2177c5c98927SRussell King dma_release_channel(host->tx_chan); 2178c5c98927SRussell King dma_release_channel(host->rx_chan); 2179c5c98927SRussell King 2180814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2181fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2182fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 21835b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 21849618195eSBalaji T K if (host->dbclk) 218594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2186a45c6cb8SMadhusudhan Chikkature 21879d1f0286SBalaji T K mmc_free_host(host->mmc); 2188a45c6cb8SMadhusudhan Chikkature 2189a45c6cb8SMadhusudhan Chikkature return 0; 2190a45c6cb8SMadhusudhan Chikkature } 2191a45c6cb8SMadhusudhan Chikkature 21923d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2193a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2194a45c6cb8SMadhusudhan Chikkature { 2195927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2196927ce944SFelipe Balbi 2197927ce944SFelipe Balbi if (!host) 2198927ce944SFelipe Balbi return 0; 2199a45c6cb8SMadhusudhan Chikkature 2200fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 220131f9d463SEliad Peller 220231f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22042cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22052cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 220631f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 220731f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 220831f9d463SEliad Peller } 2209927ce944SFelipe Balbi 2210cd03d9a8SRajendra Nayak if (host->dbclk) 221194c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22123932afd5SUlf Hansson 2213fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22143932afd5SUlf Hansson return 0; 2215a45c6cb8SMadhusudhan Chikkature } 2216a45c6cb8SMadhusudhan Chikkature 2217a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2218a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2219a45c6cb8SMadhusudhan Chikkature { 2220927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2221927ce944SFelipe Balbi 2222927ce944SFelipe Balbi if (!host) 2223927ce944SFelipe Balbi return 0; 2224a45c6cb8SMadhusudhan Chikkature 2225fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 222611dd62a7SDenis Karpov 2227cd03d9a8SRajendra Nayak if (host->dbclk) 222894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22292bec0893SAdrian Hunter 223031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 223170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22321b331e69SKim Kyuwon 2233b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2234fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2235fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22363932afd5SUlf Hansson return 0; 2237a45c6cb8SMadhusudhan Chikkature } 2238a45c6cb8SMadhusudhan Chikkature #endif 2239a45c6cb8SMadhusudhan Chikkature 2240fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2241fa4aa2d4SBalaji T K { 2242fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22432cd3a2a5SAndreas Fenkart unsigned long flags; 2244f945901fSAndreas Fenkart int ret = 0; 2245fa4aa2d4SBalaji T K 2246fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2247fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2248927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2249fa4aa2d4SBalaji T K 22502cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22512cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22522cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22532cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 22542cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22552cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2256f945901fSAndreas Fenkart 2257f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2258f945901fSAndreas Fenkart /* 2259f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2260f945901fSAndreas Fenkart * race condition: possible irq handler running on 2261f945901fSAndreas Fenkart * multi-core, abort 2262f945901fSAndreas Fenkart */ 2263f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 22642cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2265f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2266f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2267f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2268f945901fSAndreas Fenkart ret = -EBUSY; 2269f945901fSAndreas Fenkart goto abort; 2270f945901fSAndreas Fenkart } 22712cd3a2a5SAndreas Fenkart 227297978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 227397978a44SAndreas Fenkart } else { 227497978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 22752cd3a2a5SAndreas Fenkart } 227697978a44SAndreas Fenkart 2277f945901fSAndreas Fenkart abort: 22782cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2279f945901fSAndreas Fenkart return ret; 2280fa4aa2d4SBalaji T K } 2281fa4aa2d4SBalaji T K 2282fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2283fa4aa2d4SBalaji T K { 2284fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22852cd3a2a5SAndreas Fenkart unsigned long flags; 2286fa4aa2d4SBalaji T K 2287fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2288fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2289927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2290fa4aa2d4SBalaji T K 22912cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22922cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22932cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22942cd3a2a5SAndreas Fenkart 229597978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 229697978a44SAndreas Fenkart 229797978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 22982cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 22992cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23002cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 230197978a44SAndreas Fenkart } else { 230297978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23032cd3a2a5SAndreas Fenkart } 23042cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2305fa4aa2d4SBalaji T K return 0; 2306fa4aa2d4SBalaji T K } 2307fa4aa2d4SBalaji T K 23086bba4064SArvind Yadav static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23093d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2310fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2311fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2312a791daa1SKevin Hilman }; 2313a791daa1SKevin Hilman 2314a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2315efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23160433c143SBill Pemberton .remove = omap_hsmmc_remove, 2317a45c6cb8SMadhusudhan Chikkature .driver = { 2318a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2319a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 232046856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2321a45c6cb8SMadhusudhan Chikkature }, 2322a45c6cb8SMadhusudhan Chikkature }; 2323a45c6cb8SMadhusudhan Chikkature 2324b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2325a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2326a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2327a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2328a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2329