1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 402cd3a2a5SAndreas Fenkart #include <linux/irq.h> 41db0fefc5SAdrian Hunter #include <linux/gpio.h> 42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4568f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 46a45c6cb8SMadhusudhan Chikkature 47a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4811dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 50a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 59bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 65a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 67a45c6cb8SMadhusudhan Chikkature 68a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 69a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 70cd587096SHebbar, Gururaja #define HSS (1 << 21) 71a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 72a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 73eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 741b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 75a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 76a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 77a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 78a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 79a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 80a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 81a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 82a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 83ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 84a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 85a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 86a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 87a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 88a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 89a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 90a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 91a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 92a7e96879SVenkatraman S #define DMAE 0x1 93a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 94a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 95a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 96cd587096SHebbar, Gururaja #define HSPE (1 << 2) 975a52b08bSBalaji T K #define IWE (1 << 24) 9803b5d924SBalaji T K #define DDR (1 << 19) 995a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1005a52b08bSBalaji T K #define CTPL (1 << 11) 10173153010SJarkko Lavinen #define DW8 (1 << 5) 102a45c6cb8SMadhusudhan Chikkature #define OD 0x1 103a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 104a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 105a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 106a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 107a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10811dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 109a45c6cb8SMadhusudhan Chikkature 110a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 111a7e96879SVenkatraman S #define CC_EN (1 << 0) 112a7e96879SVenkatraman S #define TC_EN (1 << 1) 113a7e96879SVenkatraman S #define BWR_EN (1 << 4) 114a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1152cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 116a7e96879SVenkatraman S #define ERR_EN (1 << 15) 117a7e96879SVenkatraman S #define CTO_EN (1 << 16) 118a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 119a7e96879SVenkatraman S #define CEB_EN (1 << 18) 120a7e96879SVenkatraman S #define CIE_EN (1 << 19) 121a7e96879SVenkatraman S #define DTO_EN (1 << 20) 122a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 123a7e96879SVenkatraman S #define DEB_EN (1 << 22) 124a2e77152SBalaji T K #define ACE_EN (1 << 24) 125a7e96879SVenkatraman S #define CERR_EN (1 << 28) 126a7e96879SVenkatraman S #define BADA_EN (1 << 29) 127a7e96879SVenkatraman S 128a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 129a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 130a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define CNI (1 << 7) 133a2e77152SBalaji T K #define ACIE (1 << 4) 134a2e77152SBalaji T K #define ACEB (1 << 3) 135a2e77152SBalaji T K #define ACCE (1 << 2) 136a2e77152SBalaji T K #define ACTO (1 << 1) 137a2e77152SBalaji T K #define ACNE (1 << 0) 138a2e77152SBalaji T K 139fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1401e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1411e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1426b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1436b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1440005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 145a45c6cb8SMadhusudhan Chikkature 146e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 147e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 148e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 149e99448ffSBalaji T K 150a45c6cb8SMadhusudhan Chikkature /* 151a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 152a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 153a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 154a45c6cb8SMadhusudhan Chikkature */ 155a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 156a45c6cb8SMadhusudhan Chikkature 157a45c6cb8SMadhusudhan Chikkature /* 158a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 159a45c6cb8SMadhusudhan Chikkature */ 160a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 161a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 162a45c6cb8SMadhusudhan Chikkature 163a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 164a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 165a45c6cb8SMadhusudhan Chikkature 1669782aff8SPer Forlin struct omap_hsmmc_next { 1679782aff8SPer Forlin unsigned int dma_len; 1689782aff8SPer Forlin s32 cookie; 1699782aff8SPer Forlin }; 1709782aff8SPer Forlin 17170a3341aSDenis Karpov struct omap_hsmmc_host { 172a45c6cb8SMadhusudhan Chikkature struct device *dev; 173a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 174a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 175a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 176a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 177a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 178a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 179db0fefc5SAdrian Hunter /* 180db0fefc5SAdrian Hunter * vcc == configured supply 181db0fefc5SAdrian Hunter * vcc_aux == optional 182db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 183db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 184db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 185db0fefc5SAdrian Hunter */ 186db0fefc5SAdrian Hunter struct regulator *vcc; 187db0fefc5SAdrian Hunter struct regulator *vcc_aux; 188e99448ffSBalaji T K struct regulator *pbias; 189e99448ffSBalaji T K bool pbias_enabled; 190a45c6cb8SMadhusudhan Chikkature void __iomem *base; 191a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1924dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 193a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1940ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 195a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 196a3621465SAdrian Hunter unsigned char power_mode; 197a45c6cb8SMadhusudhan Chikkature int suspended; 1980a82e06eSTony Lindgren u32 con; 1990a82e06eSTony Lindgren u32 hctl; 2000a82e06eSTony Lindgren u32 sysctl; 2010a82e06eSTony Lindgren u32 capa; 202a45c6cb8SMadhusudhan Chikkature int irq; 2032cd3a2a5SAndreas Fenkart int wake_irq; 204a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 205c5c98927SRussell King struct dma_chan *tx_chan; 206c5c98927SRussell King struct dma_chan *rx_chan; 207a45c6cb8SMadhusudhan Chikkature int slot_id; 2084a694dc9SAdrian Hunter int response_busy; 20911dd62a7SDenis Karpov int context_loss; 210b62f6228SAdrian Hunter int protect_card; 211b62f6228SAdrian Hunter int reqs_blocked; 212db0fefc5SAdrian Hunter int use_reg; 213b417577dSAdrian Hunter int req_in_progress; 2146e3076c2SBalaji T K unsigned long clk_rate; 215a2e77152SBalaji T K unsigned int flags; 2162cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2172cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2182cd3a2a5SAndreas Fenkart #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) 2199782aff8SPer Forlin struct omap_hsmmc_next next_data; 220a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 221a45c6cb8SMadhusudhan Chikkature }; 222a45c6cb8SMadhusudhan Chikkature 22359445b10SNishanth Menon struct omap_mmc_of_data { 22459445b10SNishanth Menon u32 reg_offset; 22559445b10SNishanth Menon u8 controller_flags; 22659445b10SNishanth Menon }; 22759445b10SNishanth Menon 228bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 229bf129e1cSBalaji T K 230db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 231db0fefc5SAdrian Hunter { 2329ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2339ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 234db0fefc5SAdrian Hunter 235db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 236db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 237db0fefc5SAdrian Hunter } 238db0fefc5SAdrian Hunter 239db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 240db0fefc5SAdrian Hunter { 2419ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2429ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 243db0fefc5SAdrian Hunter 244db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 245db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 246db0fefc5SAdrian Hunter } 247db0fefc5SAdrian Hunter 248db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 249db0fefc5SAdrian Hunter { 2509ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2519ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 252db0fefc5SAdrian Hunter 253db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 254db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 255db0fefc5SAdrian Hunter } 256db0fefc5SAdrian Hunter 257db0fefc5SAdrian Hunter #ifdef CONFIG_PM 258db0fefc5SAdrian Hunter 259db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 260db0fefc5SAdrian Hunter { 2619ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2629ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 263db0fefc5SAdrian Hunter 264db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 265db0fefc5SAdrian Hunter return 0; 266db0fefc5SAdrian Hunter } 267db0fefc5SAdrian Hunter 268db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 269db0fefc5SAdrian Hunter { 2709ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2719ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 272db0fefc5SAdrian Hunter 273db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 274db0fefc5SAdrian Hunter return 0; 275db0fefc5SAdrian Hunter } 276db0fefc5SAdrian Hunter 277db0fefc5SAdrian Hunter #else 278db0fefc5SAdrian Hunter 279db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 280db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 281db0fefc5SAdrian Hunter 282db0fefc5SAdrian Hunter #endif 283db0fefc5SAdrian Hunter 284b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 285b702b106SAdrian Hunter 28669b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 287db0fefc5SAdrian Hunter int vdd) 288db0fefc5SAdrian Hunter { 289db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 290db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 291db0fefc5SAdrian Hunter int ret = 0; 292db0fefc5SAdrian Hunter 293db0fefc5SAdrian Hunter /* 294db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 295db0fefc5SAdrian Hunter * voltage always-on regulator. 296db0fefc5SAdrian Hunter */ 297db0fefc5SAdrian Hunter if (!host->vcc) 298db0fefc5SAdrian Hunter return 0; 299db0fefc5SAdrian Hunter 300db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 301db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 302db0fefc5SAdrian Hunter 303e99448ffSBalaji T K if (host->pbias) { 304e99448ffSBalaji T K if (host->pbias_enabled == 1) { 305e99448ffSBalaji T K ret = regulator_disable(host->pbias); 306e99448ffSBalaji T K if (!ret) 307e99448ffSBalaji T K host->pbias_enabled = 0; 308e99448ffSBalaji T K } 309e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 310e99448ffSBalaji T K } 311e99448ffSBalaji T K 312db0fefc5SAdrian Hunter /* 313db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 314db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 315db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 316db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 317db0fefc5SAdrian Hunter * 318db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 319db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 320db0fefc5SAdrian Hunter * 321db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 322db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 323db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 324db0fefc5SAdrian Hunter */ 325db0fefc5SAdrian Hunter if (power_on) { 326987fd49bSBalaji T K if (host->vcc) 32799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 328db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 329db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 330db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 331987fd49bSBalaji T K if (ret < 0 && host->vcc) 33299fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 33399fc5131SLinus Walleij host->vcc, 0); 334db0fefc5SAdrian Hunter } 335db0fefc5SAdrian Hunter } else { 33699fc5131SLinus Walleij /* Shut down the rail */ 3376da20c89SAdrian Hunter if (host->vcc_aux) 338db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 339987fd49bSBalaji T K if (host->vcc) { 34099fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 34199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 34299fc5131SLinus Walleij host->vcc, 0); 34399fc5131SLinus Walleij } 344db0fefc5SAdrian Hunter } 345db0fefc5SAdrian Hunter 346e99448ffSBalaji T K if (host->pbias) { 347e99448ffSBalaji T K if (vdd <= VDD_165_195) 348e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 349e99448ffSBalaji T K VDD_1V8); 350e99448ffSBalaji T K else 351e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 352e99448ffSBalaji T K VDD_3V0); 353e99448ffSBalaji T K if (ret < 0) 354e99448ffSBalaji T K goto error_set_power; 355e99448ffSBalaji T K 356e99448ffSBalaji T K if (host->pbias_enabled == 0) { 357e99448ffSBalaji T K ret = regulator_enable(host->pbias); 358e99448ffSBalaji T K if (!ret) 359e99448ffSBalaji T K host->pbias_enabled = 1; 360e99448ffSBalaji T K } 361e99448ffSBalaji T K } 362e99448ffSBalaji T K 363db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 364db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 365db0fefc5SAdrian Hunter 366e99448ffSBalaji T K error_set_power: 367db0fefc5SAdrian Hunter return ret; 368db0fefc5SAdrian Hunter } 369db0fefc5SAdrian Hunter 370db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 371db0fefc5SAdrian Hunter { 372db0fefc5SAdrian Hunter struct regulator *reg; 37364be9782Skishore kadiyala int ocr_value = 0; 374db0fefc5SAdrian Hunter 375f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 376db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 377987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 378987fd49bSBalaji T K PTR_ERR(reg)); 3791fdc90fbSNeilBrown return PTR_ERR(reg); 380db0fefc5SAdrian Hunter } else { 381db0fefc5SAdrian Hunter host->vcc = reg; 38264be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 38364be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 38464be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 38564be9782Skishore kadiyala } else { 38664be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3872cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 388e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 38964be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 39064be9782Skishore kadiyala return -EINVAL; 39164be9782Skishore kadiyala } 39264be9782Skishore kadiyala } 393987fd49bSBalaji T K } 394987fd49bSBalaji T K mmc_slot(host).set_power = omap_hsmmc_set_power; 395db0fefc5SAdrian Hunter 396db0fefc5SAdrian Hunter /* Allow an aux regulator */ 397f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 398db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 399db0fefc5SAdrian Hunter 400e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 401e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 402e99448ffSBalaji T K 403b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 404b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 405b1c1df7aSBalaji T K return 0; 406db0fefc5SAdrian Hunter /* 407987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 408987fd49bSBalaji T K * to increase usecount and then disable it. 409db0fefc5SAdrian Hunter */ 410987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 411e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 412e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 413e840ce13SAdrian Hunter 414987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 415987fd49bSBalaji T K mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 416db0fefc5SAdrian Hunter } 417db0fefc5SAdrian Hunter 418db0fefc5SAdrian Hunter return 0; 419db0fefc5SAdrian Hunter } 420db0fefc5SAdrian Hunter 421db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 422db0fefc5SAdrian Hunter { 423db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 424db0fefc5SAdrian Hunter } 425db0fefc5SAdrian Hunter 426b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 427b702b106SAdrian Hunter { 428b702b106SAdrian Hunter return 1; 429b702b106SAdrian Hunter } 430b702b106SAdrian Hunter 431b702b106SAdrian Hunter #else 432b702b106SAdrian Hunter 433b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 434b702b106SAdrian Hunter { 435b702b106SAdrian Hunter return -EINVAL; 436b702b106SAdrian Hunter } 437b702b106SAdrian Hunter 438b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 439b702b106SAdrian Hunter { 440b702b106SAdrian Hunter } 441b702b106SAdrian Hunter 442b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 443b702b106SAdrian Hunter { 444b702b106SAdrian Hunter return 0; 445b702b106SAdrian Hunter } 446b702b106SAdrian Hunter 447b702b106SAdrian Hunter #endif 448b702b106SAdrian Hunter 449b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 450b702b106SAdrian Hunter { 451b702b106SAdrian Hunter int ret; 452b702b106SAdrian Hunter 453b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 454b702b106SAdrian Hunter if (pdata->slots[0].cover) 455b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 456b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 457b702b106SAdrian Hunter else 458b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 459b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 460b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 461b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 462b702b106SAdrian Hunter if (ret) 463b702b106SAdrian Hunter return ret; 464b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 465b702b106SAdrian Hunter if (ret) 466b702b106SAdrian Hunter goto err_free_sp; 467b702b106SAdrian Hunter } else 468b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 469b702b106SAdrian Hunter 470b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 471b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 472b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 473b702b106SAdrian Hunter if (ret) 474b702b106SAdrian Hunter goto err_free_cd; 475b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 476b702b106SAdrian Hunter if (ret) 477b702b106SAdrian Hunter goto err_free_wp; 478b702b106SAdrian Hunter } else 479b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 480b702b106SAdrian Hunter 481b702b106SAdrian Hunter return 0; 482b702b106SAdrian Hunter 483b702b106SAdrian Hunter err_free_wp: 484b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 485b702b106SAdrian Hunter err_free_cd: 486b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 487b702b106SAdrian Hunter err_free_sp: 488b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 489b702b106SAdrian Hunter return ret; 490b702b106SAdrian Hunter } 491b702b106SAdrian Hunter 492b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 493b702b106SAdrian Hunter { 494b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 495b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 496b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 497b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 498b702b106SAdrian Hunter } 499b702b106SAdrian Hunter 500a45c6cb8SMadhusudhan Chikkature /* 501e0c7f99bSAndy Shevchenko * Start clock to the card 502e0c7f99bSAndy Shevchenko */ 503e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 504e0c7f99bSAndy Shevchenko { 505e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 506e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 507e0c7f99bSAndy Shevchenko } 508e0c7f99bSAndy Shevchenko 509e0c7f99bSAndy Shevchenko /* 510a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 511a45c6cb8SMadhusudhan Chikkature */ 51270a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 513a45c6cb8SMadhusudhan Chikkature { 514a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 515a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 516a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5177122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 518a45c6cb8SMadhusudhan Chikkature } 519a45c6cb8SMadhusudhan Chikkature 52093caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 52193caf8e6SAdrian Hunter struct mmc_command *cmd) 522b417577dSAdrian Hunter { 5232cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5242cd3a2a5SAndreas Fenkart unsigned long flags; 525b417577dSAdrian Hunter 526b417577dSAdrian Hunter if (host->use_dma) 5272cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 528b417577dSAdrian Hunter 52993caf8e6SAdrian Hunter /* Disable timeout for erases */ 53093caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 531a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 53293caf8e6SAdrian Hunter 5332cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 534b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 535b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5362cd3a2a5SAndreas Fenkart 5372cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5382cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5392cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 540b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5412cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 542b417577dSAdrian Hunter } 543b417577dSAdrian Hunter 544b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 545b417577dSAdrian Hunter { 5462cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5472cd3a2a5SAndreas Fenkart unsigned long flags; 5482cd3a2a5SAndreas Fenkart 5492cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5502cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5512cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5522cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5532cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5542cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 555b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5562cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 557b417577dSAdrian Hunter } 558b417577dSAdrian Hunter 559ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 560d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 561ac330f44SAndy Shevchenko { 562ac330f44SAndy Shevchenko u16 dsor = 0; 563ac330f44SAndy Shevchenko 564ac330f44SAndy Shevchenko if (ios->clock) { 565d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 566ed164182SBalaji T K if (dsor > CLKD_MAX) 567ed164182SBalaji T K dsor = CLKD_MAX; 568ac330f44SAndy Shevchenko } 569ac330f44SAndy Shevchenko 570ac330f44SAndy Shevchenko return dsor; 571ac330f44SAndy Shevchenko } 572ac330f44SAndy Shevchenko 5735934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5745934df2fSAndy Shevchenko { 5755934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5765934df2fSAndy Shevchenko unsigned long regval; 5775934df2fSAndy Shevchenko unsigned long timeout; 578cd587096SHebbar, Gururaja unsigned long clkdiv; 5795934df2fSAndy Shevchenko 5808986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5815934df2fSAndy Shevchenko 5825934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5835934df2fSAndy Shevchenko 5845934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5855934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 586cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 587cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5885934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5895934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5905934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5915934df2fSAndy Shevchenko 5925934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5935934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5945934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5955934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5965934df2fSAndy Shevchenko cpu_relax(); 5975934df2fSAndy Shevchenko 598cd587096SHebbar, Gururaja /* 599cd587096SHebbar, Gururaja * Enable High-Speed Support 600cd587096SHebbar, Gururaja * Pre-Requisites 601cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 602cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 603cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 604cd587096SHebbar, Gururaja * in capabilities register 605cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 606cd587096SHebbar, Gururaja */ 607cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 6085438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 609cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 610cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 611cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 612cd587096SHebbar, Gururaja regval |= HSPE; 613cd587096SHebbar, Gururaja else 614cd587096SHebbar, Gururaja regval &= ~HSPE; 615cd587096SHebbar, Gururaja 616cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 617cd587096SHebbar, Gururaja } 618cd587096SHebbar, Gururaja 6195934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6205934df2fSAndy Shevchenko } 6215934df2fSAndy Shevchenko 6223796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6233796fb8aSAndy Shevchenko { 6243796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6253796fb8aSAndy Shevchenko u32 con; 6263796fb8aSAndy Shevchenko 6273796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6285438ad95SSeungwon Jeon if (ios->timing == MMC_TIMING_MMC_DDR52) 62903b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 63003b5d924SBalaji T K else 63103b5d924SBalaji T K con &= ~DDR; 6323796fb8aSAndy Shevchenko switch (ios->bus_width) { 6333796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6343796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6353796fb8aSAndy Shevchenko break; 6363796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6373796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6383796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6393796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6403796fb8aSAndy Shevchenko break; 6413796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6423796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6433796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6443796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6453796fb8aSAndy Shevchenko break; 6463796fb8aSAndy Shevchenko } 6473796fb8aSAndy Shevchenko } 6483796fb8aSAndy Shevchenko 6493796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6503796fb8aSAndy Shevchenko { 6513796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6523796fb8aSAndy Shevchenko u32 con; 6533796fb8aSAndy Shevchenko 6543796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6553796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6563796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6573796fb8aSAndy Shevchenko else 6583796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6593796fb8aSAndy Shevchenko } 6603796fb8aSAndy Shevchenko 66111dd62a7SDenis Karpov #ifdef CONFIG_PM 66211dd62a7SDenis Karpov 66311dd62a7SDenis Karpov /* 66411dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 66511dd62a7SDenis Karpov * power state change. 66611dd62a7SDenis Karpov */ 66770a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 66811dd62a7SDenis Karpov { 66911dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6703796fb8aSAndy Shevchenko u32 hctl, capa; 67111dd62a7SDenis Karpov unsigned long timeout; 67211dd62a7SDenis Karpov 6730a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6740a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6750a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6760a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6770a82e06eSTony Lindgren return 0; 6780a82e06eSTony Lindgren 6790a82e06eSTony Lindgren host->context_loss++; 6800a82e06eSTony Lindgren 681c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 68211dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 68311dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 68411dd62a7SDenis Karpov hctl = SDVS18; 68511dd62a7SDenis Karpov else 68611dd62a7SDenis Karpov hctl = SDVS30; 68711dd62a7SDenis Karpov capa = VS30 | VS18; 68811dd62a7SDenis Karpov } else { 68911dd62a7SDenis Karpov hctl = SDVS18; 69011dd62a7SDenis Karpov capa = VS18; 69111dd62a7SDenis Karpov } 69211dd62a7SDenis Karpov 6935a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6945a52b08bSBalaji T K hctl |= IWE; 6955a52b08bSBalaji T K 69611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 69711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 69811dd62a7SDenis Karpov 69911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 70011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 70111dd62a7SDenis Karpov 70211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 70311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 70411dd62a7SDenis Karpov 70511dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 70611dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 70711dd62a7SDenis Karpov && time_before(jiffies, timeout)) 70811dd62a7SDenis Karpov ; 70911dd62a7SDenis Karpov 7102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7112cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7122cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 71311dd62a7SDenis Karpov 71411dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 71511dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 71611dd62a7SDenis Karpov goto out; 71711dd62a7SDenis Karpov 7183796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 71911dd62a7SDenis Karpov 7205934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 72111dd62a7SDenis Karpov 7223796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7233796fb8aSAndy Shevchenko 72411dd62a7SDenis Karpov out: 7250a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7260a82e06eSTony Lindgren host->context_loss); 72711dd62a7SDenis Karpov return 0; 72811dd62a7SDenis Karpov } 72911dd62a7SDenis Karpov 73011dd62a7SDenis Karpov /* 73111dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 73211dd62a7SDenis Karpov */ 73370a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 73411dd62a7SDenis Karpov { 7350a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7360a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7370a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7380a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 73911dd62a7SDenis Karpov } 74011dd62a7SDenis Karpov 74111dd62a7SDenis Karpov #else 74211dd62a7SDenis Karpov 74370a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 74411dd62a7SDenis Karpov { 74511dd62a7SDenis Karpov return 0; 74611dd62a7SDenis Karpov } 74711dd62a7SDenis Karpov 74870a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 74911dd62a7SDenis Karpov { 75011dd62a7SDenis Karpov } 75111dd62a7SDenis Karpov 75211dd62a7SDenis Karpov #endif 75311dd62a7SDenis Karpov 754a45c6cb8SMadhusudhan Chikkature /* 755a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 756a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 757a45c6cb8SMadhusudhan Chikkature */ 75870a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 759a45c6cb8SMadhusudhan Chikkature { 760a45c6cb8SMadhusudhan Chikkature int reg = 0; 761a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 762a45c6cb8SMadhusudhan Chikkature 763b62f6228SAdrian Hunter if (host->protect_card) 764b62f6228SAdrian Hunter return; 765b62f6228SAdrian Hunter 766a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 767b417577dSAdrian Hunter 768b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 769a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 770a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 771a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 772a45c6cb8SMadhusudhan Chikkature 773a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 774a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 775a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 776a45c6cb8SMadhusudhan Chikkature 777a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 778a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 779c653a6d4SAdrian Hunter 780c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 781c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 782c653a6d4SAdrian Hunter 783a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 784a45c6cb8SMadhusudhan Chikkature } 785a45c6cb8SMadhusudhan Chikkature 786a45c6cb8SMadhusudhan Chikkature static inline 78770a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 788a45c6cb8SMadhusudhan Chikkature { 789a45c6cb8SMadhusudhan Chikkature int r = 1; 790a45c6cb8SMadhusudhan Chikkature 791191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 792191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 793a45c6cb8SMadhusudhan Chikkature return r; 794a45c6cb8SMadhusudhan Chikkature } 795a45c6cb8SMadhusudhan Chikkature 796a45c6cb8SMadhusudhan Chikkature static ssize_t 79770a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 798a45c6cb8SMadhusudhan Chikkature char *buf) 799a45c6cb8SMadhusudhan Chikkature { 800a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 80170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 802a45c6cb8SMadhusudhan Chikkature 80370a3341aSDenis Karpov return sprintf(buf, "%s\n", 80470a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 805a45c6cb8SMadhusudhan Chikkature } 806a45c6cb8SMadhusudhan Chikkature 80770a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 808a45c6cb8SMadhusudhan Chikkature 809a45c6cb8SMadhusudhan Chikkature static ssize_t 81070a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 811a45c6cb8SMadhusudhan Chikkature char *buf) 812a45c6cb8SMadhusudhan Chikkature { 813a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 81470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 815a45c6cb8SMadhusudhan Chikkature 816191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 817a45c6cb8SMadhusudhan Chikkature } 818a45c6cb8SMadhusudhan Chikkature 81970a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 820a45c6cb8SMadhusudhan Chikkature 821a45c6cb8SMadhusudhan Chikkature /* 822a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 823a45c6cb8SMadhusudhan Chikkature */ 824a45c6cb8SMadhusudhan Chikkature static void 82570a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 826a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 827a45c6cb8SMadhusudhan Chikkature { 828a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 829a45c6cb8SMadhusudhan Chikkature 8308986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 831a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 832a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 833a45c6cb8SMadhusudhan Chikkature 83493caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 835a45c6cb8SMadhusudhan Chikkature 8364a694dc9SAdrian Hunter host->response_busy = 0; 837a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 838a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 839a45c6cb8SMadhusudhan Chikkature resptype = 1; 8404a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8414a694dc9SAdrian Hunter resptype = 3; 8424a694dc9SAdrian Hunter host->response_busy = 1; 8434a694dc9SAdrian Hunter } else 844a45c6cb8SMadhusudhan Chikkature resptype = 2; 845a45c6cb8SMadhusudhan Chikkature } 846a45c6cb8SMadhusudhan Chikkature 847a45c6cb8SMadhusudhan Chikkature /* 848a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 849a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 850a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 851a45c6cb8SMadhusudhan Chikkature */ 852a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 853a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 854a45c6cb8SMadhusudhan Chikkature 855a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 856a45c6cb8SMadhusudhan Chikkature 857a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 858a2e77152SBalaji T K host->mrq->sbc) { 859a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 860a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 861a2e77152SBalaji T K } 862a45c6cb8SMadhusudhan Chikkature if (data) { 863a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 864a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 865a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 866a45c6cb8SMadhusudhan Chikkature else 867a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 868a45c6cb8SMadhusudhan Chikkature } 869a45c6cb8SMadhusudhan Chikkature 870a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 871a7e96879SVenkatraman S cmdreg |= DMAE; 872a45c6cb8SMadhusudhan Chikkature 873b417577dSAdrian Hunter host->req_in_progress = 1; 8744dffd7a2SAdrian Hunter 875a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 876a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 877a45c6cb8SMadhusudhan Chikkature } 878a45c6cb8SMadhusudhan Chikkature 8790ccd76d4SJuha Yrjola static int 88070a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8810ccd76d4SJuha Yrjola { 8820ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8830ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8840ccd76d4SJuha Yrjola else 8850ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8860ccd76d4SJuha Yrjola } 8870ccd76d4SJuha Yrjola 888c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 889c5c98927SRussell King struct mmc_data *data) 890c5c98927SRussell King { 891c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 892c5c98927SRussell King } 893c5c98927SRussell King 894b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 895b417577dSAdrian Hunter { 896b417577dSAdrian Hunter int dma_ch; 89731463b14SVenkatraman S unsigned long flags; 898b417577dSAdrian Hunter 89931463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 900b417577dSAdrian Hunter host->req_in_progress = 0; 901b417577dSAdrian Hunter dma_ch = host->dma_ch; 90231463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 903b417577dSAdrian Hunter 904b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 905b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 906b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 907b417577dSAdrian Hunter return; 908b417577dSAdrian Hunter host->mrq = NULL; 909b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 910b417577dSAdrian Hunter } 911b417577dSAdrian Hunter 912a45c6cb8SMadhusudhan Chikkature /* 913a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 914a45c6cb8SMadhusudhan Chikkature */ 915a45c6cb8SMadhusudhan Chikkature static void 91670a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 917a45c6cb8SMadhusudhan Chikkature { 9184a694dc9SAdrian Hunter if (!data) { 9194a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9204a694dc9SAdrian Hunter 92123050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 92223050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 92323050103SAdrian Hunter host->response_busy) { 92423050103SAdrian Hunter host->response_busy = 0; 92523050103SAdrian Hunter return; 92623050103SAdrian Hunter } 92723050103SAdrian Hunter 928b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9294a694dc9SAdrian Hunter return; 9304a694dc9SAdrian Hunter } 9314a694dc9SAdrian Hunter 932a45c6cb8SMadhusudhan Chikkature host->data = NULL; 933a45c6cb8SMadhusudhan Chikkature 934a45c6cb8SMadhusudhan Chikkature if (!data->error) 935a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 936a45c6cb8SMadhusudhan Chikkature else 937a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 938a45c6cb8SMadhusudhan Chikkature 939bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 940fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 941bf129e1cSBalaji T K else 942bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 943a45c6cb8SMadhusudhan Chikkature } 944a45c6cb8SMadhusudhan Chikkature 945a45c6cb8SMadhusudhan Chikkature /* 946a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 947a45c6cb8SMadhusudhan Chikkature */ 948a45c6cb8SMadhusudhan Chikkature static void 94970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 950a45c6cb8SMadhusudhan Chikkature { 951bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 952a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9532177fa94SBalaji T K host->cmd = NULL; 954bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 955bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 956bf129e1cSBalaji T K host->mrq->data); 957bf129e1cSBalaji T K return; 958bf129e1cSBalaji T K } 959bf129e1cSBalaji T K 9602177fa94SBalaji T K host->cmd = NULL; 9612177fa94SBalaji T K 962a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 963a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 964a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 965a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 966a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 967a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 968a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 969a45c6cb8SMadhusudhan Chikkature } else { 970a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 971a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 972a45c6cb8SMadhusudhan Chikkature } 973a45c6cb8SMadhusudhan Chikkature } 974b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 975d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 976a45c6cb8SMadhusudhan Chikkature } 977a45c6cb8SMadhusudhan Chikkature 978a45c6cb8SMadhusudhan Chikkature /* 979a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 980a45c6cb8SMadhusudhan Chikkature */ 98170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 982a45c6cb8SMadhusudhan Chikkature { 983b417577dSAdrian Hunter int dma_ch; 98431463b14SVenkatraman S unsigned long flags; 985b417577dSAdrian Hunter 98682788ff5SJarkko Lavinen host->data->error = errno; 987a45c6cb8SMadhusudhan Chikkature 98831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 989b417577dSAdrian Hunter dma_ch = host->dma_ch; 990b417577dSAdrian Hunter host->dma_ch = -1; 99131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 992b417577dSAdrian Hunter 993b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 994c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 995c5c98927SRussell King 996c5c98927SRussell King dmaengine_terminate_all(chan); 997c5c98927SRussell King dma_unmap_sg(chan->device->dev, 998c5c98927SRussell King host->data->sg, host->data->sg_len, 99970a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1000c5c98927SRussell King 1001053bf34fSPer Forlin host->data->host_cookie = 0; 1002a45c6cb8SMadhusudhan Chikkature } 1003a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1004a45c6cb8SMadhusudhan Chikkature } 1005a45c6cb8SMadhusudhan Chikkature 1006a45c6cb8SMadhusudhan Chikkature /* 1007a45c6cb8SMadhusudhan Chikkature * Readable error output 1008a45c6cb8SMadhusudhan Chikkature */ 1009a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1010699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1011a45c6cb8SMadhusudhan Chikkature { 1012a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 101370a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1014699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1015699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1016699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1017699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1018a45c6cb8SMadhusudhan Chikkature }; 1019a45c6cb8SMadhusudhan Chikkature char res[256]; 1020a45c6cb8SMadhusudhan Chikkature char *buf = res; 1021a45c6cb8SMadhusudhan Chikkature int len, i; 1022a45c6cb8SMadhusudhan Chikkature 1023a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1024a45c6cb8SMadhusudhan Chikkature buf += len; 1025a45c6cb8SMadhusudhan Chikkature 102670a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1027a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 102870a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1029a45c6cb8SMadhusudhan Chikkature buf += len; 1030a45c6cb8SMadhusudhan Chikkature } 1031a45c6cb8SMadhusudhan Chikkature 10328986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1033a45c6cb8SMadhusudhan Chikkature } 1034699b958bSAdrian Hunter #else 1035699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1036699b958bSAdrian Hunter u32 status) 1037699b958bSAdrian Hunter { 1038699b958bSAdrian Hunter } 1039a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1040a45c6cb8SMadhusudhan Chikkature 10413ebf74b1SJean Pihet /* 10423ebf74b1SJean Pihet * MMC controller internal state machines reset 10433ebf74b1SJean Pihet * 10443ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10453ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10463ebf74b1SJean Pihet * Can be called from interrupt context 10473ebf74b1SJean Pihet */ 104870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10493ebf74b1SJean Pihet unsigned long bit) 10503ebf74b1SJean Pihet { 10513ebf74b1SJean Pihet unsigned long i = 0; 10521e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10533ebf74b1SJean Pihet 10543ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10553ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10563ebf74b1SJean Pihet 105707ad64b6SMadhusudhan Chikkature /* 105807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 105907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 106007ad64b6SMadhusudhan Chikkature */ 106107ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 1062b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 106307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10641e881786SJianpeng Ma udelay(1); 106507ad64b6SMadhusudhan Chikkature } 106607ad64b6SMadhusudhan Chikkature i = 0; 106707ad64b6SMadhusudhan Chikkature 10683ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10693ebf74b1SJean Pihet (i++ < limit)) 10701e881786SJianpeng Ma udelay(1); 10713ebf74b1SJean Pihet 10723ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10733ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10743ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10753ebf74b1SJean Pihet __func__); 10763ebf74b1SJean Pihet } 1077a45c6cb8SMadhusudhan Chikkature 107825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 107925e1897bSBalaji T K int err, int end_cmd) 1080ae4bf788SVenkatraman S { 108125e1897bSBalaji T K if (end_cmd) { 108294d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 108325e1897bSBalaji T K if (host->cmd) 1084ae4bf788SVenkatraman S host->cmd->error = err; 108525e1897bSBalaji T K } 1086ae4bf788SVenkatraman S 1087ae4bf788SVenkatraman S if (host->data) { 1088ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1089ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1090dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1091dc7745bdSBalaji T K host->mrq->cmd->error = err; 1092ae4bf788SVenkatraman S } 1093ae4bf788SVenkatraman S 1094b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1095a45c6cb8SMadhusudhan Chikkature { 1096a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1097b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1098a2e77152SBalaji T K int error = 0; 1099a45c6cb8SMadhusudhan Chikkature 1100a45c6cb8SMadhusudhan Chikkature data = host->data; 11018986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1102a45c6cb8SMadhusudhan Chikkature 1103a7e96879SVenkatraman S if (status & ERR_EN) { 1104699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11054a694dc9SAdrian Hunter 1106a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1107a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1108a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 110925e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1110a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 111125e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 111225e1897bSBalaji T K 1113a2e77152SBalaji T K if (status & ACE_EN) { 1114a2e77152SBalaji T K u32 ac12; 1115a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1116a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1117a2e77152SBalaji T K end_cmd = 1; 1118a2e77152SBalaji T K if (ac12 & ACTO) 1119a2e77152SBalaji T K error = -ETIMEDOUT; 1120a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1121a2e77152SBalaji T K error = -EILSEQ; 1122a2e77152SBalaji T K host->mrq->sbc->error = error; 1123a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1124a2e77152SBalaji T K } 1125a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1126a2e77152SBalaji T K } 1127ae4bf788SVenkatraman S if (host->data || host->response_busy) { 112825e1897bSBalaji T K end_trans = !end_cmd; 1129ae4bf788SVenkatraman S host->response_busy = 0; 1130a45c6cb8SMadhusudhan Chikkature } 1131a45c6cb8SMadhusudhan Chikkature } 1132a45c6cb8SMadhusudhan Chikkature 11337472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1134a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 113570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1136a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 113770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1138b417577dSAdrian Hunter } 1139a45c6cb8SMadhusudhan Chikkature 1140b417577dSAdrian Hunter /* 1141b417577dSAdrian Hunter * MMC controller IRQ handler 1142b417577dSAdrian Hunter */ 1143b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1144b417577dSAdrian Hunter { 1145b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1146b417577dSAdrian Hunter int status; 1147b417577dSAdrian Hunter 1148b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11492cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11502cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1151b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11521f6b9fa4SVenkatraman S 11532cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11542cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11552cd3a2a5SAndreas Fenkart 1156b417577dSAdrian Hunter /* Flush posted write */ 1157b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11581f6b9fa4SVenkatraman S } 11594dffd7a2SAdrian Hunter 1160a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1161a45c6cb8SMadhusudhan Chikkature } 1162a45c6cb8SMadhusudhan Chikkature 11632cd3a2a5SAndreas Fenkart static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) 11642cd3a2a5SAndreas Fenkart { 11652cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 11662cd3a2a5SAndreas Fenkart 11672cd3a2a5SAndreas Fenkart /* cirq is level triggered, disable to avoid infinite loop */ 11682cd3a2a5SAndreas Fenkart spin_lock(&host->irq_lock); 11692cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 11702cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 11712cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 11722cd3a2a5SAndreas Fenkart } 11732cd3a2a5SAndreas Fenkart spin_unlock(&host->irq_lock); 11742cd3a2a5SAndreas Fenkart pm_request_resume(host->dev); /* no use counter */ 11752cd3a2a5SAndreas Fenkart 11762cd3a2a5SAndreas Fenkart return IRQ_HANDLED; 11772cd3a2a5SAndreas Fenkart } 11782cd3a2a5SAndreas Fenkart 117970a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1180e13bb300SAdrian Hunter { 1181e13bb300SAdrian Hunter unsigned long i; 1182e13bb300SAdrian Hunter 1183e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1184e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1185e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1186e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1187e13bb300SAdrian Hunter break; 1188e13bb300SAdrian Hunter cpu_relax(); 1189e13bb300SAdrian Hunter } 1190e13bb300SAdrian Hunter } 1191e13bb300SAdrian Hunter 1192a45c6cb8SMadhusudhan Chikkature /* 1193eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1194eb250826SDavid Brownell * 1195eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1196eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1197eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1198a45c6cb8SMadhusudhan Chikkature */ 119970a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1200a45c6cb8SMadhusudhan Chikkature { 1201a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1202a45c6cb8SMadhusudhan Chikkature int ret; 1203a45c6cb8SMadhusudhan Chikkature 1204a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1205fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1206cd03d9a8SRajendra Nayak if (host->dbclk) 120794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1208a45c6cb8SMadhusudhan Chikkature 1209a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1210a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1211a45c6cb8SMadhusudhan Chikkature 1212a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12132bec0893SAdrian Hunter if (!ret) 12142bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 12152bec0893SAdrian Hunter vdd); 1216fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1217cd03d9a8SRajendra Nayak if (host->dbclk) 121894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12192bec0893SAdrian Hunter 1220a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1221a45c6cb8SMadhusudhan Chikkature goto err; 1222a45c6cb8SMadhusudhan Chikkature 1223a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1224a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1225a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1226eb250826SDavid Brownell 1227a45c6cb8SMadhusudhan Chikkature /* 1228a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1229a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 123070a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1231a45c6cb8SMadhusudhan Chikkature * 1232eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1233eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1234eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1235eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1236eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1237eb250826SDavid Brownell * 1238eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1239eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1240eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1241a45c6cb8SMadhusudhan Chikkature */ 1242eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1243a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1244eb250826SDavid Brownell else 1245eb250826SDavid Brownell reg_val |= SDVS30; 1246a45c6cb8SMadhusudhan Chikkature 1247a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1248e13bb300SAdrian Hunter set_sd_bus_power(host); 1249a45c6cb8SMadhusudhan Chikkature 1250a45c6cb8SMadhusudhan Chikkature return 0; 1251a45c6cb8SMadhusudhan Chikkature err: 1252b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1253a45c6cb8SMadhusudhan Chikkature return ret; 1254a45c6cb8SMadhusudhan Chikkature } 1255a45c6cb8SMadhusudhan Chikkature 1256b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1257b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1258b62f6228SAdrian Hunter { 1259b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1260b62f6228SAdrian Hunter return; 1261b62f6228SAdrian Hunter 1262b62f6228SAdrian Hunter host->reqs_blocked = 0; 1263b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1264b62f6228SAdrian Hunter if (host->protect_card) { 12652cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1266b62f6228SAdrian Hunter "card is now accessible\n", 1267b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1268b62f6228SAdrian Hunter host->protect_card = 0; 1269b62f6228SAdrian Hunter } 1270b62f6228SAdrian Hunter } else { 1271b62f6228SAdrian Hunter if (!host->protect_card) { 12722cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1273b62f6228SAdrian Hunter "card is now inaccessible\n", 1274b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1275b62f6228SAdrian Hunter host->protect_card = 1; 1276b62f6228SAdrian Hunter } 1277b62f6228SAdrian Hunter } 1278b62f6228SAdrian Hunter } 1279b62f6228SAdrian Hunter 1280a45c6cb8SMadhusudhan Chikkature /* 12817efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1282a45c6cb8SMadhusudhan Chikkature */ 12837efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1284a45c6cb8SMadhusudhan Chikkature { 12857efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1286249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1287a6b2240dSAdrian Hunter int carddetect; 1288249d0fa9SDavid Brownell 1289a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1290a6b2240dSAdrian Hunter 1291191d1f1dSDenis Karpov if (slot->card_detect) 1292db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1293b62f6228SAdrian Hunter else { 1294b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1295a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1296b62f6228SAdrian Hunter } 1297a6b2240dSAdrian Hunter 1298cdeebaddSMadhusudhan Chikkature if (carddetect) 1299a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1300cdeebaddSMadhusudhan Chikkature else 1301a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1302a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1303a45c6cb8SMadhusudhan Chikkature } 1304a45c6cb8SMadhusudhan Chikkature 1305c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13060ccd76d4SJuha Yrjola { 1307c5c98927SRussell King struct omap_hsmmc_host *host = param; 1308c5c98927SRussell King struct dma_chan *chan; 1309770d7432SAdrian Hunter struct mmc_data *data; 1310c5c98927SRussell King int req_in_progress; 1311a45c6cb8SMadhusudhan Chikkature 1312c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1313b417577dSAdrian Hunter if (host->dma_ch < 0) { 1314c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1315a45c6cb8SMadhusudhan Chikkature return; 1316b417577dSAdrian Hunter } 1317a45c6cb8SMadhusudhan Chikkature 1318770d7432SAdrian Hunter data = host->mrq->data; 1319c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13209782aff8SPer Forlin if (!data->host_cookie) 1321c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1322c5c98927SRussell King data->sg, data->sg_len, 1323b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1324b417577dSAdrian Hunter 1325b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1326a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1327c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1328b417577dSAdrian Hunter 1329b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1330b417577dSAdrian Hunter if (!req_in_progress) { 1331b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1332b417577dSAdrian Hunter 1333b417577dSAdrian Hunter host->mrq = NULL; 1334b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1335b417577dSAdrian Hunter } 1336a45c6cb8SMadhusudhan Chikkature } 1337a45c6cb8SMadhusudhan Chikkature 13389782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13399782aff8SPer Forlin struct mmc_data *data, 1340c5c98927SRussell King struct omap_hsmmc_next *next, 134126b88520SRussell King struct dma_chan *chan) 13429782aff8SPer Forlin { 13439782aff8SPer Forlin int dma_len; 13449782aff8SPer Forlin 13459782aff8SPer Forlin if (!next && data->host_cookie && 13469782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13472cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13489782aff8SPer Forlin " host->next_data.cookie %d\n", 13499782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13509782aff8SPer Forlin data->host_cookie = 0; 13519782aff8SPer Forlin } 13529782aff8SPer Forlin 13539782aff8SPer Forlin /* Check if next job is already prepared */ 1354b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 135526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13569782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13579782aff8SPer Forlin 13589782aff8SPer Forlin } else { 13599782aff8SPer Forlin dma_len = host->next_data.dma_len; 13609782aff8SPer Forlin host->next_data.dma_len = 0; 13619782aff8SPer Forlin } 13629782aff8SPer Forlin 13639782aff8SPer Forlin 13649782aff8SPer Forlin if (dma_len == 0) 13659782aff8SPer Forlin return -EINVAL; 13669782aff8SPer Forlin 13679782aff8SPer Forlin if (next) { 13689782aff8SPer Forlin next->dma_len = dma_len; 13699782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13709782aff8SPer Forlin } else 13719782aff8SPer Forlin host->dma_len = dma_len; 13729782aff8SPer Forlin 13739782aff8SPer Forlin return 0; 13749782aff8SPer Forlin } 13759782aff8SPer Forlin 1376a45c6cb8SMadhusudhan Chikkature /* 1377a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1378a45c6cb8SMadhusudhan Chikkature */ 13799d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 138070a3341aSDenis Karpov struct mmc_request *req) 1381a45c6cb8SMadhusudhan Chikkature { 138226b88520SRussell King struct dma_slave_config cfg; 138326b88520SRussell King struct dma_async_tx_descriptor *tx; 138426b88520SRussell King int ret = 0, i; 1385a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1386c5c98927SRussell King struct dma_chan *chan; 1387a45c6cb8SMadhusudhan Chikkature 13880ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1389a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13900ccd76d4SJuha Yrjola struct scatterlist *sgl; 13910ccd76d4SJuha Yrjola 13920ccd76d4SJuha Yrjola sgl = data->sg + i; 13930ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13940ccd76d4SJuha Yrjola return -EINVAL; 13950ccd76d4SJuha Yrjola } 13960ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13970ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13980ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13990ccd76d4SJuha Yrjola */ 14000ccd76d4SJuha Yrjola return -EINVAL; 14010ccd76d4SJuha Yrjola 1402b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1403a45c6cb8SMadhusudhan Chikkature 1404c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1405c5c98927SRussell King 1406c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1407c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1408c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1409c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1410c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1411c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1412c5c98927SRussell King 1413c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14149782aff8SPer Forlin if (ret) 14159782aff8SPer Forlin return ret; 1416a45c6cb8SMadhusudhan Chikkature 141726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1418c5c98927SRussell King if (ret) 1419c5c98927SRussell King return ret; 1420a45c6cb8SMadhusudhan Chikkature 1421c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1422c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1423c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1424c5c98927SRussell King if (!tx) { 1425c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1426c5c98927SRussell King /* FIXME: cleanup */ 1427c5c98927SRussell King return -1; 1428c5c98927SRussell King } 1429c5c98927SRussell King 1430c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1431c5c98927SRussell King tx->callback_param = host; 1432c5c98927SRussell King 1433c5c98927SRussell King /* Does not fail */ 1434c5c98927SRussell King dmaengine_submit(tx); 1435c5c98927SRussell King 143626b88520SRussell King host->dma_ch = 1; 1437c5c98927SRussell King 1438a45c6cb8SMadhusudhan Chikkature return 0; 1439a45c6cb8SMadhusudhan Chikkature } 1440a45c6cb8SMadhusudhan Chikkature 144170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1442e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1443e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1444a45c6cb8SMadhusudhan Chikkature { 1445a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1446a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1447a45c6cb8SMadhusudhan Chikkature 1448a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1449a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1450a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1451a45c6cb8SMadhusudhan Chikkature clkd = 1; 1452a45c6cb8SMadhusudhan Chikkature 14536e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1454e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1455e2bf08d6SAdrian Hunter timeout += timeout_clks; 1456a45c6cb8SMadhusudhan Chikkature if (timeout) { 1457a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1458a45c6cb8SMadhusudhan Chikkature dto += 1; 1459a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1460a45c6cb8SMadhusudhan Chikkature } 1461a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1462a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1463a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1464a45c6cb8SMadhusudhan Chikkature dto += 1; 1465a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1466a45c6cb8SMadhusudhan Chikkature dto -= 13; 1467a45c6cb8SMadhusudhan Chikkature else 1468a45c6cb8SMadhusudhan Chikkature dto = 0; 1469a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1470a45c6cb8SMadhusudhan Chikkature dto = 14; 1471a45c6cb8SMadhusudhan Chikkature } 1472a45c6cb8SMadhusudhan Chikkature 1473a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1474a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1475a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1476a45c6cb8SMadhusudhan Chikkature } 1477a45c6cb8SMadhusudhan Chikkature 14789d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14799d025334SBalaji T K { 14809d025334SBalaji T K struct mmc_request *req = host->mrq; 14819d025334SBalaji T K struct dma_chan *chan; 14829d025334SBalaji T K 14839d025334SBalaji T K if (!req->data) 14849d025334SBalaji T K return; 14859d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14869d025334SBalaji T K | (req->data->blocks << 16)); 14879d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14889d025334SBalaji T K req->data->timeout_clks); 14899d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14909d025334SBalaji T K dma_async_issue_pending(chan); 14919d025334SBalaji T K } 14929d025334SBalaji T K 1493a45c6cb8SMadhusudhan Chikkature /* 1494a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1495a45c6cb8SMadhusudhan Chikkature */ 1496a45c6cb8SMadhusudhan Chikkature static int 149770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1498a45c6cb8SMadhusudhan Chikkature { 1499a45c6cb8SMadhusudhan Chikkature int ret; 1500a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1501a45c6cb8SMadhusudhan Chikkature 1502a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1503a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1504e2bf08d6SAdrian Hunter /* 1505e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1506e2bf08d6SAdrian Hunter * busy signal. 1507e2bf08d6SAdrian Hunter */ 1508e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1509e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1510a45c6cb8SMadhusudhan Chikkature return 0; 1511a45c6cb8SMadhusudhan Chikkature } 1512a45c6cb8SMadhusudhan Chikkature 1513a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15149d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1515a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1516b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1517a45c6cb8SMadhusudhan Chikkature return ret; 1518a45c6cb8SMadhusudhan Chikkature } 1519a45c6cb8SMadhusudhan Chikkature } 1520a45c6cb8SMadhusudhan Chikkature return 0; 1521a45c6cb8SMadhusudhan Chikkature } 1522a45c6cb8SMadhusudhan Chikkature 15239782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15249782aff8SPer Forlin int err) 15259782aff8SPer Forlin { 15269782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15279782aff8SPer Forlin struct mmc_data *data = mrq->data; 15289782aff8SPer Forlin 152926b88520SRussell King if (host->use_dma && data->host_cookie) { 1530c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1531c5c98927SRussell King 153226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15339782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15349782aff8SPer Forlin data->host_cookie = 0; 15359782aff8SPer Forlin } 15369782aff8SPer Forlin } 15379782aff8SPer Forlin 15389782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15399782aff8SPer Forlin bool is_first_req) 15409782aff8SPer Forlin { 15419782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15429782aff8SPer Forlin 15439782aff8SPer Forlin if (mrq->data->host_cookie) { 15449782aff8SPer Forlin mrq->data->host_cookie = 0; 15459782aff8SPer Forlin return ; 15469782aff8SPer Forlin } 15479782aff8SPer Forlin 1548c5c98927SRussell King if (host->use_dma) { 1549c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1550c5c98927SRussell King 15519782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 155226b88520SRussell King &host->next_data, c)) 15539782aff8SPer Forlin mrq->data->host_cookie = 0; 15549782aff8SPer Forlin } 1555c5c98927SRussell King } 15569782aff8SPer Forlin 1557a45c6cb8SMadhusudhan Chikkature /* 1558a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1559a45c6cb8SMadhusudhan Chikkature */ 156070a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1561a45c6cb8SMadhusudhan Chikkature { 156270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1563a3f406f8SJarkko Lavinen int err; 1564a45c6cb8SMadhusudhan Chikkature 1565b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1566b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1567b62f6228SAdrian Hunter if (host->protect_card) { 1568b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1569b62f6228SAdrian Hunter /* 1570b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1571b62f6228SAdrian Hunter * state by resetting the command and data state 1572b62f6228SAdrian Hunter * machines. 1573b62f6228SAdrian Hunter */ 1574b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1575b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1576b62f6228SAdrian Hunter host->reqs_blocked += 1; 1577b62f6228SAdrian Hunter } 1578b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1579b62f6228SAdrian Hunter if (req->data) 1580b62f6228SAdrian Hunter req->data->error = -EBADF; 1581b417577dSAdrian Hunter req->cmd->retries = 0; 1582b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1583b62f6228SAdrian Hunter return; 1584b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1585b62f6228SAdrian Hunter host->reqs_blocked = 0; 1586a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1587a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15886e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 158970a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1590a3f406f8SJarkko Lavinen if (err) { 1591a3f406f8SJarkko Lavinen req->cmd->error = err; 1592a3f406f8SJarkko Lavinen if (req->data) 1593a3f406f8SJarkko Lavinen req->data->error = err; 1594a3f406f8SJarkko Lavinen host->mrq = NULL; 1595a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1596a3f406f8SJarkko Lavinen return; 1597a3f406f8SJarkko Lavinen } 1598a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1599bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1600bf129e1cSBalaji T K return; 1601bf129e1cSBalaji T K } 1602a3f406f8SJarkko Lavinen 16039d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 160470a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1605a45c6cb8SMadhusudhan Chikkature } 1606a45c6cb8SMadhusudhan Chikkature 1607a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 160870a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1609a45c6cb8SMadhusudhan Chikkature { 161070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1611a3621465SAdrian Hunter int do_send_init_stream = 0; 1612a45c6cb8SMadhusudhan Chikkature 1613fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16145e2ea617SAdrian Hunter 1615a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1616a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1617a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1618a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1619a3621465SAdrian Hunter 0, 0); 1620a45c6cb8SMadhusudhan Chikkature break; 1621a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1622a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1623a3621465SAdrian Hunter 1, ios->vdd); 1624a45c6cb8SMadhusudhan Chikkature break; 1625a3621465SAdrian Hunter case MMC_POWER_ON: 1626a3621465SAdrian Hunter do_send_init_stream = 1; 1627a3621465SAdrian Hunter break; 1628a3621465SAdrian Hunter } 1629a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1630a45c6cb8SMadhusudhan Chikkature } 1631a45c6cb8SMadhusudhan Chikkature 1632dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1633dd498effSDenis Karpov 16343796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1635a45c6cb8SMadhusudhan Chikkature 16364621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1637eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1638eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1639eb250826SDavid Brownell */ 1640a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16412cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1642a45c6cb8SMadhusudhan Chikkature /* 1643a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1644a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1645a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1646a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1647a45c6cb8SMadhusudhan Chikkature */ 164870a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1649a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1650a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1651a45c6cb8SMadhusudhan Chikkature } 1652a45c6cb8SMadhusudhan Chikkature } 1653a45c6cb8SMadhusudhan Chikkature 16545934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1655a45c6cb8SMadhusudhan Chikkature 1656a3621465SAdrian Hunter if (do_send_init_stream) 1657a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1658a45c6cb8SMadhusudhan Chikkature 16593796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16605e2ea617SAdrian Hunter 1661fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1662a45c6cb8SMadhusudhan Chikkature } 1663a45c6cb8SMadhusudhan Chikkature 1664a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1665a45c6cb8SMadhusudhan Chikkature { 166670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1667a45c6cb8SMadhusudhan Chikkature 1668191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1669a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1670db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1671a45c6cb8SMadhusudhan Chikkature } 1672a45c6cb8SMadhusudhan Chikkature 1673a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1674a45c6cb8SMadhusudhan Chikkature { 167570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1676a45c6cb8SMadhusudhan Chikkature 1677191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1678a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1679191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1680a45c6cb8SMadhusudhan Chikkature } 1681a45c6cb8SMadhusudhan Chikkature 16824816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16834816858cSGrazvydas Ignotas { 16844816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16854816858cSGrazvydas Ignotas 16864816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 16874816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 16884816858cSGrazvydas Ignotas } 16894816858cSGrazvydas Ignotas 16902cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16912cd3a2a5SAndreas Fenkart { 16922cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16935a52b08bSBalaji T K u32 irq_mask, con; 16942cd3a2a5SAndreas Fenkart unsigned long flags; 16952cd3a2a5SAndreas Fenkart 16962cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16972cd3a2a5SAndreas Fenkart 16985a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16992cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17002cd3a2a5SAndreas Fenkart if (enable) { 17012cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17022cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17035a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17042cd3a2a5SAndreas Fenkart } else { 17052cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17062cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17075a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17082cd3a2a5SAndreas Fenkart } 17095a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17112cd3a2a5SAndreas Fenkart 17122cd3a2a5SAndreas Fenkart /* 17132cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17142cd3a2a5SAndreas Fenkart * but always disable immediately 17152cd3a2a5SAndreas Fenkart */ 17162cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17172cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17182cd3a2a5SAndreas Fenkart 17192cd3a2a5SAndreas Fenkart /* flush posted write */ 17202cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17212cd3a2a5SAndreas Fenkart 17222cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17232cd3a2a5SAndreas Fenkart } 17242cd3a2a5SAndreas Fenkart 17252cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17262cd3a2a5SAndreas Fenkart { 17272cd3a2a5SAndreas Fenkart struct mmc_host *mmc = host->mmc; 17282cd3a2a5SAndreas Fenkart int ret; 17292cd3a2a5SAndreas Fenkart 17302cd3a2a5SAndreas Fenkart /* 17312cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17322cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17332cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17342cd3a2a5SAndreas Fenkart * with functional clock disabled. 17352cd3a2a5SAndreas Fenkart */ 17362cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17372cd3a2a5SAndreas Fenkart return -ENODEV; 17382cd3a2a5SAndreas Fenkart 17392cd3a2a5SAndreas Fenkart /* Prevent auto-enabling of IRQ */ 17402cd3a2a5SAndreas Fenkart irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); 17412cd3a2a5SAndreas Fenkart ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, 17422cd3a2a5SAndreas Fenkart IRQF_TRIGGER_LOW | IRQF_ONESHOT, 17432cd3a2a5SAndreas Fenkart mmc_hostname(mmc), host); 17442cd3a2a5SAndreas Fenkart if (ret) { 17452cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17462cd3a2a5SAndreas Fenkart goto err; 17472cd3a2a5SAndreas Fenkart } 17482cd3a2a5SAndreas Fenkart 17492cd3a2a5SAndreas Fenkart /* 17502cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17512cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17522cd3a2a5SAndreas Fenkart */ 17532cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 17542cd3a2a5SAndreas Fenkart ret = -ENODEV; 17552cd3a2a5SAndreas Fenkart devm_free_irq(host->dev, host->wake_irq, host); 17562cd3a2a5SAndreas Fenkart goto err; 17572cd3a2a5SAndreas Fenkart } 17582cd3a2a5SAndreas Fenkart 17595a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17605a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17612cd3a2a5SAndreas Fenkart return 0; 17622cd3a2a5SAndreas Fenkart 17632cd3a2a5SAndreas Fenkart err: 17642cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17652cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17662cd3a2a5SAndreas Fenkart return ret; 17672cd3a2a5SAndreas Fenkart } 17682cd3a2a5SAndreas Fenkart 176970a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17701b331e69SKim Kyuwon { 17711b331e69SKim Kyuwon u32 hctl, capa, value; 17721b331e69SKim Kyuwon 17731b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17744621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17751b331e69SKim Kyuwon hctl = SDVS30; 17761b331e69SKim Kyuwon capa = VS30 | VS18; 17771b331e69SKim Kyuwon } else { 17781b331e69SKim Kyuwon hctl = SDVS18; 17791b331e69SKim Kyuwon capa = VS18; 17801b331e69SKim Kyuwon } 17811b331e69SKim Kyuwon 17821b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17831b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17841b331e69SKim Kyuwon 17851b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17861b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17871b331e69SKim Kyuwon 17881b331e69SKim Kyuwon /* Set SD bus power bit */ 1789e13bb300SAdrian Hunter set_sd_bus_power(host); 17901b331e69SKim Kyuwon } 17911b331e69SKim Kyuwon 179270a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1793dd498effSDenis Karpov { 179470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1795dd498effSDenis Karpov 1796fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1797fa4aa2d4SBalaji T K 1798dd498effSDenis Karpov return 0; 1799dd498effSDenis Karpov } 1800dd498effSDenis Karpov 1801907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1802dd498effSDenis Karpov { 180370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1804dd498effSDenis Karpov 1805fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1806fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1807fa4aa2d4SBalaji T K 1808dd498effSDenis Karpov return 0; 1809dd498effSDenis Karpov } 1810dd498effSDenis Karpov 181170a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 181270a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 181370a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 18149782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18159782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 181670a3341aSDenis Karpov .request = omap_hsmmc_request, 181770a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1818dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1819dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 18204816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18212cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1822dd498effSDenis Karpov }; 1823dd498effSDenis Karpov 1824d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1825d900f712SDenis Karpov 182670a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1827d900f712SDenis Karpov { 1828d900f712SDenis Karpov struct mmc_host *mmc = s->private; 182970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 183011dd62a7SDenis Karpov 1831bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1832bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1833bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1834bb0635f0SAndreas Fenkart 1835bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1836bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1837bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1838bb0635f0SAndreas Fenkart : "disabled"); 1839bb0635f0SAndreas Fenkart } 1840bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18415e2ea617SAdrian Hunter 1842fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1843bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1844d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1845d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1846bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1847bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1848d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1849d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1850d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1851d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1852d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1853d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1854d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1855d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1856d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1857d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18585e2ea617SAdrian Hunter 1859fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1860fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1861dd498effSDenis Karpov 1862d900f712SDenis Karpov return 0; 1863d900f712SDenis Karpov } 1864d900f712SDenis Karpov 186570a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1866d900f712SDenis Karpov { 186770a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1868d900f712SDenis Karpov } 1869d900f712SDenis Karpov 1870d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 187170a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1872d900f712SDenis Karpov .read = seq_read, 1873d900f712SDenis Karpov .llseek = seq_lseek, 1874d900f712SDenis Karpov .release = single_release, 1875d900f712SDenis Karpov }; 1876d900f712SDenis Karpov 187770a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1878d900f712SDenis Karpov { 1879d900f712SDenis Karpov if (mmc->debugfs_root) 1880d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1881d900f712SDenis Karpov mmc, &mmc_regs_fops); 1882d900f712SDenis Karpov } 1883d900f712SDenis Karpov 1884d900f712SDenis Karpov #else 1885d900f712SDenis Karpov 188670a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1887d900f712SDenis Karpov { 1888d900f712SDenis Karpov } 1889d900f712SDenis Karpov 1890d900f712SDenis Karpov #endif 1891d900f712SDenis Karpov 189246856a68SRajendra Nayak #ifdef CONFIG_OF 189359445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 189459445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 189559445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 189659445b10SNishanth Menon }; 189759445b10SNishanth Menon 189859445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 189959445b10SNishanth Menon .reg_offset = 0x100, 190059445b10SNishanth Menon }; 19012cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19022cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19032cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19042cd3a2a5SAndreas Fenkart }; 190546856a68SRajendra Nayak 190646856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 190746856a68SRajendra Nayak { 190846856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 190946856a68SRajendra Nayak }, 191046856a68SRajendra Nayak { 191159445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 191259445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 191359445b10SNishanth Menon }, 191459445b10SNishanth Menon { 191546856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 191646856a68SRajendra Nayak }, 191746856a68SRajendra Nayak { 191846856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 191959445b10SNishanth Menon .data = &omap4_mmc_of_data, 192046856a68SRajendra Nayak }, 19212cd3a2a5SAndreas Fenkart { 19222cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19232cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19242cd3a2a5SAndreas Fenkart }, 192546856a68SRajendra Nayak {}, 1926b6d085f6SChris Ball }; 192746856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 192846856a68SRajendra Nayak 192946856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 193046856a68SRajendra Nayak { 193146856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 193246856a68SRajendra Nayak struct device_node *np = dev->of_node; 1933d8714e87SDaniel Mack u32 bus_width, max_freq; 1934dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1935dc642c28SJan Luebbe 1936dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1937dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1938dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1939dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 194046856a68SRajendra Nayak 194146856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 194246856a68SRajendra Nayak if (!pdata) 194319df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 194446856a68SRajendra Nayak 194546856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 194646856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 194746856a68SRajendra Nayak 194846856a68SRajendra Nayak /* This driver only supports 1 slot */ 194946856a68SRajendra Nayak pdata->nr_slots = 1; 1950dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1951dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 195246856a68SRajendra Nayak 195346856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 195446856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 195546856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 195646856a68SRajendra Nayak } 19577f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 195846856a68SRajendra Nayak if (bus_width == 4) 195946856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 196046856a68SRajendra Nayak else if (bus_width == 8) 196146856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 196246856a68SRajendra Nayak 196346856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 196446856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 196546856a68SRajendra Nayak 1966d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1967d8714e87SDaniel Mack pdata->max_freq = max_freq; 1968d8714e87SDaniel Mack 1969cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1970cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1971cd587096SHebbar, Gururaja 1972c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 1973c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; 1974c9ae64dbSDaniel Mack 1975c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1976c9ae64dbSDaniel Mack pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1977c9ae64dbSDaniel Mack 197846856a68SRajendra Nayak return pdata; 197946856a68SRajendra Nayak } 198046856a68SRajendra Nayak #else 198146856a68SRajendra Nayak static inline struct omap_mmc_platform_data 198246856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 198346856a68SRajendra Nayak { 198419df45bcSBalaji T K return ERR_PTR(-EINVAL); 198546856a68SRajendra Nayak } 198646856a68SRajendra Nayak #endif 198746856a68SRajendra Nayak 1988c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1989a45c6cb8SMadhusudhan Chikkature { 1990a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1991a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 199270a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1993a45c6cb8SMadhusudhan Chikkature struct resource *res; 1994db0fefc5SAdrian Hunter int ret, irq; 199546856a68SRajendra Nayak const struct of_device_id *match; 199626b88520SRussell King dma_cap_mask_t mask; 199726b88520SRussell King unsigned tx_req, rx_req; 199846b76035SDaniel Mack struct pinctrl *pinctrl; 199959445b10SNishanth Menon const struct omap_mmc_of_data *data; 200077fae219SBalaji T K void __iomem *base; 200146856a68SRajendra Nayak 200246856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 200346856a68SRajendra Nayak if (match) { 200446856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2005dc642c28SJan Luebbe 2006dc642c28SJan Luebbe if (IS_ERR(pdata)) 2007dc642c28SJan Luebbe return PTR_ERR(pdata); 2008dc642c28SJan Luebbe 200946856a68SRajendra Nayak if (match->data) { 201059445b10SNishanth Menon data = match->data; 201159445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 201259445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 201346856a68SRajendra Nayak } 201446856a68SRajendra Nayak } 2015a45c6cb8SMadhusudhan Chikkature 2016a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2017a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2018a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2019a45c6cb8SMadhusudhan Chikkature } 2020a45c6cb8SMadhusudhan Chikkature 2021a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 2022a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 2023a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2024a45c6cb8SMadhusudhan Chikkature } 2025a45c6cb8SMadhusudhan Chikkature 2026a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2027a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2028a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2029a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2030a45c6cb8SMadhusudhan Chikkature 203177fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 203277fae219SBalaji T K if (IS_ERR(base)) 203377fae219SBalaji T K return PTR_ERR(base); 2034a45c6cb8SMadhusudhan Chikkature 2035db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 2036db0fefc5SAdrian Hunter if (ret) 2037db0fefc5SAdrian Hunter goto err; 2038db0fefc5SAdrian Hunter 203970a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2040a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2041a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 2042db0fefc5SAdrian Hunter goto err_alloc; 2043a45c6cb8SMadhusudhan Chikkature } 2044a45c6cb8SMadhusudhan Chikkature 2045a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2046a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2047a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2048a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2049a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2050a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2051a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2052a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 2053fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 205477fae219SBalaji T K host->base = base + pdata->reg_offset; 20556da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20569782aff8SPer Forlin host->next_data.cookie = 1; 2057e99448ffSBalaji T K host->pbias_enabled = 0; 2058a45c6cb8SMadhusudhan Chikkature 2059a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2060a45c6cb8SMadhusudhan Chikkature 20612cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20622cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20632cd3a2a5SAndreas Fenkart 206470a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2065dd498effSDenis Karpov 20666b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2067d418ed87SDaniel Mack 2068d418ed87SDaniel Mack if (pdata->max_freq > 0) 2069d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2070d418ed87SDaniel Mack else 20716b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2072a45c6cb8SMadhusudhan Chikkature 20734dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2074a45c6cb8SMadhusudhan Chikkature 20759618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2076a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2077a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2078a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2079a45c6cb8SMadhusudhan Chikkature goto err1; 2080a45c6cb8SMadhusudhan Chikkature } 2081a45c6cb8SMadhusudhan Chikkature 20829b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20839b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 20849b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 20859b68256cSPaul Walmsley } 2086dd498effSDenis Karpov 2087fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2088fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2089fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2090fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2091a45c6cb8SMadhusudhan Chikkature 209292a3aebfSBalaji T K omap_hsmmc_context_save(host); 209392a3aebfSBalaji T K 20949618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2095a45c6cb8SMadhusudhan Chikkature /* 2096a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2097a45c6cb8SMadhusudhan Chikkature */ 2098cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2099cd03d9a8SRajendra Nayak host->dbclk = NULL; 210094c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2101cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2102cd03d9a8SRajendra Nayak host->dbclk = NULL; 21032bec0893SAdrian Hunter } 2104a45c6cb8SMadhusudhan Chikkature 21050ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21060ccd76d4SJuha Yrjola * as we want. */ 2107a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21080ccd76d4SJuha Yrjola 2109a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2110a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2111a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2112a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2113a45c6cb8SMadhusudhan Chikkature 211413189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 211593caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2116a45c6cb8SMadhusudhan Chikkature 21173a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 21183a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2119a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2120a45c6cb8SMadhusudhan Chikkature 2121191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 212223d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 212323d99bb9SAdrian Hunter 21246fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 21256fdc75deSEliad Peller 212670a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2127a45c6cb8SMadhusudhan Chikkature 21284a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2129b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2130b7bf773bSBalaji T K if (!res) { 2131b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21329c17d08cSKevin Hilman ret = -ENXIO; 2133f3e2f1ddSGrazvydas Ignotas goto err_irq; 2134a45c6cb8SMadhusudhan Chikkature } 213526b88520SRussell King tx_req = res->start; 2136b7bf773bSBalaji T K 2137b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2138b7bf773bSBalaji T K if (!res) { 2139b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21409c17d08cSKevin Hilman ret = -ENXIO; 2141b7bf773bSBalaji T K goto err_irq; 2142b7bf773bSBalaji T K } 214326b88520SRussell King rx_req = res->start; 21444a29b559SSantosh Shilimkar } 2145c5c98927SRussell King 2146c5c98927SRussell King dma_cap_zero(mask); 2147c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 214826b88520SRussell King 2149d272fbf0SMatt Porter host->rx_chan = 2150d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2151d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2152d272fbf0SMatt Porter 2153c5c98927SRussell King if (!host->rx_chan) { 215426b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 215504e8c7bcSKevin Hilman ret = -ENXIO; 215626b88520SRussell King goto err_irq; 2157c5c98927SRussell King } 215826b88520SRussell King 2159d272fbf0SMatt Porter host->tx_chan = 2160d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2161d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2162d272fbf0SMatt Porter 2163c5c98927SRussell King if (!host->tx_chan) { 216426b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 216504e8c7bcSKevin Hilman ret = -ENXIO; 216626b88520SRussell King goto err_irq; 2167c5c98927SRussell King } 2168a45c6cb8SMadhusudhan Chikkature 2169a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2170e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2171a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2172a45c6cb8SMadhusudhan Chikkature if (ret) { 2173b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2174a45c6cb8SMadhusudhan Chikkature goto err_irq; 2175a45c6cb8SMadhusudhan Chikkature } 2176a45c6cb8SMadhusudhan Chikkature 2177a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 2178a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 2179b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 218070a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 2181e1538ed7SBalaji T K goto err_irq; 2182a45c6cb8SMadhusudhan Chikkature } 2183a45c6cb8SMadhusudhan Chikkature } 2184db0fefc5SAdrian Hunter 2185b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2186db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2187db0fefc5SAdrian Hunter if (ret) 2188db0fefc5SAdrian Hunter goto err_reg; 2189db0fefc5SAdrian Hunter host->use_reg = 1; 2190db0fefc5SAdrian Hunter } 2191db0fefc5SAdrian Hunter 2192b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 2193a45c6cb8SMadhusudhan Chikkature 2194a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 2195e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 21969fa0e05eSBalaji T K ret = devm_request_threaded_irq(&pdev->dev, 21979fa0e05eSBalaji T K mmc_slot(host).card_detect_irq, 21989fa0e05eSBalaji T K NULL, omap_hsmmc_detect, 2199db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2200a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2201a45c6cb8SMadhusudhan Chikkature if (ret) { 2202b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 2203a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 2204a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 2205a45c6cb8SMadhusudhan Chikkature } 220672f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 220772f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 2208a45c6cb8SMadhusudhan Chikkature } 2209a45c6cb8SMadhusudhan Chikkature 2210b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2211a45c6cb8SMadhusudhan Chikkature 221246b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 221346b76035SDaniel Mack if (IS_ERR(pinctrl)) 221446b76035SDaniel Mack dev_warn(&pdev->dev, 221546b76035SDaniel Mack "pins are not configured from the driver\n"); 221646b76035SDaniel Mack 22172cd3a2a5SAndreas Fenkart /* 22182cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 22192cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 22202cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 22212cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 22222cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 22232cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22242cd3a2a5SAndreas Fenkart */ 22252cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22262cd3a2a5SAndreas Fenkart if (!ret) 22272cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22282cd3a2a5SAndreas Fenkart 2229b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2230b62f6228SAdrian Hunter 2231a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2232a45c6cb8SMadhusudhan Chikkature 2233191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2234a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2235a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2236a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2237a45c6cb8SMadhusudhan Chikkature } 2238191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2239a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2240a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2241a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2242db0fefc5SAdrian Hunter goto err_slot_name; 2243a45c6cb8SMadhusudhan Chikkature } 2244a45c6cb8SMadhusudhan Chikkature 224570a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2246fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2247fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2248d900f712SDenis Karpov 2249a45c6cb8SMadhusudhan Chikkature return 0; 2250a45c6cb8SMadhusudhan Chikkature 2251a45c6cb8SMadhusudhan Chikkature err_slot_name: 2252a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2253db0fefc5SAdrian Hunter err_irq_cd: 2254db0fefc5SAdrian Hunter if (host->use_reg) 2255db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2256db0fefc5SAdrian Hunter err_reg: 2257db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2258db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2259a45c6cb8SMadhusudhan Chikkature err_irq: 2260c5c98927SRussell King if (host->tx_chan) 2261c5c98927SRussell King dma_release_channel(host->tx_chan); 2262c5c98927SRussell King if (host->rx_chan) 2263c5c98927SRussell King dma_release_channel(host->rx_chan); 2264d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 226537f6190dSTony Lindgren pm_runtime_disable(host->dev); 22669618195eSBalaji T K if (host->dbclk) 226794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2268a45c6cb8SMadhusudhan Chikkature err1: 2269a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2270db0fefc5SAdrian Hunter err_alloc: 2271db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2272db0fefc5SAdrian Hunter err: 2273a45c6cb8SMadhusudhan Chikkature return ret; 2274a45c6cb8SMadhusudhan Chikkature } 2275a45c6cb8SMadhusudhan Chikkature 22766e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2277a45c6cb8SMadhusudhan Chikkature { 227870a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2279a45c6cb8SMadhusudhan Chikkature 2280fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2281a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2282db0fefc5SAdrian Hunter if (host->use_reg) 2283db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2284a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2285a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2286a45c6cb8SMadhusudhan Chikkature 2287c5c98927SRussell King if (host->tx_chan) 2288c5c98927SRussell King dma_release_channel(host->tx_chan); 2289c5c98927SRussell King if (host->rx_chan) 2290c5c98927SRussell King dma_release_channel(host->rx_chan); 2291c5c98927SRussell King 2292fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2293fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22949618195eSBalaji T K if (host->dbclk) 229594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2296a45c6cb8SMadhusudhan Chikkature 22979ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 22989d1f0286SBalaji T K mmc_free_host(host->mmc); 2299a45c6cb8SMadhusudhan Chikkature 2300a45c6cb8SMadhusudhan Chikkature return 0; 2301a45c6cb8SMadhusudhan Chikkature } 2302a45c6cb8SMadhusudhan Chikkature 2303a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2304a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2305a48ce884SFelipe Balbi { 2306a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2307a48ce884SFelipe Balbi 2308a48ce884SFelipe Balbi if (host->pdata->suspend) 2309a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2310a48ce884SFelipe Balbi 2311a48ce884SFelipe Balbi return 0; 2312a48ce884SFelipe Balbi } 2313a48ce884SFelipe Balbi 2314a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2315a48ce884SFelipe Balbi { 2316a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2317a48ce884SFelipe Balbi 2318a48ce884SFelipe Balbi if (host->pdata->resume) 2319a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2320a48ce884SFelipe Balbi 2321a48ce884SFelipe Balbi } 2322a48ce884SFelipe Balbi 2323a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2324a45c6cb8SMadhusudhan Chikkature { 2325927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2326927ce944SFelipe Balbi 2327927ce944SFelipe Balbi if (!host) 2328927ce944SFelipe Balbi return 0; 2329a45c6cb8SMadhusudhan Chikkature 2330fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 233131f9d463SEliad Peller 233231f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 23332cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23342cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23352cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 233631f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 233731f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 233831f9d463SEliad Peller } 2339927ce944SFelipe Balbi 23402cd3a2a5SAndreas Fenkart /* do not wake up due to sdio irq */ 23412cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23422cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23432cd3a2a5SAndreas Fenkart disable_irq(host->wake_irq); 23442cd3a2a5SAndreas Fenkart 2345cd03d9a8SRajendra Nayak if (host->dbclk) 234694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 23473932afd5SUlf Hansson 2348fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 23493932afd5SUlf Hansson return 0; 2350a45c6cb8SMadhusudhan Chikkature } 2351a45c6cb8SMadhusudhan Chikkature 2352a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2353a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2354a45c6cb8SMadhusudhan Chikkature { 2355927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2356927ce944SFelipe Balbi 2357927ce944SFelipe Balbi if (!host) 2358927ce944SFelipe Balbi return 0; 2359a45c6cb8SMadhusudhan Chikkature 2360fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 236111dd62a7SDenis Karpov 2362cd03d9a8SRajendra Nayak if (host->dbclk) 236394c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23642bec0893SAdrian Hunter 236531f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 236670a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23671b331e69SKim Kyuwon 2368b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2369b62f6228SAdrian Hunter 23702cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23712cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23722cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23732cd3a2a5SAndreas Fenkart 2374fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2375fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23763932afd5SUlf Hansson return 0; 2377a45c6cb8SMadhusudhan Chikkature } 2378a45c6cb8SMadhusudhan Chikkature 2379a45c6cb8SMadhusudhan Chikkature #else 2380a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2381a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 238270a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 238370a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2384a45c6cb8SMadhusudhan Chikkature #endif 2385a45c6cb8SMadhusudhan Chikkature 2386fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2387fa4aa2d4SBalaji T K { 2388fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23892cd3a2a5SAndreas Fenkart unsigned long flags; 2390fa4aa2d4SBalaji T K 2391fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2392fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2393927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2394fa4aa2d4SBalaji T K 23952cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23962cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23972cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23982cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23992cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 24002cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 24012cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 24022cd3a2a5SAndreas Fenkart 24032cd3a2a5SAndreas Fenkart WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); 24042cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 24052cd3a2a5SAndreas Fenkart host->flags |= HSMMC_WAKE_IRQ_ENABLED; 24062cd3a2a5SAndreas Fenkart } 24072cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2408fa4aa2d4SBalaji T K return 0; 2409fa4aa2d4SBalaji T K } 2410fa4aa2d4SBalaji T K 2411fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2412fa4aa2d4SBalaji T K { 2413fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 24142cd3a2a5SAndreas Fenkart unsigned long flags; 2415fa4aa2d4SBalaji T K 2416fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2417fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2418927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2419fa4aa2d4SBalaji T K 24202cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 24212cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 24222cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 24232cd3a2a5SAndreas Fenkart /* sdio irq flag can't change while in runtime suspend */ 24242cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 24252cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 24262cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 24272cd3a2a5SAndreas Fenkart } 24282cd3a2a5SAndreas Fenkart 24292cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 24302cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 24312cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 24322cd3a2a5SAndreas Fenkart } 24332cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2434fa4aa2d4SBalaji T K return 0; 2435fa4aa2d4SBalaji T K } 2436fa4aa2d4SBalaji T K 2437a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 243870a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 243970a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2440a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2441a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2442fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2443fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2444a791daa1SKevin Hilman }; 2445a791daa1SKevin Hilman 2446a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2447efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24480433c143SBill Pemberton .remove = omap_hsmmc_remove, 2449a45c6cb8SMadhusudhan Chikkature .driver = { 2450a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2451a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2452a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 245346856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2454a45c6cb8SMadhusudhan Chikkature }, 2455a45c6cb8SMadhusudhan Chikkature }; 2456a45c6cb8SMadhusudhan Chikkature 2457b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2458a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2459a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2460a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2461a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2462